arXiv (All)
open access
ReDIL-GNN: Resynthesis Domain Incremental Learning for Circuit Graph Neural Networks
Logic resynthesis preserves circuit functionality while changing gate vocabulary, topology, and structural statistics, creating domain shift for circuit graph neural networks (GNNs) without changing task labels. To study this setting, we introduce ReDIL-GNN, a resynthesis domain-incremental learning
Conceptio Open Archive
Analyze & explore related research in Conceptio
Connect this record directly into your research workflow or AI agent. Explore citations across open repositories, query full text, and export structured proof bundles.
This document is indexed with metadata only: full text is not available in the archive for this record. Open the official source ↗
Related documents
- ReDIL-GNN: Resynthesis Domain Incremental Learning for Circuit Graph Neural Networks#965438
- From topology learning to graph generation: A unifying perspective#924184
- From topology learning to graph generation: A unifying perspective#919953
- Fuel Efficiency Prediction Using Deep Learning#105427
- Graph Your Own Prompt#1129118
Record · ID 1012772
Retrieved via Conceptio: every document is proof-bundled with source, license, and retrieval metadata.
Retrieved via Conceptio: every document is proof-bundled with source, license, and retrieval metadata.
Bring this data into your agent: Connect via MCP or API · 20 free credits to start · no card required
Read the Docs → · View CLI source on GitHub · Conceptio Open Knowledge Archive
Read the Docs → · View CLI source on GitHub · Conceptio Open Knowledge Archive