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FlexVector: A SpMM Vector Processor with Flexible VRF for GCNs on Varying-Sparsity Graphs
arXiv:2604.10113v1 [cs.DC] 11 Apr 2026
Bohan Li† Shengmin Li† Xinyu Shi Enyi Yao Francky Catthoor Simei Yang∗
Abstract—Graph Convolutional Networks (GCNs) are widely adopted for tasks involving relational or graph-structured data and can be formulated as two-stage sparse–dense matrix multiplication (SpMM) during inference. However, existing accelerators often struggle with the irregular workloads induced by power-law node degree distributions. In this work, we propose FlexVector, a vector-processor-based architecture that efficiently accelerates SpMM for GCN inference. To address irregular computation patterns, FlexVector adopts a row-wise, product-based dataflow that regularizes SpMM execution and exposes vector parallelism through full-row access to vector registers, eliminating the need for multi-banked register file designs. Building on this dataflow, it introduces software-managed, flexible vector register files (VRFs) that adapt to irregular data access patterns, without sacrificing memory access efficiency. To further exploit these architectural capabilities, we develop a graph-aware preprocessing and node partitioning strategy that restructures irregular graph workloads to better match the row-wise dataflow and VRF capacity. This hardware–software co-design reduces memory traffic, leading to significant performance and energy efficiency gains on real-world GCN workloads. Experimental results on five real-world GCN datasets show that the VRF-centric FlexVector achieves a 3.78× speedup and 40.5% lower energy at comparable area cost relative to a state-of-the-art cache-centric baseline with buffers of the same size. Index Terms—GCNs, Sparse-dense Matrix Multiplication, Vector Processor, Row-wise product dataflow
I. I NTRODUCTION Graph Convolutional Networks (GCNs) [1] have become a widely adopted approach for learning from irregular graphstructured data. By capturing node relationships and connectivity patterns, GCNs can achieve high performance in applications such as social network analysis, traffic prediction, and other graph-based tasks [2], [3]. The execution of a typical GCN layer is dominated by two primary phases: aggregation and combination. The aggregation phase depends on the graph’s topology, resulting in sparse and irregular memory access patterns, whereas the combination phase consists primarily of dense operations with regular memory access. Due to the contrasting computational characteristics of aggregation and combination, existing GCN accelerators have evolved along two primary architectural directions. The first adopts heterogeneous engines [4]–[6], which dedicate separate processing engines to the aggregation and combination phases. This enables phase-specific optimizations and streaming execution, where aggregation results directly feed the combination engine for pipelining. However, workload mismatch between the phases can cause pipeline stalls, resource underutilization, † These authors contributed equally. ∗ Corresponding author.
and inter-engine synchronization overhead due to rigid partitioning. The second employs unified engines [7]–[9], where a single processing engine executes both phases by sequentially mapping them into sparse–dense matrix multiplication (SpMM) operations (Section II). Such unified designs improve resource utilization and eliminate inter-engine communication. However, executing both phases on a single processing engine makes the architecture highly sensitive to workload irregularity and sparsity variation. Unified-engine GCN accelerators face challenges due to sparsity arising from three major sources. First, the aggregation phase is much sparser than the combination phase, often by several orders of magnitude [9]. Second, nodes exhibit widely varying numbers of neighbors, resulting in highly irregular memory access patterns and computation. Both of these factors largely result from the power-law distribution of real-world graphs [10]–[12] (Section II), where a few “supernodes” are densely connected while most nodes have very few connections, particularly affecting the aggregation phase. Third, the sparsity of node features can vary across graphs or over time in evolving datasets. These variations limit the effectiveness of static dataflow optimizations for computation and memory access. To address these challenges, GCNAX [7] focuses on dataflow optimization for a unified GCN engine, supporting configurable tiling, loop ordering, and loop fusion strategies. In contrast, GROW [9] adopts a hardware-software co-design approach, combining a row-wise product dataflow (Gustavson’s algorithm [13]) with a dedicated hardware cache (or a software-managed scratchpad) and graph preprocessing techniques to handle sparsity and irregular computation. In this work, we propose a novel unified GCN engine, FlexVector, which exploits a vector-processor architecture for SpMM operations and leverages high parallelism and programmability to adapt to varying sparsity. Unlike conventional vector processors, which rely on multi-banked VRFs to sustain access bandwidth, FlexVector employs softwaremanaged flexible VRFs with both fixed and dynamic regions to support irregular memory access patterns at the register level. By integrating flexible VRFs with row-wise dataflow in a hardware–software co-designed manner, FlexVector enables full-row VRF access, eliminating the need for VRF banking and simplifying control. Prior work such as GROW [9] adopts a cache-centric design with a row-wise dataflow to handle irregular DRAM–cache data access. FlexVector directly applies row-wise dataflow to the buffer–VRF level. However, a singlelevel dataflow is insufficient for the DRAM–buffer interface in FlexVector’s memory hierarchy, where an additional dataflow
Hardware Design: We propose FlexVector, a vectorprocessor-based unified GCN engine featuring softwaremanaged VRFs with fixed and dynamic regions to handle irregular access patterns. We develop a sparsity-aware algorithm to adapt the fixed–dynamic VRF boundary, and introduce a customized coarse-grained ISA to simplify SpMM control. • Graph Preprocessing: We introduce a hybrid graph preprocessing strategy that integrates edge-cut and vertexcut partitioning to reshape irregular graph workloads under on-chip buffer and VRF capacity constraints. This strategy balances workloads across the sparsity variations of power-law graphs, improving VRF utilization and computation efficiency. • Dataflow Optimization: We introduce a hierarchical dataflow, where row-wise product execution at the buffer–VRF level enables full-row VRF access and high lane utilization, while inner-product execution at the DRAM–buffer level sustains efficient data movement across memory hierarchies. •
We implement FlexVector in RTL and an in-house simulator. We perform a comprehensive PPA evaluation, and conduct ablation studies and sensitivity analyses of buffer and VRF sizing using five real-world graph datasets. Experimental results show that FlexVector achieves up to 3.78× speedup and 40.5% energy reduction over a state-of-the-art cache-centric baseline at comparable area and buffer capacity. Moreover, the sparsity-aware algorithm that adapts the fixed–dynamic VRF partition achieves near-optimal performance, within 2% of the best static configuration. The paper is organized as follows. Section II reviews SpMM computation in GCNs and relevant related work, highlighting the innovations of our proposed FlexVector. Section III introduces the proposed FlexVector architecture. Sections IV and V illustrate the graph preprocessing strategy and hierarchical dataflow, respectively. Section VI presents experimental evaluations and Section VII concludes the paper.
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Fig. 1: The aggregation and combination stages of GCN. II. BACKGROUND AND R ELATED W ORK A. GCN and SpMM Computation 1) GCN Basics: Fig. 1 depicts the two main phases of a GCN layer, where aggregation propagates information along graph edges and combination transforms node features with a dense weight matrix. Equation 1 presents the corresponding forward propagation formulation. X (l+1) = σ(ÂX (l) W (l) )
(1)
where X (l) is the input feature matrix of layer l, W (l) is the trainable weight matrix, and  denotes the normalized sparse adjacency matrix of the graph structure. σ(·) represents a nonlinear activation function (e.g., ReLU). As reported in prior studies [7]–[9], matrix  is typically large and highly sparse, matrix X has moderate size with workload-dependent sparsity, and matrix W is small and dense. We can compute a GCN layer using two possible execution orders: (Â × X) × W and Â × (X × W ). The former order involves a sparse–sparse matrix multiplication followed by a dense–dense multiplication, whereas the latter performs two successive sparse–dense multiplications, resulting in significantly fewer multiply-accumulate (MAC) operations compared to the former [7]–[9]. Therefore, we adopt the latter execution order Â × (X × W ) to perform sparse-dense matrix multiplication (SpMM) for GCN inference. 2) Power-Law of GCN