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Exploring the Efficiency of 3D-Stacked AI Chip Architecture for LLM Inference with VOXEL

Liu, Yiqi et al.
arXiv (OAI Expanded) · Papers
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and-cluster-computingdistributedhardware-architectureparallel
To overcome the well-known memory bottleneck of AI chips, 3D-stacked architectures that employ advanced packaging technology with high-density through-silicon vias (TSVs) pins have proven to be a promising solution. The 3D-stacked AI chip enables ultra-high memory bandwidth between compute and memor
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