Reversing the Clock: Layout-Aware Recovery of Design Intent from Clock Distribution Networks

Reversing the Clock: Layout-Aware Recovery of Design Intent from Clock Distribution Networks Sascha Tommasone∗† , Zehra Karadağ‡† , Christopher Pawlowicz∗ , Michael Green∗ , Bruno Machado Trindade∗ , Eunsung SEO∗ , Christof Paar† , René Walendy† , Steffen Becker‡† ∗ TechInsights Inc., Canada, {sascha.tommasone, cpawlowicz, mgreen, btrindade, porter.seo}@techinsights.com † Max Planck Institute for Security and Privacy, Germany, {firstname.lastname}@mpi-sp.org

arXiv:2610.03182v1 [cs.CR] 2 Oct 2026

‡ Ruhr University Bochum, Germany, {firstname.lastname}@rub.de

Abstract—Hardware reverse engineering supports competitive analysis and hardware assurance by recovering information about an integrated circuit (IC) from its physical implementation. While existing techniques primarily recover the gate-level netlist, which represents logical functionality, they often overlook physical design decisions such as placement, routing, delay insertion, and interconnect optimization. The clock distribution network encapsulates many of these decisions; however, no prior published work has recovered this network from a fabricated IC to infer design intent. We present a layout-aware methodology that recovers and analyzes the clock distribution network by integrating a recovered gate-level netlist with layout information extracted from scanning electron microscope imagery. Our fourphase pipeline recovers clock-tree topology, buffering, gating and switching, interconnect delay, and crosstalk-mitigation measures. We demonstrate our methodology on a commercial 450 nm IC, recovering a global H-tree backbone with local X-tree-like branching, identifying an independent clock tree and global clock gating, quantifying latency, skew, and routing lengths, and confirming the absence of dedicated crosstalk mitigation. Together, these findings let us reason about the designer’s intent. To encourage further research and support reproducibility, we release our clock tree recovery algorithm as open source. Index Terms—hardware reverse engineering, clock distribution network, clock tree recovery, hardware assurance, design intent

I. I NTRODUCTION Competitive analysis through hardware reverse engineering (HRE)—recovering a high-level description of an integrated circuit (IC) from its physical implementation to understand how it was designed—is an established practice in the semiconductor industry [1], [2]. Beyond recovering what a circuit does, its value lies in revealing how the design was realized: the trade-offs among performance, power, and area that distinguish one implementation from another. Current HRE techniques, however, predominantly recover and analyze the gate-level netlist (GLN) [3], [4], which captures only logical functionality and omits the physical design decisions encoded in the layout—cell placement, routing, delay insertion, and interconnect optimization. The clock distribution network (CDN) concentrates such decisions like few other structures on a chip: it is among the most carefully engineered networks in an IC and a dominant consumer of dynamic power, accounting for up to 40 % [5], so its topology, buffering, and gating closely track a design’s performance and power strategy. Yet, no prior published work has

reconstructed the CDN from a physical IC to recover design intent. These design decisions make a recovered clock tree (CT)—unlike the netlist—a rich source for such analysis: its topology can be matched against reference designs to attribute implementations or localize third-party IP cores, while metalrouting lengths, interconnect propagation delays, and physical countermeasures such as crosstalk shielding or buffer sizing provide further distinguishing signatures. In this paper, we present a method to recover CDNs from reverse-engineered ICs by combining a gate-level netlist with layout information obtained from scanning electron microscope (SEM) imagery, and demonstrate its effectiveness in a real-world case study. Our contributions are as follows: A four-phase pipeline that reconstructs and analyzes the CT by combining the netlist with layout information, proceeding through netlist and layout recovery, clock-tree recovery, structural analysis, and timing analysis. • A case study on a commercial IC fabricated in a 450 nm node, where layout-aware analysis recovers the CT’s hybrid H-tree/X-tree architecture, quantifies its clock latencies, skews, and routing lengths, and detects the absence of dedicated crosstalk mitigation—enabling us to reason about the designer’s intent. • An open-source artifact comprising the algorithm for recovering the CT graph as a plugin for the HAL framework [6], and a benchmark netlist; its setup and execution scripts are permanently hosted on Zenodo.1 •

II. BACKGROUND A. Clock Distribution The physical clock distribution implementation reflects how designers balance performance, area, and power through placement, routing, delay insertion, and interconnect optimization [8]. Recovering this design intent requires reverse engineering the physical implementation and the circuit’s functional description. 1 https://doi.org/10.5281/zenodo.21263979. As the case-study netlist cannot

be published, the artifact utilizes the open-source Cloneless1 netlist [7] to remain runnable.

1) Clock Distribution Networks: Clock signals are distributed through carefully engineered structures called clock distribution networks (CDNs) or clock trees (CTs) [9]. Various topologies trade off latency, power, area, skew, jitter, and scalability [10]; the H-tree and X-tree are the most widely adopted [8], [9]. The H-tree uses symmetric, recursive Hshaped branching to keep all sinks equidistant from the source, theoretically eliminating skew, though process variations introduce minor mismatches. The X-tree instead uses diagonal X-shaped branches to reduce wire length and latency, but is harder to balance and more sensitive to layout-induced skew. 2) Clock Integrity Measures: To counter clock skew, clock buffers and inverters can balance arrival times and regenerate the signal, at the cost of area and switching power [5], [11]. To preserve signal integrity, they protect the frequently switching clock lines against crosstalk from capacitively coupled neighbors using wider spacing or grounded guard tracks, consuming routing resources [12], [13]. These choices manifest physically—as inserted cells, wire detours, and spacing patterns—and remain readable in the layout. B. Hardware Reverse Engineering To infer design intent from a physical IC, both the gatelevel netlist (GLN) for clock tree recovery (CTR) and detailed layout information for clock tree analysis (CTA) are required. These are obtained through netlist recovery (NR), the initial phase of HRE [1], [2], [4]. During NR, the IC layers are exposed and imaged, then stitched, aligned, and segmented into a coherent three-dimensional (3D) layout representation, from which standard cells and connectivity are identified, producing the GLN [14]. Because NR is error-prone, it introduces opens and shorts into both artifacts, which CTR must tolerate. Subsequent netlist analysis (NA) conventionally operates only on the GLN [3], [15], reducing CDNs to a graph of interconnected gates. However, distinguishing information about different implementations, such as topology, routing, spacing, and crosstalk control, is captured only in the recovered layout but is set aside by conventional analysis, leaving a rich source of information untapped. III. M ETHODOLOGY To reverse engineer CDNs and ultimately uncover design intent, we implement a four-phase pipeline (see Figure 1). The process begins by recovering the IC layout and gate-level netlist (GLN), followed by recovering the CT. The final two phases, structural and timing analyses, then yield the insights from which we infer design intent. A. Phase 1: Netlist & Layout Recovery We cross-section the IC to guide the subsequent delayering and to support later parasitic extraction and 3D modeling. During delayering, we image each exposed layer with a SEM and segment the images into a coherent 3D polygonal layout, and then preprocess it (dilation, per-layer unary union, erosion, simplification) to close gaps and reduce geometric noise. We

1 · Netlist & Layout Recovery extract cells, nets and physical dimensions from IC

2 · Clock Tree Recovery bottom-up traversal from sinks to global inputs

3 · Structural Analysis analyze topology, routing, buffering & crosstalk

4 · Timing Analysis analyze clock latencies & skew

Fig. 1: Our four-phase pipeline, from a physical IC to a reconstructed and analyzed CT that grounds design-intent recovery. then recover the GLN from this layout by reverse-engineering standard cells and signal-tracing interconnectivity. We refine this recovery iteratively, using the netlist as the correctness signal: basic design rule checks (DRCs) flag multidriven nets, undriven nets, and gates driving power or ground; the violations guide targeted layout corrections (fixing shorts and opens, rerunning signal tracing, adding cells), repeated until the netlist stabilizes. These checks are deliberate— undriven nets mark termination points for CTR, multi-driven nets often signal shorts that divert the clock into datapath or control logic, and power/ground-driving gates are rare enough to warrant manual inspection. The resulting cross-sectional images, layout, and GLN form the basis for all subsequent phases. B. Phase 2: Clock Tree Recovery The recovered GLN lacks structural and semantic information available during the original design process, such as module hierarchy and signal names [4]. Consequently, the CT and its associated clock signals are typically unknown. In the second phase, our novel CTR algorithm reconstructs the CT solely from recovered data, combining structural netlist properties with layout information. The algorithm is released as an open-source plugin2 for HAL [6]. It comprises three steps: integrating layout information with the netlist to identify global inputs and outputs, identifying clock-dividing structures, and constructing the CT. 1) Identifying Global Inputs: A CT may comprise multiple subtrees driven by a common global clock input. When recovery relies solely on the GLN, these subtrees appear disconnected because their roots terminate at an unidentified global input, making them resemble undriven wires. As a result, the recovered CT becomes partitioned since the CTR algorithm cannot distinguish between externally-driven wires and NR errors. Therefore, we identify global inputs before CTR to resolve this ambiguity and assemble the subtrees into a complete CT. 2 https://github.com/emsec/hal/tree/master/plugins/clock tree extractor

Global wires traverse the digital-core boundary. We identify them by approximating the boundary as a polygon and selecting metal-layer polygons that intersect this boundary. During NR, signal tracing organizes polygons into wires, referred to as nets within the context of GLNs. Consequently, boundary-crossing polygons can be directly mapped to their corresponding GLN nets. We then classify each global net heuristically as a global input if it lacks a driver in the GLN, and as a global output otherwise. 2) Identifying Clock Dividers: Flip-flops are generally sinks in the CDN, with their clock input driven by the CT [9]. However, when used within a clock divider, flip-flops function as active elements in the clock path and must be represented as such in the CT. The toggle flip-flop, which halves the clock frequency, is the most basic example: it is identifiable directly from the netlist, as its inverted output connects back to its own data input. Before CT construction, we detect all such toggle flip-flops so they can be treated as active clock elements rather than sinks during traversal. 3) Recovering the Clock Tree: We adopt a bottom-up approach where we construct the CT by tracing from sequential gates toward the clock sources. This strategy does not require a priori knowledge of clock sources and is more robust to local recovery errors than top-down CT construction. The CT construction process begins by initializing a directed acyclic graph (DAG), hereafter referred to as the CT graph, with all flip-flops as nodes. From each flip-flop, a modified Breadth-First Search (BFS) is performed on the GLN to traverse the clock network in the reverse direction. At each step, the algorithm recursively follows valid fan-in connections. In contrast, control inputs (such as set, reset, and multiplexer select signals), power and ground nets, and invalid connections (such as unrouted or multi-driven nets) are excluded. Global inputs, buffers, inverters, and delay gates are treated as active clock elements and thus serve as reference points during traversal to stay on the clock path. A branch is terminated upon reaching a latch or a non-clock-dividing flip-flop, as these sequential elements are typically part of the control logic that steers clock gates rather than the CT. If a branch cannot be traversed further and does not terminate at a reference point, it is discarded because it cannot be reliably associated with the CT. If a traversal terminates at a reference point, the gates along the clock path are merged into the CT graph. Subsequently, edges are inserted in the order of traversal, and nodes without predecessors are designated as roots. Having recovered the CT with its global inputs and outputs and clock dividers, we can now analyze its structure in depth. C. Phase 3: Clock Tree Structural Analysis Based on the output from phases 1 and 2—the CT graph, the GLN, and the physical layout—the structural analysis recovers all CT branches. It examines the implemented topology, routing, buffering strategies, dynamic power-reduction techniques, and signal-integrity measures to infer underlying

design principles. As part of the analysis, we developed the following algorithms: • An undirected graph-based layout representation enables efficient intersection queries and short detection. The graph nodes represent layout polygons, and edges denote intersections across the same or adjacent layers; it is built during signal tracing. • A ray-casting method identifies adjacent polygons and computes spacing profiles within a layer. This approach samples points along each polygon edge and extends probes along the corresponding outward edge normal until they encounter an adjacent polygon or reach a predefined maximum distance. • A centerline-graph method estimates track and total wire lengths by finding the shortest path between two points on the same wire within the layout graph. It constructs a centerline graph for each traversed metal polygon and uses adjacent via nodes as entry and exit points to estimate each segment’s length. These algorithms provide the foundation for all subsequent layout-based analyses. 1) Identifying the Topology: To infer the implemented topology, we integrate the CT graph with gate placement coordinates to produce a layout-aware visualization, since the CT graph alone does not capture physical implementation details. We visualize the CT graph at different tree-traversal depths from each root to help identify multiple combined CT topologies. 2) Branch Recovery: To perform the subsequent analyses, we must identify the various CT branches, each representing a distinct clock signal path to a sink, from the recovered CT graph. We extract these branches by traversing the CT graph from each root to every reachable sink, recording each unique root-to-sink path as an ordered sequence of triples: driver, interconnect segment, and load. 3) Identifying Buffering: Clock buffers and clock inverters serve as the primary active elements in a CT [8]. Analyzing their placement and distribution can provide insights into active delay insertion, area optimization, and slew-rate recovery. The buffering strategy can be visualized using either the previous CT-topology approach or a comprehensive 3D interconnect model. In topology-based visualization, we highlight clock buffers and inverters using distinct colors. In contrast, we construct the 3D model by extruding layout geometry using the layer heights extracted from the cross-sectional images and overlaying the active elements onto the resulting model. Compared with the two-dimensional (2D) topology, the 3D visualization offers the reconstructed physical clocktree implementation for inspection and is easier to analyze. 4) Identifying Dynamic Power Reduction: Given that CTs can contribute up to 40 % of dynamic power consumption [5], modern ICs frequently implement clock gating and clock switching to minimize dynamic power or facilitate operation across multiple clock domains [16], [17]. Clock gating is commonly implemented using combinational gates in the CT that are not buffers, inverters, or

multiplexers. In contrast, clock switching is generally realized using multiplexers or similar logic structures. These distinctive configurations enable effective identification within the CT graph. Functional analysis of these elements provides the conditions for gating or switching clock signals, while NA reveals the controlling logic and the components affected. 5) Identifying Routing: CT routing complexity is determined by two primary factors: the metal layers utilized and the number of layer transitions per branch relative to the total branch wire length. We determine metal-layer utilization by automatically estimating the physical length of each CT track and summing these lengths across all metal layers using our centerline-graph-based distance algorithm. We calculate the total branch wire length by summing the lengths of all metaltrack segments that form a branch, while layer transitions are quantified by counting the via-layer crossings along the branch. However, we exclude standard-cell interconnects from both metrics because they are not part of the CT routing. Specifically, we first identify the metal layers reserved for standard-cell routing and then exclude all CT metal polygons on these layers that intersect a standard-cell pin and overlap the corresponding standard-cell boundary by more than 50 %. 6) Determining Signal-Integrity Measures: Determining whether shielding or increased-spacing crosstalk control is implemented globally, locally, or not at all requires both the CT graph and layout information. First, we generate a spacing profile for each metal track in the recovered CT, recording its surrounding tracks and their respective spacings only within the same layer. We then apply method-specific post-processing to these spacing profiles to infer the implemented crosstalk mitigation strategy and classify it as global, local, or absent. D. Phase 4: Clock Tree Timing Analysis Structural analysis does not capture the dynamic behavior of a clock signal. Understanding system performance therefore requires evaluating its timing characteristics. Each CT branch exhibits a unique clock latency, determined by interconnect and standard-cell propagation delays [9]. Accordingly, we build a SPICE circuit model for each branch, simulate it, and use the resulting latencies to compute clock skews. We develop these branch models by representing each interconnect segment as a distributed resistance-capacitance (RC) circuit and connecting them using the corresponding SPICE standard-cell models. The standard cells can be approximated by measuring transistor characteristics, such as gate length and width, and utilizing generic SPICE transistor models to build a standard-cell model. To estimate metaltrack resistances from the layout and cross-sectional imagery, we adopt the widely used sheet-resistance model [18], and to estimate metal-track capacitances, we use the open-source 3D field solver FasterCap [19]. We construct the 3D payloads for FasterCap by integrating the layout geometry with layer heights obtained from cross-sectional imagery. IV. C ASE S TUDY The case study applies the methodology to the digital core of a real-world IC, fabricated in a 450 nm technology node

and operating at 2 MHz or 3 MHz depending on the supplied voltage. Its three metal layers, M1 to M3, have approximate track widths of 625 nm, 395 nm, and 475 nm, respectively. The CDN of the digital core has three global inputs: two clock sources and a select signal that determines which source is used. The selected clock is distributed to a partial I2 C interface consisting of X-tree-like sinks and, through an H-tree backbone, to other X-tree-like sinks. The branches to these destinations are controlled by additional logic that determines whether the I2 C module receives its clock through the path shared with the H-tree backbone enable, during normal operation, or through a dedicated direct path that can remain active, whereas the backbone is disabled (see Figure 2). The independent I2 C lets the interface stay responsive while the rest of the core is gated. This architecture can reduce power consumption by disabling the main clock distribution while keeping the I2 C interface operational to monitor external events. select

on-chip clock

ext. clock (I/O) backbone enable

clock-source select

I2 C clock select I2 C

H-tree backbone

Branches directly to I2 C Branches gated to I2 C

X-tree Branches gated to non-I2 C

Fig. 2: Clock paths from inputs to sinks, with branches and control structures highlighted. The H-tree backbone forms the primary clock distribution structure. Its symmetric topology minimizes clock skew at the expense of increased routing resources, while naturally matching the preferred routing directions of the upper metal layers. At lower levels, symmetry is gradually relaxed to improve routing efficiency and accommodate the irregular placement of sink clusters. Figure 3 shows a layout-aware visualization of the I2 C sinks connected to an H-tree. Previous NA already revealed the presence of this interface, but didn’t provide information about its specific clocking. The third subtree is a complete yet functionally deactivated divider-based clock-switching structure in the top-right region. A. The Recovered Clock Tree as Basis for Analysis The completeness of the recovered CT can be measured by the number of flip-flop coverages, since each flip-flop requires a clock. The recovered CT covers 1, 290 of the 1, 346 flip-flops (95 %). The remaining 56 flip-flops are distributed across 50 small splinters, mostly resulting from netlist errors such as opens or shorts. Covering the vast majority of expected flipflops is sufficient to reason about the design principles behind

Fig. 3: Layout-aware 2D visualization of an excerpt of the CT, constrained to a maximum traversal depth of 11, showing an H-tree structure with the I2 C subtree in the bottom-right. the clock distribution. Therefore, this case study focuses on the largest component. Within this component, three global inputs act as the root. Two are clock sources, and one serves as a clock select. All three converge at a clock-switching structure at the head of the CT, where the select signal determines which of the clock sources should be used. B. Clock Control Structures Most elements of the recovered CT serve only to distribute the clock: the metal interconnect, buffers, and inverters merely propagate the clock signal. Along these branches, however, reside four active control structures—the only points at which the clock distribution can be reconfigured during operation. They determine which source drives the tree, whether the clock reaches its sinks at all, and at which frequency. a) Clock Source Selection: The physical root of the recovered CT is a compound AOI gate that functions as a two-input MUX. This MUX is the clock-switching structure at which the three global inputs converge: the two clock sources form its data inputs, and the select signal its control input. Depending on the select signal, the recovered CT is driven either by the on-chip clock or by an external clock supplied through an I/O cell. An I/O cell also supplies the select signal. Every sink in the CT therefore operates on whichever clock this selection admits. In the analyzed configuration, this structure always selects the on-chip clock source. b) H-Tree Backbone Enable: Downstream of this source selection, an active-low enable clock gate, implemented as an OR2 gate, is positioned directly upstream of the H-tree backbone. In addition to the clock, this gate receives a control signal; when asserted high, it blocks all clock edges, preventing the entire downstream H-tree from receiving a clock. The affected flip-flops retain their state but cease switching, thereby eliminating the clock-related dynamic power of most of the digital core. A single gate with this reach constitutes coarsegrained clock gating: rather than gating individual registers or modules, the designers provide a single global switch. c) I2 C Clocked Alone: While the backbone is disabled, 2 the I C CT can remain clocked: its root is a two-input MUX

that dynamically selects the clock driving the downstream independent CT. One input is derived directly from the recovered CT root and is thus unaffected by the backbone enable; the other is obtained after the H-tree backbone clock gate, before branching into the H-tree. These two inputs enable a potential low-power mode: the gated input keeps the interface synchronized with the core under normal operation, whereas the ungated input allows the I2 C interface to monitor external events. Meanwhile, the remainder of the device is shut down. d) Clock Division and Selection: An 8-to-1 MUX in the top-right region of the digital core selects among eight clock divisions generated by a chain of toggle flip-flops. This structure taps the on-chip clock before the root selector, bypassing both source selection and the backbone enable. The divisions span from 2−7 to 2−15 of the primary clock, except 2−13 . In the configuration under analysis, the select inputs are tied high, selecting 2−15 . This clock signal drives a 10bit shift register, whose output is bypassed by a 2-to-1 MUX, rendering the structure inactive. The presence of a complete yet disabled implementation indicates a provisioned capability, potentially intended for manufacturing test, debugging, or other configurable features. C. Physical Implementation The control structures let the I2 C CT and the H-tree backbone operate independently, yet their physical implementation must still keep both parts synchronized during normal operation. We therefore examine logic depth, metal routing, buffering, and crosstalk control of the recovered CT. 1) Groups Revealed by Depth: On its way from the root to a sink, the clock traverses different numbers of gates. When logic depth is equal across branches, active delays are nearly equivalent; unequal depths translate directly into clock skew. Matching the logic depth across branches is thus the primary means of balancing their active delays [20]. The recovered CT exhibits exactly this balance: the distribution of stages per branch is unimodal (see Figure 4). The majority of branches contain 17 stages, whereas only a few exhibit 16 or 18 stages. Branches with 23, 7, or 3 stages are rare, isolated outliers unrelated to the special structures identified in Section IV-B. That over a thousand sinks scattered across the die are reached through virtually identical logic depths is no accident: paths that would naturally be short carry additional inserted stages that match them to the rest. The clock paths to the I2 C sinks are considerably shorter than those to the sinks of the H-tree backbone. Left uncorrected, this disparity would cause the clock to arrive at the interface well before it arrives in the core—a skew between the two parts that must cooperate under normal operation. Short paths cannot be shortened further, but they can be extended artificially. This extension is realized exclusively with buffers, which compensate for the shorter clock paths to the I2 C sinks by introducing active delay through stage insertion, synchronizing the interface with the remainder of the digital core during normal operation. The H-tree backbone, in contrast, needs to regenerate the signal along its long paths

Fig. 4: Number of stages per branch within the recovered CT. and relies exclusively on inverters—for driving, a typically economical choice, as it reduces area requirements and enhances robustness to duty-cycle fidelity [9]. 2) Groups Revealed by Routing: Branches can be grouped not only by logic depth but by the delay implied by their metal routing. If the CT is partitioned by function, branches within a group should share similar wire lengths and numbers of layer transitions—as observed in the data: per branch, total wire length correlates positively with the number of metal-layer transitions (i. e., via layers traversed), and the branches form distinct clusters (see Figure 5). Four dominant clusters appear between approximately 40 and 90 layer transitions, along with eight smaller clusters above 90 layer transitions. Three of the four dominant clusters, as well as all eight smaller clusters, correspond to the structures identified in Section IV-B; each functional group of the CT thus appears as its own cluster.

Fig. 5: Total wire length per recovered CT branch as a function of the number of metal-layer transitions. 3) Crosstalk Mitigation Strategies: Our analysis of metaltrack spacing in the recovered CT routing shows no shielding guard tracks. While some regions have increased spacing, it is not applied consistently. D. Timing Analysis The structural analysis suggests deliberate design intent: balanced logic depths, inserted buffers, and routing partitioned by function. Whether these measures achieve their goal is decided in nanoseconds, not in cell counts—by the time the clock

actually arrives at each sink. We therefore approximate the clock latency of every branch from the recovered geometry and its parasitics (cf. Section III-D), obtaining the two quantities that no netlist contains: clock latency and clock skew. 1) Clock Latencies: We simulated clock latencies for all branches without clock-dividing structures, defining the clock at the first inverter after source selection. The routing clusters in Section IV-C indicate a functional partitioning of the recovered CT, which the latency distribution supports by showing similar groupings (see Figure 6). Direct I2 C branches show the lowest latencies (4.39 ns to 4.60 ns), followed by I2 C branches through the backbone enable (5.59 ns to 5.75 ns). All other backbone sinks have the highest latencies (8.16 ns to 9.64 ns).

Fig. 6: Clock latencies for relevant sinks of the recovered CT. 2) Clock Skews: These latency ranges result in skews that may initially seem contradictory: while the global skew is substantial, each section of the CT remains tightly balanced internally. The timing behaviour of this IC is characterized by four metrics: global skew (8.77 ns), skew within the I2 C CT (0.21 ns), skew among H-tree-clocked sinks excluding those associated with the I2 C CT (1.49 ns), and skew across all H-tree-clocked sinks (4.05 ns). The substantial global skew primarily results from a few exceptionally short clock paths, an anticipated outcome of the partitioned CT. The acceptability of a 8.77 ns skew depends not on its absolute value but on its relationship to the clock period and critical paths. This observation is consistent with a recurring pattern identified during the structural analysis: balancing was performed mostly within functional groups rather than globally, clock gating and switching were implemented using regular MUXs and gates instead of glitch-free circuits, and crosstalk countermeasures were omitted. This pattern suggests that timing was not under pressure and the designers economized accordingly. V. D ISCUSSION AND F UTURE W ORK Our case study demonstrates that layout-aware clock tree recovery (CTR) and clock tree analysis (CTA) provide insights not accessible from the gate-level netlist (GLN) alone. The evaluation targets an IC in a mature 450 nm process with three metal layers. Therefore, broader validation across designs and technology nodes is needed to establish generality. The CTR currently targets single-driver nets and tree-like clock distribution networks (CDNs); supporting meshes, clock-gating

cells, and more complex clock dividers and multipliers would broaden the recoverable design space. Timing analysis may be further refined by incorporating target-specific cell characterization, accurate clock-gate modeling, consideration of crosstalk and inductive effects, and empirical validation of resistance and capacitance estimates. Beyond competitive analysis, we envision the following applications for our methodology in hardware assurance. a) Layout-Aware Netlist Analysis: The broader use of layout information for HRE remains largely unexplored. Physical features, including cell placement and routing characteristics, offer structural information absent from GLN-only analysis and may enhance algorithms for recovering wordlevel structures, such as DANA [21]. More broadly, exploiting layout information for netlist analysis (NA) could improve the recovery of higher-level design structures. b) Trojan Detection: Hardware Trojans may target the CDN to manipulate clock frequency, introduce glitches, or launch fault attacks [22]. For instance, a Trojan may disable the clock or increase skew in specific functional components. Such modifications often manifest as anomalous clock-tree structures or clock gates. Consequently, CTR could support detection of these Trojans, including electromagnetic-based Trojans such as the one described by Takou et al. [23]. c) IP-Core Detection: Modern system on chips (SoCs) frequently integrate intellectual property (IP) cores as semiindependent functional blocks [24]. Because these blocks often contain dedicated CTs integrated into the central CDN as subtrees, recovering CT structures may offer an effective approach for localizing and identifying third-party IP. Together, these directions show that the CDN is a rich and largely untapped source of design intent. By recovering it from a fabricated IC, our work opens the layout, not just the netlist, as a target for reverse engineering and assurance. ACKNOWLEDGMENT We thank Dr. Norman Fong for his analysis of the crosssectional images, Zoltan Manyoki for his contributions to RCdelay modeling, and Aly Ahmed, Cynthia Mar, and Keith Doherty for their work on netlist recovery and partial circuit analysis, as well as the rest of the team at TechInsights. This work was supported by the Deutsche Forschungsgemeinschaft (DFG, German Research Foundation) under Germany’s Excellence Strategy – EXC 2092 CASA – 390781972, and by the Research Center Trustworthy Data Science and Security, one of the Research Alliance Centers within the UA Ruhr. R EFERENCES [1] R. Torrance and D. James, “The State-of-the-Art in IC Reverse Engineering,” Lecture Notes in Computer Science, 2009. [2] S. E. Quadir, J. Chen, D. Forte, N. Asadizanjani, S. Shahbazmohamadi, L. Wang, J. Chandy, and M. Tehranipoor, “A Survey on Chip to System Reverse Engineering,” J. Emerg. Technol. Comput. Syst., vol. 13, no. 1, pp. 6:1–6:34, Apr. 2016. [3] L. Azriel, J. Speith, N. Albartus, R. Ginosar, A. Mendelson, and C. Paar, “A survey of algorithmic methods in IC reverse engineering,” Journal of Cryptographic Engineering, vol. 11, no. 3, pp. 299–315, Sep. 2021.

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