GreenPeas: Unlocking Adaptive Quantum Error Correction with Just-in-Time Decoding Hypergraphs Abbas B. Ziad
Jubo Xu
Hongxiang Fan
[email protected] Imperial College London London, UK
[email protected] Imperial College London London, UK
[email protected] Imperial College London London, UK
syndromes extracted from the code via specialised quantum circuits. These decoders typically operate under one of two paradigms: phenomenological, which uses a simplified model of data qubit and measurement errors, or circuit-level, which employs a complex hypergraph to capture all error mechanisms in the syndrome measurement (SM) circuit. While circuit-level decoders offer significantly higher accuracy than their phenomenological counterparts, the compilation from an SM circuit to a decoding hypergraph is a computationally intensive process. Even with state-of-theart tools like Stim [10], this translation can take tens to hundreds of milliseconds for circuits with hundreds of physical qubits. Given that current hardware SM cycles operate on microsecond [11] to millisecond [5] timescales, these tools are therefore limited to ahead-of-time (AOT) workflows. This AOT requirement imposes a critical bottleneck for adaptive circuits, where gate sequences are determined at runtime based on mid-circuit measurement outcomes, e.g., conditional logic [15] and certain adaptive SM protocols [4, 22]. Since this paradigm necessitates pre-computing all possible decoding hypergraphs—a task that scales exponentially in the number of circuit branches—this places an unsustainable burden on the system. Ultimately, this constraint relegates circuit-level decoders to static sequences or circuits with a low branching factor. To overcome this limitation, we introduce GreenPeas, a C++/CUDA toolchain designed for the rapid, just-in-time (JIT) compilation of decoding hypergraphs. A key insight of our approach is the use of an intermediate representation (IR) based on the circuit’s space-time error propagation graph. This IR enables an efficient mapping of Stim’s backtracking algorithm onto massively parallel GPU architectures. Our implementation achieves a throughput of over one million hyperedges per second across a variety of surface [14] and bivariate bicycle [6] codes—outperforming the Stim baseline by over 10× on average—thereby reducing compilation latency to the sub-millisecond regime. Our contributions are as follows:
arXiv:2604.16613v1 [quant-ph] 17 Apr 2026
Abstract Circuit-level decoders are essential for the realisation of lowoverhead fault-tolerant quantum computing. However, they rely on complex hypergraphs that are traditionally compiled ahead-of-time. This static approach introduces a significant bottleneck for an emerging class of adaptive circuits, where the structure is modified during execution based on midcircuit measurement outcomes. Pre-compiling hypergraphs for all possible circuit branches would incur an exponential memory cost, rendering current tools impractical for these workloads. Hence, we introduce GreenPeas, a C++/CUDA toolchain for the high-speed, just-in-time compilation of decoding hypergraphs. By lowering the circuit to a space-time error propagation graph, we show how Stim’s backtracking algorithm can be mapped efficiently onto massively parallel GPU architectures, decomposing the O (𝑛 × 𝑙) workload for a circuit with 𝑛 qubits and 𝑙 gate layers across thousands of concurrent threads. Our implementation achieves a greater than 10× average speedup over the Stim baseline across two of the leading fault-tolerant architectures: the surface and bivariate bicycle codes. As a key use case, we demonstrate that this speedup enables circuit-level decoding of adaptive syndrome measurement circuits, unlocking a regime previously restricted to less accurate phenomenological decoders. We aim to open-source GreenPeas to support the research of future adaptive circuit protocols.
1
Introduction
The theoretical potential of quantum computing promises to revolutionise fields ranging from cryptography [21] to material science [16] and drug discovery [1]. However, realising these applications in practice requires error rates between 10−6 and 10−12 to support the millions to trillions of operations involved [7]. Current devices remain far from this regime, with fidelities of "three nines" (99.9%) considered state-of-the-art [11]. This three-to-nine order-of-magnitude gap necessitates robust quantum error correction (QEC) to bridge the divide between noisy physical and reliable logical qubits. In general, a QEC system consists of two core components: (a) a quantum code that redundantly encodes logical information into a highly entangled state of physical qubits, and (b) a classical decoder that identifies errors by processing
• Space-Time IR: We introduce a specialised binary graph representation for SM circuits (Sec. 2.3). By storing this graph as a highly compact ELLPACK matrix, we enable perfectly coalesced memory access across the GPU during graph traversal. 1
Abbas B. Ziad, Jubo Xu, and Hongxiang Fan
• Massively Parallel Error Analysis: We reformulate the traditionally sequential backtracking algorithm into a high-throughput parallel workload (Sec. 3.1), enabling the simultaneous discovery of thousands of potential errors across the GPU’s SIMT architecture. • Dynamic Detector Instantiation: We develop a technique for adaptive circuits where detectors are conditionally defined on the fly based on the circuit’s execution path (Sec. 5.2.4). This reduces the average decoding volume and latency compared to static approaches, enabling more efficient decoding. • GreenPeas Library: We present a high-performance C++/CUDA compilation library that achieves submillisecond latency on various surface and bivariate bicycle codes. This enables circuit-level decoding of adaptive SM circuits (Sec. 5.3), a feature previously restricted to simpler phenomenological decoders.
2
Background, Motivation and Formalism
For a comprehensive treatment of stabiliser codes and their measurement circuits, we refer the reader to Section 2 of [25]. In this paper, we focus on describing the standard algorithms for error analysis, highlighting the significant computational bottlenecks involved in compiling decoding hypergraphs, especially in the context of online workflows. This motivates our proposed formalism (Sec. 2.3), which addresses these challenges by enabling embarrassingly parallel execution across the compilation pipeline.
2.1
Figure 1. Error analysis. (a) The SM circuit for a distance 3 repetition code (two rounds). We show four detectors, coloured orange, blue, green and yellow. The orange (green) detector is defined by the first measurement of ancilla qubit 0 (1). The blue (yellow) detector is defined by the parity of the measurements of ancilla qubit 0 (1). The challenge of error analysis is to find the set of detectors flipped by each of the possible circuit errors (𝐸 0 −𝐸 25 ), i.e., their equivalence classes. For example, a bit flip (𝑋 -error) on data qubit 1 after the second CNOT layer (𝐸 12 ) propagates through the subsequent entangling gates to flip the yellow and blue detectors. (b) The STEPG. Error analysis is performed via a backwards layer traversal with each node’s equivalence class being computed as the XOR sum of its successors’ classes. (c) The decoding hypergraph. Each hyperedge represents one of the nine error equivalence classes with associated probabilities, 𝑝 0 − 𝑝 8 .
Background
Circuit-level decoders require a map from physical errors to their observed effects on the system’s syndrome, typically represented as a weighted hypergraph G = (V, E). Each node 𝛿 ∈ V corresponds to a detector, a parity check of measurement outcomes that is deterministic in the absence of noise. Each hyperedge 𝜖 ∈ E denotes an error equivalence class with associated probability 𝑃 (𝜖), defined by the unique set of detectors triggered by one or more physical errors. To construct G, we must determine the equivalence class for every possible error in the circuit. This can be achieved by propagating each error through the circuit and recording the specific set of detectors it flips (e.g., see 𝐸 12 in Fig. 1(a)). However, this naive approach has complexity O (𝑛 2𝑙 2 ) for a circuit with 𝑛 qubits and 𝑙 gates layers [8]. To avoid this quadratic overhead, tools like Stim employ a backtracking approach. Instead of propagating every error forward, this method tracks the sensitivity of each detector backward through the circuit. Then, as an error 𝐸𝑖 is encountered in the walk, the set of detectors that have "passed through" that location define its error equivalence class.
2.2
Motivation
As discussed in Sec. 2.1, the backtracking algorithm implemented in Stim relies on a sequential traversal of circuit instructions. This approach fails to exploit the inherent parallelism in the error propagation problem, resulting in compilation latencies that exceed the cycle times of even "slow clock" (≈ 1 ms) platforms, such as neutral-atom and trapped-ion systems (see Fig. 3). Consequently, this sequential bottleneck remains incompatible with the strict latency constraints of real-time QEC [23]. It is worth reflecting on whether online compilation is truly necessary, or if offline compilation—for which current 2
GreenPeas: Unlocking Adaptive Quantum Error Correction with Just-in-Time Decoding Hypergraphs
tools are well-suited—suffices. For static circuits with fixed parameters, pre-computation is often acceptable. However, in long-duration computations, physical error rates often drift, necessitating periodic re-calibration of the decoding hypergraph to maintain logical fidelity. Furthermore, in adaptive workflows, where the circuit structure changes based on mid-circuit measurement results, pre-computation would incur an exponential memory cost (see Sec. 5.2.1). In these regimes, the serial nature of current approaches becomes a critical bottleneck. Supporting these dynamic use cases requires a paradigm shift: moving away from instruction-byinstruction backtracking toward a formalism that exposes massive, data-level parallelism. 2.3
components via the XOR sum in Eq. (1). We categorise these as level-1 correlated errors, while those arising from higherorder combinations are designated as level-2 (see Table 1).
3
Formalism
The key insight of our approach lies in recasting the backtracking algorithm as a data-flow process. We first lower the circuit to a space-time error propagation graph (STEPG). As shown in Fig. 1(b), the STEPG represents the circuit as a layered directed acyclic graph (DAG), where nodes denote potential Pauli error locations and edges correspond to gateinduced transformations through time. For example, an 𝑋 error on the control qubit before a CNOT gate propagates to an 𝑋 error on the target qubit afterward. Under this representation, the construction of G reduces to a straight-line program where the equivalence class 𝜖𝑢 of a node 𝑢 is computed as the bitwise XOR sum of its successors’ classes: Ê
𝜖𝑢 =
𝜖𝑣
3.1
(1)
Since multiple physical errors can share an equivalence class (e.g., 𝐸 3 , 𝐸 8 and 𝐸 13 in Fig. 1(b)), we employ a parallel sort-and-reduce pipeline to aggregate identical signatures. For each resulting hyperedge 𝜖 ∈ E, the total probability 𝑃 (𝜖) is computed by merging the probabilities 𝑝𝑖 of all constituent physical errors that map to that class: Ê
𝑝𝑖
Parallel Error Equivalence Class Generator
We implement the straight-line program for error analysis (Eq. (1)) using a layer-synchronous backward traversal of the STEPG, as detailed in Algorithm 1. To maximise throughput, we exploit the intra-layer independence of the graph to process the 𝑘 = 𝛼𝑛 nodes within each layer in parallel. Here, 𝑛 represents the number of qubits and 𝛼 is a constant determined by the correlation level, which dictates the type of Pauli errors captured by the STEPG; and, consequently, the number of nodes in each of its layers (see Table 1). This parallelisation reduces the serial complexity from O (𝑛𝑙) to a parallel execution time of O (𝑙), where 𝑙 denotes the number of gate layers in the circuit. The traversal is initialised by mapping the detector set V onto the STEPG leaf nodes V𝑙𝑒𝑎𝑓 . Each measurement 𝑀 is assigned a leaf node, leaf(𝑀), which serves as the boundary condition for the program. For a detector 𝛿 ∈ V defined by the parity of measurements {𝑀0, 𝑀1, . . . }, we initialise the corresponding bit in the error equivalence classes:
𝑣 ∈𝑁 + (𝑢 )
𝑃 (𝜖) =
Compiler Design
Following the formalism introduced in Sec. 2.3, this section describes how our compiler transforms the STEPG into a decoding hypergraph. The compilation pipeline consists of two stages: (1) a parallel error equivalence class generator that traverses the STEPG to compute the equivalence class for each node (Sec. 3.1); and (2) a high-throughput sort-and-reduce pipeline that deduplicates these classes and aggregates their combined probabilities to construct the final decoding hypergraph (Sec. 3.2).
∀𝑀 ∈ 𝛿, E [leaf(𝑀)] ← E [leaf(𝑀)] ⊕ e𝛿 (3) where e𝛿 is the elementary basis vector for detector 𝛿. 3.1.1 Data Layout Policies. To ensure high performance on GPUs, we implement a data layout policy designed for perfectly coalesced memory access. We store the STEPG as a linear array of 64-bit words, where the successors of each node are packed into the upper and lower 32-bit words. This layout allows the 𝑘 parallel threads to fetch their required successor indices in a single, contiguous memory transaction, minimising the total number of global memory requests. To represent the error equivalence classes E, we employ a bit-packed binary matrix optimised for bit-parallelism. Each class is stored as a bit array across 𝑊 = ⌈|V |/64⌉ 64-bit words. By adopting a column-major layout, we ensure that the 𝑤-th words of every class are stored contiguously in memory. This layout allows the 𝑘 parallel threads to fetch their required 𝑤-th words in a single, coalesced memory transaction, further reducing global memory traffic.
(2)
𝑖 |𝐸𝑖 ↦→𝜖
where 𝑝𝑎 ⊕ 𝑝𝑏 = 𝑝𝑎 (1 − 𝑝𝑏 ) + 𝑝𝑏 (1 − 𝑝𝑎 ). By offloading this reduction to a high-throughput radix sort, we maintain a fully parallelised pipeline from the raw circuit to the final decoding hypergraph, such as that in Fig. 1(c). The STEPG in Fig. 1(b) only represents the propagation of bit-flip (𝑋 ) errors. If phase-flip (𝑍 ) errors can also occur, we adopt a symplectic representation [12] by doubling the width of the DAG. Here, each physical location is associated with two nodes, one for 𝑋 and another for 𝑍 , allowing the graph to capture the full propagation of Pauli errors under Clifford gate operations. Correlated errors, such as 𝑌 errors, can also be accounted for by adding additional source nodes that aggregate the signatures of their constituent 𝑋 and 𝑍 3
Abbas B. Ziad, Jubo Xu, and Hongxiang Fan
the bit arrays into fixed-width keys that can be used with a high-performance sorting engine. We use the Fowler–Noll–Vo (FNV-1) hash function [9] for this projection due to its computational simplicity and low collision rate. Although 32-bit hashes are efficient to sort, they introduce a non-negligible risk of collisions in large graphs where distinct classes can be erroneously merged. Consequently, we use 64-bit hashes, but note that many circuits have a tolerance to minor approximation that could allow for lower resolution in performance-critical contexts. In practice, we implement the sorting and reduction stages using CUB primitives [18]. To minimise data movement, we use a double-buffering strategy for the radix sort, followed by a fused reduction kernel. By employing a zipped-iterator approach, we merge the error probabilities in accordance with Eq. (2) and propagate their associated indices in a single, high-bandwidth pass. Finally, we construct the decoding hypergraph by gathering the unique bit arrays and their combined probabilities into contiguous memory locations.
Algorithm 1: Error Equivalence Class Generator Input : 𝐺 : Space-time error propagation graph (STEPG) 𝑙 : Number of layers 𝑘 : Number of nodes per layer E : Error equivalence classes (modified in-place) 1
for 𝑖 ← 𝑙 − 2 to 0 do
2
parallel for 𝑗 ← 0 to 𝑘 − 1 do
3
𝑢 ← GetIndex(𝑖, 𝑗)
4
(𝑣, 𝑤) ← Unpack(𝐺 [𝑢])
5
E [𝑢] ←
E [𝑣] ⊕ E [𝑤] E [𝑣] E [𝑤] 0
if 𝑣, 𝑤 ≠ −1 if 𝑣 ≠ −1, 𝑤 = −1 if 𝑣 = −1, 𝑤 ≠ −1 if 𝑣 = 𝑤 = −1
3.1.2 Thread Decomposition. Consequently, the ⊕ operation in Algorithm 1 reduces to a sequence of 𝑊 bitwise XOR instructions. For circuits with a large number of detectors, we can further improve throughput by employing a twodimensional thread decomposition. This approach allows the 𝑊 words to be processed in parallel across the thread block, ensuring that the implementation scales with both the number of nodes and detectors, better saturating GPU resources.
3.3
Our toolchain uses a configurable correlation level (𝐿0 , 𝐿1 , and 𝐿2 ) to allow users to navigate the trade-off between model accuracy and computational efficiency during compilation and decoding. At lower levels, we consider a restricted subset of physical errors (see Table 1), generating sparser hypergraphs that reduce memory footprint and accelerate processing, albeit at the cost of worse logical accuracy. Historically, decoding strategies have been restricted to a binary classification: uncorrelated and correlated, mapping to levels 𝐿0 and 𝐿2 in our framework. Such a categorisation, however, lacks the granularity required to comprehensively explore the trade-off space that exists between these two extremes. Our multi-level approach represents an initial step toward a more nuanced treatment of this design space. Note that correlation level 𝐿0 consists entirely of pure 𝑋 - and 𝑍 -type Pauli errors. It ignores terms such as 𝑌 or 𝑋𝑍 that could simultaneously trigger both 𝑋 - and 𝑍 -type stabiliser measurements. Therefore, when using this level for a 𝑍 -basis experiment, 𝑋 -detectors should be excluded (and vice versa for 𝑋 -basis experiments). Otherwise, the resulting hypergraph may mislead the decoder, reducing logical accuracy and increasing latency.
3.1.3 Performance Optimisations. The backward traversal order creates a synergistic effect with the GPU cache hierarchy. Since the successor indices 𝑣, 𝑤 fetched for the nodes in layer 𝑖 refer to nodes exclusively located in the recently processed layer 𝑖 + 1, the bit arrays E [𝑣] and E [𝑤] exhibit high temporal locality. Consequently, the required data is typically "hot" in the L2 cache, allowing the bitwise ⊕ operations to be serviced at cache speeds rather than being throttled by global memory bandwidth. In practice, we further optimise throughput by accessing 𝐺 via the __ldg() intrinsic. Since the graph is immutable, this directive fetches node data through the specialised readonly data cache. By bypassing the standard L1 cache for these lookups, we prevent the graph’s topology data from competing for cache lines with the high-bandwidth bit-array operations in E, maximising the effective cache capacity available for the equivalence class updates. 3.2
Configurable Correlation Level
3.4
Sort and Reduce Pipeline
Output format
To ensure compatibility with the existing QEC ecosystem, GreenPeas exports the decoding hypergraph as a detector error model (DEM), a standard interface introduced by Stim. Structurally, the output comprises a weighted hyperedge list where each entry maps physical error probabilities to their respective detector triggers, enabling seamless integration with the broader error correction stack (Fig. 2).
To deduplicate the error equivalence classes post-generation, we implement a high-throughput parallel sort-and-reduce pipeline. Since the raw bit arrays occupy multiple 64-bit words (𝑊 > 1) in general, a naive sort would incur significant overhead in terms of key comparisons and data movement. As such, we introduce an additional hashing stage to project 4
GreenPeas: Unlocking Adaptive Quantum Error Correction with Just-in-Time Decoding Hypergraphs
Correlation Level
Pauli Errors
4.1
Factor (𝛼)
0
𝐼𝑋, 𝐼𝑍, 𝑋 𝐼, 𝑋𝑋, 𝑍 𝐼, 𝑍𝑍
2
1
𝐼𝑌 , 𝑋𝑍, 𝑌 𝐼, 𝑍𝑋
4
2
𝑋𝑌 , 𝑌 𝑋, 𝑌𝑌 , 𝑌 𝑍, 𝑍𝑌
7
We evaluate GreenPeas on NVIDIA RTX 3090 (Ampere) and RTX 6000 Blackwell (Server Edition) GPUs, comparing against the Stim baseline on a single core of an AMD EPYC 9335 CPU. We sweep the correlation level and measure the mean compilation time for a single round of various surface and bivariate bicycle code circuits (Fig. 3). A direct comparison between Stim and GreenPeas is only appropriate at correlation level 𝐿2 where both tools produce equivalent decoding hypergraphs, up to minor floating-point variances in error probabilities. Here, we observe a geometric mean speedup of 9× on Ampere and 12× on Blackwell. Table 2 shows the complete list of speedups. Algorithm 1 exhibits low arithmetic intensity, making its performance sensitive to memory rather than compute throughput. The performance uplift on Blackwell is thus primarily driven by its superior memory bandwidth and larger L2 cache, which mitigate the latency overhead of the irregular accesses in E and 𝐺. We note that Stim can leverage repetitive circuit structures to reduce compilation latency via loop folding. However, this optimisation requires manual circuit annotations that are difficult or impossible to generate for adaptive circuits. Consequently, to ensure a fair comparison and reflect the requirements of adaptive workloads, we disable this feature in Stim and do not implement it in GreenPeas. Stim is also recognised for leveraging SIMD accelerators, such as AVX on x86 systems, to optimise performance. However, to the best of our knowledge, its error analysis pipeline still relies exclusively on scalar instructions. Consequently, we do not utilise SIMD capabilities in our benchmarks, as they would not impact the performance of the specific workloads under evaluation.
Table 1. Classification of the 15 non-trivial CNOT Pauli errors into cumulative correlation levels (𝐿0 ⊂ 𝐿1 ⊂ 𝐿2 ). The factor 𝛼, which determines the STEPG node density via 𝑘 = 𝛼𝑛, is defined recursively as 𝛼𝑖 = 𝛼𝑖 −1 + ⌈𝑚/2⌉, where 𝑚 is the number of additional correlated errors introduced at each level (4 for 𝐿1 ; 5 for 𝐿2 ). This hierarchy applies specifically to the CNOT gate; other two-qubit gates (e.g., CZ or iSWAP) would necessitate a different hierarchical approach.
Physical Circuit
Parse
GreenPeas
Stim
Dynamic JIT
Static AOT Compile
DEM Universal IR
Target Lowering
Target A
Target B
Target C
Target D
Decoder Instruction Set Architectures (DISAs)
Figure 2. Positioning GreenPeas. The DEM serves as a universal IR for targeting various decoder architectures. Depending on the use case, viz. static vs. dynamic, either Stim or GreenPeas, respectively, can be used to compile the DEM before lowering to a target backend.
4
Compilation Latency
4.2
Decoding Accuracy and Latency
Beyond compilation latency, we also evaluate decoding accuracy and latency by integrating GreenPeas and Stim with Tesseract [3], a heuristic most-likely error (MLE) decoder. For each of the memory experiments, we compute the logical error rate, 𝑅 as the fraction of samples where the decoder mispredicts the correction operator. Since our experiments use 𝑑 error correction cycles, the logical error rate per round is then calculated as
Performance Evaluation
We perform standard Z-basis memory experiments using the surface and bivariate bicycle codes, two of the leading code families. Since we target a per-round compilation latency of ≤ 1 ms, we adopt a noise model inspired by hardware modalities with commensurate cycle times, such as neutralatom and trapped-ion architectures. This circuit-level noise model is parameterised by a noise strength 𝑝. Then, single- and two-qubit Clifford gates are followed by depolarising channels with strengths 𝑝 and 𝑝/10, respectively. Furthermore, measurement results are flipped with probability 𝑝, reset operations fail with probability 𝑝, and idle qubits are subject to a single-qubit depolarising channel of strength 𝑝/10 [4].
1 1 − (1 − 2𝑅) 1/𝑑 (4) 2 Note that we follow Appendix B of [3] and use the short beam decoder setting for all benchmarks. No alternative decoder settings are considered in this work. We measure the mean decoding time per round of Tesseract on an AMD EPYC 9335 CPU by averaging the total execution time across 105 trials and normalising the result by 𝑑. We use the logical error rates in Fig 4 to functionally verify GreenPeas. Notably, there is no degradation in logical 𝑅per round =
5
Abbas B. Ziad, Jubo Xu, and Hongxiang Fan
Surface Code Ampere Blackwell
Bivariate Bicycle Code
𝑑=3
𝑑=5
𝑑=7
𝑑=9
𝑑=6
𝑑=10
𝑑=12
Geomean
2.13 2.23
7.04 8.38
10.71 14.77
12.93 18.05
12.29 18.22
13.40 20.09
13.88 20.68
8.99 12.09
Table 2. Mean compilation time speedups of GreenPeas (correlation level 𝐿2 ) relative to Stim across various surface and bivariate bicycle codes. Results are reported for NVIDIA Ampere and Blackwell GPU architectures, with the geometric mean provided for aggregate comparison.
Mean Compilation Time Per Round (ms)
Mean Compilation Time Per Round (ms)
Surface Code
Bivariate Bicycle Code 14
3.2 12 2.4 10
1.6
8
0.8
6 1.0 0.25
0.8
0.20
0.6
0.15
0.4
0.10
0.2 3
5
Code distance (d)
Correlation Level L0 L1
L2
7
9
6
GPU Architecture Ampere Blackwell
10 Code distance (d)
12
Baseline Stim
Figure 3. Compilation latency scaling. Mean compilation time per round versus code distance 𝑑 for surface codes (left) and bivariate bicycle codes (right). Top panels show the Stim baseline, while bottom panels display GreenPeas performance across correlation levels 𝐿0 − 𝐿2 and GPU architectures (Ampere, Blackwell). Results are averaged over 10, 000 runs per circuit at a physical error rate of 𝑝 = 0.1%; latency was found to be largely independent of 𝑝. The standard deviation remained < 2% of the mean, indicating high determinism. Notably, GreenPeas maintains latencies of ≤ 1 ms across all tested configurations, satisfying the real-time constraints of neutral atom and trapped ion platforms.
6
GreenPeas: Unlocking Adaptive Quantum Error Correction with Just-in-Time Decoding Hypergraphs
accuracy when using correlation level 𝐿2 compared to the Stim decoding hypergraph. We emphasise, however, that this parity is specifically confirmed for the current noise model at a strength of 𝑝 = 0.1%. The correlation levels are primarily used to navigate the accuracy-speed trade-off. At lower levels, decoding latency is minimised at the expense of higher error rates. Conversely, higher levels yield the lowest error rates but increase latency. As the code distance increases, the accuracy gap between correlation levels widens, while the decoding time maintains a consistent overhead across levels.
5
heuristics. For the surface code results presented here, we employ the mapping shown in Fig. 5. Specifically, assuming standard N- and Z-shaped CNOT sequences for X and Z checks, each data qubit at (𝑟, 𝑐) is paired with a partner at: (𝑟 ′, 𝑐 ′ ) = (𝑑 − 1 − 𝑟, (𝑐 + 2) mod 𝑑)
where 𝑑 is the distance of the surface code. The reflection across the lattice ensures that paired qubits are supported by different surface code checks, while the cyclic shift ensures they occupy different time slots in its schedule. 5.2
Case Study: Adaptive SM Circuits
Implementation
5.2.1 Decoding Hypergraph Compilation. Adaptive SM circuits challenge the assumption that decoding hypergraphs can always be compiled ahead of time. Since the set of active checks is stochastically determined each cycle, the number of potential hypergraphs scales exponentially with the code distance. This renders ahead-of-time compilation impractical, since the memory overhead required to store pre-compiled hypergraphs would be prohibitive for all but the smallest code distances. Therefore, to decode adaptive SM circuits with circuitlevel precision, we must compile the decoding hypergraph on a per-shot basis. Given this requirement, the authors of [4] opted to use a simpler phenomenological decoder, as the compilation latency of contemporary tools was too high. GreenPeas unblocks the use of more accurate circuit-level decoders by delivering millisecond-scale compilation latency.
In this section, we explore a critical use case for JIT decoding hypergraph compilation, namely adaptive SM circuits. We begin by discussing the motivations for such circuits and the specific concatenation strategies used to implement them (Sec. 5.1). We then discuss several details about our implementation, focusing centrally on the capabilities that enable circuit-level decoding (Sec. 5.2). Lastly, we present our results in Sec. 5.3, showing how circuit-level decoding of adaptive SM circuits can both lower logical error rates and improve decoding latency. 5.1
(5)
Background
Fault-tolerance faces a fundamental challenge: measuring errors requires quantum gates, yet every gate introduces new noise. Conventional SM circuits rely on a static set of measurements that can inadvertently overwhelm the code with the very errors it seeks to correct. On the other hand, adaptive SM circuits employ a dynamic set of measurements via preliminary observations that isolate and target only probable error locations. Berthusen et al. [4] demonstrated the utility of adaptive SM circuits through a concatenated scheme, where an inner [[4, 2, 2]] Iceberg code [20] is paired with an outer hypergraph product (HGP) code [24]. By leveraging the inner checks to filter the outer layer, the protocol restricts outer syndrome measurements to only those regions where the inner codes indicate the presence of errors, minimising the injection of noise from redundant, low-fidelity operations. Figure 5 illustrates this scheme using an outer surface code. To preserve fault-tolerance, data qubits supported by the same surface code check must be mapped to separate Iceberg blocks. This ensures that a single fault within a block cannot spread into a weight-2 error in the surface code, which would reduce its effective distance. Additionally, to ensure schedulecompatibility, the mapping must assign data qubits that share a time slot in the surface code’s schedule to separate Iceberg blocks, thereby preventing hardware-level gate conflicts. Finding a mapping that satisfies these constraints can be framed as a maximum matching problem on a conflict graph. However, for regular lattices, it can be solved via geometric
5.2.2 Inner Code Decoding. Following the technique described in Section VI.A of [4], we decode the inner Iceberg code blocks prior to the outer code according to a heuristic recipe. Specifically, for every detected X (Z) error, we apply a corresponding X (Z) Pauli correction to the shared qubit of the X (Z) logical operator. However, to maintain high logical fidelity, the final decoding of the concatenated structure must integrate syndromes from both the inner and outer checks. These heuristic Pauli corrections are applied each cycle based on the absolute outcomes of the current inner-check layer. On the other hand, the execution of the outer checks is triggered by the difference syndrome—the XOR sum of the current and previous inner-check layers. This hybrid approach is consistent with the prior art, but employing difference syndromes to drive both correction and triggering logic may offer a more cohesive strategy. We defer a formal investigation of such a unified approach to future work. 5.2.3 Refresh Rate. To mitigate boundary effects, we execute all outer checks during the initial and final rounds of the experiment. Moreover, as established in Section VI.B of [4], it is essential to apply all outer checks during intermediate rounds at a refresh rate R to prevent a build-up of logical errors in the inner code blocks from overwhelming 7
Abbas B. Ziad, Jubo Xu, and Hongxiang Fan
Surface Code
Logical Error Rate Per Round
10 3 10 4
10 4
10 5
10 5
10 6
10 6
10 7
10 7
10 8
3
5
7
10 8
9
10 3 Mean Decoding Time Per Round (s)
Bivariate Bicycle Code
10 3
6
10
12
6
10 Code distance (d)
12
10 1
10 4
10 2
10 5 10 3
10 6 10 7
3
5
7
9
Correlation Level L0 L1
L2
Code distance (d)
10 4
Baseline Stim
Figure 4. Decoding accuracy and latency scaling. Logical error rate (top) and mean decoding time (bottom) per round versus code distance 𝑑 for surface codes (left) and bivariate bicycle codes (right). Results are obtained using the Tesseract decoder with decoding hypergraphs compiled by GreenPeas (𝐿0 -𝐿2 ) and Stim. The physical error rate 𝑝 = 0.1% in all cases. Top: Each data point represents 20 million samples; error bars denote 90% confidence intervals propagated through Eq. 4. Notably, no loss in logical accuracy is observed between the Stim baseline and GreenPeas 𝐿2 . Bottom: Results are averaged over 100 thousand trials. We observe a slight increase in per-round decoding latency with GreenPeas 𝐿2 when compared to the Stim baseline, likely due to minor variations in hyperedge probabilities. Correlation levels 𝐿0 and 𝐿1 trade off accuracy for speed. Across all benchmarks, the "uncorrelated" (𝐿0 ) MLE decoder decodes in under 1 ms per round, fast enough to keep pace with neutral atom and trapped ion quantum computers. the concatenated structure. In our 𝑑-round experiments, a refresh rate of R = 𝑑/2 yielded the optimal logical fidelity and distance scaling. However, a more exhaustive analysis of the impact of the refresh rate remains a valuable direction for future study.
current and previous measurement indices for each check, incrementing the current index only when a check is executed. Detectors are then instantiated if and only if these indices differ, ensuring the syndrome remains consistent with the adaptive circuit structure. Although this detector scheme can yield smaller decoding hypergraphs in terms of node count, it does not inherently reduce decoding complexity. Specifically, detectors may be defined by measurement pairs that span multiple cycles, resulting in a type of "temporal stretching" that can increase hyperedge complexity. As demonstrated in the following
5.2.4 Dynamic Detector Instantiation. Given that the sequence of operations depends on mid-circuit measurements, the circuit itself requires JIT compilation. In particular, the detectors used to construct the syndrome must be dynamically instantiated. We manage this by tracking the 8
GreenPeas: Unlocking Adaptive Quantum Error Correction with Just-in-Time Decoding Hypergraphs
12
the theoretical underpinnings for non-HGP codes are less established. We therefore use the surface code as a wellunderstood vehicle to demonstrate our contributions. At correlation levels 𝐿1 and 𝐿2 , we found MLE decoding of both static and adaptive concatenated surface codes to be computationally prohibitive. Relative to the 𝐿0 baseline, accounting for these higher-order correlations increased the average per-shot decoding latency by more than an order of magnitude, reaching 100× in the worst case. Consequently, we use 𝐿0 hypergraphs for all concatenated codes, though alternatives to the short beam decoder configuration could potentially enable 𝐿1 or 𝐿2 decoding.
13 14 15
0 1 2 3
5.3
Evaluation
To evaluate the performance of static versus adaptive SM circuits, we conduct Z-basis memory experiments using a variety of concatenated surface codes. The primary results of our experiments are summarised in Fig. 6.
14
5.3.1 Performance Trends. By employing circuit-level decoding, we identify two critical performance trends when comparing static and adaptive SM circuits at a physical error rate of 𝑝 = 0.1%. First, the relative suppression of the logical error rate scales favourably with the code distance 𝑑. Notably, at 𝑑 = 10, the adaptive scheme achieves nearly a twofold reduction in logical error rate relative to the static baseline. Second, owing to the reduced average decoding volume, adaptive SM circuits consistently exhibit lower computational overhead. For instance, we observe approximately a 35% reduction in decoding latency at 𝑑 = 10. We note that these results are obtained using MLE decoding at correlation level 𝐿0 ; the extent to which these advantages persist at higher correlation levels remains to be demonstrated.
0
Figure 5. Adaptive code concatenation. A surface code (top) implemented via concatenation with an array of Iceberg codes (bottom). Data qubits in the surface code (orange) map to logical operators within the Iceberg blocks. For example, data qubits 0 and 14 correspond to the first and second logical operators of the leading block, respectively. An initial error detection cycle measures the checks (green) of all Iceberg codes. In the subsequent error correction cycle, only surface checks with support on data qubits in an excited Iceberg block, i.e., one containing an odd number of errors (red), are executed. For example, the first and last surface checks are run since they support qubits 0 and 14, both of which belong to the excited leading Iceberg block. This adaptive protocol reduces the total CNOT gate count, resulting in a lower logical error rate than the non-adaptive baseline.
5.3.2 Comparison with Prior Art. A direct comparison between our results and those presented in [4] is precluded by the use of different outer codes. Moreover, while both studies utilise circuit-level noise, the authors of [4] employ a simpler phenomenological decoder via a combination of BP-OSD [13] and BP-LSD [19], whereas we use full circuitlevel decoding via GreenPeas and Tesseract. This distinction is significant: the use of phenomenological decoding likely explains the near- or at-threshold behaviour observed in their results at 𝑝 = 0.1%. In contrast, our approach achieves strong exponential error suppression with increasing code distance at the same physical error rate, indicating that our system remains firmly in the sub-threshold regime. Notably, we observe an increasing relative improvement from adaptive SM circuits when compared to static SM circuits as the code distance grows, a scaling benefit that is likely enabled by the use of circuit-level decoding.
section, we nonetheless observe reduced decoding latency at correlation level 𝐿0 for adaptive SM circuits compared to their static counterparts. 5.2.5 Outer Code Decoding. We employ the surface code as the outer code to showcase the benefits of circuit-level decoding enabled by JIT compilation of the decoding hypergraph. Although its low-weight checks make it a suboptimal candidate for the adaptive protocol compared to codes with higher-weight checks, such as the bivariate bicycle code, 9
Abbas B. Ziad, Jubo Xu, and Hongxiang Fan
Concatenated Surface Code
Mean Decoding Time Per Round (s)
Logical Error Rate Per Round
10 3
critical for adaptive circuits, where compilation must occur at runtime and meet strict latency requirements. For static or offline use cases, Stim remains the industry standard. Although Stim’s error analysis pipeline leverages only a single CPU core, it remains the state-of-the-art reference for decoding hypergraph compilation. A multicore CPU version of GreenPeas would be fundamentally mismatched, since its architecture is designed for massive thread concurrency where each thread performs a small unit of work. Such finegrained parallelism would lead to prohibitive scheduling overhead on a multicore CPU, whereas it is precisely what the GPU’s SIMT architecture is optimised for.
Static Adaptive
10 4 10 5 10 6
6.2
Open Challenges
Even with the millisecond-scale compilation latency of GreenPeas, simulating large-scale adaptive circuits remains a formidable challenge. This is particularly evident in the lownoise regime where physical error rates are ≤ 0.1%. Here, achieving acceptable error bars typically requires millions to billions of Monte Carlo trials. Beyond decoding hypergraph compilation, two additional challenges motivate future research: the computational overhead of error sampling and the latency of decoder initialisation.
10 3
10 4
4
6
8
Code distance (d)
6.2.1 Error Sampling. Since adaptive circuits must branch based on mid-circuit measurements, simulations must use Stim’s tableau simulator, which is orders of magnitude slower than its frame simulator. This bottleneck is especially acute for circuits with a high branching factor, such as those studied in Sec. 5. As such, the large-scale exploration of these circuits will likely require new simulation techniques that treat measurement-driven branching as a first-class primitive rather than a high-overhead exception.
10
Figure 6. Comparison of static and adaptive SM circuits. Logical error rate (top) and mean decoding time (bottom) per round versus code distance 𝑑 for concatenated surface codes. Decoding results are obtained via the Tesseract decoder with decoding hypergraphs compiled by GreenPeas at correlation level 𝐿0 . The physical error rate 𝑝 = 0.1% in all cases. Data points represent 106 samples for 𝑑 ∈ {4, 6} and 1.5 × 106 samples for 𝑑 ∈ {8, 10}. Error bars denote 90% confidence intervals propagated through Eq. 4. Adaptive SM circuits consistently outperform their static counterparts both in terms of decoding accuracy and latency.
6
Discussion
6.1
Positioning Relative to Stim
6.2.2 Decoder Initialisation. Even with low-latency decoding hypergraph compilation, many decoders rely on intensive initialisation routines that delay decoding. Spatiotemporal accelerators, such as the Local Clustering Decoder [27], offer runtime reconfiguration features that are particularly useful for adaptive workflows. However, these architectures are typically specialised for simple algorithms and graph models, limiting their general applicability. We therefore expect the broader development of low-overhead decoder initialisation techniques to be an interesting area for future research. 6.3
Towards Microsecond Timescales
GreenPeas is optimised for hardware modalities with millisecond-scale cycle times, such as neutral atom and trapped ion systems. These architectures natively support the longrange connectivity essential for high-rate quantum lowdensity parity-check (qLDPC) codes, offering a compelling path toward utility-scale quantum computing [2, 7, 17, 26]. However, superconducting and photonic qubits remain attractive for their microsecond-scale execution. Therefore,
While this paper evaluates GreenPeas against Stim, the two are fundamentally complementary. The latter provides a comprehensive ecosystem for the simulation and analysis of Clifford circuits. In contrast, the former is a specialised toolchain designed for the specific bottleneck of compiling decoding hypergraphs. This specialisation is particularly 10
GreenPeas: Unlocking Adaptive Quantum Error Correction with Just-in-Time Decoding Hypergraphs
we briefly examine how our toolchain might be extended to support these faster modalities. Most architects will recognise Algorithm 1 as a prime candidate for dataflow acceleration. Therefore, significant performance gains could be realised by mapping it onto a spatio-temporal array of processing elements, exploiting both its inherent parallelism and regular data-dependency chain. This suggests a heterogeneous model where the error equivalence class generator is offloaded to a dataflow fabric, while the subsequent sort-and-reduce pipeline remains on the GPU. Such a hybrid approach could bridge the gap to "fast clock" quantum computers.
7
Conclusion
Adaptive circuits represent a critical frontier in the realisation of large-scale fault-tolerant quantum computers. Not only are they a necessity for various fault-tolerant logical operations, but they also provide a powerful mechanism for mitigating the inherent overhead of error correction. As demonstrated in this work, adaptive protocols can significantly lower logical error rates by filtering redundant gate operations from syndrome measurement circuits. This simultaneously compresses decoding volume, thereby reducing classical computational latency, a pivotal metric for the deployment of practical, utility-scale quantum computers. Nevertheless, foundational tools are still lacking to enable the widespread adoption of adaptive circuits. In particular, decoding hypergraph compilation, a central prerequisite for circuit-level decoding, is currently limited to ahead-of-time workflows, which scale poorly when applied to adaptive circuits with large branching factors. This paper addresses this gap with GreenPeas: a just-intime compiler for decoding hypergraphs. GreenPeas is built on several key technical contributions, including an efficient space-time IR, massively parallel error analysis, and a highperformance C++/CUDA compilation library. Through extensive experiments on two of the leading code families: the surface and the bivariate bicycle codes, GreenPeas achieves an average speedup of over 10× when compared to the Stim baseline. As a case study, we demonstrate that GreenPeas enables circuit-level decoding of adaptive syndrome measurement circuits, a regime previously restricted to less accurate phenomenological decoders. More broadly, its submillisecond compilation latency makes GreenPeas especially well matched to “slow-clock” quantum computing platforms, such as neutral-atom and trapped-ion systems.
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Abbas B. Ziad, Jubo Xu, and Hongxiang Fan
References
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