Intra-layer adapter for fifth generation new radio (5g-nr) communications — Nvidia Corporation (US20220151022A1)

ABSTRACT

Abstract

Apparatuses, systems, and techniques to facilitate Fifth Generation New Radio (5G-NR) network communication. In at least one embodiment, communication in a 5G-NR network between Layer 2 and Layer 1 components is performed by a uniform interface to facilitate accelerated 5G-NR network processing using one or more parallel processing units, according to various novel techniques described herein.

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation-by-pass of PCT International Patent Application No. PCT/CN2020/128456, filed Nov. 12, 2020, entitled “INTRA-LAYER ADAPTER FOR FIFTH GENERATION NEW RADIO (5G-NR) COMMUNICATIONS,” the disclosure of which is incorporated herein by reference in its entirety.

FIELD

At least one embodiment pertains to processing resources used to facilitate Fifth Generation (5G) communication. For example, at least one embodiment, pertains to processors or computing systems used to provide a uniform interface between Layer 1 and Layer 2 components of a 5G communication network, according to various novel techniques described herein.

BACKGROUND

Communication networks, particularly with respect to Fifth Generation (5G) communications, are moving toward disaggregated architectures. Instead of having a monolithic, single-vendor structure, components of base station networks are increasingly provided by different vendors. However, these base station network components must communicate between multiple vendor interfaces. As a result, network equipment providers face significant challenges in interconnecting components from different vendors for various layers in a 5G communication network.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a vendor- specific Layer 2 to Layer 1 interface in a communication network, according to at least one embodiment;

FIG. 2 is a block diagram illustrating a Layer 2 adapter to facilitate communication between Layer 2 and Layer 1 in a communication network, according to at least one embodiment;

FIG. 3 is a block diagram illustrating an interface between one or more vendor- specific Layer 2 interfaces and uniform Layer 1 using a Layer 2 adapter in a communication network, according to at least one embodiment;

FIG. 4 is a block diagram illustrating a Layer 2 adapter to translate messages from Layer 2 to an accelerated Layer 1 in a communication network, according to at least one embodiment;

FIG. 5 is a block diagram illustrating an accelerator interface to facilitate communication between Layer 2 and accelerated Layer 1 operations using one or more parallel processing units, according to at least one embodiment;

FIG. 6 illustrates a process for uplink communication using a Layer 2 adapter and accelerated Layer 1 operations, according to at least one embodiment;

FIG. 7 illustrates a process for downlink communication using a Layer 2 adapter and accelerated Layer 1 operations, according to at least one embodiment;

FIG. 8 illustrates an example data center system, according to at least one embodiment;

FIG. 9A illustrates an example of an autonomous vehicle, according to at least one embodiment;

FIG. 9B illustrates an example of camera locations and fields of view for the autonomous vehicle of FIG. 9A , according to at least one embodiment;

FIG. 9C is a block diagram illustrating an example system architecture for the autonomous vehicle of FIG. 9A , according to at least one embodiment;

FIG. 9D is a diagram illustrating a system for communication between cloud-based server(s) and the autonomous vehicle of FIG. 9A , according to at least one embodiment;

FIG. 10 is a block diagram illustrating a computer system, according to at least one embodiment;

FIG. 11 is a block diagram illustrating computer system, according to at least one embodiment;

FIG. 12 illustrates a computer system, according to at least one embodiment;

FIG. 13 illustrates a computer system, according at least one embodiment;

FIG. 14A illustrates a computer system, according to at least one embodiment;

FIG. 14B illustrates a computer system, according to at least one embodiment;

FIG. 14C illustrates a computer system, according to at least one embodiment;

FIG. 14D illustrates a computer system, according to at least one embodiment;

FIGS. 14E and 14F illustrate a shared programming model, according to at least one embodiment;

FIG. 15 illustrates exemplary integrated circuits and associated graphics processors, according to at least one embodiment;

FIGS. 16A and 16B illustrate exemplary integrated circuits and associated graphics processors, according to at least one embodiment;

FIGS. 17A and 17B illustrate additional exemplary graphics processor logic according to at least one embodiment;

FIG. 18 illustrates a computer system, according to at least one embodiment;

FIG. 19A illustrates a parallel processor, according to at least one embodiment;

FIG. 19B illustrates a partition unit, according to at least one embodiment;

FIG. 19C illustrates a processing cluster, according to at least one embodiment;

FIG. 19D illustrates a graphics multiprocessor, according to at least one embodiment;

FIG. 20 illustrates a multi-graphics processing unit (GPU) system, according to at least one embodiment;

FIG. 21 illustrates a graphics processor, according to at least one embodiment;

FIG. 22 is a block diagram illustrating a processor micro-architecture for a processor, according to at least one embodiment;

FIG. 23 illustrates at least portions of a graphics processor, according to one or more embodiments;

FIG. 24 illustrates at least portions of a graphics processor, according to one or more embodiments;

FIG. 25 illustrates at least portions of a graphics processor, according to one or more embodiments;

FIG. 26 is a block diagram of a graphics processing engine of a graphics processor in accordance with at least one embodiment;

FIG. 27 is a block diagram of at least portions of a graphics processor core, according to at least one embodiment;

FIGS. 28A and 28B illustrate thread execution logic including an array of processing elements of a graphics processor core according to at least one embodiment;

FIG. 29 illustrates a parallel processing unit (“PPU”), according to at least one embodiment;

FIG. 30 illustrates a general processing cluster (“GPC”), according to at least one embodiment;

FIG. 31 illustrates a memory partition unit of a parallel processing unit (“PPU”), according to at least one embodiment;

FIG. 32 illustrates a streaming multi-processor, according to at least one embodiment;

FIG. 33 illustrates a network for communicating data within a 5G wireless communications network, according to at least one embodiment;

FIG. 34 illustrates a network architecture for a 5G-NR wireless network, according to at least one embodiment;

FIG. 35 is a diagram illustrating some basic functionality of a mobile telecommunications network/system operating in accordance with LTE and 5G principles, according to at least one embodiment;

FIG. 36 illustrates a radio access network which may be part of a 5G network architecture, according to at least one embodiment;

FIG. 37 provides an example illustration of a 5G mobile communications system in which a plurality of different types of devices is used, according to at least one embodiment;

FIG. 38 illustrates an example high level system, according to at least one embodiment;

FIG. 39 illustrates an architecture of a system of a network, according to at least one embodiment;

FIG. 40 illustrates example components of a device, according to at least one embodiment;

FIG. 41 illustrates example interfaces of baseband circuitry, according to at least one embodiment;

FIG. 42 illustrates an example of downlink and uplink channels, according to at least one embodiment;

FIG. 43 illustrates an architecture of a system of a network, according to at least one embodiment;

FIG. 44 illustrates a control plane protocol stack, according to at least o

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation-by-pass of PCT International Patent Application No. PCT/CN2020/128456, filed Nov. 12, 2020, entitled “INTRA-LAYER ADAPTER FOR FIFTH GENERATION NEW RADIO (5G-NR) COMMUNICATIONS,” the disclosure of which is incorporated herein by reference in its entirety.

FIELD

At least one embodiment pertains to processing resources used to facilitate Fifth Generation (5G) communication. For example, at least one embodiment, pertains to processors or computing systems used to provide a uniform interface between Layer 1 and Layer 2 components of a 5G communication network, according to various novel techniques described herein.

BACKGROUND

Communication networks, particularly with respect to Fifth Generation (5G) communications, are moving toward disaggregated architectures. Instead of having a monolithic, single-vendor structure, components of base station networks are increasingly provided by different vendors. However, these base station network components must communicate between multiple vendor interfaces. As a result, network equipment providers face significant challenges in interconnecting components from different vendors for various layers in a 5G communication network.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a vendor- specific Layer 2 to Layer 1 interface in a communication network, according to at least one embodiment;

FIG. 2 is a block diagram illustrating a Layer 2 adapter to facilitate communication between Layer 2 and Layer 1 in a communication network, according to at least one embodiment;

FIG. 3 is a block diagram illustrating an interface between one or more vendor- specific Layer 2 interfaces and uniform Layer 1 using a Layer 2 adapter in a communication network, according to at least one embodiment;

FIG. 4 is a block diagram illustrating a Layer 2 adapter to translate messages from Layer 2 to an accelerated Layer 1 in a communication network, according to at least one embodiment;

FIG. 5 is a block diagram illustrating an accelerator interface to facilitate communication between Layer 2 and accelerated Layer 1 operations using one or more parallel processing units, according to at least one embodiment;

FIG. 6 illustrates a process for uplink communication using a Layer 2 adapter and accelerated Layer 1 operations, according to at least one embodiment;

FIG. 7 illustrates a process for downlink communication using a Layer 2 adapter and accelerated Layer 1 operations, according to at least one embodiment;

FIG. 8 illustrates an example data center system, according to at least one embodiment;

FIG. 9A illustrates an example of an autonomous vehicle, according to at least one embodiment;

FIG. 9B illustrates an example of camera locations and fields of view for the autonomous vehicle of FIG. 9A , according to at least one embodiment;

FIG. 9C is a block diagram illustrating an example system architecture for the autonomous vehicle of FIG. 9A , according to at least one embodiment;

FIG. 9D is a diagram illustrating a system for communication between cloud-based server(s) and the autonomous vehicle of FIG. 9A , according to at least one embodiment;

FIG. 10 is a block diagram illustrating a computer system, according to at least one embodiment;

FIG. 11 is a block diagram illustrating computer system, according to at least one embodiment;

FIG. 12 illustrates a computer system, according to at least one embodiment;

FIG. 13 illustrates a computer system, according at least one embodiment;

FIG. 14A illustrates a computer system, according to at least one embodiment;

FIG. 14B illustrates a computer system, according to at least one embodiment;

FIG. 14C illustrates a computer system, according to at least one embodiment;

FIG. 14D illustrates a computer system, according to at least one embodiment;

FIGS. 14E and 14F illustrate a shared programming model, according to at least one embodiment;

FIG. 15 illustrates exemplary integrated circuits and associated graphics processors, according to at least one embodiment;

FIGS. 16A and 16B illustrate exemplary integrated circuits and associated graphics processors, according to at least one embodiment;

FIGS. 17A and 17B illustrate additional exemplary graphics processor logic according to at least one embodiment;

FIG. 18 illustrates a computer system, according to at least one embodiment;

FIG. 19A illustrates a parallel processor, according to at least one embodiment;

FIG. 19B illustrates a partition unit, according to at least one embodiment;

FIG. 19C illustrates a processing cluster, according to at least one embodiment;

FIG. 19D illustrates a graphics multiprocessor, according to at least one embodiment;

FIG. 20 illustrates a multi-graphics processing unit (GPU) system, according to at least one embodiment;

FIG. 21 illustrates a graphics processor, according to at least one embodiment;

FIG. 22 is a block diagram illustrating a processor micro-architecture for a processor, according to at least one embodiment;

FIG. 23 illustrates at least portions of a graphics processor, according to one or more embodiments;

FIG. 24 illustrates at least portions of a graphics processor, according to one or more embodiments;

FIG. 25 illustrates at least portions of a graphics processor, according to one or more embodiments;

FIG. 26 is a block diagram of a graphics processing engine of a graphics processor in accordance with at least one embodiment;

FIG. 27 is a block diagram of at least portions of a graphics processor core, according to at least one embodiment;

FIGS. 28A and 28B illustrate thread execution logic including an array of processing elements of a graphics processor core according to at least one embodiment;

FIG. 29 illustrates a parallel processing unit (“PPU”), according to at least one embodiment;

FIG. 30 illustrates a general processing cluster (“GPC”), according to at least one embodiment;

FIG. 31 illustrates a memory partition unit of a parallel processing unit (“PPU”), according to at least one embodiment;

FIG. 32 illustrates a streaming multi-processor, according to at least one embodiment;

FIG. 33 illustrates a network for communicating data within a 5G wireless communications network, according to at least one embodiment;

FIG. 34 illustrates a network architecture for a 5G-NR wireless network, according to at least one embodiment;

FIG. 35 is a diagram illustrating some basic functionality of a mobile telecommunications network/system operating in accordance with LTE and 5G principles, according to at least one embodiment;

FIG. 36 illustrates a radio access network which may be part of a 5G network architecture, according to at least one embodiment;

FIG. 37 provides an example illustration of a 5G mobile communications system in which a plurality of different types of devices is used, according to at least one embodiment;

FIG. 38 illustrates an example high level system, according to at least one embodiment;

FIG. 39 illustrates an architecture of a system of a network, according to at least one embodiment;

FIG. 40 illustrates example components of a device, according to at least one embodiment;

FIG. 41 illustrates example interfaces of baseband circuitry, according to at least one embodiment;

FIG. 42 illustrates an example of downlink and uplink channels, according to at least one embodiment;

FIG. 43 illustrates an architecture of a system of a network, according to at least one embodiment;

FIG. 44 illustrates a control plane protocol stack, according to at least one embodiment;

FIG. 45 illustrates a user plane protocol stack, according to at least one embodiment;

FIG. 46 illustrates components of a core network, according to at least one embodiment; and

FIG. 47 illustrates components of a system to support network function virtualization (NFV), according to at least one embodiment.

DETAILED DESCRIPTION

FIG. 1 is a block diagram illustrating a vendor- specific Layer 2 104 to Layer 1 110 interface in a communication network, according to at least one embodiment. In at least one embodiment, a Fifth Generation (5G) New Radio (NR) communication network comprises a 5G Protocol stack to facilitate communication. A 5G Protocol Stack, in an embodiment, comprises at least a Layer 1 (L1) 110 , Layer 2 (L2) 104 , and Layer 3 (L3). In at least one embodiment, L1 110 , L2 104 , and L3 are hardware components and/or software instructions that, when executed, perform 5G-NR communication network operations, further described herein. In at least one embodiment, L1 110 , L2 104 , and L3 are logical groupings of operations performed in a 5G-NR communication network. In at least one embodiment, L1 110 , L2 104 , and L3 are physically separate hardware and software components of a 5G-NR communication network. In at least one embodiment, L1 110 , L2 104 , and L3 are hosted by one or more computing systems of a 5G communication network. In at least one embodiment, L1 110 , L2 104 , and L3 interact over a communication interface, such as shared memory, network communication, a hardware bus, or any other communication medium further described herein. In at least one embodiment, L2 104 is referred to as a Medium Access Control (MAC) sublayer (L2/MAC) 104 of a 5G Protocol Stack. In at least one embodiment, L1 110 is referred to as a Physical (PHY) Layer (L1/PHY) 110 of a 5G Protocol Stack.

In at least one embodiment, L2/ MAC 104 communicates with L1/ PHY 110 in a 5G-NR communication network over a communication interface 108 . In at least one embodiment, L2/ MAC 104 is hardware components and/or software instructions that, when executed, conduct specific Layer 2 or MAC sublayer operations in a 5G-NR communication network. In at least one embodiment, L1/PHY @ 101 is hardware components and/or software instructions that, when executed, conduct specific Layer 1 or PHY Layer operations in a 5G-NR communication network. In at least one embodiment, Layer 2 or MAC operations comprise beam management operations, random access procedures, mapping operations between logical communication channels and physical communication channels, concatenation of data into blocks, multiplexing and/or de-multiplexing, reporting, error correction, prioritization of data, and data padding. Layer 2 or MAC operations, in an embodiment, comprise any other Layer 2 or MAC operation further described herein. In at least one embodiment, Layer 1 or PHY operations comprise error detection and indication of errors, encoding and/or decoding of communication channels, code segmentation, rate matching, concatenation of data blocks, scrambling, modulation, layer mapping, antenna processing, beamforming, and radio frequency (RF) processing. Layer 1 or PHY operations comprise, in an embodiment, any other Layer 1 or PHY operation further described herein.

In at least one embodiment, L2/ MAC 104 has a specific implementation corresponding to a specific vendor 102 . In at least one embodiment, a specific implementation for a vendor 102 performs a class of shared operations with other operations, but using different underlying implementation structure and using differently-configured interfaces and data types. In at least one embodiment, an implementation is a configuration or way of formatting data and/or communications with other layers, such as L1/ PHY 110 . In at least one embodiment, an implementation corresponds to one or more vendors 102 and/or is provided by or associated with a specific vendor 102 . In at least one embodiment, a vendor 102 is an entity that designs or develops one or more L2/ MAC 104 components of a 5G-NR communication network. In at least one embodiment, an L2/ MAC 104 associated with or provided by a vendor 104 in a 5G-NR communication network interfaces 108 with L1/ PHY 110 using a vendor- specific interface 106 . In at least one embodiment, a vendor- specific interface 106 is hardware components and/or software instructions that, when executed, generate and/or receive L2 messages to be communicated to or received from L1/ PHY 110 . In at least one embodiment, a vendor-specific interface generates and receives L2 messages in a format specific to a vendor 102 . In at least one embodiment, L2 messages conform to or utilize a functional application programming interface (FAPI), such as O-RAN FAPI, SCF 5G FAPI, 5G-nFAPI, or any other FAPI. In at least one embodiment, L2 messages are non-FAPI messages and conform to or use a vendor-specific format.

In at least one embodiment, a vendor-specific 102 L2/ MAC 104 communicates using a vendor- specific interface 106 with L1/ PHY 110 using a communication interface 108 . In at least one embodiment, a communication interface 108 is hardware components and/or software instructions to facilitate interaction between two or more components of a 5G-NR communication network. In at least one embodiment, a communication interface 108 is shared memory. A communication interface 108 is, in an embodiment, central processing unit (CPU) shared memory. In at least one embodiment, a communication interface is parallel processing unit (PPU) shared memory, such as graphics processing unit (GPU) shared memory. In at least one embodiment, a communication interface 108 facilitates User Datagram Protocol (UDP) communication. In at least one embodiment, a communication interface 108 facilitates or utilizes any other type of communication technique further described herein.

In at least one embodiment, a vendor-specific 102 L2/ MAC 104 communicates over a communication interface 108 by transmitting and receiving vendor-specific L2 messages generated by or received by a vendor- specific interface 106 . In order to communicate with a vendor-specific 102 L2/ MAC 104 , L1/ PHY 110 utilizes a vendor- specific PHY driver 112 . In at least one embodiment, a vendor- specific PHY driver 112 is data values and software instructions that, when executed, receive, transmit and process L2 messages to/from a vendor-specific 102 L2/ MAC 104 . In at least one embodiment, a vendor- specific PHY driver 112 provides an interface with PHY operations or resources provided or performed by L1/ PHY 110 . In at least one embodiment, a vendor- specific PHY driver 112 receives L1 messages or slot commands. In at least one embodiment, vendor-specific L1 messages or slot commands conform to vendor-specific L2 messages generated and received by a vendor- specific interface 106 . In at least one embodiment, a different vendor- specific PHY driver 112 is needed for each vendor 102 providing L2/ MAC 104 in a 5G-NR communication network. In at least one embodiment, a uniform PHY driver is used when an L2 adapter is provided in L1/PHY, as described below in conjunction with FIGS. 2 and 3 . In at least one embodiment, a vendor- specific PHY driver 112 is a PHY driver associated with an application programming interface to perform parallel computing, such as CUDA. In at least one embodiment, a vendor- specific PHY driver 112 is cuPHYDriver or any other PHY driver further described herein.

In at least one embodiment, a PHY driver, such as a vendor- specific PHY driver 112 , provides an interface between messages received by said PHY driver from L2/ MAC 104 and L1/ PHY 110 resources. In at least one embodiment, a PHY driver, such as a vendor- specific PHY driver 112 , facilitates operations performed by L1/ PHY 110 resources according to L2 messages received from a vendor-specific 102 L2/ MAC 104 . In at least one embodiment, L1/ PHY 110 comprises virtual network functions 114 . In at least one embodiment, virtual network functions 114 are data values and software instructions that, when executed, provide virtualized network services. In at least one embodiment, virtualized network services are software functions implementing network functionality that are abstracted away from specific network hardware, such as a Network Interface Controller (NIC) 120 . In at least one embodiment, a NIC 120 is hardware components and/or software instructions that facilitate and perform network communication, such as local area network (LAN) communication or any other network communication as further described herein. In at least one embodiment, virtual network functions 114 are any other network operation provided or performed by L1/ PHY 110 further described herein. In at least one embodiment, virtual network functions 114 are associated with a parallel computing API 216 , such as cuVNF in association with CUDA. In at least one embodiment, virtual network functions 114 , such as cuVNF, send 5G messages and/or data directly to parallel processing unit (PPU) memory from one or more NICs 120 , as further described herein.

In at least one embodiment, L1/ PHY 110 comprises signal processing libraries 116 . In at least one embodiment, signal processing libraries 116 are data values and software instructions that, when used or executed, perform software-based 5G-NR PHY operations, as described above. In at least one embodiment, signal processing libraries 116 implement functions to perform error detection and/or correction. Signal processing libraries 116 , in an embodiment, implement functions to perform encoding and decoding of communication channel data. In at least one embodiment, signal processing libraries 116 implement functions to perform mapping of coded communication channels onto physical communication channels. In at least one embodiment, signal processing libraries 116 implement functions to perform software aspects of rate matching, scrambling, modulation, and beamforming. In at least one embodiment, signal processing libraries 116 implement functions to perform any other operation performed by a PHY layer of a 5G-NR communication network, as further described herein.

In at least one embodiment, one or more functions implemented by signal processing libraries 116 utilize virtual network functions 114 . In at least one embodiment, one or more functions implemented by signal processing libraries 116 are performed by a central processing unit (CPU) 122 , as further described herein. In at least one embodiment, one or more functions implemented by signal processing libraries 116 utilize a parallel computing API 118 to be performed or executed using one or more parallel processing units (PPUs) 124 , such as graphics processing units (GPUs), as further described herein. In at least one embodiment, signal processing libraries 116 are specific to a parallel computing API 118 , such as cuPHY or any other signal processing libraries 116 further described herein. In at least one embodiment, signal processing libraries 116 such as cuPHY provide a fully- or partially-offloaded 5G-NR signal processing pipeline performable by one or more PPUs 124 , such as GPUs, as further described herein.

In at least one embodiment, a parallel computing API 118 is data values and software instructions that, when executed, provide an application programming interface to facilitate or perform parallel computing using one or more PPUs 124 , such as CUDA. In at least one embodiment, a parallel computing API 118 , such as CUDA, facilitates performance of one or more functions implemented by signal processing libraries 116 to be performed fully or partially using one or more PPUs, such as GPUs, as further described below in conjunction with FIGS. 4 and 5 . In at least one embodiment, a vendor- specific PHY driver 112 utilizes a parallel computing API 118 to invoke one or more functions implemented by signal processing libraries 116 to be performed using one or more PPUs, such as GPUs, as further described herein.

FIG. 2 is a block diagram illustrating a Layer 2 adapter 204 to facilitate communication between L2 and Layer 1 202 in a communication network, according to at least one embodiment. In at least one embodiment, Layer 1 (L1/PHY) 202 comprises software and hardware resources such as virtual network functions 212 , signal processing libraries 214 , a parallel computing API 206 such as CUDA, one or more Network Interface Controllers (NICs) 218 , a central processing unit (CPU) 220 , and one or more parallel processing units (PPUs) 222 , such as graphics processing units (GPUs), as described above in conjunction with FIG. 1 and further described herein. In at least one embodiment, L1/ PHY 202 receives messages or other data, such as API calls, from Layer 2 (L2/MAC) in a Fifth Generation (5G) New Radio (NR) communication network. As described above, messages or other data received from L2/MAC are structured in a format corresponding to an individual vendor, in an embodiment. In at least one embodiment, multiple vendors are utilized to implement L2/MAC components of a 5G-NR communication network, and messages or other data received from each vendor-specific L2/MAC have a plurality of formats.

In at least one embodiment, rather than comprising a vendor-specific PHY driver for each vendor providing L2/MAC in a 5G-NR communication network, L1/ PHY 202 comprises a uniform PHY driver 210 in conjunction with a PHY- L2 Adapter 204 , also referred to as L2 Adapter. In at least one embodiment, a uniform PHY driver 210 is data values and software instructions that, when executed, manage use of L1/ PHY 202 resources, as described above, using a single interface regardless of what vendor provides a L2/MAC implementation. In at least one embodiment, a uniform PHY driver 210 provides an application programming interface (L1/PHY API) 206 . In at least one embodiment, an L1/ PHY API 206 is data values and software instructions that, when executed, provide one or more functions to facilitate communication between a uniform PHY driver 210 and a PHY- L2 adapter 204 . In at least one embodiment, a uniform PHY driver 210 provides callbacks 208 to a PHY- L2 adapter 204 . In at least one embodiment, callbacks 208 are asynchronous messages indicating results of L1/ PHY API 206 operations performed or facilitated by a uniform PHY driver 210 .

In at least one embodiment, in order to enable communication between a uniform PHY driver 210 and one or more vendor-specific L2/MAC components of a 5G-NR communication network, L1/PHY comprises an L2 adapter or PHY- L2 adapter 204 . In at least one embodiment, a PHY- L2 adapter 204 is data values and software instructions that, when executed, translate or otherwise facilitate communication between uniform PHY driver 210 and one or more vendor-specific L2/MAC components of a 5G-NR communication network. In at least one embodiment, a PHY- L2 adapter 204 is an interface between a uniform PHY driver 210 and one or more vendor-specific L2/MAC components of a 5G-NR communication network. In at least one embodiment, a PHY- L2 adapter 204 is a peripheral component of L1/ PHY 202 . In at least one embodiment, a PHY- L2 adapter 204 interfaces with one or more L2/MAC vendors utilized in a 5G-NR communication network.

In at least one embodiment, a PHY- L2 adapter 204 translates communication between a uniform PHY driver 210 and one or more vendor-specific L2/MAC components of a 5G-NR communication network by converting one or more data values from a format supported by said one or more vendor-specific L2/MAC components to a format supported by L1/ PHY 202 . In at least one embodiment, a PHY- L2 adapter 204 translates communication between a uniform PHY driver 210 and one or more vendor-specific L2/MAC components of a 5G-NR communication network by converting one or more function, interface, or API calls from a format supported by said one or more vendor-specific L2/MAC components to a format supported by L1/ PHY 202 . In at least one embodiment, a PHY- L2 adapter 204 performs translation through the use of a lookup table. In at least one embodiment, a PHY-<figure-callout id="204" label="L2

CLAIMS

Claims ( 30 )

What is claimed is:

1 . A processor comprising:

one or more circuits to cause data to be communicated between one or more physical (PHY) Fifth Generation New Radio (5G-NR) network layers corresponding to one or more first vendors and one or more medium access control (MAC) 5G-NR network layers corresponding to one or more second vendors using a first interface.

2 . The processor of claim 1 , further comprising:

a PHY 5G-NR driver to provide an application programming interface to the first interface; one or more signal processing libraries accessible through the application programming interface; and one or more parallel processing units accessible through the application programming interface.

3 . The processor of claim 2 , wherein the first interface translates the data communicated by the one or more MAC 5G-NR network layers and provides the data to the PHY 5G-NR driver through the application programming interface.

4 . The processor of claim 1 , wherein the one or more MAC 5G-NR network layers corresponding to the one or more second vendors use the first interface to communicate data to one or more functions provided by one or more signal processing libraries to be performed by one or more parallel processing units.

5 . The processor of claim 1 , wherein the one or more PHY 5G-NR network layers comprise an application programming interface to perform parallel computing accessible through the first interface.

6 . The processor of claim 1 , wherein the one or more PHY 5G-NR network layers comprise one or more signal processing libraries implementing operations to be performed by one or more parallel processing units, the operations invoked using the first interface.

7 . The processor of claim 1 , wherein the one or more PHY 5G-NR network layers comprise a second interface to access one or more parallel processing units, the second interface usable by the first interface to communicate the data from the one or more MAC 5G-NR network layers to the one or more parallel processing units.

8 . The processor of claim 7 , wherein the first interface indicates one or more signal processing operations to be performed by the one or more parallel processing units using the second interface.

9 . A system comprising:

one or more processors to cause data to be communicated between one or more physical (PHY) Fifth Generation New Radio (5G-NR) network layers corresponding to one or more first vendors and one or more medium access control (MAC) 5G-NR network layers corresponding to one or more second vendors using a first interface.

10 . The system of claim 9 , wherein the first interface translates the data to be communicated between the one or more PHY 5G-NR network layers and the one or more MAC 5G-NR network layers.

11 . The system of claim 9 , wherein:

the one or more PHY 5G-NR network layers comprise a driver to access one or more signal processing libraries; the driver provides an application programming interface; and the first interface translates the data to be communicated based, at least in part, on the signal processing libraries accessible by the application programming interface.

12 . The system of claim 9 , wherein the one or more PHY 5G-NR network layers comprise one or more signal processing libraries and the first interface determines one or more operations of the one or more signal processing libraries to be performed by one or more parallel processing units based, at least in part, on the data to be communicated.

13 . The system of claim 9 , wherein the one or more PHY 5G-NR network layers comprise a second interface to access one or more parallel processing units, and the first interface accesses the one or more parallel processing units through the second interface.

14 . The system of claim 9 , wherein the one or more PHY 5G-NR network layers comprise a second interface, and the first interface indicates one or more signal processing functions to be performed by one or more parallel processing units using the second interface.

15 . The system of claim 9 , wherein:

each of the one or more MAC 5G-NR network layers corresponding to the one or more second vendors comprise one or more second interfaces; each of the one or more PHY 5G-NR network layers comprise one or more third interfaces; and the first interface translates the data to be communicated from the one or more second interfaces to the one or more third interfaces.

16 . The system of claim 9 , wherein:

each of the one or more PHY 5G-NR network layers comprise one or more second interfaces; each of the one or more MAC 5G-NR network layers corresponding to the one or more second vendors comprise one or more third interfaces; and the first interface translates the data to be communicated from the one or more second interfaces to the one or more third interfaces.

17 . A machine-readable medium having stored thereon a set of instructions, which if performed by one or more processors, cause the one or more processors to at least:

communicate data between one or more physical (PHY) Fifth Generation New Radio (5G-NR) network layers corresponding to one or more first vendors and one or more medium access control (MAC) 5G-NR network layers corresponding to one or more second vendors using a first interface.

18 . The machine-readable medium of claim 17 , wherein the set of instructions further comprises instructions that, if performed by the one or more processors, further cause the one or more processors to:

determine one or more signal processing operations corresponding to the one or more PHY 5G-NR network layers to be performed by one or more parallel processing units; communicate the data using the first interface to a second interface, the second interface corresponding to the one or more parallel processing units; and perform the one or more signal processing operations on the data using the one or more parallel processing units.

19 . The machine-readable medium of claim 18 , wherein the one or more MAC 5G-NR network layers comprise one or more third interfaces associated with each of the one or more second vendors, and the first interface translates the data to be communicated from the one or more third interfaces to the second interface.

20 . The machine-readable medium of claim 17 , wherein the one or more PHY 5G-NR network layers comprise a second interface to access one or more parallel processing units usable by the one or more PHY 5G-NR network layers, and the first interface uses the second interface to communicate the data from the one or more MAC 5G-NR network layers to the one or more parallel processing units.

21 . The machine-readable medium of claim 17 , wherein the one or more PHY 5G-NR network layers comprise an application programming interface to perform parallel computing accessible through the first interface.

22 . The machine-readable medium of claim 17 , wherein the set of instructions further comprises instructions that, if performed by the one or more processors, further cause the one or more processors to:

translate, using the first interface, the data to be communicated from one or more second interfaces for each of the one or more MAC 5G-NR network layers corresponding to the one or more second vendors to a third interface corresponding to the one or more PHY 5G-NR network layers.

23 . The machine-readable medium of claim 17 , wherein the set of instructions further comprises instructions that, if performed by the one or more processors, further cause the one or more processors to:

translate, using the first interface, the data to be communicated from a second interface corresponding to the one or more PHY 5G-NR network layers to one or more third interfaces for each of the one or more MAC 5G-NR network layers corresponding to the one or more second vendors.

24 . A method comprising:

communicating data between one or more physical (PHY) Fifth Generation New Radio (5G-NR) network layers corresponding to one or more first vendors and one or more medium access control (MAC) 5G-NR network layers corresponding to one or more second vendors using a first interface.

25 . The method of claim 24 , further comprising:

receiving, by the first interface, the data; determining, by the first interface, one or more tasks to be performed by one or more parallel processing units corresponding to a second interface of the one or more PHY 5G-NR network layers; instructing, by the first interface through the second interface, the one or more parallel processing units to perform the one or more tasks; receiving, by the first interface, a request for results corresponding to the one or more tasks; and transmitting, by the second interface to the first interface, the results corresponding to the one or more tasks.

26 . The method of claim 25 , wherein the second interface comprises an application programming interface to facilitate interaction with the one or more parallel processing units.

27 . The method of claim 24 , wherein the PHY 5G-NR network layers comprise a second interface to facilitate interaction between the first interface and one or more parallel processing units usable to perform one or more signal processing operations corresponding to the PHY 5G-NR network layers.

28 . The method of claim 24 , wherein the PHY 5G-NR network layers comprise an application programming interface to perform parallel computing operations, and the first interface communicates the data based, at least in part, on the application programming interface.

29 . The method of claim 24 , further comprising:

translating, by the first interface, the data received from one or more second interfaces for each of the one or more MAC 5G-NR network layers corresponding to the one or more second vendors to a third interface corresponding to the one or more PHY 5G-NR network layers.

30 . The method of claim 24 , further comprising:

translating, by the first interface, the data received from a second interface corresponding to the one or more PHY 5G-NR network layers to one or more third interfaces for each of the one or more MAC 5G-NR network layers corresponding to the one or more second vendors.

US17/129,473

2020-11-12

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Intra-layer adapter for fifth generation new radio (5g-nr) communications

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