This work has been submitted to the ACM for possible publication. Copyright may be transferred without notice, after which this version may no longer be accessible.
ARCHES: Adaptive Real-Time Switching of AI Models for the RAN Neagin Neasamoni Santhi★, Davide Villa★‡ , Michele Polese★, Salvatore D’Oro★, Yunseong Lee† , Koichiro Furueda† , Tommaso Melodia★ ★Institute for Intelligent Network Systems, Northeastern University, Boston, MA, U.S.A.
arXiv:2604.23397v1 [cs.NI] 25 Apr 2026
{neasamonisanthi.n, villa.d, m.polese, s.doro, t.melodia}@northeastern.edu † Technology Unit, SoftBank Corp., Tokyo, Japan [email protected], [email protected] ‡ NVIDIA Corporation, Santa Clara, CA, U.S.A. [email protected]
Abstract
CCS Concepts
Artificial Intelligence (AI) has become a powerful tool for modelfree Radio Access Network (RAN) signal processing and optimization. However, it is challenging to design and train a single model that generalizes reliably across all radio environments. Specialized AI models often outperform conventional algorithms only under specific channel conditions, while their substantially higher compute and energy cost makes unconditional execution impractical at the base station. This creates a need for real-time expert switching: dynamically activating the most appropriate AI or conventional signal-processing expert based on current network conditions. To address this, we propose ARCHES (Adaptive Real-time CUDA Hot-swapping of Experts in the RAN Stack), a framework that hosts multiple AI-based and conventional signal processing experts within a Graphics Processing Unit (GPU)-accelerated Physical (PHY) pipeline and dynamically selects the most appropriate expert at slot-boundary granularity, without dropping or corrupting inflight data. ARCHES includes a lightweight Compute Unified Device Architecture (CUDA) switch kernel for zero-gap output selection, a dApp-based control plane that collects cross-layer telemetry and drives the switching policy, and a reusable process for telemetry selection and policy design based on controlled perturbation, monotonicity filtering, and hierarchical clustering. We validate ARCHES on uplink (UL) channel estimation, switching between an AI-based and a Minimum Mean Square Error (MMSE) estimator in response to changing propagation and interference conditions. The prototype, implemented on the X5G platform with NVIDIA Aerial and OpenAirInterface (OAI), demonstrates median UL PHY throughput gains of 5.32% and 7.23% under good and poor conditions, respectively, with an end-to-end control-loop latency of ≈140 𝜇s and sub-microsecond decision inference. Under good conditions, defaulting to MMSE saves 15.8 W of GPU power (9.6%) and 17 percentage points of GPU utilization versus unconditional AI execution, validating the performance-per-watt tradeoff that motivates adaptive expert selection.
• Networks → Network performance analysis.
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]. MobiHoc ’26, Tokyo, Japan © 2026 Copyright held by the owner/author(s). Publication rights licensed to ACM. ACM ISBN 978-1-4503-XXXX-X/18/06 https://doi.org/XXXXXXX.XXXXXXX
Keywords O-RAN, dApp, real-time expert switching, 5G NR, GPU-accelerated PHY, AI/ML, AI-RAN, channel estimation, mixture of experts
1
Introduction
Artificial Intelligence (AI)-based techniques have demonstrated significant potential across a range of Physical (PHY) and Radio Access Network (RAN) functions in 5G and beyond [1, 2]. In channel estimation, neural-network-based approaches can capture complex propagation characteristics that traditional linear estimators struggle to model [3, 4]. In beam management, AI enables faster and more accurate beam prediction, reducing overhead from exhaustive beam sweeps [5]. In positioning, learning-based methods improve localization accuracy by exploiting spatial features of the radio environment beyond conventional geometry-based approaches [6]. In resource allocation and scheduling, AI-driven strategies can adapt to dynamic traffic patterns and interference conditions more effectively than rule-based heuristics [7]. A common requirement across all of these functions is real-time processing under strict latency constraints, as they operate within the tight timing budgets of the PHY and Medium Access Control (MAC) layers. Such constraints demand lightweight models capable of fast inference, but their limited capacity often prevents them from generalizing across diverse channel conditions, spanning indoor and outdoor environments, pedestrian versus vehicular mobility, rural and urban deployments, and small and large cells. As a result, they tend to be specialized to a subset of conditions, where they can outperform traditional approaches, but may fail when operating outside their area of expertise [8, 9]. Crucially, even when an AI model outperforms its conventional counterpart across all observed conditions, operational considerations may still favor selective activation. Our measurements on a production Graphics Processing Unit (GPU)-accelerated Next Generation Node Base (gNB) show that an AI-based channel estimator draws 15.8 W more GPU power and consumes 17 percentage points more GPU utilization than its conventional counterpart under favorable conditions, for a throughput gain of only ∼5%. At scale, with dozens of cells and multiple User Equipments (UEs) per cell, unconditional AI execution becomes impractical: the compute and energy cost per marginal bit of throughput does not justify alwayson inference. As AI components proliferate across the RAN, this
MobiHoc ’26, Nov 23–26, 2026, Tokyo, Japan
N. Neasamoni Santhi, D. Villa, M. Polese, S. D’Oro, Y. Lee, K. Furueda, T. Melodia
performance-per-watt tradeoff will force operators to selectively activate AI experts only when the performance benefit warrants the additional resource expenditure. A common approach to address this lack of generalization is the Mixture-of-Experts (MoE) paradigm [10, 11], in which multiple specialized models are maintained simultaneously and incoming inputs are routed to the most suitable expert based on current channel conditions. While classical MoE routes inputs among subnetworks within a single model, in this paper we extend the concept to switching between independent signal processing modules in a live pipeline. However, applying this idea to real-time signal processing functions in the RAN introduces additional challenges. The routing decision itself must be made under strict latency constraints, requiring the system to detect changing conditions and switch between experts at PHY-timescale using inputs from different parts of the protocol stack and processing pipeline. Beyond decision latency, switching must occur seamlessly within a live processing pipeline without dropping or corrupting in-flight data, since each uplink (UL) slot carries irreplaceable user traffic that cannot be buffered or replayed. Furthermore, the decision must be informed by crosslayer metrics spanning PHY, MAC, and higher layers, requiring tightly coordinated telemetry collection across disaggregated RAN components operating on different timescales. Motivated by this, we propose ARCHES (Adaptive Real-time CUDA Hot-swapping of Experts in the RAN Stack), a generalpurpose framework for real-time expert switching inside GPUaccelerated 5G PHY pipelines. ARCHES enables the simultaneous operation of multiple AI-based and conventional signal processing experts and dynamically selects the most appropriate one based on current network conditions, without disrupting data flow or introducing processing gaps. The framework continuously monitors live RAN metrics through a dApp-based control plane, evaluates prevailing network conditions using a lightweight policy, and selects the most suitable expert at slot boundaries.
dApp Switching Logic
Cross-Layer KPMs
Expert Selection
gNB
Switchable Expert Bank
PUSCH I/Q
Expert1
…..
UE
ExpertN
" !"#$%& H !
...…
Expert2
Eq
PUSCH Pipeline
Figure 1: High-level system architecture of ARCHES. Multiple signal processing experts execute within the PHY pipeline. A dApp collects cross-layer KPMs and drives the switching logic, which selects the appropriate expert output. Shown here for channel estimation; the same architecture applies to other PHY functions. As a first instantiation, we validate ARCHES on UL channel estimation, where the framework switches between an AI-based
and a Minimum Mean Square Error (MMSE) estimator in response to changing propagation and interference conditions. Channel estimation serves only as the first validating case study; the core contribution is the switching mechanism itself. The expert bank, the Compute Unified Device Architecture (CUDA) switch kernel, the dApp-based control path, and the telemetry-driven policy design are designed to generalize to any PHY/MAC function where multiple processing strategies coexist and the optimal choice depends on current network conditions. Our main contributions are as follows: • We establish the design principles for real-time expert switching in GPU-accelerated PHY pipelines, including dual execution modes balancing switching latency and resource efficiency, memory aliasing for a uniform downstream interface, slot-boundary timing semantics, and fail-safe defaults. • We implement the ARCHES framework: a generic CUDA switch kernel and dApp-based control path with structured host-to-device propagation and E3-based telemetry collection. • We present a reusable process for selecting telemetry and switching policy design, based on controlled perturbation, monotonicity filtering, and redundancy reduction via hierarchical clustering. • We validate ARCHES through a case-study instantiation on UL channel estimation, demonstrating sub-microsecond decision latency, an end-to-end control loop of ∼140 𝜇s, throughput gains, and quantified GPU power and utilization savings via extensive Over-the-Air (OTA) experiments on the X5G platform. The remainder of the paper is organized as follows. Section 2 presents the design principles for real-time expert switching. Section 3 details the ARCHES framework. Section 4 describes the methodology for policy design. Section 5 presents the channel estimation case study. Section 6 describes the experimental evaluation. Section 7 discusses generalization to other RAN functions. Related work is reviewed in Section 8. Finally, Section 9 concludes the paper.
2
Design Principles for Real-Time Expert Switching in the RAN
Before detailing the ARCHES framework, we state the design invariants that any real-time expert-switching mechanism for GPUaccelerated PHY pipelines must satisfy. These principles are independent of the specific signal processing function being switched and emerge from the constraints of inline GPU processing at submillisecond timescales. Dual execution modes balancing latency and efficiency. ARCHES supports two execution modes. In concurrent mode, all candidate experts execute in parallel on every slot, ensuring the selected output is always readily available and eliminating cold-start penalties; this mode also enables online benchmarking by exposing all expert outputs simultaneously. In selected-only mode, only the active expert executes per slot, reducing compute and energy consumption at the cost of at least a one-slot activation delay when switching. The choice between modes reflects a deployment-specific trade-off: concurrent mode prioritizes switching responsiveness and observability, while selected-only mode prioritizes resource efficiency.
ARCHES : Adaptive Real-Time Switching of AI Models for the RAN
MobiHoc ’26, Nov 23–26, 2026, Tokyo, Japan
mode(0=AI, 1=MMSE) E3 Control Message
dApp
KPMs
Switching Logic
E3
MMSE LS
4
2c
1
Switch 2e LS
7
10
11
12
2a 2b
1 Root
6
3
2d
AI
5
NVIDIA Aerial
2e Switch kernel
2a LS for MMSE 2b LS for AI-based
KPMs E3
8
OAI L2 / L3
9 PUSCH Pipeline
3 CFO/TA estimator kernel 4 Noise/Interference estimator kernel 5 Equalizer coefficients kernel
8 RSSI kernel 9 RSRP kernel 10 LDPC decoder
2d AI-based Channel estimator
6 Fused equalizer and soft-demapper
11 CB CRCs kernel
2c MMSE Channel estimator
7 Rate de-matching kernel
12 TB CRCs kernel
Figure 2: ARCHES prototype instantiated for channel estimation, illustrating NVIDIA Aerial, OAI, and the dApp. The switch kernel (node 2e) selects between Expert A (MMSE, node 2c) and Expert B (AI-based, node 2d). The dApp collects KPMs and communicates the mode variable via the E3 interface (Section 3.3). The same kernel and control path generalize to other PHY functions. Uniform downstream interface via memory aliasing. Downstream processing stages (equalization, demapping, decoding) read from a single, fixed memory buffer. The switch kernel either performs a no-op or copies the alternative expert’s output into that buffer, depending on which expert is active. Downstream modules therefore require no modification regardless of how many experts are added. Slot-boundary timing semantics. Switching decisions take effect at slot boundaries. A decision generated during slot 𝑛 is applied at the setup phase of slot 𝑛 + 1. Because timing is deterministic, no in-flight data is corrupted mid-slot and the control loop has a well-defined, predictable latency. Fail-safe defaults. The switch defaults to the conventional (non-AI) expert at initialization and on dApp failure. The system therefore never depends on the availability of either the AI model or the dApp control plane for baseline operation. External control plane with independent policy evolution. The switching policy resides in a dApp external to the real-time pipeline. Because the policy lives outside the pipeline, it can be updated, retrained, or replaced without modifying the PHY pipeline or its CUDA graphs. The dApp communicates only a single scalar (the mode variable) to the pipeline per slot. Cross-layer telemetry as policy input. The switching decision is informed by Key Performance Measurements (KPMs) collected across multiple protocol layers, from PHY-layer channel quality metrics to MAC-layer scheduling and throughput indicators. No single metric suffices to capture the multi-dimensional trade-off between estimation quality, compute cost, and throughput gain.
3
The ARCHES Framework
This section describes the ARCHES framework, independent of the specific signal processing function being switched. ARCHES has three main components, illustrated in Figure 1: (i) a switchable expert bank integrated into the PHY pipeline, where 𝑁 experts can
execute on the same input and a CUDA switch kernel selects the designated output; (ii) an external switching logic that determines which expert best suits the operating regime; and (iii) a dApp-based control path that collects cross-layer telemetry and propagates the switching decision to the pipeline. The system architecture builds on the O-RAN disaggregated gNB model, which separates base station functionality into modular, programmable components connected via open interfaces: the Radio Unit (RU), Distributed Unit (DU), and Central Unit (CU). ARCHES is built on this architecture, where NVIDIA Aerial [12] implements high-PHY processing and OpenAirInterface (OAI) manages Layer 2 and higher layers. We use NVIDIA Aerial CUDA Baseband (cuBB), a Software Development Kit (SDK) that handles Low-DU/High-PHY signal processing for GPUs, implemented in CUDA and C++. cuBB operates with slot-level granularity, where each slot has a duration of 500 𝜇s (30 kHz subcarrier spacing). Inline GPU acceleration is what makes ARCHES possible: multiple experts run within the same pipeline, and the switching decision is applied at the output selection stage without interrupting the processing flow. Figure 2 shows the detailed prototype instantiated for channel estimation: the Physical Uplink Shared Channel (PUSCH) CUDA graph executes both experts in parallel (nodes 2c and 2d), with the switch kernel (node 2e) selecting the output, while the dApp collects KPMs from both Aerial and OAI and communicates the mode variable back to Aerial.
3.1
Switchable Expert Bank
The switchable expert bank resides within the Low-DU (High-PHY), where it replaces a single processing module with a bank of 𝑁 experts (Expert1, Expert2, . . . , Expert𝑁 ) that execute on the same input data. ARCHES supports concurrent execution of all experts for two reasons: (i) it eliminates switching latency, since the selected output is always readily available regardless of when the switch logic updates its decision, and (ii) it enables the pipeline to expose
MobiHoc ’26, Nov 23–26, 2026, Tokyo, Japan
intermediate outputs from all experts, which helps monitor online performance and benchmark the switching policy offline. Each expert produces its own output, and a CUDA switch kernel selects the designated result, forwarding it to downstream processing stages. Alternatively, ARCHES supports a selected-only execution mode in which only the active expert runs per slot, reducing compute and energy consumption at the cost of at least a one-slot activation delay when switching. In this work, we use concurrent execution to validate seamless switching and quantify expert-level tradeoffs.
3.2
CUDA Switch Kernel
The switch kernel implements the runtime selection logic on the GPU. Its behavior is controlled by a binary variable, mode, assigned during the slot setup phase. By default, mode is initialized to 1 (MMSE), ensuring fail-safe operation before the dApp issues its first decision or in case of dApp failure. To support efficient switching, separate memory locations are allocated for each expert’s output. Downstream modules consistently read from the AI-designated memory buffer. When mode=0 (AI), the kernel performs no operation, as the AI output is already in place. When mode=1, the kernel copies the MMSE output into the AI buffer using coalesced memory access. This memory layout choice means the MMSE path incurs a small copy overhead, while the AI path incurs none, a deliberate trade-off, since the AI-based estimator already dominates the latency budget and the additional copy overhead is better absorbed by the lighter MMSE path. We profile the execution times in Section 6.1.
3.3
dApp-Based Control Path
The switching logic resides in a dApp, a lightweight application deployed directly on the gNB that can access PHY/MAC telemetry and execute control actions at sub-10 ms timescales [13]. The ARCHES dApp collects relevant KPMs from both NVIDIA Aerial and OAI via the E3 interface, processes them through a switching policy, and determines the optimal expert. The selected expert is encoded in the mode variable and conveyed to the PHY pipeline to trigger the corresponding switch. We leverage the dApp framework [14] implemented in the NVIDIA Aerial stack [15]. dApps are real-time, co-located applications interfacing directly with the gNB through a structured pre-standard E3-based control and data plane. This provides low-latency access to fine-grained PHY/MAC telemetry and optional control over RAN behavior. At the interface level, the E3 Agent within the RAN exposes telemetry (e.g., channel estimates, I/Q samples, and metadata) via shared memory and lightweight indication messages, while the E3 Manager within the dApp handles setup, subscription, and data delivery to the application logic. Internally, the dApp has three main components: (i) an orchestration layer (E3 Manager), (ii) a processing layer implementing the dApp logic, and (iii) a client interface for lifecycle management. Multiple inference engines and AI backends can therefore be integrated without structural changes. At runtime, data flows from the CUDA-based L1 pipeline to pinned host memory and sharedmemory buffers, giving co-located dApps near zero-copy access while preserving isolation and real-time performance. dApp–Switch Kernel Interaction. The control path from the dApp to the GPU follows a structured sequence: Decision and signaling: The dApp encodes its expert selection into the mode variable
N. Neasamoni Santhi, D. Villa, M. Polese, S. D’Oro, Y. Lee, K. Furueda, T. Melodia
and transmits it to NVIDIA Aerial via the E3 interface. This value is made available on the host (CPU) side. Control integration: The mode parameter is incorporated into the derived UE group parameters during the setup phase of each UL slot. Host-to-device propagation: The mode parameter is copied from host memory to GPU memory together with the rest of the processing context. Kernel-level execution: On the GPU, the switch kernel reads mode and selects the corresponding expert output. Timing semantics: Mode updates take effect at slot boundaries. A value generated during slot 𝑛 is applied at slot 𝑛 + 1; mid-slot updates are deferred.
4
Methodology for Policy Design
Given a bank of experts, the next question is how to select telemetry inputs and design the switching policy. We design the switching policy in three stages that are transferable across different PHY functions. We demonstrate this through the channel estimation case study, but the stages themselves — controlled perturbation, monotonicity filtering, and redundancy reduction — are generic.
1
2a
AWGN
𝑵
2c
+
MMSE
4 " 𝒏𝒐𝒊𝒔𝒚 𝑯 𝑴𝑴𝑺𝑬
"𝑴𝑴𝑺𝑬 𝐻
7 5
3
6
10
11
12
8 9
PUSCH Pipeline
Figure 3: Controlled perturbation for KPM sensitivity analysis: noise injection into the channel estimates within Expert A (node 2c), reusing the node descriptions from Figure 2.
4.1
Stage 1: Sensitivity Analysis via Controlled Perturbation
The first stage identifies candidate KPMs that are sensitive to the quality of the processing function under study. The approach is to inject controlled, calibrated degradation into one expert’s output and observe which downstream metrics respond. By isolating the effect of processing quality from the switching logic itself, we ensure that the selected KPMs genuinely reflect processing accuracy rather than artifacts of the switching process. Note that the ARCHES switching mechanism and the AI-based estimator are not included, as this setup is designed solely to serve as a baseline platform for KPM extraction. For the channel estimation case study, we inject Additive White Gaussian Noise (AWGN) into the MMSE channel estimates at node 2c, as illustrated in Figure 3. The wireless channel is characterized by the Channel State Information (CSI) H ∈ C𝑁ant ×𝑁l ×𝑁sc ×𝑁sym , where 𝑁 ant = 4 is the number of antenna ports, 𝑁 l = 1 is the number of transmission layers, 𝑁 sc = 12 × 𝑁 PRB is the number of subcarriers with 𝑁 PRB denoting the number of Physical Resource Blocks (PRBs) allocated for UL transmission, and 𝑁 sym = 14 is the number of Orthogonal Frequency Division Multiplexing (OFDM) symbols in a slot. At the receiver, H is estimated using DeModulation Reference Signal (DMRS)-based MMSE estimation with frequency-domain interpolation at DMRS positions, yielding DMRS ĤMMSE ∈ C𝑁ant ×𝑁l ×𝑁sc ×𝑁sym , where estimates are obtained from DMRS = 3 pilot symbols and later interpolated across all OFDM 𝑁 sym symbols by the equalizer.
LCID4 Tput [Mbps]
MobiHoc ’26, Nov 23–26, 2026, Tokyo, Japan
20
60 SNR [dB]
TB Size [kB]
ARCHES : Adaptive Real-Time Switching of AI Models for the RAN
40 20
15 10 5 0
0
50
100 𝜌[%]
150
200
(a) TB size vs. 𝜌.
0
50
8 6 4 2
100 150 200 𝜌[%]
0
(b) SNR vs. 𝜌.
50
100 𝜌[%]
150
200
(c) LCID4 throughput vs. 𝜌.
Figure 4: KPM degradation trends showing incremental performance loss with increasing perturbation intensity 𝜌 for the channel estimation case study.
The parameter 𝜌 ∈ [0, 2] controls the noise intensity. We sweep 𝜌 from 0 to 2 in steps of 0.1 to evaluate performance degradation under gradually increasing noise levels. The resulting corrupted noisy channel estimate ĤMMSE is therefore given by noisy ĤMMSE = ĤMMSE + 𝜌 · E | ĤMMSE | · CN (0, 1),
(3)
as illustrated in Figure 3. We then evaluate the degradation of candidate KPMs derived from NVIDIA Aerial Data Lake, described in Section 6 and OAI as a function of 𝜌, identifying those that exhibit consistent sensitivity to channel estimation errors. For other functions, the perturbation would differ: for beam management, one might inject perturbations into channel estimates or angular offsets into beam predictions; for Low Density ParityCheck Code (LDPC) decoding variants, one might degrade decoder inputs by injecting noise into log-likelihood ratios at controlled rates. The idea is the same: perturb the expert output and observe how downstream performance changes.
4.2
Stage 2: Monotonicity Filtering
Having identified candidate KPMs via perturbation, the second stage retains only those that exhibit a consistent and monotonic degradation trend as perturbation intensity (𝜌) increases, indicating a direct sensitivity to processing quality. As shown in Figure 4, all three representative KPMs exhibit a clear monotonic decline as 𝜌 increases. Transport Block (TB) size (Figure 4a) and Signal-to-Noise-Ratio (SNR) (Figure 4b) follow a similar trajectory: both remain relatively stable at low noise levels before dropping sharply in the mid-range of 𝜌, reflecting the point at which channel estimation errors begin to significantly impact link adaptation and demodulation. LCID4 throughput (Figure 4c) follows an analogous trend at the MAC layer, confirming that the PHYlayer degradation propagates upward through the protocol stack. The narrow 95% confidence intervals across all three plots indicate that these trends are consistent and repeatable across experimental runs.
1
.74 .75 .76 .79
.74
1
SINR QAM Order Num CB
.75 .83
.8
.8 -.32 -.58
.83 .81 .87 .91 .91 -.23 -.72 .85 .93 .92 .93 -.19 -.64
1
.76 .81 .85
1
.79 .87 .93 .95
.95 .97 .96 -.28 -.69 1
1 .46
1
.7
.67 .77
MAC RX
.44
.7
1
.63 .69
.99 .99 -.25 -.69
MCS Index
.8
.91 .92 .97 .99
1
1 -.26 -.71
TB Size
.8
.91 .93 .96 .99
1
1 -.26 -.71
NDI -.32 -.23 -.19 -.28 -.25 -.26 -.26 1
.16
RSRP -.58 -.72 -.64 -.69 -.69 -.71 -.71 .16
1
.46 .44 .23 .27
LCID4 RX LCID4 Tput
SNR MAC Tput
.23 .67 .63
1
.73
.27 .77 .69 .73
1
S AC NR Tp ut
where the standard deviation is proportional to the mean magnitude of ĤMMSE : 𝜎 = 𝜌 · E | ĤMMSE | . (2)
PDU Len CodeRate
M
(1)
Stage 3: Redundancy Reduction via Hierarchical Clustering
LC I LC D4 ID RX 4 T M put AC RX
N ∼ CN (0, 𝜎 2 ),
4.3
PD U Co Len de Ra te QA SI M NR Or Nu der M mC CS B In d TB ex Si ze ND I RS RP
To induce degraded channel knowledge for OTA transmissions, controlled synthetic noise N of identical dimensions is injected into ĤMMSE , modeled as complex AWGN:
(a) DataLake cluster.
(b) OAI cluster. Correlation Coefficient
−1
−0.5
0
0.5
1
Figure 5: Clustered correlation matrices for Data Lake and OAI KPMs, revealing redundancy structure used to select a compact input set for the switching policy. While the preceding analysis identifies KPMs that are individually sensitive to channel estimation quality, several of these metrics may carry redundant information. This redundancy arises because metrics are tightly coupled through link adaptation (e.g., MCS index and TB size move in lockstep as the scheduler adapts to channel quality). To distill the KPM set into a compact and non-redundant input for the ARCHES dApp, we compute pairwise Pearson correlation coefficients across all candidate KPMs and reorder the resulting matrices using hierarchical clustering, which groups highly correlated KPMs into visually identifiable block-like structures. PHY throughput from Aerial is excluded from the correlation analysis due to its cumulative computation, unlike the other per-slot metrics from Aerial. Figure 5a shows the correlation matrix for the Aerial Data Lake KPMs. We apply a conservative correlation threshold of 0.8, chosen to retain KPMs that, despite moderate correlation, may carry complementary information under specific channel conditions. We observe only one redundant cluster, visible as the darker blue shaded block containing code rate, Signal to Interference plus Noise Ratio (SINR), Quadrature Amplitude Modulation (QAM) order, Modulation and Coding Scheme (MCS) index, TB size, and the number of Code Blocks (CBs), with pairwise correlation coefficients ranging
5
Case Study: UL Channel Estimation
This section instantiates the ARCHES framework for UL channel estimation, detailing the domain-specific aspects: the two experts (AI-based and MMSE), the background on channel estimation, and the specific switching policy.
5.1
Background: Channel Estimation
UL channel estimation at the gNB is performed using DMRS embedded within the PUSCH. The DMRS patterns and sequences are predefined by the standard and configured by the gNB, with the corresponding parameters conveyed to the UE through Downlink Control Information (DCI). Upon reception, the gNB correlates the known DMRS sequences with the received signal at the DMRS locations to estimate the channel response, thereby characterizing the effects of propagation, fading, and other impairments. These initial channel estimates are then interpolated in the frequency domain across all subcarriers to obtain channel estimates over the entire frequency band, as shown in Figure 6. The left image in Figure 6 shows a representative OFDM UL slot, where user data resource elements are shown in white and the channel estimates computed at the DMRS resource elements are shown in dark-green. We use DMRS with a Type 1 configuration with interleaved frequency-domain placement, occupying OFDM symbols 0, 5, and 10. The right-hand image in Figure 6 illustrates the frequencydomain interpolated channel estimates in light-green, where the
Freq. domain Estimates interpolation at DMRS Interpolated Estimates User Data
Channel Estimation
OFDM Symbols
Subcarriers
from 0.81 to 1. Link adaptation causes these parameters to change together as channel quality varies. From this cluster, we keep MCS index as the representative, as it directly reflects the scheduling decision and subsumes the effect of the remaining parameters. The remaining KPMs (Packet Data Unit (PDU) length, New Data Indicator (NDI), and Reference Signal Received Power (RSRP)) fall below the threshold with respect to each other and are preserved as independent inputs to the switching logic. Notably, RSRP exhibits a consistent negative correlation with the main block (from −0.58 to −0.71). Since RSRP in Aerial is computed from the mean squared magnitude of the channel estimates, additive noise inflates the measured power (RSRP ≈ RSRPclean + 𝜎 2 ). As a result, RSRP increases as channel estimation quality degrades, while the remaining KPMs decline. Figure 5b shows the corresponding matrix for the OAI KPMs. No pairwise correlation exceeds the 0.8 threshold, with the strongest association being MAC throughput and LCID4 throughput (0.77). Consequently, all OAI-derived KPMs are retained. The generally moderate correlations suggest that these KPMs capture complementary aspects of system performance, for instance, LCID4 RX exhibits the weakest correlations overall (0.23–0.46), reflecting user-plane delivery rather than PHY-layer link adaptation, and providing the ARCHES dApp with a cross-layer view of system health. Based on this analysis, the final set of KPMs selected for the ARCHES switching logic comprises: PHY throughput, MCS index, PDU length, NDI, and RSRP from Aerial Data Lake; and SNR, MAClayer throughput, LCID4 throughput, MAC received bytes, and LCID4 received bytes from OAI. Together, these KPMs span multiple protocol layers, from PHY-layer channel quality metrics to MAC-layer scheduling and throughput indicators, giving ARCHES a multi-layer perspective on channel conditions that no single metric could provide alone.
N. Neasamoni Santhi, D. Villa, M. Polese, S. D’Oro, Y. Lee, K. Furueda, T. Melodia
Subcarriers
MobiHoc ’26, Nov 23–26, 2026, Tokyo, Japan
OFDM Symbols
Figure 6: DMRS-Based Channel Estimation and Frequency-Domain Interpolation in a 5G NR UL Slot. initial estimates at the DMRS resource elements are extended across all subcarriers within the corresponding OFDM symbols, thereby reconstructing the channel over the entire bandwidth. The interpolation and smoothing strategy depends on the specific estimator used. Some estimators also perform time-domain interpolation. In the current implementation of ARCHES on NVIDIA Aerial, however, the channel estimator performs only frequencydomain interpolation, while time-domain interpolation across OFDM symbols is handled by the subsequent equalizer. The MMSE estimator leverages prior knowledge of channel and noise statistics but relies on assumptions (accurate covariance matrices, quasi-stationary statistics) that limit its robustness under time-selective channels, strong multipath, or statistical mismatch. Various neural-network estimators have shown promising performance under specific conditions, but no single estimator dominates across all scenarios [4]. This motivates the ARCHES approach: rather than committing to one estimator, the framework maintains both and selects per-slot.
5.2
Expert Bank: AI-Based and MMSE Estimators
The PUSCH CUDA graph (Figure 2) is extended to execute both the MMSE (node 2c) and AI-based (node 2d) estimators in parallel, with the switch kernel (node 2e) selecting the output. For this instantiation, mode=0 selects AI-based estimates and mode=1 selects MMSE. Separate memory is allocated for ĤMMSE and ĤAI , with downstream modules reading from the AI-designated buffer. The MMSE estimator (Expert A) is the conventional channel estimator native to the NVIDIA Aerial PUSCH pipeline, performing frequency-domain interpolation based on power-delay profile approximation [16], as described in Section 5.1. The AI-based estimator (Expert B) employs a deep neural network with convolutional layers and residual connections, following architectures that have shown strong performance for OFDM channel estimation [17], taking Least Squares (LS) channel estimates at DMRS locations as input and producing frequency-interpolated estimates across the full bandwidth. The model is integrated via the Channel-Estimate Factory on the Aerial platform using the TensorRT inference engine, and is tested in the open-source cuBB 25-3 [18]. The current NVIDIA Aerial integration supports AI-based estimation for a single UE; extending to multi-UE scheduling is left to future work. We will release the ARCHES extensions, including the switch kernel and dApp integration, as open source components. The AI-based estimator’s inference time and GPU utilization are reported in Section 6.2.
ARCHES : Adaptive Real-Time Switching of AI Models for the RAN
5.3
MobiHoc ’26, Nov 23–26, 2026, Tokyo, Japan
Switching Policy: Decision Tree
The switching policy is implemented as a lightweight decision tree classifier in the ARCHES dApp. It takes as input the KPMs selected via the methodology in Section 4 and outputs the binary mode variable. Training data and labeling. The decision tree is trained via supervised learning on OTA data, where each slot is labeled mode=0 under interference conditions and mode=1 otherwise. The goal is to identify when the additional performance from AI justifies its higher compute and energy cost (Section 6.2). We use interference presence as the supervisory signal because OTA profiling shows that AI provides its largest gains under interference, while MMSE remains near-optimal in clean conditions. Model configuration. The tree has a maximum depth of 2 with Gini impurity splitting across 10 KPMs. The most informative features are MAC-layer throughput (94.27%), MAC received bytes (4.30%), and LCID4 throughput (1.42%). The shallow depth ensures sub-microsecond inference while avoiding overfitting. Performance. As shown in Table 1, the decision tree achieves 99.66% accuracy, 97.56% precision, 99.60% specificity, and a 98.77% F1 score on a held-out test set (80/20 split). Table 1: Decision tree classification performance.
6
Accuracy
Precision
Specificity
F1 Score
99.66%
97.56%
99.60%
98.77%
Experimental Evaluation
OTA data collection. All experiments are conducted on the X5G platform [19], an O-RAN–compliant, multi-vendor private 5G network built on NVIDIA Aerial [12], covering an entire floor of the EXP building at Northeastern University. Each node features OAI for upper layers and the NVIDIA Aerial SDK for the DU-Low, running on GH200 GPU systems. The OTA experiments are conducted in an indoor open space with a dynamic environment (Figure 7a). All measurements are performed under Line-of-Sight (LOS) conditions between the gNB1– UE1 pair, with UE1 placed on a stand and gNB1 mounted on a wall (Figure 7a). To evaluate performance under different conditions, we introduce frequency-selective in-band UL interference from a neighboring cell [20]: UE2 transmits to gNB2 in the same frequency band, with the interference level controlled by the MAC scheduler via PRB allocation (Figure 7b). We refer to conditions as good (no interference) and poor (interference present).
6.1
Mechanism-Level Results: Temporal Analysis
Switch Kernel. Figure 8 summarizes the runtime statistics for the AI expert (dark-green) and the MMSE estimator (light-green), profiled using NVIDIA Nsight Systems. The switch kernel executes in an average of 3.36 𝜇s when selecting AI and 4.89 𝜇s when selecting MMSE. The higher latency in MMSE mode reflects the coalesced memory copy discussed in Section 3.2, which is absent in AI mode. Similar trends are observed across the median, and standard deviations remain comparable for both modes, indicating consistent execution. Switch (AI)
UE1 gNB2
1m
4.89 3.36
5.04
100
4.83 3.36
Decision Tree
4.61
0.41
UE2
(a) Floor plan showing two cell sites. Insets: UE (top center), RF environment for gNB1–UE1 (top left), O-RU (top right), server (bottom right).
MMSE
432.37
102 Time [𝜇s]
Cell 1 Cell 2 gNB1
AI
Switch (MMSE)
432.33
0.38
0.840.83 0.410.47 0.12
Average
Median
Std Dev
Figure 8: Runtime statistics for all components of the switching mechanism.
Cell Edge UE1 gNB2
gNB1 UE2 (Interferer) Desired Cell
Interfering Cell
(b) Introduction of interference via UL transmissions between UE2 and gNB2.
Figure 7: Experimental setup. Aerial Data Lake. To collect the KPMs that drive the switching policy, we use NVIDIA Aerial Data Lake, a telemetry framework within the NVIDIA Aerial CUDA-accelerated RAN that captures UL I/Q samples from the O-RAN 7.2x fronthaul interface along with FAPI metadata exchanged between the L1 and L2 layers.
Decision Tree. The inference time of the decision tree (purple bars in Figure 8), described in Section 5.3, running on the ARCHES dApp averages 0.41 𝜇s on the GH200 (median 0.38 𝜇s, std. dev. 0.12 𝜇s), achieving an accuracy above 99%. The model is executed at a configurable periodicity, enabling timely adaptation to channel dynamics without introducing measurable processing overhead. End-to-end Control Loop Latency. The end-to-end control loop latency accounts for the full data path from the GPU-accelerated PUSCH pipeline to the dApp, including the decision tree inference and the switch kernel execution. Prior to any model execution, the dApp incurs approximately 135 𝜇s of framework overhead, comprising several tightly optimized data-movement and messaging steps, such as copying data into shared memory buffers and sending pointers and metadata to the dApp via the ZeroMQ interface.
PHY Throughput [Mbps]
Poor
Good
Good
40 200
400 Slot Index
600
800
Figure 9: PHY throughput over time as channel conditions transition from good to poor and back. Dashed lines: throughput under continuous execution of each estimator; solid lines: throughput under ARCHES. AI (Good)
AI (Poor)
MMSE (Good)
1
1
0.8
0.8
0.4 0.2 0
AI(Good) AI(Poor) MMSE(Good) MMSE(Poor)
CDF
0.6
0.6
0
(a) PHY throughput
0
0.4
10 20 MCS Index
(b) MCS index
1
0.6
AI(Good) AI(Poor) MMSE(Good) MMSE(Poor)
0.4
0 20 40 60 80 100 PHY Throughput [Mbps]
0.8
MMSE (Poor)
0.2
1 0.8 AI(Good) AI(Poor) MMSE(Poor) MMSE(Good) −1 0
1
2
3
CDF
Expert Inference Times. We profile the execution time of the AI-based estimator (blue) and the MMSE filtering kernel (orange) in Figure 8. The AI-based estimator inference time is profiled using TensorRT, while the MMSE latency is measured using Nsight Systems by profiling the dispatch kernel, which internally invokes the kernel that performs the actual MMSE estimation. The MMSE CUDA kernel executes in approximately 5.04 𝜇s, while the AI-based estimator requires approximately 432 𝜇s, making it roughly 85 times slower. This overhead, along with the GPU utilization discussed later in this subsection, is the primary motivation for the switching mechanism proposed in this work. Although the AI-based estimator delivers consistent throughput gains under the tested conditions, its substantially higher compute cost makes unconditional execution impractical, particularly in multi-UE scenarios where per-slot latency budgets are shared across users. The dApp therefore dynamically activates the AI-based estimator only when the switching policy determines that conditions warrant it. Time Series of PHY Throughput. Figure 9 shows the PHY throughput over time (indexed by slot) for an OTA experiment in which channel conditions transition from good to poor and back. Dashed lines show the throughput each estimator would achieve if run continuously; solid lines show the throughput under ARCHES. In good conditions, ARCHES selects MMSE: although AI consistently improves throughput, the gain is too small to justify its substantially higher compute and energy cost, as quantified under GPU and CPU Resources below. In poor conditions, ARCHES switches to the AI-based estimator, where the larger throughput advantage outweighs the additional resource consumption. KPMs. Figure 10 presents CDFs of six KPMs used in the switching logic. Under good conditions, the AI-based estimator achieves a median PHY throughput of 93.97 Mbps versus 89.23 Mbps for MMSE (5.32% gain) and a median MAC throughput of 93.67 Mbps versus 87.99 Mbps (6.45% gain). Under poor conditions, the AI advantage persists: median PHY throughput of 52.14 versus 48.64 Mbps (7.23%) and MAC throughput of 52.18 versus 47.77 Mbps (9.23%). For MCS index (Figure 10b), the AI-based estimator yields a median of 20 versus 19 under good conditions and 12 versus 11 under poor conditions. For PDU length (Figure 10e), both estimators produce larger PDUs under good conditions, with AI shifting the distribution toward higher values. LCID4 RX bytes (Figure 10c) follow a similar trend, confirming that PHY-layer gains propagate to user-plane
MMSE
60
0.6
AI(Good) AI(Poor) MMSE(Good) MMSE(Poor)
0.4 0.2 0
4
0 20 40 60 80 100 MAC Throughput [Mbps]
LCID4 RX [×109 bytes] (c) LCID4 RX bytes
(d) MAC throughput
1 0.8
1
0.6
0.8
0.4 0.2 0
AI(Good) AI(Poor) MMSE(Good) MMSE(Poor) 0 0.5 1 1.5 2 2.5
CDF
Case-Study Results: Performance Comparison
ARCHES (MMSE)
80
0
CDF
6.2
AI
ARCHES (AI)
CDF
The decision tree classifier adds 0.41 𝜇s on average, and the switch kernel itself executes in approximately 4.5 𝜇s, yielding a total endto-end control loop latency of approximately 140 𝜇s. Note that this latency assumes the switching decision is applied at the beginning of the current slot; if the decision arrives after the slot boundary, it takes effect in the following slot. Data Integrity. Since PHY throughput in Aerial is computed from successfully decoded transport blocks based on TB Cyclic Redundancy Check (CRC) checks, any corruption introduced by switching would therefore appear as reduced throughput. The stable throughput observed during switching confirms that slot-boundary switching does not corrupt in-flight data.
N. Neasamoni Santhi, D. Villa, M. Polese, S. D’Oro, Y. Lee, K. Furueda, T. Melodia
CDF
MobiHoc ’26, Nov 23–26, 2026, Tokyo, Japan
0.6 0.2 0 5
PDU Length [×104 bytes] (e) PDU length
AI(Good) AI(Poor) MMSE(Good) MMSE(Poor)
0.4
10 15 RSRP [dBFS]
(f) RSRP
Figure 10: CDF comparison of AI (blue) and MMSE (orange) estimators under good (solid) and poor (dashed) channel conditions.
ARCHES : Adaptive Real-Time Switching of AI Models for the RAN
MobiHoc ’26, Nov 23–26, 2026, Tokyo, Japan
delivery. RSRP (Figure 10f) remains comparable across estimators, consistent with its dependence on received signal power rather than estimation quality.
CDF
AI (Good)
1 0.8 0.6 0.4 0.2 0
AI (Poor)
140
(a) GPU power draw
1 0.8 0.6 0.4 0.2 0
150 GPU Power [W]
160
AI (Good) AI (Poor) MMSE (Good) MMSE (Poor) 20
30
40 50 GPU Utilization [%]
60
70
CDF
(b) GPU utilization
1 0.8 0.6 0.4 0.2 0
AI (Good) AI (Poor) MMSE (Good) MMSE (Poor) 19.5
20
20.5 21 21.5 22 CPU Memory Usage [%] (c) CPU memory usage
22.5
7
Generalization to Other RAN Functions
The ARCHES mechanism is not specific to channel estimation. The design principles in Section 2 are function-agnostic; only the experts and telemetry inputs change per use case. For beam management, multiple prediction models (e.g., pedestrian vs. vehicular) [21] could execute, with the policy driven by beam failure rate and mobility indicators. For equalization or LDPC decoding, experts with different configurations (e.g., iteration counts or neural-augmented variants [22]) could be switched based on Block Error Rate (BLER) and compute-budget metrics. For interference detection and Integrated Sensing and Communication (ISAC), prior work on the same platform [15, 20] could be extended with multiple detection models selected based on observed interference patterns. In all cases, the validated mechanism-level properties—a 140 𝜇s control loop, submicrosecond policy inference, and a 3–5 𝜇s switch kernel—transfer directly. The switching mechanism remains unchanged; only the experts and telemetry inputs are adapted to the target function.
MMSE (Poor)
AI (Good) AI (Poor) MMSE (Good) MMSE (Poor) 130
CDF
MMSE (Good)
rationale: activating AI only when conditions warrant it improves KPMs while avoiding unnecessary power expenditure.
23
Figure 11: CDF comparison of GPU power draw, GPU utilization, and CPU memory usage for AI (blue) and MMSE (orange) estimators under good (solid) and poor (dashed) channel conditions. GPU and CPU Resources. Figure 11 presents the CDFs of GPU power, utilization, and CPU memory. Measurements are collected with each estimator running independently, quantifying the perexpert resource profile that informs the switching decision. Under good conditions, MMSE shows a clear advantage: median GPU power decreases from 164.2 W (AI) to 148.4 W, saving 15.8 W (9.6%), while GPU utilization drops from 67% to 50% (17 percentage points). Under poor conditions, reduced scheduling grants lower overall GPU load for both estimators, shrinking the power gap to ∼1 W and converging utilization to 36% versus 35%. CPU memory remains comparable across all cases, confirming negligible host-side overhead. The resource gap is most pronounced under good conditions, thus reinforcing the case for defaulting to MMSE when conditions are favorable. Concurrent execution is used here to validate seamless slotboundary switching, deterministic latency, and fail-safe operation. In practical deployment, the selected-only mode (Section 3.1) would directly realize these savings at the cost of at least a one-slot activation delay. These resource profiles validate the ARCHES design
8
Related Work
MoE and adaptive model selection. The MoE paradigm [10, 11, 23, 24] has been widely studied in machine learning, where a gating network routes inputs to specialized sub-models. However, conventional MoE systems operate in batch or near-real-time settings and do not address the challenges of seamless switching within a live, sub-millisecond signal processing pipeline without data loss. ARCHES adapts the MoE concept to the constraints of GPU-accelerated 5G PHY processing. AI-based channel estimation. Deep learning has emerged as a promising alternative to conventional MMSE and LS estimation in OFDM systems. Several works have proposed Convolutional Neural Network (CNN) and residual architectures that consider the channel time-frequency responses as 2D images [3, 4, 17], while others have targeted high-mobility scenarios with Recurrent Neural Network (RNN)-based interpolators [25] or focused specifically on the 5G NR PUSCH with Artificial Neural Network (ANN) and online-trained estimators [26, 27]. A common finding in these works, further highlighted by the CeBed benchmark [4], is that no single estimator dominates across all propagation scenarios, directly motivating condition-aware selection. Notably, ChannelNet [3] itself proposes SNR-based switching between two specialized networks, but remains simulation-only. Real-time AI in GPU-accelerated RAN. All of the above evaluations are conducted in simulation. Ford et al. [28] take a significant step toward real-world validation by demonstrating a ResNet-based AI channel estimator on the same NVIDIA testbed platform used in this work, achieving OTA throughput gains of up to 40% over MMSE. Boccuzzi et al. [29] present a GPU-accelerated AI-RAN reference design and end-to-end verification methodology on NVIDIA Aerial, while other recent work has demonstrated real-time GPUaccelerated AI inference co-located with 5G NR PHY processing for interference detection and ISAC applications on the same platform [15, 20]. However, none of these works incorporates dynamic selection between AI and conventional experts; instead, the AI model runs continuously, incurring inference overhead regardless of channel conditions.
MobiHoc ’26, Nov 23–26, 2026, Tokyo, Japan
To our knowledge, this work is the first to present a system for real-time expert switching inside a live GPU-accelerated 5G PHY pipeline, validated end-to-end through OTA experiments with switching decisions driven by a dApp using cross-layer KPMs collected from the live system. The contribution of this paper is therefore not a better AI estimator, but the infrastructure required to safely switch between experts in real time.
9
Conclusions and Future Work
This paper presents ARCHES, a framework for real-time expert switching inside GPU-accelerated 5G PHY pipelines. ARCHES demonstrates that real-time expert switching is practical by enabling multiple AI and conventional signal-processing experts to coexist within the pipeline, hot-swapping between them at slotboundary granularity via a lightweight CUDA kernel, and driving the switching decision through cross-layer telemetry collected by a dApp—all without dropping or corrupting in-flight data. The framework is accompanied by a reusable three-stage process for telemetry selection and policy design. Validated through a case study on UL channel estimation on the X5G platform, ARCHES achieves an end-to-end control-loop latency of ∼140 𝜇s with sub-microsecond decision inference. The case study demonstrates median UL PHY throughput improvements of 5.32% and 7.23% under good and poor conditions, respectively. Critically, under good conditions where the throughput gain from AI is marginal (∼5%), defaulting to MMSE saves 15.8 W of GPU power and 17 percentage points of utilization—quantifying the performance-per-watt tradeoff that motivates condition-aware expert selection as AI components proliferate across the RAN. Future work includes extending ARCHES to support 𝑁 > 2 experts for finer-grained adaptation, scaling the AI-based estimator to multi-UE scenarios, evaluating additional propagation conditions (Non-Line-of-Sight (NLOS), high mobility), characterizing the selected-only execution mode under realistic channel dynamics, reporting BLER and HARQ statistics to complement throughputbased evaluation, comparing alternative switching policies such as threshold-based gating, and applying the framework to other real-time RAN functions.
References [1] 3GPP, “Study on Artificial Intelligence (AI)/Machine Learning (ML) for NR Air Interface,” 3rd Generation Partnership Project, Technical Report TR 38.843, 2023, release 18. [2] W. Chen et al., “AI assisted PHY in future wireless systems: Recent developments and challenges,” China Communications, vol. 18, no. 5, pp. 285–297, 2021. [3] M. Soltani, V. Pourahmadi, A. Mirzaei, and H. Sheikhzadeh, “Deep Learning-Based Channel Estimation,” IEEE Communications Letters, vol. 23, no. 4, pp. 652–655, 2019. [4] A. Feriani, D. Wu, X. Liu, and G. Dudek, “CeBed: A Benchmark for Deep DataDriven OFDM Channel Estimation,” arXiv preprint arXiv:2306.13761, 2023. [5] Y. Wang, A. Klautau, M. Ribero, A. C. K. Soong, and R. W. Heath, “MmWave vehicular beam selection with situational awareness using machine learning,” IEEE Access, vol. 7, pp. 87 479–87 493, 2019. [6] X. Wang, L. Gao, S. Mao, and S. Pandey, “CSI-based fingerprinting for indoor localization: A deep learning approach,” IEEE Transactions on Vehicular Technology, vol. 66, no. 1, pp. 763–776, 2017. [7] L. Bonati, S. D’Oro, M. Polese, S. Basagni, and T. Melodia, “Intelligence and learning in O-RAN for data-driven NextG cellular networks,” IEEE Communications Magazine, vol. 59, no. 10, pp. 21–27, 2021.
N. Neasamoni Santhi, D. Villa, M. Polese, S. D’Oro, Y. Lee, K. Furueda, T. Melodia
[8] J. Corgan et al., “How critical is site-specific RAN optimization? 5G open-RAN uplink air interface performance test and optimization from macro-cell CIR data,” in Proc. IEEE Vehicular Technology Conference (VTC), 2024. [9] R. Verdecia-Peña, R. Oliveira, and J. I. Alonso, “Enhancing mmWave channel estimation: A practical experimentation approach with modeled physical layer impairments incorporated in deep learning training,” IEEE Open Journal of the Communications Society, 2024. [10] R. A. Jacobs, M. I. Jordan, S. J. Nowlan, and G. E. Hinton, “Adaptive mixtures of local experts,” Neural Computation, vol. 3, no. 1, pp. 79–87, 1991. [11] N. Shazeer, A. Mirhoseini, K. Maziarz, A. Davis, Q. V. Le, G. E. Hinton, and J. Dean, “Outrageously large neural networks: The sparsely-gated mixture-ofexperts layer,” in Proc. of International Conference on Learning Representations (ICLR), 2017. [12] “Aerial RAN co-lab over-the-air (ARC-OTA),” 2025. [Online]. Available: https://docs.nvidia.com/aerial/aerial-ran-colab-ota/current/index.html [13] S. D’Oro, M. Polese, L. Bonati, H. Cheng, and T. Melodia, “dApps: Distributed Applications for Real-Time Inference and Control in O-RAN,” IEEE Communications Magazine, vol. 60, no. 11, p. 52–58, Nov. 2022. [14] A. Lacava, L. Bonati, N. Mohamadi, R. Gangula, F. Kaltenberger, P. Johari, S. D’Oro, F. Cuomo, M. Polese, and T. Melodia, “dApps: Enabling Real-Time AI-Based Open RAN Control,” Computer Networks, vol. 269, p. 111342, September 2025. [15] D. Villa, M. Belgiovine, N. Hedberg, M. Polese, C. Dick, and T. Melodia, “Programmable and GPU-Accelerated Edge Inference for Real-Time ISAC on NVIDIA Aerial Testbed,” April 2026. [Online]. Available: https://arxiv.org/pdf/ 2512.06493 [16] K.-C. Hung and D. W. Lin, “Pilot-based LMMSE channel estimation for OFDM systems with power-delay profile approximation,” IEEE Transactions on Vehicular Technology, vol. 59, no. 1, 2010. [17] L. Li, H. Chen, H.-H. Chang, and L. Liu, “Deep Residual Learning Meets OFDM Channel Estimation,” IEEE Wireless Communications Letters, vol. 9, no. 5, pp. 615–618, 2020. [18] NVIDIA Aerial™ CUDA-Accelerated RAN. [Online]. Available: https://github. com/NVIDIA/aerial-cuda-accelerated-ran/commits/main/ [19] D. Villa, I. Khan, F. Kaltenberger, N. Hedberg, R. S. da Silva, S. Maxenti, L. Bonati, A. Kelkar, C. Dick, E. Baena, J. M. Jornet, T. Melodia, M. Polese, and D. Koutsonikolas, “X5G: An Open, Programmable, Multi-Vendor, End-to-End, Private 5G O-RAN Testbed With NVIDIA ARC and OpenAirInterface,” IEEE Transactions on Mobile Computing, vol. 24, no. 11, pp. 11 305–11 322, 2025. [20] N. Neasamoni Santhi, D. Villa, M. Polese, and T. Melodia, “InterfO-RAN: RealTime In-band Cellular Uplink Interference Detection with GPU-Accelerated dApps,” in Proc. of ACM International Symposium on Theory, Algorithmic Foundations, and Protocol Design for Mobile Networks and Mobile Computing (MobiHoc), Houston, TX, USA, October 2025, p. 71–80. [21] Q. Xue et al., “AI/ML for beam management in 5G-advanced: A standardization perspective,” IEEE Communications Surveys & Tutorials, vol. 26, no. 4, 2024. [22] E. Nachmani, E. Marciano, L. Lugosch, W. J. Gross, D. Burshtein, and Y. Be’ery, “Deep learning methods for improved decoding of linear codes,” IEEE Journal of Selected Topics in Signal Processing, vol. 12, no. 1, pp. 119–131, 2018. [23] M. I. Jordan and R. A. Jacobs, “Hierarchical mixtures of experts and the EM algorithm,” Neural Computation, vol. 6, no. 2, pp. 181–214, 1994. [24] W. Fedus, B. Zoph, and N. Shazeer, “Switch transformers: Scaling to trillion parameter models with simple and efficient sparsity,” in Journal of Machine Learning Research, vol. 23, no. 120, 2022, pp. 1–39. [25] A. K. Gizzini and M. Chafii, “RNN Based Channel Estimation in Doubly Selective Environments,” IEEE Transactions on Machine Learning in Communications and Networking, vol. 2, pp. 1–18, 2024. [26] A. B. Dayi, “Improving 5G NR Uplink Channel Estimation with Artificial Neural Networks: A Practical Study on NR PUSCH Receiver,” in Proceedings of the IEEE International Black Sea Conference on Communications and Networking (BlackSeaCom), 2022, pp. 129–134. [27] K. Weththasinghe, B. Jayawickrama, and Y. He, “Machine Learning-Based Channel Estimation for 5G New Radio,” IEEE Wireless Communications Letters, vol. 13, no. 4, pp. 1133–1137, 2024. [28] R. Ford, H. Chen, P. Madadi, M. Kulkarni, X. Ma, D. Burghal, G. Chen, Y. Hu, C. Tarver, P. Skrimponis, V. Loseu, Y. Zhang, Y. Xin, Y. Li, J. Zhang, S. Khunteta, Y. G. Reddy, A. K. R. Chavva, M. Kothiwale, and D. Villa, “Sim2Field: End-to-End Development of AI RANs for 6G,” in Proceedings of ACM Workshop on Open and AI RAN, Hong Kong, China, November 2025. [29] J. Boccuzzi, R. Chavan, R. Lekhwani, S. Lin, M. Hoang, N. Hedberg, Q. Wang, S. Samala, P. Marini, S. Sarpotdar, and M. Adamczyk, “GPU Accelerated High Capacity, AI-Ready 5G/6G Reference Design and Verification Methodology,” IEEE Wireless Communications, vol. 32, no. 6, pp. 216–223, 2025.