RefEvo: Agentic Design with Co-Evolutionary Verification for Agile Reference Model Generation Yifan Zhang1,2 , Jianmin Ye1,2 , Jiahao Yang2 , Xi Wang1,2* 1
School of Integrated Circuits, Southeast University, China National Center of Technology Innovation for EDA, China Email: {yifan.zhang, jianmin y, xi.wang}@seu.edu.cn, [email protected] * Corresponding author.
arXiv:2604.24218v1 [cs.SE] 27 Apr 2026
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Abstract—As the complexity of Systems-on-Chip (SoC) escalates, the “shift-left” strategy necessitates the rapid development of high-fidelity reference models (e.g., in SystemC) for early architecture exploration and verification. While Large Language Models show promise in code generation, applying them to hardware modeling faces distinct challenges: (1) rigid, static workflows fail to adapt to varying design complexities, causing inefficiency; (2) context overflow in long-turn interactions leads to the catastrophic forgetting of critical specifications; and (3) the “Coupled Validation Failure” problem—where generated TBs falsely verify flawed models due to shared hallucinations—severely undermines reliability. To address these limitations, we introduce RefEvo, a dynamic multi-agent framework designed for agile and reliable modeling. RefEvo features three key innovations: (1) A Dynamic Design Planner that autonomously decomposes specifications and constructs tailored execution workflows based on semantic complexity; (2) A Co-Evolutionary Verification Mechanism, which employs a Dialectical Arbiter to simultaneously rectify the model and verification logic against the specification (Spec) oracle, effectively mitigating false positives; and (3) A Spec Anchoring Strategy for lossless context compression. Evaluated on a diverse benchmark of 20 hardware modules, RefEvo achieves a 95% pass rate, outperforming static baselines by a large margin. Furthermore, our context optimization reduces token consumption by an average of 71.04%, achieving absolute savings of over 70,000 tokens per session for complex designs while maintaining 100% specification recall. Index Terms—LLM, LLM-aided Design, Function Verification, Reference Model, Agentic System
I. I NTRODUCTION In the modern Electronic Design Automation (EDA) landscape, high-level reference models written in languages like SystemC or C++ have become critical assets [1]. These models serve as the “golden standard” for verifying Register Transfer Level (RTL) implementations and act as virtual prototypes for early software development [2]–[4]. Their importance is further amplified by the industry-wide adoption of the “shift-left” methodology, which mandates early validation through virtual platforms to enable hardware-software co-verification prior to silicon fabrication. However, despite their necessity, manually crafting these high-fidelity models remains a labor-intensive and error-prone process, creating a significant bottleneck in the agile hardware development cycle [5], [6].
Fig. 1. Performance capability of state-of-the-art LLMs using optimized prompt engineering and structured generation workflows (without CoEvolutionary Verification). The radar chart highlights the significant struggle of current models in generating correct SystemC reference models across various hardware domains, particularly in Control Logic and Memory & I/O.
To alleviate this engineering burden, recent advancements in Large Language Models (LLMs) have sparked intense interest in automating EDA tasks [7], [8]. While LLMs like GPT4 have demonstrated remarkable proficiency in generating generic software, applying them to the strict constraints of hardware modeling presents unique challenges. Within the hardware domain, the majority of research progress has been concentrated on RTL code generation, exemplified by approaches such as RTLCoder [9], ChatChisel [10], ReChisel [11], and ChatCPU [12]. Complementing these generation efforts, benchmarking studies [13] have also established robust evaluation frameworks specifically for assessing LLM capabilities in Verilog. However, SystemC modeling, which requires precise handling of transaction-level modeling (TLM) semantics, bitwidths, concurrency, and delta-cycle timing, remains a distinct challenge [14]. As illustrated in Fig. 1, even when equipped with specialized design workflows and sophisticated prompt engineering [15], [16], advanced models struggle significantly to produce functional SystemC models across various hardware domains. A naive or purely structured application of
LLMs often results in code that looks plausible but fails to compile or simulate correctly. We identify three primary hurdles hindering the practical adoption of LLMs in this domain: Syntactic and Semantic Correctness: Hardware models must adhere to strict event-driven simulation semantics. LLMs frequently generate code with subtle API misuses or missing library dependencies, leading to compilation failures that naive generation cannot resolve. Coupled Validation Failure: A critical risk arises when LLMs generate both the design under test (DUT) and the testbench (TB). Traditional static flows [17] often lead to a sycophantic scenario where the TB is inadvertently tailored to match the DUT’s hallucinations, resulting in a false-positive “PASS”. While introducing manual human-written TBs could mitigate this, it re-introduces the very bottleneck automation seeks to eliminate, as addressed by recent verification frameworks like ChatTest [18] and FIXME [19]. Furthermore, in early agile stages where specifications change frequently, manual TBs suffer from error propagation, where outdated verification logic fails to catch new design errors [20], [21]. Therefore, an automated mechanism to validate the validator itself is essential. Context Limitations: As design complexity grows, the extensive interaction logs required for iterative refinement often exceed the context window of LLMs [22]–[24]. This causes the model to suffer from Catastrophic Forgetting, losing track of initial specifications such as register maps or interface protocols during long interaction sessions. To overcome these challenges, we propose RefEvo, an agent-based framework designed for the agile generation of reliable hardware reference models. Unlike static generation approaches, RefEvo treats generation as a dynamic, coevolutionary process. Building on the collaborative paradigm of modern multi-agent frameworks [25]–[27]—where planners, coders, and debuggers work in concert—RefEvo introduces domain-specific innovations to address the aforementioned problems: Dynamic Design Planner: To address workflow rigidity, we introduce a planner that acts as a “Brain”, analyzing semantic complexity to autonomously decompose specifications and construct bespoke execution workflows. • Co-Evolutionary Verification: To mitigate coupled validation failures, we propose a dialectical mechanism where a dedicated Arbiter Agent validates both the code and the TB against the specification oracle, significantly reducing false positives. • Spec Anchoring Context Management: To solve catastrophic forgetting, we implement a strategy that anchors the immutable specification while compressing interaction history, ensuring 100% recall of critical constraints.
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The remainder of this paper is organized as follows: Section II reviews related work. Section III details the RefEvo methodology. Section IV presents the experimental results and analysis. Section V concludes the paper.
II. R ELATED W ORK A. LLM-Based Hardware Code Generation The application of LLMs in hardware design has gained significant traction. Early benchmarking efforts [13] established evaluation frameworks demonstrating that LLMs could generate syntactically correct Verilog code. Tools like RTLCoder [9] have demonstrated that fine-tuned LLMs can generate syntactically correct RTL code, while iDSE [28] also explored the integration of LLMs in high-level synthesis design space exploration. However, these works primarily focus on RTL generation. High-level modeling (SystemC/C++), which requires a higher level of abstraction and distinct simulation semantics, remains under-explored. RefEvo bridges this gap by targeting the specific challenges of reference model generation. A critical challenge in LLM-based code generation is the hallucination problem. Recent work on code hallucination detection has categorized errors into mapping, naming, resource, and logic errors. Our work addresses the more subtle “Coupled Validation Failure”, where both the model and its TB may be flawed. Unlike prior works that rely on fixed TBs, RefEvo introduces a co-evolutionary approach to dynamically refine the verification logic itself. B. Automated Debugging and Program Repair Automated program repair (APR) has emerged as a critical research area [29]. Recent work has demonstrated the effectiveness of conversation-based APR [30], where iterative dialogue with LLMs can fix bugs at remarkably low cost. Practical APR approaches [31] have focused on reducing reliance on extensive test suites. In the hardware domain, recent works have attempted to use LLMs to fix RTL bugs based on compiler feedback. However, most existing approaches assume a fixed, correct TB. RefEvo distinguishes itself by introducing a dialectical arbiter that validates the TB against the specification, ensuring that ”repairs” do not simply mask bugs. C. Dynamic Planning and Agent Reasoning The ability to dynamically decompose complex tasks is fundamental to effective agentic systems. TDAG [32] introduced a framework that dynamically decomposes tasks into subtasks. Recent advances [33] have integrated dynamic task decomposition with tool selection. RefEvo’s Dynamic Design Planner draws inspiration from these advances, employing semantic complexity analysis to construct tailored execution workflows. III. M ETHODOLOGY RefEvo is structured as a hierarchical multi-agent framework comprising three functional components: Dynamic Planning, the Symbiotic Verification Loop, and SpecAnchored Context Management. The overall execution flow coordinates four specialized agents to transform ambiguous specifications into verified SystemC models.
Fig. 2. The logical architecture of RefEvo. (A) The Dynamic Planning phase where Agent 1 analyzes complexity to construct an execution plan. (B) The Symbiotic Verification Loop where the Modeler (Agent 2) and Verifier (Agent 3) co-evolve under the supervision of the Dialectical Arbiter (Agent 4).
A. Dynamic Task Planning Traditional LLM-based EDA flows often enforce a rigid, linear execution sequence, leading to token wastage for simple logic and verification failures for complex systems. As illustrated in Fig. 2A, the Design Planner (Agent 1) serves as the methodological orchestrator of the system. Upon receiving the Design Specification and optional Legacy Assets, Agent 1 performs a dual-stage assessment: • Asset Evaluator: It examines existing codebases or Verification Intellectual Property to determine reusability, minimizing redundant generation. • Semantic Analyzer: It evaluates the design’s complexity across three dimensions: Interface Protocol (e.g., AXI vs. GPIO), State Space (e.g., complex FSMs), and Concurrency (e.g., multi-clock domains). The output of this component is a structured Execution Plan (JSON), which defines the task decomposition and selects the appropriate routing strategy.
Arbiter to strictly verify the specific constraints anchored in the Spec against the simulation trace, it analyzes the Execution Logs against the Oracle Reference (the anchored specification) to resolve mismatches through four distinct routing paths: Syntax Repair: For compilation errors, the Arbiter extracts error signatures and triggers an implicit repair loop for Agent 2 or 3. • Design Refinement (Red Path): If a functional mismatch violates the specification, the Arbiter identifies the flaw in the DUT and directs Agent 2 to rectify the model logic. • TB Realignment (Blue Path): If the DUT aligns with the specification but the TB asserts a false failure, the Arbiter identifies the hallucination in the verification logic and directs Agent 3 to correct the TB. This path is critical for breaking the symmetry of shared hallucinations. • Success (Green Path): Once the Arbiter confirms functional equivalence, it outputs the Golden Model (verified SystemC and TB). •
B. Symbiotic Verification Loop
C. Spec Anchoring Context Management
Guided by the strategy defined in the Execution Plan, the framework enters the execution phase. The core execution engine, shown in Fig. 2B, employs a symbiotic relationship between generation and verification. This component addresses the Coupled Validation Failure by decoupling the modeling and verification responsibilities. 1) Dual-Generator Setup: The framework dispatches two concurrent tasks: the Modeler Agent (Agent 2) generates the SystemC Reference Model, while the Verifier Agent (Agent 3) constructs the TB. These components are integrated into a Simulation Environment for compilation and execution. 2) The Dialectical Mechanism: The Dialectical Arbiter (Agent 4) acts as the central authority. By prompting the
To support the long-turn reasoning required in verification loop, we implement an Optimization component to prevent Catastrophic Forgetting. As illustrated in Fig. 4, we partition the LLM’s context window into three segments to ensure 100% recall of the specification. The Anchor (Immutable): The initial Design Specification is pinned at the top of the context. It is never evicted during sliding window operations, serving as the constant Oracle Reference for Agent 4. • The Summary (Compressed): Historical interaction rounds are summarized into concise state representations, preserving the “reasoning chain” while saving token budget. •
Fig. 3. End-to-End Success Rate across different models and modes. RefEvo consistently outperforms baselines.
FixedTB: iterative refinement enabled, but TB modification is strictly forbidden. • RefEvo (Ours): The full framework with CoEvolutionary Verification enabled. For ground-truth validation, we employed a SystemVerilog DPI-based co-simulation framework. The generated SystemC models were compared against Golden RTL implementations under identical stimuli. •
B. Generation Capability Analysis
Fig. 4. Comparison of context management strategies. Spec Anchoring pins the specification as an immutable anchor and compresses historical logs, ensuring the Dialectical Arbiter always has access to the ground-truth oracle.
The Workspace (Dynamic): The most recent error logs and code snippets are placed here for active processing. This partitioning allows the Dialectical Arbiter to maintain a consistent truth standard throughout the co-evolutionary process, even as the interaction history grows. •
IV. E XPERIMENTS AND R ESULTS A. Experimental Setup We evaluated RefEvo on a benchmark of 20 hardware modules ranging from simple logic to complex protocols (e.g., AXI DMA, FFT, Keccak). The dataset was curated from opensource repositories including OpenCores [34], GenBen [35], and the XuanTie [36] RISC-V project. To ensure evaluation validity, all specifications were vetted by senior verification engineers. We tested five state-of-the-art LLMs, including Gemini2.5-Pro, GPT-5.1, GPT-4.1, Qwen3, and Claude-Opus-4.1. We compared four experimental modes to isolate the contributions of our framework: • Naive: One-shot generation without any verification loop. • Flow Only: Structured generation (Planning + Code Gen) without iterative refinement.
Fig. 3 illustrates the overall success rates. The Naive approach fails almost completely (0-10%) due to pervasive syntax errors and incomplete code structures. Flow Only improves structural correctness, raising the pass rate to 1535%, yet functional bugs persist. RefEvo achieves superior performance, with Gemini-2.5 and GPT-5.1 reaching a 95% pass rate. Notably, for Claude-Opus-4.1, our mode outperforms Flow Only by 70%. Complex modules like fpu div and keccak consistently fail in baselines but are successfully resolved in the RefEvo mode. C. Ablation Study: Mechanism Effectiveness To validate our verification strategy, we analyzed the failure distribution and the impact of Co-Evolutionary Verification (Fig. 5). 1) Impact of iterative refinement: In Naive/Flow modes, the dominant failure mode is Compile Fail. The introduction of the verification loop in FixedTB mode effectively eliminates these syntax errors, shifting the failure distribution towards Func Fail. 2) Impact of Co-Evolution: The comparison between FixedTB and RefEvo modes highlights the ”Coupled Validation Failure” problem. In FixedTB mode, functional failures persist because the agent is forbidden from modifying the TB. When Co-Evolution is enabled, the Func Fail rate drops significantly. This confirms that many failures were due to incorrect verification logic rather than flawed models, and our dialectical mechanism successfully resolved them. D. Methodological Robustness To assess whether our framework’s improvements are model-agnostic, we analyzed the performance trend across
Fig. 5. Failure distribution breakdown. The transition from Flow to FixedTB eliminates compilation errors, while the transition to RefEvo resolves functional mismatches via Co-Evolution.
Fig. 6. Methodological Robustness Analysis. The consistent upward trend across all models confirms that RefEvo effectively enhances generation reliability independent of the underlying LLM’s capability.
As shown in Fig. 7, our Spec Anchoring strategy achieves an average token reduction of 71.04% compared to the baseline. While the relative saving percentage peaks at 81.76% for medium-scale designs, it remains substantial (68.89%) for complex designs. The slight decrease in the savings ratio for the complex scenario is a deliberate architectural trade-off. To ensure 100% Specification Recall—defined as the ratio of critical design constraints correctly retained across interaction turns—RefEvo intentionally preserves the full-length initial specification as an immutable anchor. However, from the perspective of absolute efficiency, the benefit scales dramatically with complexity. RefEvo saves over 73,900 tokens in the complex scenario—nearly 10× more than in the simple case. Fig. 7. Token consumption comparison across Simple, Medium, and Complex design scales. RefEvo achieves an average reduction of 71.04%, with absolute savings scaling significantly for complex designs.
different LLMs. As shown in Fig. 6, despite the varying baseline capabilities of different models, the introduction of the RefEvo workflow consistently yields an upward trend in pass rates. This demonstrates that our method provides a robust enhancement component that effectively augments the capabilities of the underlying LLM. E. Efficiency Analysis: Context Compression To evaluate the scalability of our context management, we conducted controlled experiments across three design scales: Simple, Medium, and Complex.
V. C ONCLUSION This paper presented RefEvo, an agentic framework for agile reference model generation that bridges the gap between LLM capabilities and rigorous hardware verification standards. By integrating dynamic task planning with a co-evolutionary verification loop, RefEvo effectively addresses the challenges of semantic complexity and validation reliability. Our experiments demonstrate that the Dialectical Arbitration mechanism significantly mitigates “Coupled Validation Failure”, achieving a 95% success rate. Moreover, the Spec Anchoring strategy proves highly scalable, reducing token consumption by over 70%. RefEvo paves the way for fully automated, high-fidelity SoC verification, enabling a more efficient hardware-software co-design workflow.
ACKNOWLEDGMENTS This work is supported by the National Natural Science Foundation of China under NSFC (Grant No. 92464301), the National Key Research and Development Program (Grant No. 2024YFB4405600), and the Key Research and Development Program of Jiangsu Province (Grant No. BG2024010). R EFERENCES [1] A. Habibi and S. Tahar, “Design and verification of systemc transactionlevel models,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 1, pp. 57–68, 2006. [2] M. Abdollahi, S. F. Yeganli, M. Baharloo, and A. Baniasadi, “Hardware design and verification with large language models: A scoping review, challenges, and open issues,” Electronics (2079-9292), vol. 14, no. 1, 2025. [3] J. Ye, T. Liu, Q. Tian, S. Su, Z. Jiang, and X. Wang, “Chatmodel: Automating reference model design and verification with llms,” 2025. [Online]. Available: https://arxiv.org/abs/2506.15066 [4] A. Moursi, R. Samhoud, Y. Kamal, M. Magdy, S. El-Ashry, and A. Shalaby, “Different reference models for uvm environment to speed up the verification time,” in 2018 19th International Workshop on Microprocessor and SOC Test and Verification (MTV), 2018, pp. 67– 72. [5] H. D. Foster, “Trends in functional verification: A 2014 industry study,” IEEE, 2015. [6] P. Ghosh, S. Ghosh, P. Singh, and S. Mishra, “Case study: Re-visiting soc verification challenges and best practices,” IEEE, 2015. [7] M. Liu, T.-D. Ene, R. Kirby, C. Cheng, N. Pinckney, R. Liang, J. Alben, H. Anand, S. Banerjee, I. Bayraktaroglu et al., “Chipnemo: Domainadapted llms for chip design,” arXiv preprint arXiv:2311.00176, 2023. [8] H. Liu, Y. Lu, M. Wang, X. Yao, and B. Yu, “LLM-assisted circuit verification: A comprehensive survey,” in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), Hong Kong, 2026. [9] S. Liu, W. Xiao, Y. Li, D. Z. Pan, and Z. Hu, “Rtlcoder: Fully opensource and efficient llm-assisted rtl code generation technique,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024, arXiv:2312.08617. [10] T. Liu, Q. Tian, J. Ye, L. Fu, S. Su, J. Li, G.-W. Wan, L. Zhang, S.-Z. Wong, X. Wang, and J. Yang, “Chatchisel: Enabling agile hardware design with large language models,” in 2024 2nd International Symposium of Electronics Design Automation (ISEDA), 2024, pp. 710–716. [11] J. Niu, X. Liu, D. Niu, X. Wang, Z. Jiang, and N. Guan, “Rechisel: Effective automatic chisel code generation by llm with reflection,” in 2025 62nd ACM/IEEE Design Automation Conference (DAC). IEEE, 2025, pp. 1–7. [12] X. Wang, G.-W. Wan, S.-Z. Wong, L. Zhang, T. Liu, Q. Tian, and J. Ye, “Chatcpu: An agile cpu design and verification platform with llm,” in Proceedings of the 61st ACM/IEEE Design Automation Conference, ser. DAC ’24. New York, NY, USA: Association for Computing Machinery, 2024. [Online]. Available: https://doi.org/10.1145/3649329.3658493 [13] S. Thakur, B. Ahmad, Z. Fan, H. Pearce, B. Tan, R. Karri, B. DolanGavitt, and S. Garg, “Benchmarking large language models for automated verilog rtl code generation,” arXiv preprint arXiv:2212.11140, 2022. [14] H. M. Le, V. Herdt, D. Große, and R. Drechsler, “Towards formal verification of real-world systemc tlm peripheral models - a case study,” IEEE, 2016. [15] J. Li, G. Li, C. Tao, J. Li, H. Zhang, F. Liu, and Z. Jin, “Large language model-aware in-context learning for code generation,” 2023. [16] S. Kim, S. Joo, D. Kim, J. Jang, S. Ye, J. Shin, and M. Seo, “The cot collection: Improving zero-shot and few-shot learning of language models via chain-of-thought fine-tuning,” Proceedings of the 2023 Conference on Empirical Methods in Natural Language Processing, 2023. [17] S. Qamar, W. H. Butt, M. W. Anwar, F. Azam, and M. Khan, “A comprehensive investigation of universal verification methodology (uvm) standard for design verification,” Proceedings of the 2020 9th International Conference on Software and Computer Applications, pp. 339–343, 2020.
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