HAL Science
metadata only
Modelling and Simulation of the IR-Drop phenomenon in integrated circuits
Scaling technology in deep-submicron has reduced the voltage supply level and increased the number of transistors in the chip, increasing the power supply noise sensitivity of the ICs. Excessive power supply noise affects the timing performance increasing the gate delay and may cause timing faults.
Conceptio Open Archive
Analyze & explore related research in Conceptio
Connect this record directly into your research workflow or AI agent. Explore citations across open repositories, query full text, and export structured proof bundles.
This document is indexed with metadata only: full text is not available in the archive for this record. Open the official source ↗
Related documents
- A simple model of EMI-induced timing jitter in digital circuits, its statistical distribution and its effect on circuit performance#444202
- Noise and small-signal modeling of nanoscale MOSFETs#1394401
- Enhanced thermal stability of SiGeSn by suppressing surface-mediated degradation#1013721
- Integrated broadband optical isolator via dynamic rotating destructive interference#1386197
- A Reliable Release Method for A Back-End-Of-Line Nems Switch of A Monolithic Three-Dimensional Integrated Cmos-Nems Circuit#464510
Record · ID 1425702
Retrieved via Conceptio: every document is proof-bundled with source, license, and retrieval metadata.
Retrieved via Conceptio: every document is proof-bundled with source, license, and retrieval metadata.
Bring this data into your agent: Connect via MCP or API · 20 free credits to start · no card required
Read the Docs → · View CLI source on GitHub · Conceptio Open Knowledge Archive
Read the Docs → · View CLI source on GitHub · Conceptio Open Knowledge Archive