arXiv (All)
open access
AnalogPortBench: Benchmarking LLMs on Analog Circuit Porting
Analog circuit design still relies heavily on expert knowledge, and porting proven designs to new process nodes is a recurring bottleneck. As a lower supply reduces available voltage headroom, a working topology may require redesign or fail to meet specifications. While large language models (LLMs)
Conceptio Open Archive
Analyze & explore related research in Conceptio
Connect this record directly into your research workflow or AI agent. Explore citations across open repositories, query full text, and export structured proof bundles.
This document is indexed with metadata only: full text is not available in the archive for this record. Open the official source ↗
Related documents
- Multi-LLM Orchestration for High-Quality Code Generation: Exploiting Complementary Model Strengths#1355937
- PLSQLBench: Benchmarking LLM Systems for Executable Procedural Database Programming#617052
- PLSQLBench: Benchmarking LLM Systems for Executable Procedural Database Programming#616552
- Rosetta: Automating First-Principles Performance Modeling Using Multi-Agent LLMs#1013972
- ProcArena: A Multi-Scenario Benchmark for LLMs on Direct and Interactive PL/SQL Development from Natural Language#673625
Record · ID 1455569
Retrieved via Conceptio: every document is proof-bundled with source, license, and retrieval metadata.
Retrieved via Conceptio: every document is proof-bundled with source, license, and retrieval metadata.
Bring this data into your agent: Connect via MCP or API · 20 free credits to start · no card required
Read the Docs → · View CLI source on GitHub · Conceptio Open Knowledge Archive
Read the Docs → · View CLI source on GitHub · Conceptio Open Knowledge Archive