RecIS: Unifying Sparse and Dense Computation for Efficient Recommendation Training

RecIS: Unifying Sparse and Dense Computation for Efficient Recommendation Training Author version. Accepted to FRecSys 2026 (ACM SIGOPS ATC 2026). Hua Zong1,*† , Shuai Yang2,† , Zhengxiong Zhou1 , Qingtao Zeng1 , Jiawei Liu1 , Hao Wan1 , Hongbin Zhou1 , Jiahao Wang1 , Hao Zhang1 , Bencheng Yan1 , Yuheng Huang1 , Huimin Yi1 , Jiamang Wang1 , Han Zhu1 , Jian Xu1 , Bo Zheng1 , Lin Qu1 1

arXiv:2610.41457v1 [cs.DC] 30 Oct 2026

2

Alibaba Group University of Chinese Academy of Sciences China

{yuhuan.zh,zhouzhengxiong.zzx,zengqingtao.zqt, lanling.ljw,wanhao.wh,hongbin.zhouhb,wjh177423, zh138764,huimin.yhm,jiamang.wang,zhuhan.zh, bozheng}@alibaba-inc.com {bencheng.ybc,hexing.hyh,xiyu.xj,xide.ql}@taobao.com, yangshuai2022@iscas.ac.cn

Abstract

Keywords

Modern recommender models scale sparse representations and dense computation together. They process thousands of heterogeneous feature fields, long user-behavior sequences, and trillion-scale Embedding parameters, while their dense networks increasingly use large Transformer architectures. The resulting execution mismatch creates fine-grained operations within stages, load imbalance and synchronization delays across devices, and GPU resource bubbles between stages. As models grow, these costs become a primary limit to scalable recommender training. Although existing systems improve Embedding caching and data prefetching, these inefficiencies still coexist in the GPU-centric workloads we study and jointly limit end-to-end throughput. We present RecIS, a unified framework for GPU-centric recommender training. RecIS treats the complete path from input features to dense computation as one optimization target and coordinates three complementary mechanisms. First, adaptive fusion combines fragmented feature transformations with vectorized memory access. Second, a GPU Embedding engine uses hash-based sharding and hierarchical communication to balance request placement and eliminate redundant transfers; it also specializes aggregation for forward and backward index structures. Third, a multistage pipeline overlaps input preparation for future iterations with dense computation in the current iteration. Together, these mechanisms reorganize a fragmented sparse front end into a dataflow that continuously feeds dense computation. We evaluate RecIS on representative industrial recommender models across distributed training platforms. Compared with PICASSO and TorchRec, RecIS reaches up to 2.62× and 1.15× their throughput, respectively, while reducing step latency by up to 61.5% and 12.9%. RecIS provides an efficient and scalable training system for large recommender models.

Recommender systems, GPU training, Embedding communication, Operator fusion, Pipeline scheduling

1 Introduction Modern recommender training places two nearly opposite execution paradigms on the same GPU dataflow. The sparse front end processes thousands of heterogeneous feature fields, long behavior sequences, and trillion-scale embedding parameters through fragmented transformations, random lookups, and irregular communication [2, 17, 28]. The dense back end is evolving toward billionparameter Transformers and sparse mixture-of-experts models [6, 20, 26, 27] that require regular, continuous, and compute-intensive tensor pipelines. As both sides scale, the central systems challenge is no longer to accelerate sparse or dense components in isolation. It is to reorganize fragmented, skewed, and unevenly arriving sparse work into a stable stream that continuously feeds dense computation. This mismatch creates a chain of bottlenecks whose effects compound along the dataflow. Thousands of variable-length transformations decompose input processing into small kernels and scattered memory accesses. Skewed feature accesses further create imbalanced embedding lookups and all-to-all communication, allowing the slowest device to determine the iteration time. Coarse iteration boundaries finally expose sparse-side tail latency to the dense network, leaving compute, memory, and communication resources idle in turn. In other words, task granularity determines sparse execution efficiency, device load determines its tail latency, and iteration scheduling determines whether that latency can be hidden by dense computation. Existing systems improve operator packing, embedding caching, or data prefetching [3, 10, 18, 28], but these mechanisms are generally designed around a particular stage or a fixed execution boundary. When the three problems occur together, accelerating one stage can simply move the bottleneck to the next point in the dataflow. We present RecIS, a unified framework for GPU-centric recommender training. RecIS treats the path from raw features to dense computation as a schedulable dataflow and reorganizes sparse work at three connected levels:

CCS Concepts • Information systems → Recommender systems; • Computer systems organization → Heterogeneous (hybrid) systems; • Computing methodologies → Parallel computing methodologies; • Software and its engineering → Runtime environments. ∗

Corresponding author: Hua Zong (yuhuan.zh@alibaba-inc.com). Both authors contributed equally to this work.

†

1

Zong et al.

2.2

Repeated Requests and Embedding Imbalance

Embedding accesses are highly skewed. Popular IDs recur both within and across GPUs, amplifying lookup and communication work. Even a balanced distribution of stored parameters need not yield a balanced distribution of requests. Table-wise and contiguous row-wise sharding place parameters by table size or ID range, which need not match the access distribution of a particular batch [10, 14, 28]. Unequal lookup and all-to-all traffic loads leave dense computation waiting for the slowest device. Aggregation remains expensive after requests reach their owners. Forward outputs follow ordered compressed sparse row (CSR) segments defined by offsets, whereas backward contributions can target embedding rows in an arbitrary and highly concentrated order. Using the same element-wise atomic scatter for both paths introduces unnecessary forward atomics and contention at popular rows during backward execution. The embedding engine must therefore address request imbalance, duplicate accesses, and indexdependent aggregation costs together.

Figure 1: A profiling timeline exposes fragmented featurepreprocessing work and frequent kernel launches.

• Across operators. Adaptive fusion regularizes task granularity by grouping compatible transformations across fields into fewer CUDA kernels while preserving dependencies. Vectorized memory access reduces instruction overhead and improves bandwidth utilization. • Across devices. Hash-based sharding distributes ownership of distinct IDs across workers in expectation. Hierarchical communication merges requests within each source node to reduce inter-node traffic, then deduplicates requests at each owner to reduce physical lookups. Index-aware aggregation reduces irregular memory access and atomic contention. • Across iterations. The multistage pipeline overlaps future input preparation that is independent of parameter updates with current dense computation, using their complementary resource demands to hide sparse-side overhead.

2.3

Idle Time at Iteration Boundaries

Training systems commonly organize execution around fixed iteration boundaries. Even with prefetching or local communication overlap, input I/O, feature processing, embedding operations, and dense computation often follow a largely sequential schedule. Our profiling shows that these stages stress different resources. Executing them in sequence leaves compute, memory, and I/O resources idle at different points in the iteration. Some of this idle time comes from scheduling constraints rather than data dependencies. Work independent of parameter updates can begin before the current iteration finishes. However, prefetching a single batch is insufficient when preparation exceeds the available overlap window, and unrestricted background execution can interfere with dense kernels. Effective scheduling must expose more parallelism while preserving parameter consistency and controlling contention.

Together, these mechanisms reduce sparse-stage overhead and overlap the remaining preparation work, allowing the sparse front end to feed dense computation more continuously. The source code of RecIS is publicly available at https://github.com/alibaba/recis.

2 Background and Motivation 2.1 Feature-Preprocessing Bottlenecks

3 RecIS System Design

GPU-centric training systems increasingly move feature preprocessing from CPUs to GPUs [18, 28]. Offloading hashing, bucketization, and sequence truncation does not by itself ensure high throughput. Production models contain thousands of heterogeneous feature fields, each with a chain of two to five preprocessing operations. Executing each field independently launches many short kernels, whose launch and scheduling overhead can exceed their useful computation (Figure 1). Fusion reduces these costs, but feature fields differ in both operator dependencies and sequence lengths. Small fusion groups leave substantial launch overhead, whereas overly coarse groups can introduce divergence and long-running tasks. Effective fusion must therefore account for both the operator structure and the distribution of input sizes. Memory access presents a separate constraint. Hashing and modulo operations have low arithmetic intensity and are often limited by global-memory bandwidth [25]. Scalar accesses add memory instructions and can underutilize the bandwidth available to contiguous, aligned transfers.

RecIS jointly optimizes feature preprocessing, distributed embedding operations, and pipeline scheduling. Each component reduces overhead that would otherwise delay the next stage of the sparseto-dense dataflow.

3.1

Fused and Vectorized Feature Processing

FeatureEngine addresses kernel-launch overhead, work imbalance across feature fields, and inefficient scalar memory access. Dependency-aware fusion. Feature fields differ in both their transformation chains and input lengths. Small fusion groups retain substantial launch overhead, whereas overly coarse groups can introduce divergence and long-running tasks. FeatureEngine therefore fuses independent operations of the same category while preserving the dependencies of each feature. The transformations in Figure 2 include bucketization, modulo, hashing, sequence truncation, and masking. The scheduler first topologically orders these operations. For example, SeqTrunc must 2

Input

Feature 1

Transform

RecIS: Unifying Sparse and Dense Computation for Efficient Recommendation Training

Hash

Feature 2 Feature 3

Hash

Feature 4

Feature 5 ... Feature n

SeqTrunc

SeqTrunc

Bucket Hash

...

Bucket

Bucket

In summary, FeatureEngine regularizes feature preprocessing through these three complementary mechanisms, consolidating thousands of heterogeneous transformation chains into a small set of regular, high-throughput GPU kernels. This design improves data preparation for subsequent embedding lookups and pipelined execution across stages.

N Features

N+ operations

a) Fragmentary feature transformation operators

Executor

Sort & Fuse

Feature Context

FusedSeqTrunc Fea 4 / Fea 5

FusedHash Fea 1 / Fea 2 / Fea 4

3.2

FusedBucket Fea 3 / Fea 5 / Fea n

Output Fea 1,..., n

Hash-based sharding. Balanced storage need not imply balanced requests: table-wise and contiguous row-wise placement can concentrate popular tables or ID ranges. RecIS hashes IDs to spread ownership across workers in expectation, reducing this dependence on table size or ID range. Sharding distributes distinct IDs; repeated requests for the same ID still require deduplication.

b) Fused feature transformation operators

Figure 2: FeatureEngine preserves operator dependencies while fusing compatible transformations across feature fields. finish before Hash for Feature 4. Independent operations from other fields can join the same fusion group when they are of a compatible category. Fusion thus shares execution across fields without reordering a dependent transformation ahead of its input. For 𝐹 feature fields, let 𝑑𝑖 be the number of operations on field 𝑖 and 𝒢 the resulting fusion groups. The kernel-launch counts satisfy 𝐹

𝐾RecIS = |𝒢| ≤ 𝐾base = ∑ 𝑑𝑖 .

Embedding Engine with Hierarchical Communication

(1)

𝑖=1

Each group replaces multiple launches when fields share compatible transformations; otherwise, the inequality allows equality. Thread mapping for skewed inputs. Fusion exposes more work to each kernel, but equal treatment of feature fields would not imply equal work for threads. Long behavior sequences can contain many more elements than short categorical fields. Static assignment by field would carry this skew into the fused kernel, leaving some threads idle while others process long sequences. FeatureEngine flattens elements across fields into one logical index space and partitions it into equally sized tiles. A grid-stride mapping distributes these tiles to threads, which use feature-boundary indices to locate the corresponding input intervals. Work is therefore divided by element count rather than by the number of fields. This mapping reduces idle threads and limits the execution tail of long inputs without changing the transformation assigned to each element. Vectorized memory access. Fusion does not by itself eliminate memory-instruction overhead. Hashing and modulo have low arithmetic intensity and are often limited by memory bandwidth [25]. Element-wise operators use fixed-width vector loads and stores where dependencies, alignment, and boundaries permit. Packed kernels process groups of elements; select_pack_size selects the largest valid pack at compile time, with up to 16 bytes accessed per thread per memory instruction. Smaller valid packs accommodate stricter alignment or boundary constraints. Contiguous, aligned transfers reduce instruction count and improve effective bandwidth.

Hierarchical communication. Flat communication (Figure 3(a)) deduplicates IDs per GPU but still sends separate requests for IDs shared across GPUs. RecIS merges these requests within each source node over NVLink, routes them to their owners over same-rail links, and distributes each returned vector locally to the requesting GPUs. Figure 3(b) shows the forward path. Each deduplication stage retains an inverse map for restoring the original requests. ¬ Local Reduce-ID: each GPU removes duplicate IDs from its local requests. ­ Intra Shuffle-Reduce-ID: NVLink routes requests to the sourcenode GPU with the same local GPU index as the owner, where duplicates from different GPUs are merged. ® Inter Shuffle-ReduceID: same-rail groups connect corresponding GPUs across nodes and route remote requests to their owners, which merge duplicates from all source nodes. ¯ Lookup Embed: each owner performs one lookup per unique ID in its local shard. ° Inter Flatten-ShuffleEmbed: the inverse map from step ® expands responses for return over the same rails, with one vector per ID per remote source node. ± Intra Flatten-Shuffle-Embed: the inverse map from step ­ expands vectors for NVLink delivery to the requesting GPUs. ² Local Flatten-Embed: the inverse map from step ¬ restores the original request order and multiplicity. To compare traffic, consider one embedding table and the same batch, sharding, and GPU-local deduplication in both modes. There are 𝑁 nodes with 𝑀 GPUs each. Let 𝐼𝑛,𝑚 be the set of unique IDs requested by GPU 𝑚 on node 𝑛 whose owners reside on other nodes, 𝑀−1 and let 𝐼𝑛 = ⋃𝑚=0 𝐼𝑛,𝑚 . Counting each logical inter-node transfer once, with one vector returned per request, gives

𝑁 −1 𝑀−1

𝑆𝑖flat = 𝑆𝑒flat = ∑ ∑ |𝐼𝑛,𝑚 |, 𝑛=0 𝑚=0

𝑁 −1

𝑆𝑖hier = 𝑆𝑒hier = ∑ |𝐼𝑛 |. 𝑛=0 3

(2)

Zong et al.

8002 8002 5130 5130 7003

⑤ Local Flatten-Emb.

Node 1

② Inter Shuffle ID. ( )

GPU 0

④ Inter Shuffle-Emb. ( )

GPU 1

a) Flat Communication Mode

shard

5130 5130 5130 7003 6100 7003 6100

8002 8002 5130 5130 7003

Emb.

① Local Reduce Reduced ids

w/ NVLink

④ lookup Emb. Emb.

⑦ Local Flatten-Emb. ⑥ Intra FlattenOutput ShuffleEmb.

⑤ Local Flatten-Emb. Output

NIC

shard

④ lookup Emb.

Queried ids

shard ⑦ Local Flatten-Emb.

Output

③ Inter Shuffle ID. ( ⑤ Inter Flatten-Shuffle-Emb. (

5130 5130 5130 7003 6100

Emb.

Reduced ids

1: Forward: CSR-guided reduction 2: for all output feature packs (𝑠, 𝑝) in parallel do 3: a←0 4: for 𝑟 = 𝑜𝑠 to 𝑜𝑠+1 − 1 do 5: a ← a + 𝑤𝑟 E[𝑖𝑟 , 𝑝] 6: end for 7: Y[𝑠, 𝑝] ← a 8: end for

GPU 1

8002 8002 5130 5130 7003

shard

Output

Node 0

③ lookup Emb.

Node 1

Emb.

5130 7003 6100

① Local Reduce Reduced ids

③ lookup Emb.

Queried ids

Algorithm 1 Index-aware Segment Reduction

Embedding

② Intra Shuffle ID ① Local Reduce & Unique

5130 5130 5130 7003 6100

Reduced ids

8002 5130 7003

Node 0

① Local Reduce

ID Query GPU 0

5130 5130 5130 7003 6100

Queried ids

7003

8002 8002 5130 5130

Queried ids

Local Processing

GPU 1

8002 5130

NVLink

NIC GPU 0

) )

w/ Same Rail

9: Backward: Wave-level duplicate merging 10: Initialize ∇E ← 0 11: for all GPU waves 𝜔 in parallel do 12: Assign one lane group to each contributor 𝑟 13: Load 𝑤𝑟 G[𝑠(𝑟), ∶] into lanes 14: Match identical destination IDs 𝑖𝑟 15: for all distinct destination IDs 𝑢 in 𝜔 do 16: a𝑢 ← ∑𝑟∈𝜔∶ 𝑖𝑟 =𝑢 𝑤𝑟 G[𝑠(𝑟), ∶] 17: Elect one leader row group 18: for all features 𝑑 assigned to leader lanes do 19: atomicAdd(∇E[𝑢, 𝑑], 𝑎𝑢,𝑑 ) 20: end for 21: end for 22: end for

②

GPU 0 ⑥

▷ Unique writer

GPU 1

b) Hierarchical Communication Mode

Figure 3: Flat and hierarchical embedding communication. 𝑆𝑖 counts IDs sent across nodes; 𝑆𝑒 counts embedding vectors returned. The reduced IDs in (b) are the result of steps ¬ and ­; step ® also deduplicates requests at the owner.

Let 𝐺𝑛 (𝑥) = |{𝑚 ∣ 𝑥 ∈ 𝐼𝑛,𝑚 }| be the number of GPUs on node 𝑛 requesting ID 𝑥 . The reduction in each type of transfer is then redistribute values through shuffle operations to enable coalesced feature-wise updates. Within each wave, row groups with identical destination IDs are identified and their contributions are reduced using lane shuffles. Only the leader row group performs atomic additions for the merged feature values. For 𝑘 contributions targeting the same row within a wave, this reduces the number of scalar atomic updates from 𝑘𝐷 to 𝐷 . Contributions targeting the same row across different waves or thread blocks are still combined through global atomics, preserving correctness without sorting destination indices.

Δ𝑆 = 𝑆𝑖flat − 𝑆𝑖hier = 𝑆𝑒flat − 𝑆𝑒hier 𝑁 −1

= ∑ ∑ (𝐺𝑛 (𝑥) − 1) ≥ 0.

(3)

𝑛=0 𝑥∈𝐼𝑛

Thus, step ­ replaces 𝐺𝑛 (𝑥) inter-node requests and returned vectors with one of each. Owner-side deduplication in step ® reduces physical lookups, but cannot remove transfers that have already occurred. Index-aware segment reduction. Restoring gathered embeddings to the original ragged layout requires weighted segment aggregation. Let E ∈ ℝ𝑈 ×𝐷 denote the unique embedding matrix, o the CSR offsets defining 𝑆 segments, i the reverse indices mapping 𝑁 contributions to embedding rows, and w their weights. Although forward and backward share the same reduction semantics, their destination indices exhibit different access patterns, motivating specialized GPU kernels. Algorithm 1 outlines their execution workflows. Forward. The CSR offsets define a contiguous contributor range [𝑜𝑠 , 𝑜𝑠+1 ) for each output segment 𝑠 . RecIS directly traverses these 𝑜𝑠+1 −1 ranges and computes Y𝑠,∶ = ∑𝑟=𝑜 𝑤𝑟 E𝑖𝑟 ,∶ . Each thread owns 𝑠 one or more non-overlapping feature packs of an output segment, gathers the corresponding embedding values, and accumulates the weighted sum in registers. Once the segment is processed, the thread commits its result through a vectorized store. Even when embedding IDs repeat within a segment, all contributions to each output element are handled by its unique writer. Empty segments produce zero. This ownership-based mapping eliminates global atomic operations and their associated read-modify-write traffic. Backward. In contrast, backward scatters gradients to embedding rows indexed by i, whose entries may appear in arbitrary order and contain highly frequent duplicates. Each contributor 𝑟 generates 𝑤𝑟 G𝑠(𝑟),∶ , where 𝑠(𝑟) is its forward segment ID and G is the output gradient. RecIS assigns a group of GPU lanes to each contributor row. Lanes cooperatively load contiguous feature packs,

3.3

Multistage Pipeline Execution

Fixed iteration boundaries can serialize input preparation with dense computation even after the feature and embedding engines reduce sparse-stage costs. A largely sequential schedule leaves different resources idle at different times. The multistage pipeline in RecIS begins independent work earlier while preserving the dependencies of parameter access and updates. Resource demands and dependencies. Two observations guide scheduling. First, stages stress different resources. Input I/O uses host processing and interconnect bandwidth; feature transformations and request formatting mainly consume memory bandwidth; physical embedding lookup accesses device memory; and dense forward and backward passes mainly use Tensor Core computation. Overlapping these partly complementary demands can use otherwise idle capacity. Second, iteration boundaries can impose waits beyond those required by training semantics. RecIS restricts asynchronous crossiteration preparation to modules that do not participate in backpropagation and do not depend on parameter values updated by the current iteration. Input loading, feature transformation, and ID request formatting satisfy these conditions and can proceed before the current update finishes. Physical embedding lookup, dense forward and backward computation, and all parameter updates remain in the main training workflow with their original ordering 4

RecIS: Unifying Sparse and Dense Computation for Efficient Recommendation Training

CPU & IO Intense

Bandwidth Intense

PRE_ Default SPARSE_ DENSE_ OPTIM_ METRICS BACKWARD STEP stream FORWARD FORWARD FORWARD

PRE_ FORWARD

step t

CPU+PCIe HBM BW Tensor Cores

Group Stream 0 / thread 0 Group Stream 1 / thread 1 CPU+PCIe HBM BW Tensor Cores

...

step t + 1

idle bubble

Ad Search Lazada Ad

idle bubble

SPARSE_ DENSE_ METRICS BACKWARD FORWARD FORWARD

OPTIM_ STEP

step t Data IO Feature Trans Emb Format & (step t+1) (step t+1) Part. (step t+1)

Logical emb. Input features tables

Model

idle bubble

(a) Serial Execution (Baseline) Default stream

Table 1: Statistics of the evaluated recommender models.

Computation Intense

saved time

879 589 367

519 398 73

Batch / device

Embedding dimensions

1,200 8–128 256 4–128 1,024 4–416

Device Type

Nodes × devices/node

PPU 810e H20 L20

6 × 16 8×8 1×8

SPARSE_ ... FORWARD step t + 1

policy to limit interference while exploiting otherwise idle capacity. Stage count and overlap topology provide controls for different workloads; the appropriate schedule depends on preparation time relative to the available overlap window. The pipeline hides preparation work that remains after feature and embedding optimization, while retaining the order required for parameter-dependent computation.

cross-step dependendcy

Data IO Feature Trans Emb Format & (step t+2) (step t+2) Part. (step t+2)

cycles

reduced idle bubble

(b) Multi-stage pipeline

Figure 4: Multistage scheduling overlaps future input preparation with current dense computation while preserving dependencies.

4 Evaluation We evaluate end-to-end throughput and step latency, then examine feature fusion, hierarchical request merging, index-aware segment reduction, and multistage scheduling.

dependencies. In particular, preparation does not prefetch embedding values. The next iteration reads them only after the preceding updates on which it depends have completed. This separation preserves parameter-access and update semantics while allowing independent preparation to overlap training.

4.1

Experimental Setup

We evaluate three industrial recommender models on distributed training infrastructure: Ad and Lazada Ad for advertising ranking, and Search for search ranking. Table 1 summarizes their input features, logical embedding tables, embedding dimensions, and perdevice batch sizes. Ad runs on 96 PPUs, Search on 64 NVIDIA H20 GPUs, and Lazada Ad on 8 NVIDIA L20 GPUs. For each model, all compared systems use the same hardware and training configuration. We compare RecIS with PICASSO [28] and TorchRec [10]. For each model, all three frameworks use the same hardware, model, batch size, numerical precision, and optimizer configuration, including learning rates. End-to-end performance values are averaged across repeated runs to reduce the influence of run-to-run variability

Stage decomposition and scheduling. We divide each iteration into six stages: SPARSE_FORWARD, DENSE_FORWARD, METRICS_OP, BACKWARD, OPTIM_STEP, and PRE_FORWARD. SPARSE_FORWARD performs physical embedding lookups. PRE_FORWARD contains input I/O, feature transformations, and embedding request formatting and partitioning. Stage descriptors distinguish this preparation from the parameter-dependent training path. Figure 4 shows the resulting schedule. Iteration 𝑡 follows its dependency order on the default stream. Independent preparation for subsequent iterations runs in a separate asynchronous workflow, the Group Stream, alongside compatible current-iteration stages. For example, input loading, feature transformations, and request formatting for iteration 𝑡 + 1 can overlap DENSE_FORWARD of iteration 𝑡 . The prepared requests then feed SPARSE_FORWARD when its parameter dependencies are satisfied. The overlap pattern is configurable to suit the dependencies and resource demands of each model.

4.2

End-to-End Performance

Figure 5 reports throughput per GPU and step latency. RecIS achieves the highest throughput and lowest latency on all three workloads. It delivers 1.04–1.15× the throughput of TorchRec with 3.9%–12.9% lower step latency, and 1.48–2.62× the throughput of PICASSO with 32.3%–61.5% lower latency. These results establish the end-toend benefit of the combined system; the component experiments examine the underlying reductions in sparse work and exposed latency. RecIS reaches 924 IPS at 1,299 ms per step on Ad, 1,268 IPS at 202 ms on Search, and 2,058 IPS at 498 ms on Lazada Ad. These workloads use different deployment scales, so comparisons use a fixed training configuration for each model. The maximum gain over PICASSO occurs on Search, whereas the largest relative gain over TorchRec occurs on Ad.

Preparation depth and contention. Preparation time varies with the model and input. Prefetching a single batch is insufficient when this work exceeds the available overlap window: the unhidden remainder still delays the next iteration. RecIS supports multiple preparation stages that distribute work across threads and asynchronous streams. Figure 4 illustrates preparation for successive iterations in separate Group Stream workflows, allowing preparation to extend beyond the overlap window of a single iteration. More concurrency is useful only when contention remains manageable. Background kernels can compete with dense kernels for execution resources and memory bandwidth even when the dense computation is dominated by Tensor Core GEMMs. Asynchronous streams therefore use the conservative StreamPriority.DEFAULT

4.3

Training Loss and AUC

To evaluate whether RecIS’s optimizations affect model accuracy, we compare its training behavior against TorchRec using the Search 5

Zong et al.

TorchRec

2000

2000

1500

1500

1000

1000

500

500

0

Lazada Ad Search

Ad

Table 2: Preprocessing operator invocations before and after cross-field fusion.

RecIS

Lazada Ad Search

Ad

Step time (ms)

Throughput (IPS)

PICASSO

Model Ad Search Lazada Ad

0

Baseline

RecIS

Reduction

1,351 1,071 688

79 158 136

94.15% 85.25% 80.23%

Step time (ms)

Step time

Figure 5: End-to-end throughput per GPU and step latency for PICASSO, TorchRec, and RecIS on three industrial workloads. RecIS

Training loss

0.75 0.8 0.65

0.7

0.55

0.6

0.45

0.5 0

2,500

5,000 0

2,500

5,000

Cumulative training AUC

TorchRec

909

3000 2000 1320

1414

IPS

1000

3115

848

763 1573

716 2591 1675

463

385

500

1000 0 l Fu

e e d d cy se ze od ag st line den sion tori ess -ba ing a-n ing i t ul ipe en Fu ec Acc ash ard ntr erg I M M P ep e V h /o D ar w/o ory /o H S w/o est w /o aw u em w q w M Re

0

IPS (instances/s)

Model

IS ec lR

Figure 7: Single-node cumulative ablation on Ad with eight H20 GPUs. From left to right, each configuration additionally disables the named optimization. Request merging denotes intra-node ID deduplication.

Recorded training step

Figure 6: Training loss and cumulative AUC of the Search model under TorchRec and RecIS.

908.76 IPS at 1,320.48 ms per step. Overall, RecIS achieves 2.36× the baseline throughput and reduces latency by 57.6%. Dependency-aware fusion. Table 2 reports preprocessing operator invocations before and after cross-field fusion. Counts fall model. Both systems are trained from scratch for 5,000 steps unfrom 1,351 to 79 on Ad, from 1,071 to 158 on Search, and from 688 to der identical hyperparameters, including a per-device batch size 136 on Lazada Ad: reductions of 94.15%, 85.25%, and 80.23%, respecof 256, a sparse learning rate of 0.01, and a dense learning rate of tively. Across the three models, fusion reduces 3,110 invocations to 10−5 . TorchRec runs on 32 NVIDIA H20 GPUs, while RecIS runs 373, an 88.01% reduction. Fewer invocations reduce the launch and on 32 PPU 810e accelerators. scheduling overhead addressed by FeatureEngine. Figure 6 compares the training loss and cumulative AUC of both Hierarchical communication. To evaluate the effectiveness systems. The loss is averaged across all 32 ranks at each sampled of hierarchical communication, we compare its communication trafstep, while the AUC is computed from globally aggregated statisfic and overhead against Flat communication using an advertistics accumulated throughout training. Both systems exhibit simiing model deployed on 16 nodes with 128 accelerators. Both aplar training trends, with decreasing loss and increasing AUC. At proaches use identical configurations except for the communicatheir respective final recorded points, TorchRec and RecIS achieve tion strategy. Table 3 reports the average per-step communication training losses of 0.441442 and 0.441274, and cumulative AUCs costs across all ranks for three representative embedding tables. of 0.824599 and 0.824424, respectively. These closely matched reCompared with Flat, Hierarchical reduces inter-node embedding sults indicate that RecIS’s optimizations preserve training accuracy traffic by 59.34%, 72.37%, and 31.71%, respectively, with correspondwithout observable degradation compared to TorchRec. ing retained ID fractions of 40.71%, 27.65%, and 68.36%. These reductions are achieved by merging redundant embed4.4 Component Analysis ding requests within each source node before inter-node communication (Eq. 3). However, Hierarchical introduces additional overCumulative ablation. We evaluate successive configurations of Ad on a single server with eight H20 GPUs (Figure 7). Starting from head from intra-node embedding redistribution and ID partitionthe configuration with all studied optimizations disabled, intra-node ing. Consequently, its performance benefit depends on whether request merging and hash-based sharding raise throughput from the inter-node communication savings outweigh these additional 385.19 to 716.26 IPS and reduce step latency from 3,115.36 to 1,675.38 ms, costs. a 46.2% reduction. Vectorized access and dependency-aware fusion The timing breakdown further illustrates this trade-off. For the further increase throughput to 848.37 IPS and reduce latency to FP32 embedding table with dimension 32, Hierarchical reduces inter1,414.48 ms. With these optimizations enabled, the multistage pipeline node communication time from 76.695 ms to 30.487 ms, while inremoves another 94 ms and raises throughput by 7.1%, reaching troducing 5.405 ms of intra-node embedding communication and 6

RecIS: Unifying Sparse and Dense Computation for Efficient Recommendation Training

Flat emb traffic (GB) Hier inter emb traffic (GB) Retained IDs (%)

2.976 1.210 40.71

215.590 59.568 27.65

193.013 131.806 68.36

Flat emb time (ms) Hier intra emb time (ms) Hier inter emb time (ms) Hier extra processing (ms)

2.031 0.088 1.203 0.851

76.695 5.405 30.487 5.262

69.227 5.003 53.622 5.487

102

2 D=16

3 D=32

4 D=128

1 D=8

3 D=32

4 D=128

2.97x

4.45x

4.10x 3.45x

1 D=8

(a) Forward

2 D=16

(b) Backward

Figure 8: Index-aware segment reduction on AMD MI308X. 𝐷 is the embedding dimension; annotations show speedup over the original kernels.

Scheduling complements these optimizations by overlapping preparation and training. RAP co-schedules GPU preprocessing and training [22], while Bagpipe uses future minibatches to prefetch embeddings [3]. PICASSO coordinates embedding-operation packing, interleaved execution, and hierarchical caching [28]. GPipe and PipeDream pipeline model stages across devices [9, 16]. RecIS pipelines preparation across iterations: parameter-independent feature processing and request preparation overlap current dense computation, while parameter accesses and updates retain their required ordering.

5.262 ms of additional ID partitioning. In contrast, for the smaller FP32 table with dimension 16, the combined embedding communication time is 1.291 ms, only 0.740 ms lower than Flat, while the additional ID partitioning takes 0.851 ms. These results demonstrate that reducing inter-node traffic alone does not guarantee a performance improvement, as the additional intra-node processing overhead may offset the communication savings. The reported component times do not directly represent critical-path latency or endto-end training time. Index-aware segment reduction. We compare the original and specialized aggregation kernels on AMD MI308X across four workloads (Figure 8). The forward kernel uses CSR segments to assign unique writers; the backward kernel locally merges contributions to the same row. Forward latency decreases by 71.0%– 85.8% and backward latency by 60.5%–97.7%, with speedups of up to 7.02× and 44.08×, respectively. Exploiting the index structure substantially reduces aggregation overhead in both directions.

5

103

2.53x

3 int8 / 128

104

11.79x

2 FP32 / 32

10

RecIS

7.02x

1 FP32 / 16

Latency (us)

Table Type / dimension

Baseline 5

44.08x

Table 3: Comparison of communication traffic and overhead between Flat and Hierarchical embedding communication. All measurements are per-step averages across ranks.

6 Conclusion RecIS coordinates three aspects of GPU-centric recommender training: operator granularity, embedding request distribution, and execution order. Adaptive fusion and vectorization reduce preprocessing overhead; sharding, hierarchical communication, and indexaware aggregation reduce embedding costs; and multistage scheduling overlaps future preparation with current dense computation. Across the evaluated workloads, RecIS achieves up to 1.15× the throughput of TorchRec and 2.62× that of PICASSO, with steplatency reductions of up to 12.9% and 61.5%, respectively.

Related Work

7 Acknowledgments

Wide & Deep, DeepFM, xDeepFM, and DCN V2 model feature interactions [4, 8, 12, 21], while DIN and DIEN model user interests from behavior sequences [29, 30]. To support these workloads, TensorFlow and PyTorch provide general execution primitives [1, 19], while DeepRec, HugeCTR, TorchRec, and PERSIA specialize in large-scale recommendation training [5, 10, 13, 24]. Feature heterogeneity motivates tailored GPU execution. RecFlex adapts schedules to heterogeneous features [18]. RecIS groups compatible transformations across fields while preserving dependencies, using fusion and vectorized access to reduce preprocessing overhead. Embedding optimizations target execution, storage, and communication. Kwon and Rhu optimize GPU embedding execution [11], while EL-Rec reduces storage via tensor-train representations [23]. ScaleFreeCTR and HET cache embeddings to reduce remote access [7, 15]; FEC combines embedding tiering with prefetching to reduce communication overhead [14]. RecIS merges repeated IDs across GPUs in each source node before inter-node exchange, reducing both transmitted requests and returned vectors.

This work is supported by Alibaba Group. We thank Chuan Wang, Han Wu, Kui Ma, Yuejie Lei, Feifan Yang, Bin Liu, Zhangming Chan, Ziru Xu, and Yong Bai for useful pointers regarding the writing of this paper. We appreciate Qi Wang, Yiwen Hu, Hechen Sun, Mingjie Liu, Yihan Xian, Zhensong Yan, Houyuan Xiang, Wenjie Guo, Shihang Yan, Ning Zhang, and Yingyu Ji for implementing the key components of the training infrastructure. We also thank Lei Wu, Tianhao Shen, Fuwei Yang, and ChunHung Wang from AMD for their technical support and assistance in optimizing core components of the framework.

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