PRISM: Preference-based Reward and Uncertainty-Integrated Synthesis Minimization for RTL PPA Optimization

PRISM: Preference-based Reward and Uncertainty-Integrated Synthesis Minimization for RTL PPA Optimization Armin Abdollahi, Negin Ashrafi, Mehdi Kamal, Massoud Pedram University of Southern California Los Angeles, CA, USA {arminabd, ashrafin, mehdi.kamal, pedram}@usc.edu

arXiv:2611.11051v1 [cs.AR] 8 Nov 2026

Abstract—This paper introduces a budget-aware, multi-objective framework (called PRISM) for RTL optimization that improves power, performance, and area (PPA) while sharply limiting expensive commercial synthesis tool calls. Starting from a synthesizable baseline and functional testbench, the method iterates through LLM-driven rewrite generation, fast compile/simulation equivalence filtering, low-cost proxy feature extraction, and selective commercial synthesis tool (Synopsys Design Compiler (DC)) evaluation. To prioritize which candidates deserve high-quality synthesis, we train a preference-based reward model using pairwise ranking supervision derived from commercial synthesis tool outcomes, and combine ensemble uncertainty with a diversity-aware acquisition rule to avoid early bias and redundant evaluations. A key advantage is that PRISM maintains a best-tradeoff set G of non-dominated designs throughout the run: G preserves the best solutions found so far, is fed back into generation and refinement, and enables consistent, cumulative improvements rather than repeatedly restarting from the baseline. Across RTLLM v2.0 modules, the approach consistently yields post-synthesis gains under fixed commercial synthesis tool call budgets, and ablations confirm that reward-guided selection and candidate dropping are central to sample-efficient progress. PRISM efficacy is evaluated across multiple technology nodes (7 nm, 15 nm, and 45 nm) using identical pipelines without retraining.

I. I NTRODUCTION

Power, performance, and area (PPA) remain the blunt instruments that decide whether an RTL design is merely working or actually shippable. Even for a fixed micro-architecture, small RTL-level structural choices such as sharing arithmetic, factoring enables, simplifying control, and rewriting compares can shift the downstream synthesis result enough to matter in timing closure and power budgets [1], [2], [3]. Beyond RTL rewriting, recent hardware-design efforts have also explored domain-specific acceleration and optimization, including mixed-signal acceleration for edge inference [4] and hybrid approaches for QUBO solving [5]. In practice, engineers iterate with an RTL synthesis engine and its optimization knobs to converge on acceptable tradeoffs; commercial tools such as Synopsys Design Compiler explicitly target concurrent timing/area/power optimization and are widely used as a reference point [6], [7], [8]. The catch is that full-fledged synthesis is expensive as an inner loop. Exploring many rewrite directions by running synthesis on everything quickly collapses under runtime, tool capacity, and iteration latency [9], [10], [11]. This makes naive search over RTL transformations unrealistic. The evaluation oracle is accurate but slow, and the combinatorics of code-level edits explode. As a result, practical flows largely rely on heuristics, human insight, and limited what-if exploration, rather than systematic exploration of the RTL rewrite space [12]. Recent progress in code generation motivates treating RTL optimization as a generate and test problem [13], [14]. Many candidate RTL variants can be proposed and the ones that improve PPA can be retained. But for RTL, test is not only functional equivalence [15], [16]. The expensive part is the PPA measurement under a fixed library, fixed constraints, and a fixed synthesis script. What is needed is a

pipeline that enforces correctness cheaply, prioritizes which candidates are worth paying the synthesis cost for, and still explores diverse rewrite directions so the search does not get trapped in one stylistic neighborhood of the code [17], [18], [19]. This paper presents a time-efficient, budgeted approach to multiobjective RTL optimization that uses full-fledged commercial synthesis sparingly while still targeting simultaneous improvements in area, power, and delay. Starting from a baseline synthesizable design and a functional testbench, the method searches for functionally equivalent variants that improve post-synthesis PPA and outperform prior state of the art approaches under the same tool, library, and constraint settings. The core pipeline iterates through four stages of candidate generation, fast filtering, cheap proxy extraction, and selective synthesis evaluation, followed by refinements phase around the strongest candidates. A central component is a learned reward model that predicts which surviving candidates are likely to improve PPA before we spend a DC run [20], [21]. We train this model using preferencestyle supervision derived from DC outcomes, rather than unstable direct regression of raw PPA across designs. The training objective is pairwise ranking with a logistic loss, aligning naturally with classic pairwise-comparison models, and avoiding absolute scaling across modules and constraints. To make this practical, we instantiate the reward model via parameter-efficient fine-tuning (LoRA), enabling fast scoring over a large candidate pool [22]. We also incorporate uncertainty estimation through an ensemble of independently trained reward models, using disagreement to moderate early-model bias and improve robustness of candidate selection. Candidate selection for DC explicitly balances predicted reward, uncertainty, and diversity to avoid wasting time on near-duplicates [23]. Because PPA is inherently multi-objective, the output of the search should not be forced into a single scalar winner. Instead, we maintain a running best-tradeoff set of non-dominated designs so the method naturally returns multiple high-quality variants representing different tradeoffs. This matches standard multiobjective optimization logic. When objectives conflict, the meaningful result is a set of nondominated solutions rather than a single optimum. We additionally feed representatives back into generation and use them as seeds for a refinement stage, concentrating on small, targeted edits around already-competitive designs rather than repeatedly resetting from. II. R ELATED W ORKS ChipSeek-R1 [24] and [25] rely on on-policy RL updates from synthesis-derived rewards, which are sparse and noisy; stabilizing credit assignment typically requires many DC-evaluated rollouts per update. As the policy shifts, the data distribution changes and forces repeated re-synthesis, so DC labels cannot be amortized well—making the approach sample-hungry and hard to scale to large RTL modules. ROVER [12] and ASPEN [26] treat PPA optimization as structured, semantics-preserving rewriting (e-graph/equality-saturation plus

guided extraction). Their main limitation is coverage and scalability. Effectiveness depends on the rewrite-rule set and extraction heuristics, e-graphs can blow up on large designs, and accurate PPA ranking still typically falls back to expensive synthesis. VeriOpt [27] and LLMVeriPPA [28] represent LLM-in-the-loop PPA optimization via iterative generate–check–refine, typically enforcing compilability/functional constraints before using synthesis feedback to steer toward better PPA. Their main limitation is speed and evaluation efficiency. Without a principled acquisition rule for which candidates deserve DC, they often produce many near-duplicate candidates and multiple refinement rounds to find improvements which is time consuming and inefficient. MCTS [29], and RTLSquad [30] wrap the LLM with an explicit search controller such as tree search, evolutionary populations, or multi-agent propose and verify loops to improve exploration beyond greedy decoding. Their shared weakness is DC-bounded scaling. Stronger exploration increases the number of candidates that must be evaluated or compared, so runtime and cost grow quickly on large RTL modules. More broadly, the multi-objective tradeoff and uncertainty-aware acquisition principles PRISM employs echo a wider optimization literature, spanning multi-objective and metaheuristic optimization [31], [32], nonsmooth/constrained numerical optimization via neurodynamic and quasi-Newton methods [33], [34], [35], [36], [37], optimization under imprecise parameters [38], and budgetconstrained resource allocation [39]. The contributions of our work are: • We propose a budget-aware LLM-in-the-loop RTL optimization framework that jointly targets power, performance, and area (PPA) while sharply reducing reliance on expensive commercial synthesis calls via staged filtering and selective evaluation. • We introduce a preference-learning reward model trained from pairwise comparisons induced by post-synthesis outcomes, enabling reward-guided ranking of candidate RTL rewrites without requiring dense regression targets. • We develop an uncertainty-aware and diversity-aware acquisition/selection strategy that prioritizes high-utility and nonredundant candidates for synthesis evaluation, improving sample efficiency under fixed synthesis budgets. • We present a persistent best-tradeoff archive G (a non-dominated set) that is maintained across iterations and used for warmstarting generation/refinement; unlike prior approaches that may accept edits that worsen PPA, G ensures the reported best-so-far solutions always improve or, at minimum, maintain PPA relative to previously discovered designs. • We evaluate the approach on RTLLM v2.0 benchmark modules across multiple technology libraries, demonstrating consistent post-synthesis gains under budget-matched settings, and we provide ablations quantifying the effects of reward guidance, diversity selection, and candidate dropping. III. M ETHODOLOGY

scoring. Let EDC (·) denote a DC run under a fixed library, constraints, and synthesis script: EDC (D) → A(D), P (D), Dly(D)

(1)

where A is cell area, P is power, and Dly is critical-path delay. Functional correctness is enforced via simulation equivalence on T B. Candidates that fail compilation or simulation matching are discarded before DC. B. Pipeline Overview Our proposed method proceeds iteratively through four stages: i) Candidate generation, where PRISM produces diverse RTL candidates from a fixed set of rewrite strategies; ii) Fast filtering, where each candidate is compiled and simulated to enforce functional equivalence to D0 ; iii) Cheap hardware proxies and reward scoring, where proxy features and score candidates are obtained using a fine-tuned reward model; and iv) Selective DC evaluation and refinement, where DC is run on only a small subset of candidates and PRISM uses the best-performing results to guide a refinement stage. Throughout, PRISM framework maintains a running set of best-sofar designs that capture different PPA tradeoffs (defined precisely in subsection G); this set is used both to report final results and to guide subsequent generation and refinement. The general flow of the PRISM is illustrated in Fig. 1. C. Candidate Generation Using Rewrite Prompts We define a set of rewrite strategies S = {s1 , . . . , s|S| }. Each strategy s is implemented as a rewrite prompt that instructs the generator model to produce a functionally equivalent RTL variant focused on a specific transformation family. At each iteration, we generate candidates by applying a selected list of strategies. Formally, the candidate pool is: C=

[

Gen(D0 , G, T B, s; τ )

(2)

s∈S

where G is the maintained set of best-so-far designs, and τ is the decoding temperature. We use a strategy set that covers the most common RTL-level sources of unnecessary area/power/delay while remaining compatible with automated equivalence checking via the provided testbench. The strategies are chosen to (i) act on both datapath and control, (ii) encourage synthesis-friendly structure (enables, mux factoring, reduced logic depth), and (iii) provide diverse rewrite modes so the generator does not collapse to near-duplicate edits. These strategies shown in Table I are applied repeatedly with random seeds and temperatures to produce diversity while staying within synthesizable Verilog constraints. Concretely, each strategy is converted into a natural-language rewrite prompt consisting of the baseline RTL, functional-preservation constraints under the provided testbench, and the strategy-specific instruction summarized in Table I.

A. Problem Formulation: Time-Efficient Multi-Objective RTL Optimization

D. Fast Functional Filtering and Non-DC Hardware Proxies

Given a baseline synthesizable RTL design D0 and a functional testbench T B, PRISM’s goal is to automatically generate a functionally equivalent RTL variant D by employing the LLMs that improves post-synthesis design quality under standard-cell synthesis. PRISM targets multi-objective optimization over area, delay, and power (PPA). The practical challenge is that exploring many rewrite directions by running DC for every candidate is prohibitively slow; therefore, the method is designed to avoid DC evaluation for most candidates by filtering and ranking them using inexpensive checks and learned

Since the proposed framework does not run DC on all candidates, it first removes incorrect candidates and then obtains proxy features (e.g., case statement count) that approximate hardware cost/complexity. 1) Functional filtering (compile + simulation equivalence) For each candidate D ∈ C, PRISM compiles it with a fast simulator (iverilog), simulates under T B(D), and compares normalized output traces against the baseline trace T B(D0 ). Candidates that fail compilation, time out, or mismatch the baseline trace are discarded immediately.

Fig. 1: Overview of PPA-Minimizer: closed-loop RTL optimization with LLM candidate generation, reward-model scoring, and DCin-the-loop evaluation.

2) RTL normalization using Yosys Many LLM-generated RTL differences are stylistic (temporary wires, redundant assigns, superficial restructuring) and can create noise in proxy extraction and downstream ranking. To reduce this, each candidate is passed through Yosys [40] to obtain a more canonical representation. Given RTL text D, PRISM runs a fixed Yosys script that reads Verilog, resolves hierarchy and sets the top module, converts processes to netlists, applies standard logic optimizations, flattens hierarchy, performs techmapping to Yosys internal primitives, and writes back Verilog without attributes. This produces a normalized RTL that is syntactically cleaner and more consistent across candidates and is used for proxy feature extraction. 3) Hardware-aware proxy features For each candidate passing simulation, PRISM computes a feature vector z(D) using only non-DC tools. a) RTL-structure features (from direct RTL parsing) Computed by parsing the Verilog text (token/regex + lightweight syntax scanning): module count, always block count, case statement count; number of blocking/nonblocking assignments; counts of arithmetic ops (+, −, ∗, shifts), comparisons (==, <, >), bitwise ops; mux-like pattern counts (if-else ladders; ternary operators); inferred register count proxies (nonblocking assignments in clocked always blocks); estimated maximum/minimum bitwidth per key signals (from declared widths and slice usage); and fanout proxy from repeated signal usage counts (text-level approximation). b) Yosys statistics (from stat on normalized netlist) Computed by running Yosys and extracting statistics: number of internal cells by type ($add, $sub, $mux, $dff, $logic_not, etc.); number of wires, number of memories inferred; depth proxies (where available via simple passes; otherwise approximated via logic cone summaries); and normalized operator footprint as a stable representation of datapath/control complexity. PRISM concatenates the RTL-structure features and Yosys statistics into a fixed-length proxy feature vector z(D), using a consistent ordering of components across all designs. Scalar counts (e.g., block counts and operator counts) are included directly, while Yosys celltype counts are represented as a vector indexed by the set of supported internal cell types (missing types are assigned zero). The resulting z(D) provides a deterministic, hardware-aware summary of each candidate that can be used for scoring and for computing similarity between candidates. These proxy features are deterministic outputs of RTL parsing and Yosys analysis.

E. Reward Model for Multi-Objective Ranking (Area, Power, Delay) A learned reward model Rϕ (·) predicts candidate quality by using candidate RTL and proxy features before calling DC. The purpose is to select a small subset of candidates that are most likely to improve PPA. 1) Utility definition for training labels (using DC metrics only as supervision) Directly regressing raw A, P, Dly across different designs is unstable due to scale variation. Instead, we define a normalized utility relative to each design’s baseline D0 . Let (A0 , P0 , Dly0 ) be baseline DC metrics and (A, P, Dly) be candidate DC metrics. We define: U (D) =

A0 − A P0 − P + A0 P0 Dly0 − Dly . + Dly0

(3)

This utility is used only to convert DC outcomes into preference labels for training; it is not used as an input to the reward model. 2) Preference-based training objective We train Rϕ as a ranking model [41], [42]. From candidates evaluated by DC for the same design instance, we form pairs (D+ , D− ) such that U (D+ ) > U (D− ). The model is trained to satisfy Rϕ (D+ ) > Rϕ (D− ) using the logistic ranking loss: h
i L(ϕ) = −E(D+ ,D− ) log σ Rϕ (x+ ) − Rϕ (x− ) .

(4)

Here, the reward model input x includes the baseline RTL D0 and a compact edit representation ∆D that explains the candidate RTL D as a difference against D0 to reduce length and emphasize edits, along with structured proxy features z(D0 ) and z(D). The x, is then passed to the reward head to predict score.   x = D0 ; ∆D ; z(D0 ) ; z(D)

(5)

3) Fine-tuned 7B reward model implementation We instantiate Rϕ as a parameter-efficient fine-tuning (LoRA) of Qwen2.5-7B code-capable language model. The model reads the structured input x and outputs a scalar reward score. A learned linear regressor is applied to the final hidden state of the input sequence to obtain the scalar reward. Training uses the pairwise ranking loss above. At inference time, scoring is fast enough to rank a large candidate pool.

TABLE I: Rewrite strategies used for RTL generation. ID S1

S2 S3 S4 S5

S6 S7 S8 S9 S10 S11 S12 S13

S14 S15

Strategy name What the prompt instructs Why it helps PPA Resource shar- Reuse adders/comparators Reduces area/power from ing across mutually exclusive duplicated arithmetic; can branches; move ops under shorten logic in control-heavy shared enables designs Register merg- Merge redundant state regs; use Cuts FF count and mux ing a single state reg with muxed overhead; often reduces both updates area and delay Enable Factor common enables/guards; Simplifies control cone; can factoring reduce nested if-else logic reduce critical-path delay through smaller logic depth FSM simplifica- Merge equivalent states, Reduces control logic and tion remove unreachable states, improves timing by shrinking simplify transition conditions next-state logic Comparator Replace wide compares with Shrinks comparator area and simplification narrower or structured checks can reduce delay on control (e.g., MSB tests, saturating paths counters) Counter Narrow counter bitwidth, reuse Cuts FFs and comparator logic; optimization counters, remove redundant can reduce both area and delay counters Datapath Reduce internal bitwidths when Reduces adder/mux size; often bitwidth provably safe under TB improves delay due to smaller narrowing behavior arithmetic Common Hoist repeated expressions into Reduces duplicated logic; subexpression a shared wire/reg improves timing by avoiding elimination repeated cones Mux factoring / Convert deep if-else chains into Improves synthesis structure case restructur- case + shared mux patterns and can reduce delay on select ing paths Constant propa- Precompute constant Removes dead logic and gation / folding expressions; remove shortens paths; typically helps constant-controlled branches all PPA axes Dead logic re- Remove unused signals/regs Cuts area/power; reduces moval and unreachable branches congestion of logic feeding while preserving TB outputs timing paths Reset/initial Simplify reset logic; avoid Reduces control overhead; can cleanup redundant reset assignments reduce delay in reset-driven cones Pipeline-safe re- Move registers across purely Can reduce critical-path delay timing hints combinational boundaries when TB tolerance allows without changing I/O behavior (kept conservative) under TB Sharing of Merge duplicated Reduces replicated control/data address/control address/control generation and generation logic; can reduce buses distribute delay in fanout-limited designs Structured Re-express logic to expose Helps delay by reducing depth; refactor synthesis optimizations (e.g., helps area if it reveals sharing balanced trees, associative opportunities regrouping)

4) Uncertainty Estimation Reward scores can be unreliable early in the run or when candidates differ substantially from training patterns. To avoid repeatedly selecting candidates that the model is confidently wrong about, we estimate uncertainty using an ensemble approach. We train M independent reward models {Rϕm }M m=1 using different random seeds (and different LoRA initializations). For each candidate D, we compute: µ(D) =

M
1 X Rϕm x(D) , M m=1

M  2 X
1 σ(D) = Rϕm x(D) − µ(D) . M − 1 m=1

(6)

µ(D) captures predicted quality; σ(D) captures disagreement across models and is used to occasionally prioritize candidates the model is uncertain about, which improves selection robustness and reduces the chance of getting stuck evaluating only one rewrite style. F. Selection of Candidates for DC Evaluation From the candidate pool C that passes simulation, PRISM computes reward scores and selects a small subset for evaluation by DC. The selection criterion balances i) high predicted reward (PPA improvement), ii) model uncertainty (avoid over-committing to early

biases), iii) diversity (avoid sending many near-duplicate edits to DC). For each candidate D, an acquisition score is calculated by: a(D) = µ(D) + βσ(D).

(7)

where µ(D) and σ(D) come from uncertainty estimation (subsection E.4), and β is a fixed exploration weight [43]. PRISM then greedily selects K candidates maximizing total acquisition score while penalizing redundancy using a similarity measure sim(·, ·) computed from feature embeddings [44], where E denotes the set of the K selected candidates: max

|E|=K

X

X

a(D) − λ

sim(Di , Dj ).

(8)

Di ̸=Dj ∈E

D∈E

sim(Di , Dj ) =

z(Di )⊤ z(Dj ) . ∥z(Di )∥ ∥z(Dj )∥

(9)

This ensures the DC runs cover meaningfully different rewrite directions. G. Maintaining the Best-Tradeoff Set PRISM maintains a set G, called the best-tradeoff set, containing designs that represent the best PPA tradeoffs observed so far. A design is included in G if it is not strictly worse than another design in all three objectives (area, power, delay). Concretely, for two DC-evaluated designs D1 and D2 , we say D1 is strictly worse than D2 if: A(D1 ) ≥ A(D2 ), P (D1 ) ≥ P (D2 ), Dly(D1 ) ≥ Dly(D2 ),

A(D1 ), P (D1 ), Dly(D1 ) ̸= A(D2 ), P (D2 ), Dly(D2 ) .

(10)

In that case, D1 is removed from G. Otherwise, it remains as a useful tradeoff point. In the proposed framework, we maintain G throughout because the search produces multiple high-quality RTL variants rather than a single clear winner, and G lets the framework report those alternatives without collapsing everything into one arbitrary weighted objective. We also feed representatives from G back into generation so the model can start from strong existing designs instead of repeatedly rewriting from the initial design, which encourages small, cumulative improvements rather than noisy resets. Finally, G provides strong starting points for the refinement in the next iteration, so refinement focuses on polishing already-competitive tradeoffs instead of spending budget rediscovering them. Finally, we emphasize that the pruning criteria can be relaxed; for example, just power consumption is considered in cases where power consumption is the only design metric of interest. H. Refinement After DC evaluation of the selected set E, PRISM updates G and then runs a refinement stage to intensify search around the most promising candidates. This stage is designed to reuse the same generation + scoring + selective DC evaluation pattern, but over strong seeds. a) Seed selection PRISM picks a small number of seed designs from the current best-tradeoff set G. To ensure coverage of distinct tradeoffs, PRISM includes the designs with best area, best power, and best delay in G. In addition, it includes the design in G with the highest normalized utility U (·), capturing the strongest balanced improvement observed so far.

b) Neighborhood generation For each seed, PRISM generates a neighborhood by re-applying a subset of the rewrite strategies S, chosen adaptively by the policy router based on the seed’s structure and the current search state. The router allocates a variable number of neighborhood candidates per strategy (including the possibility of allocating none), and when multiple candidates are allocated to the same strategy, PRISM diversifies generations by varying decoding temperature. Concretely, we instruct the generator to keep module interfaces unchanged, preserve sequential behavior under T B. c) Scoring and selection All neighborhood candidates pass through the same compile-andsimulate equivalence filter. For survivors, the framework computes proxy features and reward scores. It then selects a small number of diverse neighborhood candidates for DC evaluation. d) Acceptance and iteration If a neighborhood candidate improves the best-tradeoff set G (i.e., it is not strictly worse than existing members), it is added and may replace dominated designs. The refinement repeats for a small number of steps, enabling a controlled tightening process around good seeds without evaluating every candidate in DC. This refinement stage is the mechanism that converts coarse, strategy-driven rewrites into consistent improvements by repeatedly proposing and validating small structural changes around already-strong designs. I. Learned Policy Router Instead of allocating candidate generations for each rewrite strategy, we learn a router πψ (s | D) that outputs a distribution over strategies s ∈ S conditioned only on the current seed RTL module. We train πψ offline from logged runs by using the observed post-DC utility U (·) as supervision. For each seed design D and strategy s, we define a strategy payoff as the best utility achieved among candidates generated by applying s to D: r(D, s) = ′ max U (D′ ), (11) D ∈C(D,s)

where C(D, s) denotes candidates produced by strategy s from D (after passing the compile/simulation filter). We convert these payoffs into a soft target distribution q(s | D) = P

exp( r(D, s)) , exp( r(D, s′ ))

We trained the reward model using a large-scale, synthesis-grounded preference dataset constructed offline using GPT4.0. Specifically, we curated approximately 11K Verilog modules paired with passing testbenches, and ran each design through a fixed DC flow to obtain reference reports and baseline (A, P, Dly). For each module, we then generated multiple function-preserving RTL variants that induce diverse PPA trade-offs. The functional equivalence was verified by rerunning the corresponding testbench for every variant; each variant was synthesized to obtain its DC report, and we formed the proxyfeature vector z(D). We kept 1k of the dataset for our validation and tuning the hyperparameters, and used 10k for fine-tuning our reward model. The reward-model input x concatenates the baseline RTL D0 and candidate RTL D (explained as a diff against D0 to reduce length and emphasize edits), baseline proxy features z(D0 ), and proxy features z(D). We instantiated Rϕ as a parameter-efficient LoRA finetuning of the Qwen2.5-7B code-capable language model, trained with the pairwise ranking objective provided in Eq. (4) over DC-derived preferences. Note that at inference time, scoring is sufficiently fast to rank large candidate pools and drive acquisition. TABLE II: Hyperparameters (tuned on the validation split).

and train the router by minimizing KL divergence to this target, with a regularizer toward a uniform allocation to preserve exploration: + γ ED [KL(πψ (· | D) ∥ Unif(S))] .

B. Reward-Model Training Data and Validation Date creation

(12)

s′ ∈S

Lrouter = ED [KL(q(· | D) ∥ πψ (· | D))]

the post-synthesis area, power, and delay of the optimized implementations against the original benchmark designs under the same synthesis settings and constraints. All hardware PPA measurements were obtained using Synopsys Design Compiler (DC). We evaluated the proposed method under multiple technology nodes, including NanGate45 [46], NanGate15 [47], and ASAP7 [48]. Importantly, the same optimization pipeline, reward model, and generation strategy are used across all configurations, without any retraining, fine-tuning, or embedding modification. The technology enters the flow solely through the DC configuration. The proposed optimization pipeline uses two language models with distinct roles. In this work, PRISM uses GPT-4.0 [49] as the primary generation model to propose candidate RTL transformations, while the reward model is a separately trained LoRA-fine-tuned Qwen2.5 [50] model used to score and guide candidate selection during iterative refinement. This separation allows the generator to explore a broad space of code edits while the reward model provides a stable optimization signal aligned with PPA objectives.

(13)

At inference time, πψ (· | D) determines how generation budget is distributed across strategies. We implement πψ as a lightweight MLP over z(D), followed by a softmax layer that produces the strategy distribution. When multiple samples are allocated to the same strategy, we diversify outputs by varying the decoding temperature. IV. R ESULTS A. Experimental Setup We evaluated the proposed PPA optimization framework on the RTLLM v2.0 [45] benchmark, which contains a diverse collection of compact RTL modules representing common hardware building blocks. For each benchmark module, PRISM generates candidate RTL rewrites, filters candidates through compilation and testbenchbased functional checks, and prioritizes promising implementations for synthesis evaluation using the learned reward model. We compare

Param. M K β λ γ

Brief description Reward-model ensemble size DC evaluations per iteration Exploration weight in Eq. (6) Diversity penalty weight in Eq. (7) Router exploration regularization weight

Value 5 10 0.5 0.2 0.05

We tuned the hyperparameters provided in Table II on the held-out 1K-design validation split (kept separate from the 10K designs used to fine-tune the reward model), selecting the configuration that maximizes validation best-so-far normalized utility under a fixed DC budget. We set M =5 to obtain a stable disagreement estimate σ(D) without excessive training overhead, and K=10 to keep each DC round small while still covering multiple rewrite directions per iteration. We used β=0.5 to ensure uncertainty meaningfully influences acquisition early in the run (mitigating over-commitment to spurious high-reward modes) while preserving exploitation through µ(D). We set λ=0.2 as a moderate redundancy penalty that empirically reduces duplicate-atDC behavior without collapsing selection diversity, and used a γ=0.05 as the router exploration weight.

TABLE III: The design parameters of the RTLLM v2.0 baseline modules and those of optimized ones by PRISM, both synthesized with Synopsys Design Compiler using the NanGate45 standard-cell library. For each design, critical-path Delay (ns), Area (µm²), and Total Power (W) are reported. Baseline numbers (Original Benchmark) Ours Delay (ns) Area (µm2 ) Power (W) Delay (ns) Area (µm2 ) Power (W) asyn fifo 0.72 1397.03 7.67e-5 0.25 1369.10 7.21e-5 LFSR 0.06 23.41 1.88e-6 0.05 22.39 1.72e-6 0.07 36.18 2.71e-6 0.07 36.18 2.39e-6 right shifter barrel shifter 0.19 31.39 2.48e-5 0.19 25.65 2.48e-5 LIFObuffer 0.39 198.17 1.63e-5 0.31 159.19 1.18e-5 0.38 624.04 4.36e-5 0.25 401.24 3.65e-5 RAM alu 1.95 1300.21 1.10e-3 1.78 1168.30 6.72e-4 2.81 2103.53 1.80e-4 2.33 2103.53 1.74e-4 pe 0.13 117.04 8.31e-6 0.13 117.04 8.31e-6 instr reg signal generator 0.34 61.71 5.15e-6 0.29 58.46 4.48e-6 square wave 0.54 94.16 8.09e-6 0.54 94.16 8.09e-6 0.55 154.28 1.14e-5 0.55 141.94 7.98e-6 calendar parallel2serial 0.05 46.55 3.68e-6 0.05 44.28 3.12e-6 pulse detect 0.04 14.63 1.17e-6 0.04 12.87 1.01e-6 0.31 157.47 1.13e-5 0.25 94.48 7.91e-6 serial2parallel width 8to16 0.18 185.93 1.31e-5 0.16 156.18 1.24e-5 traffic light 0.45 129.54 1.04e-5 0.41 122.92 9.04e-6 edge detect 0.18 17.82 1.35e-6 0.16 9.29 4.73e-7 0.24 44.95 3.96e-6 0.24 44.95 3.96e-6 freq divbyfrac freq divbyeven 0.20 19.15 1.54e-6 0.16 14.20 1.21e-6 JC counter 0.06 340.48 2.35e-5 0.05 85.12 4.70e-6 0.11 28.99 2.28e-6 0.10 25.28 1.89e-6 counter 12 up down counter 1.00 177.42 1.28e-5 0.84 139.22 7.24e-6 adder bcd 0.51 27.93 3.65e-5 0.46 22.82 2.78e-5 adder pipe 64bit 1.09 2323.78 1.64e-4 0.96 929.51 1.43e-4 adder 32bit 1.52 170.24 1.72e-4 1.06 132.79 1.45e-4 adder 16bit 0.98 68.10 5.65e-5 0.57 32.91 3.83e-5 0.50 34.05 2.75e-5 0.30 22.28 1.76e-5 adder 8bit fixed point adder 2.92 546.63 7.11e-4 0.48 37.89 3.20e-5 fixed point subtractor 2.37 416.56 4.80e-4 0.38 17.47 1.10e-5 0.32 163.06 1.19e-5 0.23 127.19 9.50e-6 multi pipe 4bit multi pipe 8bit 0.86 816.62 5.51e-5 0.58 582.21 3.68e-5 multi 16bit 2.85 790.02 5.98e-5 1.84 687.32 4.34e-5 comparator 4bit 0.19 18.89 1.42e-5 0.16 15.39 9.33e-6 0.12 13.03 1.00e-5 0.12 11.39 9.48e-6 comparator 3bit radix2 div 0.70 367.08 2.92e-5 0.58 289.30 2.07e-5 7.88 898.02 2.29e-3 5.62 652.33 1.83e-3 div 16bit 0.64 138.85 1.15e-5 0.56 122.91 1.03e-5 accu sub 64bit 3.86 339.42 3.35e-4 2.98 256.87 2.46e-4 Design

C. Discussion Table III summarizes post-synthesis PPA for the RTLLM v2.0 benchmark designs, reporting each module’s baseline (Original Benchmark) timing, area, and power alongside optimized implementation under the same evaluation setup. Overall, the optimized variants consistently preserve or improve critical-path delay while also reducing silicon cost and/or power on many designs, for example, the delay of asyn fifo is improved from 0.72→0.25 ns with lower area and power, delay of RAM is improved 0.38→0.25 ns with a sizable area reduction, and design parameters of the ALU show simultaneous gains in delay (1.95→1.78 ns), area, and power (1.1e-3→ 6.72e-4 W). Several control-oriented blocks also see meaningful design parameter improvements (e.g., in the cases of the LIFObuffer and serial2parallel, both area and power are improved), while a small subset remains unchanged (e.g., instr reg, square wave, freq divbyfrac), indicating the method is conservative when no clear PPA improvement is available without risking correctness. In Table IV, across all three technology nodes, the proposed pipeline achieves consistent post-synthesis gains in area, power, and delay across RTLLM v2.0. The improvements remain stable when switching libraries, indicating the method is largely technology-agnostic in practice: the same generation, filtering, reward-guided selection, and refinement loop transfers across nodes. Figure 2 reports DC-budget convergence by plotting the normalized

TABLE IV: Average post-synthesis PPA improvements across technology nodes under a budget-matched setting across RTLLM v2.0. Results report mean percentage reductions (↓) in area, total power, and critical-path delay relative to each design’s baseline within the same DC flow and constraints for that library. Configuration NanGate45 (45 nm) NanGate15 (15 nm) ASAP7 (7 nm)

Avg Area ↓ 23.56% 22.61% 22.79%

Avg Power ↓ 25.12% 24.60% 26.01%

Avg Delay ↓ 20.55% 21.19% 20.46%

best-so-far utility (baseline mapped to 0) as a function of the number of Design Compiler (DC) evaluations, averaged across RTLLM2 modules. In the early budget (≈0–15 DC calls), improvements are modest because the search is primarily exploring and screening multiple candidate strategies; once promising directions are identified, utility rises sharply (≈15–30 calls) as the method exploits higherquality transformations, and then gradually saturates as additional DC evaluations yield diminishing returns. Figure 3 decomposes the end-to-end pipeline into five stages—LLM generation, compile/simulation filtering, Yosys-based normalization and proxy extraction, reward scoring, and DC synthesis/report parsing—and reports each stage’s share of total runtime across RTLLM v2.0 benchmark modules. DC synthesis and report parsing account for

Fig. 2: Normalized best-so-far utility vs. DC evaluations. Fig. 4: Average % improvement over RTLLM v2.0 under a budget-matched DC budget.

Fig. 3: Runtime share breakdown across pipeline stages for RTLLM2 modules

50% of the total runtime, while compile/simulation filtering accounts for 18%, LLM generation and reward scoring each account for 12%, and Yosys-based normalization and proxy extraction account for 8%. Reporting percentages rather than absolute times avoids machine- and license-dependent variability while illustrating the relative computational costs of the pipeline. We evaluate a set of budget-matched baselines under the same DC flow, constraints, and RTLLM v2.0 designs, and report average percent improvement over the published baseline PPA. Specifically, Random Search samples candidates uniformly at random and returns the best design observed under the same DC-call budget; Generator-only + DC uses the same LLM candidate generator but selects candidates without a learned reward model (self-scored ranking) and evaluates them in DC; Bandit/BO (UCB/TS) treats a discrete set of rewrite templates/operators as arms and uses DC utility feedback to adaptively allocate evaluation budget via standard bandit/Bayesian-optimization policies; and Evolutionary Search iteratively mutates RTL using the same edit operators and applies selection based on DC utility to form the next population. This analysis isolates the contribution of rewardmodel-guided acquisition and diversity-aware selection by comparing against representative, reproducible black-box optimization strategies under identical synthesis conditions. Figure 5 compares our average PPA gains on RTLLM v2.0 against three representative LLM-based baselines reported in prior work. Under the same evaluation protocol (percent improvement relative to the RTLLM v2.0 baseline), a pure GPT-4.0 generation approach yields modest gains (3.04% timing, 8.02% area, 8.42% power). ChipSeek-R1 improves over GPT-4.0 (13.55% timing, 10.88% area, 14.65% power) but remains consistently below our approach. PPA-RTL is competitive on area (25.15%) and achieves solid power reduction (19.97%), yet our method achieves substantially stronger and more balanced improvements overall, especially on timing and power (20.55% and 25.12%), while remaining comparable on area (23.56%). In terms of utility (Equation 3), our method also achieves the highest overall score (23.08), outperforming PPA-RTL (19.93), ChipSeek-R1 (13.03), and pure GPT-4.0 generation (6.49).These results suggest that rewardmodel-guided candidate scoring and selection within a synthesis-inthe-loop pipeline is critical for translating LLM-generated RTL edits into consistent, design-wide PPA gains.

Fig. 5: Average % improvement over RTLLM v2.0. D. Ablation Study Table V summarizes an ablation study under a fixed DC evaluation budget, reporting the maximum normalized best-so-far utility achieved by each variant. Starting from the full method, we remove key components of the pipeline—reward-based selection, candidate dropping/filters, multi-strategy exploration, normalization/deduplication, and diversity-aware selection—to quantify their individual contributions. The resulting utilities show how much each component matters for reaching high-quality PPA tradeoffs within the same DC budget, with the largest degradations indicating the most critical mechanisms. TABLE V: Ablation study under a fixed DC evaluation budget. We report the maximum normalized best-so-far utility achieved (baseline=0). Variant

Best utility (↑)

Full (ours)

0.98

No reward: Random-after-filter No reward: Proxy-only heuristic

0.72 0.79

Weaker drop: Compile-only (no sim) No drop: No compile/sim filter

0.81 0.60

No exploration: Single-strategy No exploration: Reduced strategy set

0.85 0.88

No dedup/normalization No diversity selection

0.90 0.92

V. C ONCLUSION This paper presents an LLM-in-the-loop RTL optimization pipeline that makes multi-objective PPA improvement practical under realistic synthesis constraints by combining functional filtering, proxy-guided scoring, preference-trained reward modeling, uncertainty-aware acquisition, and diversity-driven selection to concentrate DC evaluations on high-value candidates. Beyond the selection machinery, our persistent best-tradeoff set G is a core mechanism that ensures we always improve in a best-so-far sense: by retaining and updating non-dominated

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