Accelerating Distributed Variational Quantum Computing over Wireless Networks with Incentive Mechanism Design

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Accelerating Distributed Variational Quantum Computing over Wireless Networks with Incentive Mechanism Design

arXiv:2611.16155v1 [cs.DC] 12 Nov 2026

Shaba Shaon, Dinh C. Nguyen, Member, IEEE, and Octavia Dobre, Fellow, IEEE

Abstract—Distributed variational quantum computing (DVQC) appears as the emerging paradigm to address the limitations of near-term quantum devices by decomposing large parameterized quantum circuits (PQCs) into smaller subcircuits executed across multiple quantum processors. In this context, how to incentivize quantum processors to participate actively is crucial for accelerating DVQC, yet remains largely unexplored in the literature. To address this significant gap, we propose a novel two-stage incentive framework for wireless DVQC. In the first stage, we minimize processor-side energy cost via a joint optimization of subcircuit parameters, number of noise measurements, and transmit power, efficiently solved using block coordinate descent (BCD) and successive convex approximation (SCA). In the second stage, we maximize aggregator-side system utility by selecting an optimal subset of processors based on their optimized energy costs derived from the first stage, formulating a non-convex combinatorial selection problem addressed using the alternating direction method of multipliers (ADMM). Extensive numerical experiments on the MNIST and CIFAR-10 datasets demonstrate that our DVQC framework achieves training and testing performance comparable to centralized quantum computing in terms of accuracy and loss, with similar convergence behavior on MNIST and slightly slower initial convergence on CIFAR-10. Moreover, our optimization approach consistently outperforms baseline schemes in energy efficiency and system utility, revealing a strong synergy between processor-level energy minimization and incentive-driven processor selection, where reduced energy costs directly enhances a processor’s likelihood of selection and contributes to higher overall system utility. Index Terms—Distributed variational quantum computing, wireless network, incentive design.

I. I NTRODUCTION Variational quantum computing (VQC) has emerged as a powerful hybrid computing paradigm for leveraging the capabilities of near-term quantum devices to tackle complex learning and optimization problems [1]. This approach employs parameterized quantum circuits (PQCs), where circuit parameters are iteratively tuned using classical optimization routines. By combining quantum state evolution with classical feedback, variational quantum computing can execute meaningful computations even under limited coherence times, Shaba Shaon and Dinh C. Nguyen are with ECE Department, University of Alabama in Huntsville, Huntsville, AL 35899, USA, emails: (ss0670@uah.edu, dinh.nguyen@uah.edu). Octavia Dobre is with the Faculty of Engineering and Applied Science, Memorial University, Canada (e-mail: odobre@mun.ca). *This work was supported in part by the U.S. National Science Foundation (NSF) under Grant SaTC-2513164. The work of Dr. Octavia Dobre was supported in part by the Canada Research Chairs Program CRC-2022-00187 and the Natural Sciences and Engineering Research Council of Canada (NSERC), Discovery Program, Grant RGPIN-2026-04392.

restricted connectivity, and qubit counts of today’s hardware [2]. However, scaling variational quantum computing to solve real-world problems remains challenging due to qubit resource constraints on near-term quantum devices. Distributed variational quantum computing (DVQC) offers a promising approach to scaling quantum workloads by distributing computation across a network of quantum processors [3]. However, a key challenge lies in motivating individual processors to participate. Each processor must expend valuable resources, such as energy, communication bandwidth, and the finite duration over which quantum information can be preserved, i.e., quantum coherence time, to perform its assigned quantum operations and report results. Without effective incentives, processors may act selfishly or refuse to collaborate, compromising both the reliability and scalability of the distributed system. Therefore, designing an effective incentive mechanism is essential to ensure cooperative participation of quantum processors while optimizing system level performance. This work aims to improve energy consumption, system utility, and communication performance in DVQC networks under practical constraints such as limited qubit resources, transmission overhead, and processor self-interest. A. Related Work Variational Quantum Computing: Recently, a diverse range of VQC schemes have been explored. The work in [4] investigated how VQC can address the NP-hard problem of optimally assigning and scheduling computations across heterogeneous cloud or edge architectures. The authors in [5] explored how VQC can be used to solve differential equations on near-term quantum devices. In [6] the authors presented a hybrid quantum-classical graph neural network framework that uses VQCs and quantum approximate optimization algorithm to boost molecular classification performance, demonstrating the advantages of quantum computing in complex biochemical tasks. The authors in [7] used VQCs enhanced by a metalearning framework to improve training efficiency and scalability in solving optimization and molecular simulation tasks on near-term quantum devices devices. Besides, the work in [1], [3], [8], [9] leverage VQCs for solving combinatorial optimization, reinforcement learning, image segmentation, and robust parameter training under noise, respectively. The authors in [10] and [11] utilized VQCs for solving power system analytics via quantum linear solvers and for optimizing beamforming in wireless communications through hybrid quantumclassical neural networks, respectively. Although all these

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TABLE I: Comparison with related work Features General VQC VQC for wireless or power systems DVQC Circuit cutting Wireless communication modeling NOMA-based Uplink Processor energy optimization System utility optimization Incentive mechanism design for processor Optimization based on BCD, SCA, ADMM

✗ ✗ ✗

✗ ✗ ✗

✗ ✗ ✓

✓ ✓ ✗

✓ ✓ ✗

✓ ✓ ✓

✗ ✗

✗ ✗

✗ ✗

✗ ✗

✗ ✗

✓ ✓

✗

✗

✗

✗

✗

✓

do they optimize system utility in a distributed setting. Importantly, none of the existing studies model a realistic communication uplink, such as power-domain NOMA, or integrate networking considerations into the DVQC framework. Since transmitting measurement outcomes to the aggregator is a core and recurring operation in DVQC, incorporating wireless communication modeling from a networking perspective is essential for practical deployment, yet remains unaddressed by existing works. A comprehensive comparison between the proposed framework and existing studies is provided in Table I to highlight the key differences and the unique contributions of this work.

✗

✗

✗

✗

✗

✓

B. Our Contributions

✗

✗

✗

✗

✗

✓

As discussed above, despite significant research efforts on VQCs and circuit cutting techniques, existing works do not jointly address several practical challenges. Current near-term quantum hardware is severely qubit-limited and noise-prone, making large monolithic PQCs infeasible. Moreover, quantum processors are energy-constrained devices, and repeated circuit execution and measurement transmission incur substantial energy overhead. In realistic market-driven environments, quantum processors are owned by independent entities that act in their self-interest and may not participate in distributed computation unless adequately compensated for their energy expenditure. Furthermore, since DVQC critically relies on transmitting measurement outcomes to an aggregator, it is essential to model a realistic wireless uplink with interference consideration, such as power-domain NOMA. Therefore, jointly addressing qubit limitations, incentive-driven participation, system utility maximization, energy efficiency, and communication-aware design is necessary for a holistic and practically deployable DVQC framework. While existing works have addressed several individual aspects of VQC, circuit cutting, and distributed quantum computing, no prior work jointly integrates distributed VQC, processor’s energy optimization, incentive-aware processor selection, system utility maximization, and communication-aware wireless networking into a unified framework suitable for practical deployment. Motivated by these gaps, we propose a unified energy-, communication-, and incentive-aware DVQC framework tailored for distributed quantum processor networks. Our novelty lies in jointly integrating circuit cutting based distributed VQC, processor-side energy optimization, incentivecompatible processor selection, system utility maximization, and a practical NOMA-based uplink model with interference consideration into a single coherent framework. Specifically, our contributions are summarized as follows: • We develop a novel DVQC framework in which large PQCs are decomposed into smaller subcircuits and executed in parallel across multiple low-qubit and independent quantum processors. The processors communicate measurement outcomes to a central aggregator through a power-domain NOMA uplink with interference modeling and successive interference cancellation (SIC), enabling practical wireless-assisted DVQC deployment (Section II). • We introduce a novel two-stage incentive framework for

[1], Our [10] [11] [12]–[14] [15]–[17] [3]–[9] work ✓ ✓ ✓ ✗ ✗ ✓ ✗ ✓ ✓ ✗ ✗ ✓

works leverage VQCs to solve diverse application problems, they generally assume the availability of sufficiently large and reliable quantum hardware. In practice, however, near-term quantum devices are severely qubit-limited and constrained by noise, decoherence, and imperfect connectivity, which often prevents the execution of large monolithic PQCs and, in some cases, even moderate-scale circuits. Consequently, these studies do not consider distributed quantum computing frameworks to overcome such hardware limitations, nor do they incorporate incentive mechanisms to motivate participation of independently operated processors in a distributed quantum environment. Distributed VQC over Networks: A few works have addressed qubit limitations by employing circuit cutting techniques to partition large quantum circuits across networked quantum processors. In [12], the authors proposed a hybrid quantum-classical framework that enables execution of large quantum circuits by partitioning them into smaller subcircuits runnable on limited near-term quantum devices, followed by classical postprocessing to reconstruct the full output. The work in [13] presented a quantum circuit partitioning method using quantum circuit knitting to minimize qubit requirements and reduce runtime, enabling efficient execution on nearterm quantum hardware. In [14], a cluster-based simulation scheme was introduced that enables quantum circuits with limited inter-cluster communication to be efficiently executed on small quantum devices, reducing qubit requirements for tasks such as variational eigensolvers. The works in [15]– [17] also leveraged circuit cutting techniques to facilitate efficient distributed quantum computing across a range of application domains. However, these studies implicitly assume that distributed quantum processors are readily available and willing to participate in cooperative execution. In practical, market-driven environments, quantum processors are often owned by independent entities and may not participate without proper incentives, making incentive design a crucial requirement that is largely missing in the existing literature. Moreover, prior works do not consider energy minimization of quantum computation and measurement transmission, nor

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DVQC, where quantum processors, owned by independent entities, act in their self-interest and participate if only their energy costs are properly compensated (Section II). In the first stage, each processor solves a nonconvex energy minimization problem. This problem is efficiently solved via block coordinate descent (BCD) and successive convex approximation (SCA). Each processor reports its minimized energy cost to the aggregator. Based on these optimized energy costs, the aggregator then solves a system utility maximization problem to select an optimal set of processors under payment budget and qubit coverage constraints. This selection, formulated as a nonconvex combinatorial NP-hard problem, is addressed using alternating direction method of multipliers (ADMM) (Section III). • We conduct extensive numerical experiments to evaluate the learning performance, convergence behavior, and system-level efficiency of the proposed DVQC framework. Results on the MNIST and CIFAR-10 datasets show that DVQC achieves training and testing performance comparable to centralized quantum computing in terms of accuracy and loss, with similar convergence behavior on MNIST and slightly slower initial convergence on CIFAR-10. We further evaluate the proposed energy minimization and system utility maximization frameworks, demonstrating significant gains over baseline strategies. In addition, we compare the proposed NOMAbased uplink with a TDMA scheme, showing that NOMA provides superior energy efficiency and lower transmission latency due to simultaneous measurement outcome transmission. These results confirm the practicality and effectiveness of the proposed framework, particularly in real-world scenarios (Section IV). The principal symbols and notations used throughout this work are summarized in Table II. TABLE II: List of key notations Notation K

Definition Number of quantum processors

Notation S

Definition Optimal subset of processors

fk xk Ôk fagg (·; γ)

Input features Selection variable Observable Post-processing function ground-truth label DVQC iterations

ck θ ϕtk ŷ

(t)

Measurement output Trainable parameters Number of shots Final prediction

L(ŷ, y) quant Ek

Training loss Quantum computing energy Processor’s combined energy

y T Ektrans (t)

sk

(t) γk (t) pk,tra (t) Ak (t) pk,1 (t) pk,M

Nk,2 mk

Measurement transmission energy

Ek

Measurement data size

Rk

(t)

Uplink rate

SNR

B

Bandwidth

Transmit power

σ2

Gaussian noise i

Signal power

Bk

(t)

Interference

1-qubit gate power

pk,2

(t)

2-qubit gate power

Measurement gate power Average 2-qubit gate count Monetary payment

Nk,1

Average 1-qubit gate count Average measurement gate count Payment budget

Nk,M Mmax

Subcircuit 2

… Subcircuit K

𝑅𝑥

𝑅𝑥

𝑅𝑥

𝑅𝑥

𝑅𝑥

𝑅𝑥

𝑅𝑦

𝑅𝑦

𝑅𝑦

𝑅𝑦

𝑅𝑦

𝑅𝑦

Subcircuit 1 Centralized parameterized quantum circuit (PQC)

Circuit cutting Loss

Predicted label

ℒ(𝒚, 𝒚)

𝒚 = 𝒇𝒂𝒈𝒈 (𝒎; 𝜸)

Feature extraction

Data

|0⟩

|0⟩

Encoding |0⟩ |0⟩

𝑅𝑥

𝑅𝑥

𝑅𝑥

𝑅𝑥

|0⟩

|0⟩

𝑅𝑥

𝑅𝑥

𝑅𝑥

𝑅𝑥

𝑅𝑥

𝑅𝑥

𝑅𝑥

𝑅𝑥

𝑅𝑦

𝑅𝑦

𝑅𝑦

𝑅𝑦

𝑅𝑦

𝑅𝑦

Z

Z

Z

Z

Z

Z

Aggregator

Measurement concatenation 𝒎 = [𝑚1 𝑻 , 𝑚2 𝑻 , 𝑚3 𝑻 , … , 𝑚𝐾 𝑻 ]𝑻

𝑚𝐾

…

𝑚2

𝑚1

Measurement SGD

SGD

SGD

Training angle Processor 1

Processor 2 … Processor K

SGD update 𝜃𝑘𝑡+1 = 𝜃𝑘𝑡 − 𝜂𝛻𝜃𝑘 ℒ(𝒚, 𝒚)

Fig. 1: DVQC framework where large PQCs are decomposed into smaller subcircuits that are executed in parallel across independent quantum processors, while a central aggregator orchestrates the process.

II. S YSTEM M ODEL AND P ROBLEM F ORMULATION A. DVQC Learning Model We propose a DVQC framework, as shown in Fig. 1, where a PQC is decomposed into multiple smaller subcircuits leveraging circuit cutting techniques, each executed independently on a dedicated quantum processor. Circuit cutting allows the division of a large quantum circuit into smaller, nonoverlapping subcircuits, such that each can be implemented on devices with fewer qubits [18]. We consider a set of available quantum processors in the market denoted by K = {1, 2, . . . , K}. At the beginning of our DVQC framework, each processor submits a bid to take part in subcircuit execution based on its available qubit capacity and corresponding reported energy cost. Due to the incentive-based selection mechanism introduced later, not all processors are necessarily selected. Instead, the aggregator determines an optimal subset of processors S ⊆ K, where S = {k | xk = 1} denotes the set of winning processors. Here, xk is the binary decision variable that represents whether processor k’s bid wins or not. Only the selected processors in S are assigned subcircuits for DVQC, while the remaining processors may participate in future bidding rounds. A central aggregator extracts features from data, distributes the relevant features to processors according to their assigned qubits, and coordinates optimization through classical feedback. This approach is particularly beneficial when the aggregator lacks quantum processor capable of executing the full PQC requiring a large number of qubits [18], [19]. Instead, the aggregator allocates subcircuit tasks across multiple processors, enabling parallel execution [12], improved hardware utilization, and overcoming qubit count and connectivity limitations of individual devices. We note that qubit constraints in practical quantum systems are not solely determined by the size of the large-scale PQCs. They

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are also influenced by hardware non-idealities such as noise, decoherence, dissipation, limited connectivity, and imperfect gate fidelity. Consequently, even small or moderately sized PQCs may face qubit limitations due to reduced reliability and usable qubit capacity in near-term quantum devices. The steps of our proposed DVQC framework are outlined below: 1) In our proposed DVQC framework, a PQC is decomposed into multiple smaller subcircuits using circuit cutting, where each subcircuit is executed independently on a dedicated quantum processor [18]. The aggregator holds the classical input data (e.g., images, signal values, or sensor measurements), extracts feature representations, and distributes the relevant features to processors based on their assigned qubits for subcircuit execution. 2) Each processor initializes its assigned qubits and encodes the received classical features using parameterized rotation gates before executing its designated subcircuit. The processor then applies its trainable subcircuit to the encoded quantum state. After execution, each processor performs measurements and sends the classical outcomes to the aggregator, which concatenates them into a single measurement vector. 3) The aggregator applies classical post-processing (e.g., a linear layer followed by softmax) to generate predictions and compute the loss, which is then sent back to the processors. The processors use the loss to compute gradients and update their subcircuit parameters via stochastic gradient descent (SGD). These steps repeat until convergence. A block diagram of the proposed DVQC framework is shown in Fig. 2. In our framework, let each classical input data point be denoted by the feature vector f ∈ Rd . Here, the classical input data point corresponds to real samples drawn from a labeled training dataset such as MNIST or CIFAR-10. Each f represents the feature vector of a single data sample (for example, one image) used for supervised learning. Each processor k receives a subset of the input features denoted by fk ∈ Rqk , corresponding to its assigned qubits, where qk is the number of qubits handled by processor k. This feature partitioning is necessary because the original full PQC would encode the entire feature vector across all qubits of a single large quantum device. Due to limited qubit availability, the aggregator distributes the feature vector across multiple selected processors according to their qubit capacities, such that each processor handles only the portion of features mapped to its assigned qubits. Consequently, every data sample is collectively processed by all selected processors. In this work, we adopt feature-based angle encoding, where normalized classical features directly parameterize single-qubit rotation gates. We note that in this work, we use image datasets such as MNIST and CIFAR-10. However, the encoding scheme is dataset-agnostic and can be applied to other data types such as sensor or signal measurements after appropriate feature extraction and processing. After receiving a subset of the input features denoted by fk , processor k initializes its qubits in the |0⟩⊗qk state and performs classical-to-quantum encoding using an encoding unitary Ek (fk ). The resulting quantum state on

processor k is given by |ψk (fk )⟩ = Ek (fk )|0⟩⊗qk ,

(1)

where Ek (fk ) typically consists of parameterized single-qubit rotation gates such as Rx , Ry . We emphasize that the encoding is performed locally at each processor using these featuredependent rotation gates, where the classical features directly act as rotation parameters to embed task-relevant information into quantum states. The full PQC U (θ) is partitioned into |S| smaller subcircuits using circuit cutting techniques, where each subcircuit Uk (θk ) is executed on independent processor k ∈ S over disjoint qubit subsets. Since the selected processors operate on independent Hilbert spaces, the overall distributed quantum operation can be represented as the tensor product of subcircuit unitaries, O U (θ) = Uk (θk ), (2) k∈S

where θ = {θk }k∈S denotes the collection of trainable parameters across all distributed subcircuits. After classicalto-quantum encoding, the encoded quantum state at processor k is given by |ψk (fk )⟩, which serves as the input to its assigned parameterized subcircuit. The quantum evolution at processor k is therefore expressed as |µk ⟩ = Uk (θk )|ψk (fk )⟩,

(3)

where Uk (θk ) is the trainable subcircuit executed locally on processor k ∈ S with parameter vector θk . Following quantum evolution, each processor k ∈ S performs measurements on its local qubits to generate classical outcomes. Let Ôk be the observable measured by processor k, which typically corresponds to Pauli-Z operators. For each input sample at (t) iteration t, processor k executes its assigned subcircuit ϕk times, (i.e., number of measurement repetitions or shots), and measurements are performed after each circuit execution. Denoting the measurement outcome of the r-th repetition by ork , the measurement output is computed as the expectation value averaged over all repetitions as (t)

ϕk 1 X (t) ork ≈ ⟨µk |Ôk |µk ⟩ ck = (t) ϕk r=1

(4)

(t)

where ck ∈ Rqk represents the measurement vector obtained from the qk qubits of processor k ∈ S. The averaging operation reduces the variance caused by finite sampling, i.e., the effect of quantum shot noise. The classical measurement vectors from all selected processors are then transmitted back to the aggregator through classical communication links. The aggregator then concatenates the received measurement vectors to form a global measurement representation given by  ⊤ (t) ⊤ (t) ⊤ (t) ⊤ c(t) = c1 c2 . . . c|S| . (5) Since all subcircuits correspond to disjoint partitions of the original PQC, the concatenated measurement outcomes collectively represent the same input sample. Subsequently, the aggregator performs classical post-processing using a parameterized function fagg (·; γ), such as a fully connected layer

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Feature extraction Feature in aggregator distribution

Encoding and subcircuit 1 execution in processor 1

Measurement

Encoding and subcircuit 2 execution in processor 2

Measurement

Concatenated measurement

Classical post-processing in aggregator

…

Distributed variational quantum computing (DVQC) framework

Encoding and subcircuit K execution in processor K

Measurement

Predicted label

Loss value SGD update in subcircuits

Loss calculation in aggregator

t=1

Fig. 2: Proposed DVQC framework with parallel subcircuit execution and central aggregator coordination.

followed by a softmax activation, to produce the final prediction ŷ = fagg (m; γ), where γ denotes the trainable parameters of the classical layer. This post-processing stage maps the concatenated quantum measurements to task-specific outputs such as class probabilities in classification tasks, thereby linking the distributed quantum computation with a well-defined learning objective. Using the ground-truth label y from the labeled dataset, the aggregator computes a training loss L(ŷ, y), where L can be any suitable loss function such as mean squared error or cross-entropy. Therefore, the optimization objective of the DVQC framework is to minimize the empirical training loss over the dataset. The computed loss value is then transmitted back to the selected quantum processors. Upon receiving the loss information, each processor k ∈ S updates the parameters of its assigned subcircuit θk using gradient-based optimization such as SGD, while the aggregator simultaneously updates the classical aggregation parameters γ. We note that, for the quantum parameters, gradient estimation is performed using quantum-compatible techniques such as the parameter-shift rule. Let t ∈ {1, 2, . . . , T } denote the iteration index of the DVQC training process, where T is the total number of training iterations. At iteration t, the quantum parameters of subcircuit k ∈ S are updated using SGD as θkt+1 = θkt − η∇θk L(ŷ, y),

on all encoded quantum states corresponding to its allocated share of training inputs at each iteration t. Inspired by [2], the quantum computing energy consumption of a selected processor k ∈ S over T DVQC training iterations is expressed as T   X (t) (t) (t) (t) Ekquant = Dk qk ϕk pk,1 Nk,1 + pk,2 Nk,2 + pk,M Nk,M ,

(6)

where η denotes the learning rate of the SGD optimizer. The above steps are executed iteratively across multiple training iterations until the model parameters converge, yielding stable predictions and minimized loss. B. DVQC Processor Energy Model In the proposed DVQC framework, each candidate quantum processor k ∈ K first estimates the total energy required to execute the assigned training workload announced by the aggregator, taking into account its available qubit resources and computational capabilities. Based on this announced workload, all processors in the market locally solve an energy minimization problem to obtain their minimum expected energy consumption for both quantum computation and measurement transmission. The minimized energy value is then reported to the aggregator as a bid, reflecting the processor’s cost of participation and its willingness to contribute computational resources in exchange for monetary incentives. 1) Quantum Computing Energy: If processor k is selected by the aggregator (i.e., k ∈ S), it executes its assigned subcircuit

(7) where Dk is the number of encoded training samples processed by processor k in each DVQC iteration, and qk is the number of qubits involved in the subcircuit. The quantities (t) (t) (t) pk,1 , pk,2 , and pk,M represent the power consumption at iteration t per physical 1-qubit gate, 2-qubit gate, and measurement gate, respectively. In our model, we consider 1-qubit and 2qubit gate operations to align with the practical limitations of near-term quantum processors [12]. Additionally, Nk,1 , Nk,2 , and Nk,M are the average counts of these gates executed in (t) parallel at each time step within the PQC, while ϕk corresponds to the number of noise measurement repetitions during iteration t aimed at error mitigation. In this work, we assume a fixed batch size throughout the DVQC training process, such that each processor k processes a constant number of training samples Dk at every iteration. Therefore, Dk is independent of the iteration index t and is placed outside the summation in (7). For practical scenarios involving varying batch sizes, the formulation can be readily extended by replacing Dk with (t) the iteration-dependent quantity Dk inside the summation. 2) Measurement Transmission Energy: After executing the allocated subcircuits, each quantum processor k ∈ S transmits its measurement outcomes back to the aggregator for further processing. We consider a spatial communication setup where the aggregator and the processors are located at fixed positions. The processors simultaneously upload their measurement data over a shared uplink bandwidth B using power-domain nonorthogonal multiple access (NOMA). We note that our model adopts a NOMA-based uplink communication architecture for measurement transmission, while the DVQC learning framework itself remains general and can be applied to different wireless network architectures. However, we adopt a NOMAbased uplink in this work because NOMA generally outperforms orthogonal multiple access schemes (e.g., TDMA) in terms of transmission efficiency and energy consumption. The wireless channel between processor k and the aggre(t) gator at iteration t is characterized by channel gain hk , which captures large-scale path loss and small-scale Rayleigh fading. We note that the iteration-dependent channel gain does not necessarily imply independent fading realizations across consecutive training iterations. Rather, temporal variations in small-scale fading depend on the channel coherence time and underlying propagation environment. Accordingly, the channel may remain approximately constant over multiple training iterations under slowly varying conditions, while channel variations can be incorporated when the channel conditions change. Let us denote the noise power spectral density as n0 , then the additive white Gaussian noise power over the bandwidth B is given by σ 2 = Bn0 . At the aggregator, SIC is employed to decode the superposed uplink signals. The

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received signals from processors are ordered according to their (t) (t) (t) received signal strength |hk |2 pk,tra , where pk,tra is the uplink transmit power of processor k. Stronger signals are decoded first and subtracted successively during the SIC process. Under this NOMA transmission model, the achievable uplink rate of processor k at iteration t is expressed as   (t) (t) Rk = B log2 1 + γk ,

(8)

(t)

where γk denotes the received signal-to-interference-plusnoise ratio (SINR) of processor k, defined as (t)

(t) γk =

Ak (t)

Bk + σ 2

.

(t)

(t)

Ak = |hk |2 pk,tra

(10)

represents the received signal power from processor k, and (t)

(t)

X

Bk =

(t)

|hj |2 pj,tra

(11)

j∈S,j̸=k (t) (t) (t) (t) |hj |2 pj,tra <|hk |2 pk,tra

denotes the interference from weaker processors whose signals have not yet been canceled by SIC. Consequently, the transmission energy consumption for uploading the measurement outcomes of processor k ∈ S during iteration t is given by (t)

trans,(t)

Ek

=

sk

(t) p , (t) k,tra Rk

(12)

(t)

where sk denotes the size of measurement data transmitted by processor k. Hence, the total transmission energy of processor k over T iterations is calculated as Ektrans =

T X

trans,(t)

Ek

min (t)

(t)

(t)

(t)

(t)

Ek

(15a)

pk,1 , pk,2 , pk,M , ϕk , pk,tra

s.t.

(t)

pk,1 > 0,

∀k, t

(t) pk,2 > 0, ∀k, t (t) pk,M > 0, ∀k, t (t) pk,tra > 0, ∀k, t (t) ϕk > 0, ∀k, t (t) (t) (t) (t) (t) pk,1 + pk,2 + pk,M + pk,tra ≤ Pk,max ,

(15b) (15c) (15d) (15e) (15f) ∀k, t,

(15g)

(9)

Here, (t)

Problem 1:

.

(13)

t=1

Therefore, the combined energy consumption of processor k for quantum computing and measurement transmission over T iterations is quantified as Ek = Ekquant + Ektrans .

(14)

At the beginning of our proposed DVQC framework, processor k solves the following optimization problem to minimize its overall energy consumption for quantum computing and measurement transmission. Hence, we formulate an energy minimization problem
that jointly optimizes subcircuit (t) (t) (t) parameters pk,1 , pk,2 , pk,M , number of noise measurements (t) (t)
ϕk , and resource allocation, i.e., transmit power pk,tra .

where the constraint in (15g) is imposed to ensure that, during each SCA optimization iteration, the values of the left hand side power variables remain within a feasible range and do not exceed the processor’s maximum power budget, thereby maintaining physically realistic and hardware-compliant operation. C. Incentive Model for DVQC In practical DVQC deployments, quantum processors are typically owned and operated by independent entities such as academic institutions, cloud service providers, or private companies. These processors act in their self-interest and are generally unwilling to participate in distributed quantum computing tasks unless they are adequately compensated for the energy and computational resources they expend. This is particularly important for near-term quantum hardware, which is highly energy constrained. Moreover, repeated circuit execution, measurement operations, and transmission of measurement outcomes to the aggregator can incur significant energy consumption. To address this challenge, we propose a two-stage incentive mechanism for DVQC. At the beginning of the DVQC framework, the aggregator announces the quantum computing task along with its required workload to the available processors in the market. In Stage 1, each processor locally minimizes its estimated DVQC energy cost based on the announced workload and its available qubits by solving the processor-side energy minimization problem (i.e., Problem 1) that jointly optimizes subcircuit execution parameters, the number of noise measurements, and communication transmit power. The minimized energy cost is then reported to the aggregator as the processor’s bid. In Stage 2, the aggregator uses the reported energy costs to solve a system utility maximization problem to select an optimal subset of processors under payment budget and qubit coverage constraints. In practical quantum computing market, multiple processors compete to execute portions of the PQC in order to earn these incentives [18], creating a competitive environment that encourages efficient use of computational resources and reliable task execution. In our framework, the aggregator offers processor k a monetary payment mk as a compensation for executing its assigned subcircuit and transmitting measurement outcomes for T iterations. Each processor k reports its estimated minimized total energy cost Ek to the aggregator. Based

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on these reported energy costs and available qubit capacities of the processors, the aggregator determines the set of winner processors by solving a system utility maximization problem. The objective is to maximize the net system utility, defined as the aggregate difference between the offered payments and the energy costs of the processors, while satisfying the payment budget and required qubit coverage constraints. Specifically, at the beginning of the DVQC framework, the aggregator solves the following optimization problem: Problem 2:

max xk

s.t.

K  X

 mk − Ek xk

(16a)

III. P ROPOSED S OLUTION A. Energy Optimization using BCD and SCA Problem 1 is difficult to solve directly because of its nonconvex objective function, making it unsuitable for standard convex optimization techniques. To overcome this, we use block coordinate descent (BCD) and successive convex approximation (SCA) techniques that splits the problem into two smaller, tractable subproblems. In particular, we divide (t) (t) (t) (t) the control variables into two groups: (pk,1 , pk,2 , pk,M , ϕk ) (t) and (pk,tra ). The two subproblems are solved in an iterative manner until the convergence is achieved. Sub-problem 1 (Joint processor subcircuit power control and number of noise measurements optimization):

k=1

xk ∈ {0, 1}, K X k=1 K X

∀k,

mk xk ≤ Mmax , qk xk ≥ Q,

∀k,

(16b) ∀k,

(16c)

(16d)

k=1

where xk is the binary decision variable indicating whether processor k is selected by the aggregator to participate in subcircuit execution (i.e., xk = 1 if selceted, and xk = 0 otherwise), and (16b) is the corresponding binary constraint. Moreover, Mmax in (16c) is the total payment budget the aggregator can allocate. Furthermore, to guarantee sufficient qubit coverage in the DVQC framework, we impose the constraint (16d), where qk is the number of qubits in processor k and Q is the total number of qubits in the original PQC. This ensures the selected subcircuits collectively cover the entire PQC. From Problem 2, it is clear that the aggregator does not pre-define how qubits are divided among subcircuits; instead, this partitioning emerges as a result of the system utility maximization process. We note that, our proposed incentive mechanism is closely tied to the energy optimization performed by each processor. To increase their chances of selection and maximize system utility, processors minimize their reported energy costs by solving the processor-side energy minimization problem (i.e., Problem 1). Using these reported energy values, the aggregator then solves the system utility maximization problem (i.e., Problem 2) to select an optimal subset of processors for DVQC execution. Therefore, Problem 1 and Problem 2 are interdependent in our framework. Since the aggregator selects processors based on the difference between offered payment and reported energy cost, processors that operate in a more energy-efficient way are more likely to be selected and compensated. This interaction establishes a natural equilibrium between processor incentives and aggregator objectives, where processors minimize energy to improve their selection probability while the aggregator maximizes system utility under budget and qubit constraints. Consequently, the proposed two-stage framework achieves a balanced trade-off between processor compensation and system efficiency.

min (t)

(t)

(t)

(t)

Ek

(17a)

pk,1 , pk,2 , pk,M , ϕk

s.t.

(t)

pk,1 > 0,

∀k, t

(t) pk,2 > 0, ∀k, t (t) pk,M > 0, ∀k, t (t) ϕk > 0, ∀k, t (t) (t) (t) (t) (t) pk,1 + pk,2 + pk,M + pk,tra ≤ Pk,max ,

(17b) (17c) (17d) (17e) ∀k, t.

(17f)

Sub-problem 2 (Processor transmit power optimization): min

Ek

(t)

(18a)

pk,tra (t)

pk,tra > 0,

s.t.

∀k, t

(t) (t) (t) (t) (t) pk,1 + pk,2 + pk,M + pk,tra ≤ Pk,max ,

(18b) ∀k, t.

(18c)

⋆ Sub-problem 1 (Joint processor’s subcircuit power control and number of noise measurements optimization): Sub-problem 1 in (17) is inherently non-convex because of the objective function in (17a). Consequently, our next step is to transform (17) into a convex formulation. (17a): We express the objective function as Ek =Dk qk

T X

(t)

ϕk



(t)

(t)

(t)

pk,1 Nk,1 + pk,2 Nk,2 + pk,M Nk,M



t=1

+ Ektrans .

(19)

The first, second, and third terms in the objective function of (19) is non-convex; therefore, we proceed to apply convexification techniques to these terms. For the first term of the (t) (t) objective function, and ϕk > 0 and pk,1 > 0, we leverage (t) (t) SCA to approximate ϕk pk,1 as (t)

(t) 1 ϕk i (t) 2 (t) 2 ϕ + p , 2 ϕ(t) k 2 p(t) k,1 k i k,1 i

1 (t) (t) ϕk pk,1 ≤

pk,1 i

(20) (t)

where i denotes the SCA iteration index. Similarly, for pk,2 > (t) 0 and pk,3 > 0, we convexity the second and third terms as

8

p

(t) (t)

(t)

(t) 2

i ϕk pk,2 ≤ 21 k,2 (t) ϕk

ϕk

(t) 1 ϕk i (t) 2p k,3 i

ϕ

(t)

(t) 2

(t) (t)

p

(t)

(t) 2

k i i pk,2 , ϕk pk,3 ≤ 21 k,3 + 21 (t) (t) ϕk

pk,2

i

(t) 2

ϕk

i

+

i

pk,3 .

After convexification, Sub-problem 1 is written as follows. Sub-problem 1 (convex equivalent):  (t) (t) T  X 1 pk,2 i (t) 2 1 ϕk i (t) 2 min Dk qk ϕ + p Nk,1 (t) (t) 2 ϕ(t) k 2 p(t) k,2 pk,1 , pk,2 , t=1 k i k,2 i (t)

(t)

pk,M , ϕk

 +  +

s.t.

 (t) (t) 1 pk,3 i (t) 2 1 ϕk i (t) 2 ϕ p + Nk,2 2 ϕ(t) k 2 p(t) k,3

k i k,3 i   (t) (t) 1 pk,M i (t) 2 1 ϕk i (t) 2 trans,(t) ϕ pk,M Nk,M + Ek + 2 ϕ(t) k 2 p(t) k i k,M i

(17b), (17c), (17d), (17e), (17f).

(21a) (21b)

The problem in (21) is a standard convex optimization problem that can be solved efficiently using tools such as CVX. Complexity Analysis of Sub-problem 1: This problem contains 4KT scalar decision variables and 5KT linear constraints, resulting in a per-iteration computational √
complexity approximately proportional to O (4KT )2 5KT [20]. ⋆ Sub-problem 2 (Processor’s transmit power optimization): Sub-problem 2 in (18) in non-convex because of the objective function in (18a). Hence, we now convexify (18a). (18a): From (14), we have Ek = Ekquant + Ektrans .

Ek = Ekquant +

(t) k p . (t) k,tra

The detailed convexification process is provided in Appendix A. i (26b): Using the inequality ln(1 + ψ) ≥ ln(1 + ψi ) + ψψ − i +1 (ψi )2 1 ψi +1 ψ [21], the left-hand side of (26b) is written as follows:

ln(1 + δi ) +

(23)

(t) (t) |hk |2 pk,tra i (t) Bk +σ 2

B log2 1 +

(t)

(t)

 ≤ α.

(t)

|hk |2 pk,tra (t)

Bk +σ 2

and δi =

(t)

(t)

(t)

(24)

(t)

αpk,tra ≤

1 pk,tra i 2 1 αi (t) 2 α + p . 2 αi 2 p(t) k,tra

(29)

k,tra i

After convexification, Sub-problem 2 is written as follows. Sub-problem 2 (convex equivalent):

(t) |hk |2 pk,tra

(28)

approximate αpk,tra as

The second term in (24) is non-convex because of the presence of the log function. For the second term of the objective function, we introduce a slack variable α defined as 

δi (δi )2 1 β ln 2 − ≥ , δi + 1 δi + 1 δ B

. For α > 0 and pk,tra > 0, we use SCA to

Bk +σ

sk

)), while β serves as

a lower bound on the achievable transmission rate log2 (1 + (t) (t) (t) (|hk |2 pk,tra /(Bk + σ 2 ))). By introducing α and β, the nonconvex fraction is transformed into two constraints: a bilinear constraint (26a), and logarithmic constraint (26b). This decomposition enables us to handle the bilinear and logarithmic terms separately and apply SCA to obtain a tractable convex surrogate at each iteration, while preserving equivalence to the original non-convex objective function. Next, we investigate the convexity properties of the inequalities within this system. (26a): Using first-order Taylor expansion, we approximate (26a) as   1 (αi + βi )2 + 2(αi + βi )(α + β − αi − βi ) 4 1 (t) (27) − sk ≥ (α − β)2 . 4

(t)

s  k (t) (t)  p(t) k,tra . |hk |2 pk,tra t=1 B log (t) 2 1+ 2

(t) Bk +σ 2

(t)

t=1 Rk

T X

(t)

|hk |2 pk,tra

where δ and δi are defined as δ =

Substituting (8), (9), and (10) into (23), we write Ek =Ekquant +

(t)

(t)

component (sk /B log2 (1 +

(22)

Substituting (13) and (12) into (22), we get T (t) X s

fractional term that involves the logarithmic rate expression under the NOMA-based uplink model. As we aim to minimize the objective function, i.e., the energy consumption, we introduce α as an upper bound on the transmission time

(25)

(t)

Bk +σ 2

Next, we introduce an additional slack variable β, and reformulate (25) as follows:  (t)  (26a)  sk ≤ αβ,  ! (t) 2 (t) (25) ⇔ |hk | pk,tra  ≥ β. (26b)   B log2 1 + (t) Bk + σ 2 Equation (25) is equivalent to this system of inequalities. This reformulation is adopted to decouple the original non-convex

min (t)

pk,tra

s.t.

Ekquant +

(t) T  X 1 pk,tra t=1

i

2 αi

(42), (28), (18b), (18c).

α2 +

1 αi (t) 2 p 2 p(t) k,tra

 (30a)

k,tra i

(30b)

The problem in (30) is a standard convex optimization problem that can be solved efficiently using tools such as CVX. The procedure for solving Problem 1 using the proposed BCD-SCA method is summarized in Algorithm 1. Complexity Analysis of Sub-problem 2: This problem contains (KT ) scalar decision variables and (4KT ) linear constraints, resulting in a per-iteration computational √
complexity approximately proportional to O (KT )2 4KT [20].

9

Algorithm 1 SCA-based Joint Optimization Algorithm Input: Set the iteration index i = 0; (t) (t) (t) (t) (t) Define a feasible initial solution pk,1 , pk,2 , pk,M , ϕk 0 , pk,tra for 0 0 0 0 Problem 1; Repeat Set i ← i + 1 (t) (t) (t) Solve Sub-problem 1 (Equivalent) to obtain pk,1 , pk,2 , pk,M , i

(t)

ϕk i ;

i

B. ADMM-based Winner Selection Optimization The winner selection optimization problem, i.e., Problem 2, maximizes a linear objective function subject to binary selection constraints and a global payment budget. The binary (integer) selection constraints make the feasible set discrete and non-convex. Although the objective function is linear, these binary constraints cause the overall winner selection problem to become a non-convex combinatorial optimization problem that is NP-hard and computationally challenging to solve optimally. To efficiently solve the problem, we adopt the alternating direction method of multipliers (ADMM) framework. Variable updates of ADMM: To enable tractable optimization, we first relax the binary constraints to continuous box constraints and then apply variable splitting to decompose the problem into simpler subproblems. Specifically, the binary variable xk ∈ {0, 1} is relaxed to continuous variable xk ∈ [0, 1], enabling a convex relaxation of the original problem. We now introduce an auxiliary variable zk to separate the budget constraint from the objective function, leading to the following equivalent reformulation:

xk ,zk

s.t.

K  X

 mk − Ek xk

(31a)

k=1

xk ∈ {0, 1}, K X k=1 K X

∀k,

(31b)

mk zk ≤ Mmax ,

(31c)

qk zk ≥ Q,

(31d)

∀k,

k=1

xk = zk ,

∀k.

(32)

k=1

(i)

(t)

−

k=1

2 K  ρ X (i) (i) (i) + xk − z k + λ k , 2

i

Solve Sub-problem 2 (Equivalent) to obtain pk,tra ; i Until convergence. Output: (t) ∗ (t) ∗ (t) ∗ (t) ∗ (t) ∗ Optimal pk,1 , pk,2 , pk,M , ϕk , pk,tra .

min

function at ADMM iteration i is defined as  K  X (i) (i) (i) (i) Lρ (xk , zk , λk ) = − mk − Ek xk

(31e)

Since ADMM is inherently designed to solve minimization problems, we minimize the negative of the original maximization objective function. We denote the inner iteration index within the ADMM algorithm itself as i. Specifically, before starting the DVQC training, ADMM runs several update iterations indexed by i = 1, 2, 3, . . . , I until convergence for winner selection optimization. The augmented Lagrangian

where ρ > 0 is a penalty parameter and λk is a scaled dual variable associated with the equality constraint. In ADMM, the augmented Lagrangian combines the objective function and the constraints using dual variables and penalty terms, enabling decomposition of the problem into simpler subproblems while enforcing constraint satisfaction. Now, at ADMM iteration i + 1, the algorithm updates the variables as follows: (i) (i) 1) Update of xk : Fixing zk and λk , variable xk is updated    mk − E k (i+1) (i) (i) , xk = min 1, max 0, zk − λk + ρ ∀k ∈ K. (33) The detailed derivation of the update for xk is provided in Appendix B. (i) (i) (i) 2) Update of zk : Fixing xk and λk , variable zk is updated by solving the following optimization problem at iteration i + 1:   ρ (i+1) (i+1) (i) 2 zk = arg min ∥x − zk + λk ∥2 zk 2 k K X s.t. mk zk ≤ Mmax , ∀t, k=1 K X

qk zk ≥ Q,

k=1

0 ≤ zk ≤ 1,

∀k.

(34)

More specifically, the problem in (34) reduces to finding the Euclidean projection of v onto the half-space   ⊤ ⊤ C = z|m z ≤ Mmax , q z ≥ Q, 0 ≤ z ≤ 1 . (35) We note that v, x(i+1) , λ(i) , m, z, and q are vectors defined (i+1) (i+1) (i+1) , . . . , xK ], as v = [v1 , v2 , . . . , vK ], x(i+1) = [x1 , x2 (i) i i i λ = [λ1 , λ2 , . . . , λK ], m = [m1 , m2 , . . . , mK ], z = [z1 , z2 , . . . , zK ], and q = [q1 , q2 , . . . , qK ], representing the vectors of auxiliary variables (v), processor selection variables, dual variables, payment offers, auxiliary variables (z), and qubit capacities, respectively. If v ∈ C, i.e., m⊤ z ≤ Mmax , q⊤ z ≥ Q, 0 ≤ z ≤ 1, then the projection is z(i+1) = v, (i+1) (i+1) (i+1) , . . . , zK ]. Otherwise, z(i+1) where z(i+1) = [z1 , z2 is obtained as the solution to the convex quadratic programming problem in (34), which finds the point in C closest to v in Euclidean distance. This projection is generally computed using numerical solvers specialized for QP. In this work, we solve the problem in (34) using the CVXPY optimization library, which efficiently finds the closest feasible point to v under the budget, qubit coverage, and box constraints. We note that at ADMM iteration (i + 1), the optimization variables are updates sequentially in the order xk , zk , and

10

(i+1)

(i+1)

λk . Therefore, when updating zk , the variable xk has (i+1) already been updated, while λk is not yet available and (i) remains at its previous value λk . Consequently, the quadratic (i+1) (i) term in (34) depends on xk and λk , which motivates defining an auxiliary variable (vector) v as v := x(i+1) + λ(i) .

(36)

Since the objective function in (34) contains only the quadratic (i+1) (i) − zk + λk ∥22 , the update of z correpenalty term ρ2 ∥xk sponds to minimizing the squared Euclidean distance between z and the intermediate point x(i+1) +λ(i) . Therefore, the problem is equivalently interpreted as projecting v = x(i+1) + λ(i) onto the feasible set defined by the budget constraint, qubit capacity constraint, and box constraint. Clearly, the objective is strictly convex and the constraints are linear. Therefore, the resulting problem is a convex quadratic program (QP) with a unique global solution. 3) Update of λk : After updating xk and zk for all k ∈ K, the variable λk is updated as (i+1) (i) (i+1) (i+1) λk = λk + xk − zk ,

∀k ∈ K.

(37)

(i+1) (i+1) (i) From (37), it is clear that if xk and zk are close, λk

changes less, indicating the constraint (31e) is being better satisfied. Convergence criteria of ADMM: The ADMM algorithm iterates until: • The primal residual measures how close x and z are as ∥xi+1 − zi+1 ∥2 . • The dual residual measures how much z changes between iterations, scaled by penalty ρ as ρ∥zi+1 − zi ∥2 . The algorithm terminates when both primal and dual residuals fall below predefined thresholds ϵprim , ϵdual as: ( ∥xi+1 − zi+1 ∥2 ≤ ϵprim (38) ρ∥zi+1 − zi ∥2 ≤ ϵdual . When both residuals fall below the preset small thresholds, the algorithm is considered to have converged, indicating: • Primal feasibility: x ≈ z. • Dual feasibility: The updates have stabilized. Final rounding step of ADMM: Because the binary constraint xk ∈ {0, 1} was relaxed to continuous constraint xk ∈ [0, 1], the solution xk at convergence is not binary. To obtain a feasible binary solution, a thresholding or rounding step is applied as ( (i) 1, if xk ≥ τ, xk ∗ = ∀k ∈ K, (39) 0, otherwise, where τ is a threshold, typically set to 0.5. We mention that our ADMM approach differs from standard ADMM by incorporating complex, problem-specific constraints, including total payment budget, qubit coverage, and box constraints. While standard ADMM often uses simple, closed-form updates for unconstrained or lightly constrained problems [22], our formulation requires solving a constrained quadratic program during the projection step, i.e., update of zk . This projection ensures feasibility under all incentive and resource constraints and is

handled numerically using CVXPY, making our method more specialized and tailored than generic ADMM. Complexity Analysis of ADMM: The computational complexity of the ADMM-based incentive optimization is dominated by the zk -update , which requires solving a convex quadratic program with complexity O(K 3 ) per ADMM iteration, while the updates of xk and λk are both of complexity O(K) [23]. Overall, the total complexity is O(IK 3 ), where I is the number of ADMM iterations. In practice, the ADMMbased winner selection algorithm converges within a very small number of iterations (e.g., around 3-5 iterations as observed in Fig. 10) and is executed only once prior to DVQC training, resulting in negligible overhead compared to the overall learning process. Moreover, unlike exhaustive search with exponential complexity O(2K ), the proposed method achieves scalable polynomial-time complexity O(IK 3 ). IV. S IMULATION R ESULTS AND E VALUATION A. Parameter Setting for DVQC framework We evaluate our proposed DVQC framework using TorchQuantum across two benchmark datasets: MNIST [24] and CIFAR-10 [25]. To simulate circuit cutting, we use two partitioning configurations of PQCs. In the first configuration, a 4-qubit PQC is decomposed into two 2-qubit subcircuits, each executed independently by a quantum processor. In the second configuration, a 6-qubit PQC is partitioned into three subcircuits consisting of 1, 2, and 3 qubits, respectively. For both configurations, classical input features are encoded into quantum states via single-qubit Rx gates. The encoded quantum state is then distributed across multiple quantum processors, each executing its designated subcircuit. All quantum subcircuits contain trainable single-qubit rotation gates, i.e., Rx and Ry , followed by Pauli-Z measurements. Measurement results from all subcircuits are aggregated and processed by a classical linear layer, followed by a log-softmax activation function for final classification. All models are trained using the SGD optimizer with a learning rate of 0.001. We train the models for 50 epochs using batch sizes of 64 for training. The models are evaluated on previously unseen test samples using a batch size of 64 to assess their classification accuracy and loss, where 80% of the MNIST and CIFAR-10 datasets are used for training and the remaining 20% for testing. Experiments are conducted on GPU-enabled environments. B. Parameter Setting for DVQC Energy Minimization To evaluate the performance of our proposed energyefficient DVQC framework, we conduct simulations that jointly optimize several critical parameters: processor’s PQC power consumption, the number of noise measurements, and resource allocation (communication transmission power). The simulation parameters are chosen to align with realistic operational settings [26], [27]. All experiments are implemented in MATLAB using the YALMIP toolbox in conjunction with the MOSEK solver. The system bandwidth is considered to be of 20 MHz. The processor’s total power budget for PQC (t) operation and wireless transmission, denoted by Pk,max , ranges from 20 to 40 dB. The number of noise measurements ranges from 20 to 40. The noise power spectral density n0 is assumed

11

0

10

0

10

0.72

0.575 0.550 0.525 0.500 0.475 0.450 0.425 0

10

(c) Training accuracy on CIFAR-10.

20

Epoch

30

40

0.56

50

Accuracy

0.70 0.69 0.68 0.67

10

20

Epoch

30

40

0.75 0.70 0.65 0.60

0

10

Proposed DVQC with circuit cutting Centralized quantum computing 20 30 40 50 Epoch

0.68 0.66 0.64 0.62 0.60 0.58 0.56 0.54

0

10

Proposed DVQC with circuit cutting Centralized quantum computing 20 30 40 50 Epoch

(c) Training accuracy on CIFAR-10 dataset.

Epoch

30

40

0.68 0.67 0.66 0.65 0.64 0.63 0.62 0.61

Accuracy

50

Proposed DVQC with circuit cutting Centralized quantum computing

10

20

Epoch

30

40

20

30 40 Epoch

50

60

70

10

20

30 40 Epoch

50

60

70

Loss

(d) Testing loss on CIFAR-10 dataset.

0.50 0.45

0.86

0.40

0.84

0

10

0.690 0.685 0.680 0.675 0.670 0.665 0.660

Proposed DVQC with circuit-cutting Centralized quantum computing

0.35 0.30

Proposed DVQC with circuit-cutting Centralized quantum computing 20 30 40 50 60 70 Epoch

0.25

0

10

0

10

30 40 Epoch

50

60

70

Proposed DVQC with circuit-cutting Centralized quantum computing

0.63

Proposed DVQC with circuit-cutting Centralized quantum computing 20 30 40 50 60 70 Epoch

20

(b) Testing loss on MNIST dataset. 0.64

(c) Testing accuracy on CIFAR-10 dataset. 0

10

Proposed DVQC with circuit-cutting Centralized quantum computing

0

(a) Testing accuracy on MNIST dataset. 20

(b) Training loss on MNIST dataset.

Loss

Accuracy

(a) Training accuracy on MNIST dataset.

Proposed DVQC with circuit-cutting Centralized quantum computing 20 30 40 50 60 70 Epoch

0.88

0.80

10

0

0.700 0.695 0.690 0.685 0.680 0.675 0.670 0.665 0.660

0.90

0.82

0

Proposed DVQC with circuit cutting Centralized quantum computing

Fig. 5: Testing accuracy and loss on MNIST and CIFAR-10 datasets using a 4-qubit PQC, where the proposed DVQC model applies circuit cutting by dividing the circuit into two 2-qubit subcircuits, compared against a centralized 4-qubit baseline.

Accuracy

Loss

Accuracy

0.80

Proposed DVQC with circuit cutting Centralized quantum computing

0.69 0.68 0.67 0.66 0.65 0.64 0.63 0.62 0.61

(b) Testing loss on MNIST dataset.

(c) Testing accuracy on CIFAR-10 dataset.

to be −174 dB. 0.85

10

50

Fig. 3: Training accuracy and loss on MNIST and CIFAR-10 datasets using a 4-qubit PQC, where the proposed DVQC model applies circuit cutting by dividing the circuit into two 2-qubit subcircuits, compared against a centralized 4-qubit baseline.

0.65 0.60 0.55 0.50 0.45 0.40 0.35 0.30

10

0.600 0.575 0.550 0.525 0.500 0.475 0.450 0

0

(d) Training loss on CIFAR-10 dataset.

0.90

0

Proposed DVQC with circuit cutting Centralized quantum computing 20 30 40 50 60 70 Epoch

(a) Testing accuracy on MNIST dataset.

Proposed DVQC with circuit cutting Centralized quantum computing

0.71

Proposed DVQC with circuit cutting Centralized quantum computing 20 30 40 50 Epoch

0.60 0.58

(b) Training loss on MNIST dataset.

Loss

Accuracy

(a) Training accuracy on MNIST dataset.

0.62

Loss

0.56

Proposed DVQC with circuit cutting Centralized quantum computing 20 30 40 50 Epoch

0.64

Loss

0.58

0.66

Loss

0.60

Proposed DVQC with circuit cutting Centralized quantum computing

0.68 0.67 0.66 0.65 0.64 0.63 0.62

Accuracy

0.62 Loss

Accuracy

0.64

0.62 0.61 0.60 0.59

0

10

20

30 40 Epoch

50

60

70

(d) Testing loss on CIFAR-10 dataset.

50

(d) Training loss on CIFAR-10 dataset.

Fig. 4: Training accuracy and loss on MNIST and CIFAR-10 datasets using a 6-qubit PQC, where the proposed DVQC model applies circuit cutting by splitting the circuit into three subcircuits consisting of 1, 2, and 3 qubits, respectively, compared against a centralized 6-qubit baseline.

C. Parameter Setting for Utility Maximization for Incentive Mechanism In our utility maximization experiments, we consider a scenario with K = 10 candidate quantum processors. The payment offer mk lies within the range of 10 to 50 units, reflecting the monetary compensation proposed by the aggregator for executing the assigned subcircuit and transmitting (t) measurement outcomes. The energy cost Ek ranges from 10 to 30 Joules, capturing both the quantum computation energy and the communication energy required by processor. The qubit capacity qk varies between 2 and 7 qubits, indicating the number of qubits available for subcircuit execution on each processor. The total incentive budget at the aggregator is set to

Fig. 6: Testing accuracy and loss on MNIST and CIFAR-10 datasets using a 6-qubit PQC, where the proposed DVQC model applies circuit cutting by splitting the circuit into three subcircuits consisting of 1, 2, and 3 qubits, respectively, compared against a centralized 6-qubit baseline.

Mmax = 120 units, and the required qubit coverage to complete the centralized PQC is Q = 12. The aggregator solves a utility maximization problem under these constraints using the ADMM algorithm, aiming to select a subset of processors that maximizes the system utility while satisfying the budget and qubit constraints. D. DVQC Model Training Performance Fig. 3 shows training accuracy and loss performance on the MNIST and CIFAR-10 datasets using a 4-qubit PQC, where the proposed DVQC model applies circuit cutting by dividing the circuit into two 2-qubit subcircuits, each assigned to a separate quantum processor, and compares it against a 4-qubit centralized quantum computing baseline. Fig. 3a presents the training accuracy on the MNIST dataset where both models exhibit competitive performance, maintaining

12

Proc-T-OPT Proc-PC-NM Proc-PC Proc-CTP Greedy

700

Energy (Joule)

600 500 400 300 200 100 0

2

4

6

8

Iteration

10

Fig. 7: Comparison of energy optimization performance among different schemes.

24 22 20 18

Proc-T-OPT Proc-PC-NM Greedy

50.0

Energy (Joule)

26

Energy (Joule)

52.5

Proc-T-OPT Proc-PC-NM Proc-PC Proc-CTP Greedy

28

47.5 45.0 42.5 40.0 37.5

20

25

30

35

Processor's power budget, Pk,(t)max (dB)

40

(a) Processor’s energy consumption versus its maximum allowable power threshold.

35.0

20

25

30

35

40

Number of maximum noise measurements, k,(t)max

(b) Processor’s energy consumption versus its maximum noise measurements.

Fig. 8: Performance evaluation of processor’s energy consumption under varying system parameters.

similar accuracy levels across 50 training epochs. This demonstrates that DVQC can effectively scale quantum computing models without sacrificing learning performance, making it a viable solution for near-term, resource-constrained quantum hardware. Fig. 3b illustrates the corresponding training loss where both approaches demonstrate a consistent downward trend. The DVQC model, which utilizes two 2-qubit subcircuits, closely tracks the centralized model’s loss performance throughout the epochs. Minor fluctuations in the centralized model suggest slightly higher sensitivity to noise. Fig. 3c demonstrates the training accuracy on the CIFAR-10 dataset under similar settings, exhibiting a trend consistent with the MNIST results. Fig. 3d presents the corresponding training loss, where DVQC and centralized models exhibit similar behavior, confirming that DVQC maintains stable and effective learning even for more complex datasets. Fig. 4 shows the training accuracy and loss on the MNIST (Fig. 4a and Fig. 4b) and CIFAR-10 (Fig. 4c and Fig. 4d) datasets using a 6-qubit PQC. The proposed DVQC model applies circuit cutting by splitting the 6-qubit PQC into three smaller subcircuits of 1, 2, and 3 qubits. It achieves similar final training accuracy and loss to the centralized 6-qubit model on both MNIST and CIFAR-10 datasets. Although the

proposed DVQC framework exhibits convergence behavior similar to centralized quantum computing on MNIST, it shows slower initial convergence on the more complex CIFAR-10 dataset, as observed in Fig. 4d. Initially, the proposed DVQC framework requires additional training epochs to obtain the loss performance achieved by centralized quantum computing. The slower initial convergence is attributed to the partitioning of the original PQC into smaller subcircuits, which changes the circuit architecture and parameterization, potentially affecting gradient-based optimization. This effect may be more pronounced for complex datasets such as CIFAR-10, despite the coordinated parameter updates guided by a common global loss. Nevertheless, the difference in training loss gradually diminishes, and both approaches achieve approximately the same final loss after 50 epochs. These results demonstrate that by distributing the computation across smaller subcircuits, DVQC achieves comparable final training performance, despite differences in convergence speed, making it practical for near-term quantum hardware with limited qubit capacity. We note that the objective of DVQC is not to surpass centralized quantum computing. Rather, it aims to enable feasible execution of large PQCs under realistic qubit limitations by distributing the workload across multiple quantum processors with smaller qubit capacities, while still achieving comparable performance in terms of final accuracy and loss. Therefore, these results are consistent with the theoretical design of the proposed DVQC framework. Specifically, although the original PQC is partitioned into multiple smaller subcircuits, all processors are jointly optimized through a common global loss computed at the aggregator, enabling coordinated parameter updates across the distributed quantum processors. Consequently, circuit cutting primarily reduces the per-processor qubit requirement while allowing the distributed framework to achieve similar final learning performance, although its convergence rate may differ from that of centralized quantum computing, particularly for more complex datasets such as CIFAR-10. These observations validate that the proposed DVQC framework effectively addresses the practical qubit limitations without introducing degradation in learning capability. To further evaluate the generalization capability of the proposed DVQC framework, Fig. 5 and Fig. 6 present the testing accuracy and testing loss on the MNIST and CIFAR10 datasets under the 4-qubit (2+2) and 6-qubit (1+2+3) PQC partitioning configurations, respectively, compared with their corresponding centralized quantum computing baselines. As shown in Fig. 5a and Fig. 5b, the proposed DVQC framework achieves testing accuracy and loss comparable to the centralized 4-qubit model on MNIST, with both approaches exhibiting similar performance trends. Likewise, Fig. 5c and Fig. 5d demonstrate that DVQC closely matches the testing accuracy and loss of centralized quantum computing on CIFAR-10, while exhibiting slightly faster initial improvement in accuracy and reduction in loss. For the 6-qubit configuration, Fig. 6a and Fig. 6b show that the proposed DVQC and centralized quantum computing models achieve nearly identical testing accuracy and loss on MNIST. Meanwhile, Fig. 6c and Fig. 6d indicate that the DVQC achieves similar testing accuracy to centralized quantum computing on CIFAR-10, although its

Proposed Proc-T-OPT with NOMA Proc-T-OPT with TDMA

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(a) Convergence of the energy minimiza-

(b) Processor energy consumption versus the

(c) Measurement outcome transmission time

tion approach Proc-T-OPT under NOMA and TDMA transmission schemes.

number of selected quantum processors under NOMA and TDMA.

versus the number of selected quantum processors under NOMA and TDMA.

Fig. 9: Comparison between the proposed NOMA-based DVQC framework and the TDMA baseline in terms of overall energy consumption and transmission performance.

testing loss converges more slowly during the initial epochs, with both approaches eventually reaching similar loss values. Overall, these testing results complement the training performance and demonstrate that the proposed DVQC framework achieves testing accuracy and loss comparable to centralized quantum computing across both datasets and circuit partitioning configurations, providing further evidence of its ability to generalize to previously unseen data while reducing the qubit requirements of individual quantum processors. E. DVQC Energy Optimization Performance We compare our proposed joint optimization approach, referred to as Proc-T-OPT, with four benchmark schemes: (i) Proc-PC-NM, which optimizes only processor’s PQC power control and number of noise measurements; (ii) Proc-PC, which optimizes only processor’s PQC power control, (iii) Proc-CTP, which optimizes only processor’s communication transmit power; and (iv) a Greedy scheme that performs uncoordinated resource allocation without joint consideration of optimization variables. Fig. 7 compares the energy optimization performance of Proc-T-OPT with four benchmark schemes over ten iterations. As illustrated in the figure, ProcT-OPT achieves substantial reduction in processor energy consumption, converging to a much lower energy level than the other schemes. After six iterations, the energy consumed by Proc-T-OPT is reduced by approximately 89.74%, 92.59%, 93.33%, and 94.87% relative to Proc-PC-NM, Proc-PC, ProcCTP, and Greedy, respectively. The superior performance of Proc-T-OPT stems from the joint optimization of quantum computation and communication resources through the proposed BCD-SCA framework. By jointly optimizing PQC gate powers, number of noise measurements, and transmit power, the algorithm effectively exploits the interdependence among these variables, leading to a significantly lower overall energy consumption than optimizing only a subset of variables. Fig. 8a shows how processor energy consumption varies with its maximum allowable power budget for different optimization schemes. As the power budget increases, energy consumption rises for all methods. However, Proc-T-OPT consistently achieves the lowest energy consumption across all power budget levels. In contrast, Greedy and Proc-CTP incur

significantly higher energy use, while Proc-PC-NM and ProcPC provide moderate improvements. These results highlight that joint optimization in Proc-T-OPT leads to more efficient energy use, especially as resource constraints are relaxed. Fig. 8b illustrates the effect of increasing the maximum number of noise measurements on processor energy consumption. Across all schemes, energy consumption increases with more noise measurements, but the rate of increase is much lower for Proc-T-OPT compared to the others. Although Proc-PC-NM outperforms Greedy, it lags behind Proc-T-OPT, emphasizing the advantage of comprehensive joint optimization over partial or uncoordinated strategies. This demonstrates Proc-T-OPT’s effectiveness in controlling energy costs even as noise measurement demands grow. The observed trends are consistent with the proposed processor energy model, where both the maximum budget and the number of noise measurements directly influence the total energy consumption. A larger power budget allows higher operating power during quantum gate execution and communication, while increasing the number of noise measurements requires additional circuit executions, thereby increasing quantum computing energy. Since Proc-TOPT jointly optimizes all energy-related variables, it results in significantly slower increase in energy consumption than the benchmark schemes as system resources increase. We note that only Proc-T-OPT, Proc-PC-NM, and the Greedy scheme are shown in Fig. 8b, since the maximum number of (t) noise measurements ϕk,max affects only schemes that optimize (t) number of noise measurements ϕk , whereas Proc-PC and Proc-CTP are independent of this parameter. Fig. 9 compares the proposed NOMA-based DVQC framework with the TDMA baseline in terms of energy consumption and transmission performance. Fig. 9a demonstrates the convergence performance of the joint optimization approach Proc-T-OPT for processor energy minimization under NOMA and TDMA schemes. It is observed that the processor energy consumption decreases sharply during the first few iterations before reaching a stable minimum, while consistently achieving lower energy under NOMA than under TDMA. This behavior directly follows from the proposed NOMA-based uplink model, where simultaneous measurement transmission

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reduces idle waiting, thereby shortening the communication phase of each DVQC iteration. Consequently, the proposed BCD-SCA optimization converges to a lower operating point because the transmission energy component in the processor energy model is significantly reduced compared with the TDMA scheme. TDMA enforces sequential time-slot allocation for each processor, leading to prolonged transmission duration due to increased waiting and idle periods, which in turn amplifies cumulative communication energy consumption. Fig. 9b shows the average processor energy consumption versus the number of selected processors. As more processors are selected, the energy under TDMA increases sharply due to sequential time-slot allocation, which introduces long idle and waiting periods where processors remain active and consume additional energy. In contrast, NOMA allows simultaneous transmission of measurement outcomes, significantly reducing waiting time and communication duration. However, the average energy consumption under NOMA still increases slightly with the number of processors, as the presence of slower processors can extend the effective transmission phase. Fig. 9c presents the total transmission time versus the number of selected processors, where TDMA exhibits significantly higher latency because processors transmit sequentially in orthogonal time slots, while NOMA enables concurrent transmissions using power-domain multiplexing and SIC at the aggregator, resulting in substantially reduced transmission delay. These results validate the design choice of incorporating a NOMAbased uplink into the proposed DVQC framework. Since measurement transmission is performed after every training iteration, reducing the communication latency also shortens the overall DVQC cycle, thereby improving the practicality and scalability of the proposed framework. F. DVQC Incentive Optimization Performance In this subsection, we assess the performance of the proposed ADMM-based incentive optimization scheme for DVQC. We compare our method with three benchmarks: relaxed upper bound, greedy, and fixed selection, where the

relaxed upper bound allows fractional choices in [0,1] to provide an ideal performance ceiling, the greedy method selects processors by highest utility-to-qubit ratio under budget and coverage constraints, and the fixed strategy chooses processors solely by qubit counts, ignoring utility and cost. Fig. 10 shows the convergence of the proposed ADMMbased incentive optimization versus three baselines: relaxed upper bound, greedy, and fixed selection. The relaxed upper bound serves as an ideal benchmark, achieving the highest utility. ADMM quickly approaches this benchmark within five iterations, demonstrating effective handling of payment and qubit constraints. The greedy method shows only moderate utility and rapidly plateaus because it makes straightforward selections based on a simple utility-to-qubit ratio without iterative refinement, while the fixed scheme yields the lowest, non-improving utility. These results highlight the superior convergence and solution quality of the ADMM approach compared to simpler alternatives. Specifically, the rapid convergence of ADMM is attributed to its alternating optimization strategy, which iteratively refines the processor selection while enforcing the payment budget and qubit coverage constraints through the augmented Lagrangian formulation. Unlike the greedy and fixed schemes, ADMM continuously adjusts the selection variables to maximize system utility. Consequently, the proposed algorithm converges to a solution that closely approaches the relaxed upper bound while maintaining feasibility under the practical constraints of the DVQC incentive framework. Fig. 11a compares the system utility of the four schemes as the payment budget increases. As the payment budget increases, the system utility improves for the relaxed upper bound, ADMM, and greedy schemes with ADMM consistently remaining close to the relaxed upper bound across the entire budget range. This trend is expected because a larger payment budget allows the aggregator to compensate and recruit a more suitable set of processors, thereby enlarging the feasible solution space for maximizing the system utility while satisfying the required qubit coverage. The proposed ADMM algorithm is able to exploit the additional budget more effectively than the greedy and fixed schemes, maintaining performance close to the relaxed upper bound. The greedy scheme achieves only moderate utility improvement because it makes processor selection based on the utility-to-qubit ratio without optimizing the overall system utility. The fixed scheme exhibits constant

15

utility since it selects processors solely according to their qubit capacities, without adapting to the available payment budget. Fig. 11b illustrates the impact of the required qubit coverage Q on the system utility. As Q increases, the system utility decreases across all schemes because satisfying the higher qubit coverage requirement becomes more challenging under the same payment budget. Consequently, the aggregator may need to select additional processors or processors with higher energy costs to satisfy the increased qubit requirement, resulting in a lower system utility. The relaxed upper bound provides the highest utility as an ideal benchmark, while ADMM closely matches its performance by effectively balancing the payment budget and qubit coverage constraints. In contrast, the greedy and fixed schemes exhibit a more pronounced utility degradation since their simpler selection strategies can not efficiently trade off processor energy costs against qubit contributions. These results demonstrate that the proposed ADMM framework maintains high system utility even under increasing resource requirements by optimizing processor selection with respect to both incentive and qubit constraints. V. C ONCLUSIONS This paper has proposed a two-stage incentive mechanism design for DVQC over wireless networks to enable scalable execution of large PQCs through parallel subcircuit processing. In the first stage, we have addressed the processor-side energy minimization problem by jointly optimizing subcircuit parameters, number of noise measurements, and transmit power, and have solved it using an efficient combination of BCD and SCA. In the second stage, the aggregator has leveraged the optimized energy costs from the first stage to solve a system utility maximization problem, selecting the optimal set of processors. This NP-hard, non-convex combinatorial selection problem has been effectively addressed using the ADMM framework. Extensive numerical results have demonstrated that our DVQC framework’s performance matches centralized quantum computing, while significantly outperforming baseline methods in both energy efficiency and system utility. Future work will focus on extending the framework to incorporate more realistic quantum hardware noise models, and developing adaptive incentive strategies for large-scale distributed quantum computing systems. A PPENDIX A C ONVEXIFICATION OF (26a) (t)

We re-write (26a) as αβ ≥ sk . (t)

αβ ≥ sk ⇔

1 1 (t) (α + β)2 − sk ≥ (α − β)2 . 4 4

(40)

Although the right-hand side of (40) is convex, the left-hand side is still non-convex. Using the first-order Taylor expansion, we approximate (α + β)2 as, (α + β)2 ≥ (αi + βi )2 + 2(αi + βi )(α + β − αi − βi ). (41)

Putting (41) into (40), we arrive at   1 (αi + βi )2 + 2(αi + βi )(α + β − αi − βi ) 4 1 (t) − sk ≥ (α − β)2 . 4 A PPENDIX B U PDATE OF xk (i)

(42)

(i)

Fixing zk and λk , variable xk is updated by minimizing the augmented Lagrangian over the box constraint xk ∈ [0, 1] as    (i+1) xk = arg min − mk − Ek xk xk ∈[0,1]

 2  ρ (i) (i) + xk − z k + λ k , 2

∀k ∈ K.

(43)

For  minimizing,  we now  take its derivative  and set it to zero as (i) (i) − mk − Ek xk + ρ xk − zk + λk = 0, ∀k ∈ K. Solving (i)

(i)

k it for xk , we obtain xk = zk − λk + mk −E , ∀k ∈ K. ρ Projecting onto [0, 1], we arrive at    mk − E k (i+1) (i) (i) xk = min 1, max 0, zk − λk + , ρ ∀k ∈ K. (44)

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[15] S. Kan et al., “Scalable circuit cutting and scheduling in a resourceconstrained and distributed quantum system,” in Proc. IEEE International Conference on Quantum Computing and Engineering (QCE), vol. 1, Sept. 2024, pp. 1077–1088. [16] A. Pawar et al., “QRCC: Evaluating large quantum circuits on small quantum computers through integrated qubit reuse and circuit cutting,” in Proc. ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Vol. 4, Apr. 2024, pp. 236–251. [17] I. Shehzad et al., “Automated cut finding and circuit knitting on large quantum circuits,” in Proc. IEEE International Conference on Quantum Computing and Engineering (QCE), 2024, pp. 406–407. [18] A. Carrera Vazquez et al., “Combining quantum processors with realtime classical communication,” Nature, pp. 1–5, Nov. 2024. [19] M. Caleffi et al., “Distributed quantum computing: A survey,” Computer Networks, vol. 254, p. 110672, Dec. 2024. [20] A. Ben-Tal et al., Lectures on Modern Convex Optimization: Analysis, Algorithms, and Engineering Applications. SIAM, Jan. 2001. [21] V.-D. Nguyen et al., “Precoder design for signal superposition in MIMO-NOMA multicell networks,” IEEE Journal on Selected Areas in Communications, vol. 35, no. 12, pp. 2681–2695, Jul. 2017. [22] B. Wang et al., “Max-min beamforming for large-scale cell-free massive MIMO: A randomized ADMM algorithm,” IEEE Transactions on Wireless Communications, Jan. 2025. [23] T.-H. Chang et al., “Asynchronous distributed ADMM for large-scale optimization—part i: Algorithm and convergence analysis,” IEEE Transactions on Signal Processing, vol. 64, no. 12, pp. 3118–3130, Mar. 2016. [24] Y. LeCun et al., “Gradient-based learning applied to document recognition,” Proceedings of the IEEE, vol. 86, no. 11, pp. 2278–2324, 1998. [25] A. Krizhevsky et al., “Learning multiple layers of features from tiny images,” 2009. [26] Z. Yang et al., “Energy efficient federated learning over wireless communication networks,” IEEE Transactions on Wireless Communications, vol. 20, no. 3, pp. 1935–1949, Nov. 2020. [27] Y. Zeng et al., “Energy-efficient UAV communication with trajectory optimization,” IEEE Transactions on Wireless Communications, vol. 16, no. 6, pp. 3747–3760, Mar. 2017.

Shaba Shaon (Graduate Student Member, IEEE) is currently pursuing the Ph.D. degree in Computer Engineering with the Department of Electrical and Computer Engineering at The University of Alabama in Huntsville, Huntsville, AL, USA. She is a member of the Networking, Intelligence, and Security Research Lab at the same institution, where her research focuses on developing intelligent, efficient, and scalable computational frameworks for nextgeneration wireless networks and quantum-enabled distributed systems. Her research interests include federated learning, wireless networking, distributed quantum computing, distributed quantum sensing, and classical and quantum optimization algorithms.

Dinh C. Nguyen (Member, IEEE) is an Assistant Professor at the Department of Electrical and Computer Engineering, The University of Alabama in Huntsville, USA. He worked as a postdoctoral research associate at Purdue University, USA from 2022 to 2023. He obtained the Ph.D. degree in computer science from Deakin University, Australia in 2021. His current research interests include quantum computing, federated machine learning, wireless networking, and security. He is an Associate Editor of IEEE Transactions on Network Science and Engineering and ACM Computing Survey Journal. He received the Best Editor Award from IEEE Open Journal of Communications Society in 2023.

Octavia A. Dobre (Fellow, IEEE) is a Professor and Tier-1 Canada Research Chair with Memorial University, Canada. Her research spans wireless communications and networking technologies, as well as optical and underwater communications. She was honored with numerous Best Paper Awards, including the IEEE Communications Society Heinrich Hertz Award. Dr. Dobre served as the VP Publications of the IEEE Communications Society, the founding Editor-in-Chief of the IEEE Open Journal of the Communications Society, and the Editor-inChief of the IEEE Communications Letters. Currently, she is Editor-in-Chief of the IEEE Wireless Communications Magazine. Dr. Dobre is a Clarivate Highly Cited Researcher, a Fellow of the Royal Society of Canada, the Canadian Academy of Engineering, and the Engineering Institute of Canada. She is also an elected member of the European Academy of Sciences and Arts and the Academia Europaea.

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