Accelerating State-Vector Quantum Simulation on Integrated GPUs via Cache Locality Optimization: A Cross-Architecture Evaluation Gabriel Fernandes Thomaz∗ , Jerusa Marchi∗ , † , Eduarda Rodrigues Monteiro∗ , ‡ , Fernando Augusto Caletti de Barros∗ , and Evandro Chagas Ribeiro da Rosa∗ , † ∗ Instituto de Pesquisas Eldorado, Porto Alegre, Brazil
arXiv:2605.15098v1 [quant-ph] 14 May 2026
† Universidade Federal de Santa Catarina, Florianópolis, Brazil ‡ Pontifı́cia Universidade Católica do Rio Grande do Sul, Porto Alegre, Brazil
Abstract—The classical simulation of quantum algorithms is a crucial tool for circuit development, testing, and validation. Although acceleration using GPUs significantly reduces simulation time, most high-performance simulators rely on vendor-specific frameworks that target data-center hardware. To broaden access to quantum simulation, this work proposes a vendor-agnostic approach targeting the integrated GPUs commonly found in consumer-grade laptops. A primary challenge in state-vector simulation is its inherently poor spatial locality, which creates a memory bandwidth bottleneck. Consequently, baseline implementations experience a severe degradation in relative GPU speedup as the number of simulated qubits increases. To address this limitation, we introduce a state partitioning optimization that reorganizes the quantum state vector to maximize the lastlevel cache locality and minimize costly main memory fetches. We evaluate this strategy using a Quantum Phase Estimation algorithm across diverse architectures from Intel, AMD, and Apple. The experimental results demonstrate that the proposed optimization successfully mitigates performance degradation at larger qubit scales. In particular, for a 28-qubit simulation, the optimization reversed a performance deficit on an Intel Core i5, improving the GPU speedup over the CPU from 0.95× to 1.89×, and increased the Apple M1 Pro speedup from 3.71× to 5.88×. Overall, this approach yields consistent execution time improvements, demonstrating the viability of integrated GPUs for efficient quantum circuit simulation. Index Terms—Quantum Circuit Simulation, State-Vector, Integrated GPU, Cache Locality, Multi-Vendor
I. I NTRODUCTION Quantum simulation is an important component for quantum computing development toolchain. Simulators enable the execution of quantum algorithms on classical computers and are widely used for algorithm design, testing, and validation [1]. Although general quantum simulation requires resources that grow exponentially with the number of qubits [2], simulation remains relevant for research and education purposes. Many algorithms of practical interest can be studied on small scales, where the limited number of qubits does not justify the cost and limited availability of quantum hardware. In addition, access to quantum devices may be constrained by financial cost, queue times, or institutional availability, particularly in developing countries. For small circuits, the waiting time for hardware execution can exceed the time required for classi-
cal simulation. Moreover, simulation provides exact results without the effects of noise and decoherence, which facilitates algorithm analysis. Several approaches exist for the classical simulation of quantum computers [3], including tensor networks, decision diagrams, and sparse-state representations. Under specific restrictions, such as Clifford circuits [4], polynomial-time simulation is possible using methods such as the stabilizer formalism. However, no single simulation technique is optimal for all classes of algorithms: some of them demonstrate to be efficient for particular circuits. Nevertheless, the state vector method seems to be the most direct approach: the quantum state is stored as a complex vector, and quantum gates are applied as linear transformations following the standard linear-algebra formulation of quantum mechanics. This implementation closely reflects the algebraic description of the theory without relying on alternative representations or reductions, providing predictable time and memory requirements and serving as a general baseline method. State vector simulation is dominated by linear algebra operations, primarily structured matrix-vector multiplications. These operations exhibit a high degree of data parallelism, which makes them suitable for multithreaded and GPU execution. Furthermore, the regular structure of the quantum gates allows the matrix operations to be implemented implicitly, avoiding the explicit construction of large matrices [5]. Also, the method requires limited CPU-GPU communication, with the CPU mainly responsible for kernel dispatch. Most high-performance quantum simulators target datacenter GPUs with high memory bandwidth, large core counts, and fast interconnects such as NVLink, enabling multi-GPU simulations of larger systems [6]. But this infrastructure is expensive and not available to many research groups. Consumer discrete GPUs offer a more accessible alternative and are supported by several existing simulators. An even more widely available platform is the integrated GPU (iGPU) present in most modern laptops and some desktop processors. Integrated GPUs share memory with the CPU and provide fewer compute units, but their ubiquity makes them a relevant target for lowcost quantum simulation.
In this work, we investigate the use of integrated GPUs for state vector simulation [5]–[7]. We evaluate systems based on Intel, AMD, and Apple architectures. Our experiments show that, once kernel launch overhead is amortized, integrated GPUs can provide speedup over CPU execution for moderate circuit sizes. However, this advantage decreases as the number of qubits grows. To address this limitation, we propose an optimization that reorganizes the state vector to improve cache spatial locality, resulting in measurable performance gains. The remainder of this paper is organized as follows. Section II reviews previous work on GPU-based quantum simulation and cache locality optimizations. Section III describes the state vector algorithm and the proposed state partition strategy. Section IV presents the evaluation methodology, metrics, and hardware platforms. Section V analyzes the experimental results, and Section VI concludes the paper. II. R ELATED W ORK The landscape of classical quantum circuit simulation is broad and heterogeneous, encompassing multiple algorithmic strategies, hardware, and optimization techniques. To provide a coherent foundation for our contribution, this section reviews the main classes of simulators and acceleration strategies most closely related to our work. We begin with state-vector simulators, the dominant approach for the exact simulation of quantum circuits. Next, we discuss GPU-accelerated frameworks that leverage vendor-specific hardware to reduce execution time in Section II-A. Finally, in Section II-B, we examine locality-aware optimization techniques that mitigate memory bandwidth bottlenecks, a central issue for state-vector simulation and one directly addressed by our proposed method. Throughout this review, we contrast previous approaches with our vendor-agnostic, cache-optimized strateg for iGPUs. State vector simulation is one of the most widely adopted methods for accurate emulation of quantum circuits, as it directly represents a quantum state of n qubits using a complex vector of size 2n . One of the first high-performance implementations operating under this model is qHiPSTER [5], later expanded and renamed Intel Quantum Simulator (IntelQS) [7]. The qHiPSTER framework introduced a distributed memory formulation for applying quantum gates based on MPI, allowing the complete state vector to be partitioned across computing nodes, with communication patterns optimized to support generic one- and two-qubit gates at scale. Its initial version demonstrated efficient simulation of circuits up to 40 qubits in High Performance Computing (HPC) systems, combining multithreading, vectorization, and communication overlap techniques. Based on this foundation, Intel-QS has evolved into a production-ready simulator focused on cloud and HPC usability. The updated system introduced an execution model “pool” that allows the simultaneous simulation of multiple related quantum circuits, significantly improving throughput in variational algorithms and ensemble-based workloads. Current studies demonstrate Intel-QS scaling to more than 40 qubits,
benefiting from optimized memory layouts, communication scheduling, and careful exploitation of CPU parallelism. While these simulators provide robust high-performance baselines, they share a limitation common to most CPU-centric state vector tools: their performance degrades as the qubit count increases due to the inherently poor spatial locality of the state vector data structure. The technologies mentioned rely heavily on multicore CPUs and distributed memory clusters, and while they achieve excellent scalability in HPC infrastructure, they do not address the growing need for vendor-agnostic simulators for consumer hardware, nor do they address the cache locality degradation that suppresses iGPU speed gains in memory-bottlenecked scenarios. This contrasts with the goal of the present work, which targets integrated GPUs and introduces a state partitioning optimization specifically designed to maximize cache reuse and mitigate memory bandwidth limitations. As our evaluation demonstrates, such optimizations allow integrated GPUs to achieve competitive and scalable acceleration on Intel, AMD, and Apple architectures, even in regimes where conventional simulations would suffer from bandwidth-induced performance collapse. A. GPU-Accelerated Simulators GPU acceleration has become a central strategy for reducing execution time in classical quantum circuit simulation. Proof of this is NVIDIA’s cuQuantum SDK [6], a representative, production-grade toolset that exposes GPU-optimized primitives for state vector (cuStateVec) and tensor network (cuTensorNet) backends. These building blocks are designed for modern NVIDIA architectures and enable substantial speed gains over CPU-only execution, with direct scaling from single GPU to distributed multi-GPU deployments in HPC or cloud environments. In other words, cuQuantum is a vendor-specific acceleration layer that subsequent simulators can adopt to achieve high performance on discrete NVIDIA GPUs. In addition to libraries, complete simulations have also been designed around GPUs. HyQuas [8] proposes a hybrid partitioner that automatically selects the most suitable simulation method for each region of the circuit, combining shared memory optimizations (OShareMem) and matrix multiplication rework (TransMM) that leverages cuBLAS/Tensor cores. HyQuas adds a GPU-centric communication pipeline to scale across multiple GPUs, reporting a speed increase of up to 10.7× on individual GPUs and 227× on GPU clusters compared to previous systems, explicitly targeting discrete CUDA devices and NVLink/NCCL interconnects. Among general-purpose simulations, QuEST stands out for unifying multithreading, distributed MPI, and GPU execution in a single C library. Jones et al. [9] demonstrate strong/weak scalability down to 38 qubits across thousands of CPU cores and document GPU support as part of a high-performance portable stack that runs from laptops to supercomputers, a novelty at the time for bringing together CPU paths, distributed memory, and accelerators into a single interface. Still, the GPU path in QuEST follows the conventional model of discrete accelerators, focusing on HPC environments.
With a specific focus on large-scale performance in heterogeneous clusters, SV-Sim [10] is a PGAS-based state vector simulator with GPU-centric and CPU-GPU-centric communication strategies to reduce choppy data exchange between nodes. It supports NVIDIA and AMD GPUs and integrates with front-ends such as Qiskit, Cirq, Q#, OpenQASM, and QIR, presenting scalability on the supercomputers such as Summit, Theta, Cori with GPUs NVIDIA V100, NVIDIA A100, and AMD MI100. The emphasis is on distributed execution across multiple GPUs, communication/compute orchestration, and end-to-end HPC throughput. In contrast to the solutions above, which assume discrete GPUs and vendor-specific stacks, our study targets GPUs integrated into consumer-grade architectures (Intel, AMD, Apple), with a direct focus on the spatial locality of the statevector. Unlike cuQuantum, HyQuas, QuEST, and SV-Sim, which maximize FLOPs and high-throughput communication on discrete GPUs and/or clusters, we address the bandwidth and cache bottleneck of the state-vector simulation via partition reorganization to maximize last-level cache locality in the iGPU scenario. While the cited works show how to achieve high performance in data-center GPUs and specialized interconnects, our result demonstrates that iGPUs can achieve consistent gains when the state layout is adjusted to cache behavior, filling a gap little explored by the literature. B. Cache Locality Optimizations State-vector simulation is fundamentally constrained by memory-system behavior: as the target-qubit index t increases, the stride-2t access pattern forces the simulator to read and update amplitudes that are increasingly distant in memory. This quickly exhausts cache capacity and shifts execution from compute-bound to memory-bound, causing performance degradation even on modern multicore CPUs and discrete GPUs. To mitigate this, prior work has explored techniques that improve spatial and temporal locality through (i) circuitlevel restructuring, (ii) hierarchical decomposition of the circuit into smaller state vectors, and (iii) architecture-aware tiling for GPU shared memory. Doi and Horii [11] introduce a cache-blocking technique in Qiskit Aer, where circuits are transpiled such that gates are reassigned to low-index qubits within fixed-size chunks, and noiseless SWAP gates are inserted when qubits must migrate across chunk boundaries. This remapping ensures that gate operations operate on contiguous sub-states that fit into fast memory (GPU memory or CPU cache), reducing cross-chunk traffic and enabling scalable multi-GPU/MPI execution. The method is circuit-centric: locality is improved by changing the circuit structure itself, rather than altering the state layout. The hierarchical state-vector simulation model [12] represents the quantum circuit as a dependency graph and then partitions this graph into acyclic subgraphs, each corresponding to a subcircuit with a limited data footprint. These subcircuits are simulated hierarchically by constructing and evolving smaller state vectors, which reduces the number of full-vector passes and improves temporal locality during gate application. By
lowering the working-set size and confining operations to smaller blocks of amplitudes, the method achieves better timeto-solution and improved scalability on multicore systems. Unlike circuit-level cache blocking, this approach enhances locality by graph-based partitioning and hierarchical execution rather than explicit cache-aware data reordering. HyQuas [8] incorporates techniques relevant to locality by selecting between two GPU execution modes: (i) OShareMem, which tiles gate operations into on-chip shared memory, enhancing reuse and reducing global memory traffic; and (ii) TransMM, which reformulates gate application as batched GEMMs to exploit Tensor Cores and cuBLAS. While HyQuas does not target CPU cache locality, it is an example of architecture-aware locality optimization, tailored specifically to CUDA-class discrete GPUs [8]. While these approaches improve locality through circuit transformations, graph-based subcircuit extraction, or GPUspecific tiling strategies, they all assume high-bandwidth, discrete hardware environments, either multi-GPU clusters (Qiskit Aer cache blocking), NUMA-aware multicore servers (hierarchical state-vector simulation), or CUDA-optimized accelerators with large on-chip shared memory (HyQuas). None of them directly addresses locality constraints in integrated GPUs, where memory bandwidth is significantly lower and cache resources are shared with CPU cores. Our experimental results show that cache-aware reorganization successfully mitigates performance degradation at larger qubit scales and restores integrated GPU speedup, where locality-unaware approaches typically collapse. This fills a gap in the prior literature by demonstrating the viability of iGPUbased quantum simulation through cache-centric, rather than circuit-centric, or GPU-specific, locality optimizations. III. S TATE V ECTOR S IMULATION In this section, we describe the state vector simulator used in our work. Section III-A presents the base algorithm for parallel execution, using the approach adopted in simulators such as qHiPSTER [5] and QuEST [9]. Section III-B introduces the proposed optimization based on dividing the quantum state into blocks, a technique related to those employed in distributed [7] and multi-GPU simulations [6], here adapted to reduce cache misses on a single processor. Implementation details are presented in Section III-C, and the impact of the optimization is analyzed in Section V. A. Base Algorithm In the state vector simulation, the state of an n-qubit system is represented by an array of complex numbers with 2n elements. Although the mathematical formulation associates each computational step with a 2n × 2n unitary matrix, a universal simulator does not need to explicitly construct this matrix. Gate application can be expressed directly in terms of operations on the state vector with two fundamental cases: single-qubit gates and controlled gates.
The application of a single-qubit gate U on qubit k of an n-qubit system corresponds to the operator: Uk = I ⊗k ⊗ U ⊗ I ⊗n−k−1 .
(1)
Algorithm 1 shows the procedure for applying Uk . Each iteration of the inner and outer loop is independent and can be executed in parallel. Within the inner loop, two positions of the state vector are read and written, and the access pattern does not create data races. Figure 1 illustrates the memory addresses accessed when a gate is applied to qubit index 1 of a three-qubit system, explicitly the absence of accesses conflicts. Algorithm 1 Single-qubit gate application algorithm. S: state vector of size 2n ; U : 2 × 2 single-qubit gate; t: target qubit index (starting at 0). 1: procedure A PPLY G ATE(S, U , t) 2: for i = 0 to 2n − 1 step 2t+1 do 3: for j = i to i + 2t − 1 do 4: a ← S[j] ▷ State |0⟩ amplitude 5: b ← S[j + 2t ] ▷ State |1⟩ amplitude 6: S[j] ← U1,1 · a + U1,2 · b 7: S[j + 2t ] ← U2,1 · a + U2,2 · b 8: end for 9: end for 10: end procedure
Fig. 1. Memory positions read and written when applying a single-qubit gate to qubit index 1 of a three-qubit system. The dashed line separates the regions processed by each iteration of the outer loop in Algorithm 1. Lines connecting elements represent the pairs accessed in the inner loop.
Controlled gates can be implemented by conditioning the execution of the inner loop of Algorithm 1. For a control qubit c, the j-th iteration is executed only if the c-th bit of j is 1. This algorithm is also the basis for distributed quantum simulation. The index of the target qubit determines how pairs of amplitudes are accessed, which in turn defines whether operations can be performed locally or require communication. In the next section, we employ the same observation not for distribution across nodes but to improve cache locality. B. Dividing the Quantum State The proposed optimization divides the quantum state into blocks in order to improve cache locality. This strategy is similar to that used in distributed and multi-GPU simulators, but here it is evaluated for a single processor. In Figure 1, when a gate is applied to qubit index 1, part of the amplitude pairs accessed lies in the first half of the vector, while the corresponding pairs lie in the second half. In a distributed setting, each half could be stored on a different
node, allowing operations on some qubits to be performed independently. Operations on higher-index qubits would require communication between nodes. This observation motivates the division of the state into blocks. After partitioning, qubits are classified as local or global. Operations on local qubits access data inside a single block, while operations on global qubits require data from multiple blocks. Figure 2 illustrates a four-qubit system divided into four blocks. For a simulation of n qubits divided into blocks of size 2l , qubits with index 0 to l − 1 are local and those with index l to n − 1 are global. When an operation targets a global qubit, a SWAP operation is performed to map that qubit to a local position within the block. A least-recently-used (LRU) policy selects the local qubit to be swapped. The simulator maintains a logical-tophysical qubit mapping that is updated after each SWAP. The optimization relies on selecting a block size that fits in the last-level cache (LLC). To improve the reuse of cached data, operations acting on local qubits are delayed rather than executed immediately. These deferred operations are batched and executed only when an operation targeting a global qubit is required. During this execution phase, all delayed local operations are applied entirely to a single block before the simulator transitions to the next block, effectively keeping the active data resident in the cache. Furthermore, for controlled operations, only the target qubit is considered when determining if a global SWAP is necessary. If a global qubit acts solely as a control, the simulator simply evaluates whether the operation applies to a specific block by checking the block’s index, thereby avoiding unnecessary state reorganizations. Despite of these optimizations, operations targeting global qubits inherently require block reorganizations, which typically generate additional cache misses. Consequently, a tradeoff exists: small blocks increase the number of global qubits and required SWAPs, whereas large blocks reduce intra-block locality. This trade-off between block size and cache behavior is evaluated in Section V. C. GPU Implementation The algorithm described above was implemented for both CPU and GPU execution. The CPU version is based on the multithreading KBW simulator of the Ket quantum programming platform [13], implemented in Rust. The GPU implementation uses CubeCL 0.9, a Rust-based General-Purpose GPU framework, with the graphics library wgpu backend, enabling execution through Vulkan and Metal on Linux, macOS, and Windows. As detailed in Section IV, the implementation was evaluated on Intel, AMD, and Apple processors under Linux and macOS. The simulator was also validated on Windows systems using the same code base. IV. E XPERIMENTAL S ETUP We evaluated the proposed optimization using a Quantum Phase Estimation algorithm, detailed in Section IV-A. The evaluation considered three metrics: wall-clock time, cache
Fig. 2. Four-qubit system with the state divided into four blocks. Qubits 0 and 1 correspond to local qubits, whereas qubits 2 and 3 correspond to global qubits. The connecting lines represent the pairs of amplitudes accessed during the application of a gate to a specific qubit index. TABLE I H ARDWARE SPECIFICATIONS OF THE CONSUMER - GRADE LAPTOP SYSTEMS USED TO EVALUATE THE PROPOSED OPTIMIZATION . Laptop
CPU
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OS
Kernel
Inspiron 13 5330 Yoga Slim 7 14ILL10 IdeaPad 3 15ALC6 MacBook Pro (14-inch, 2021)
Intel Core i5-1340P Intel Core Ultra 7 258V AMD Ryzen 5 5500U Apple M1 Pro (8 cores)
Intel Iris Xe Graphics Intel Arc Graphics 130V AMD Lucienne Apple M1 Pro (14 cores)
Arch Linux Debian GNU/Linux 13 Fedora Linux 43 macOS Sequoia 15.6.1
Linux 6.18.9-zen1-2-zen Linux 6.12.69+deb13-amd64 Linux 6.18.7-200.fc43. Darwin 24.6.0
misses, and global-local qubit SWAPs, which are discussed in Section IV-B. The benchmarks were executed on four distinct systems encompassing Intel, AMD, and Apple processors with integrated GPUs; the hardware specifications are presented in Section IV-C. The benchmark results and subsequent analysis are presented in Section V.
H
|0⟩
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A. Quantum Phase Estimation Algorithm Given a unitary operator U and its eigenstate |ψ⟩, the Quantum Phase Estimation (QPE) algorithm [14, §5.2] determines the angle θ of the corresponding eigenvalue e2πiθ . As presented in Figure 3, the algorithm circuit utilizes the inverse Quantum Fourier Transform (QF T † ), which is implemented using controlled-phase and Hadamard gates. For our benchmark, we simulate n+1 qubits, where n qubits control the application of the exponential of U , and one qubit is prepared in the state |1⟩ to act as the eigenstate of U . For the unitary U , we use a phase gate defined as: 1 0 U (n) = P (2π2−n ) = . (2) −n 0 e2πi2 In this (n + 1)-qubit simulation, the angle θ is 2−n . This specific angle facilitates straightforward verification of the execution, as the measured bitstring is expected to be exactly 00 . . . 01. Additionally, the exponential of U can be computed directly as: U (n)a = P (2π2−n a). (3) The experiment was implemented in Rust. This implementation resulted in a compiled binary that takes the number of qubits and the block size as execution arguments. B. Metrics To automate the execution of the experiments, a Python script was used. We measured the wall-clock time required to
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Fig. 3. Circuit for the Quantum Phase Estimation Algorithm.
execute the simulation from program initialization to termination. For cache metrics, the Linux perf tool was used to record cache references and cache misses from the last-level cache (LLC) via the processor’s Performance Monitoring Unit (PMU). Because these hardware registers cannot be directly accessed during GPU execution, the CPU results served as a proxy to analyze the cache behavior. In both the CPU and GPU executions, we also recorded the total number of SWAP operations required during the algorithm’s execution. Analyzing cache misses helps to understand whether the proposed block division strategy improves cache locality, which can positively impact execution time. Conversely, the SWAP count indicates the additional operations required to perform the necessary gate applications, which negatively impacts execution time. The working hypothesis is that when the block size fits within the LLC, cache locality improves, reducing wall-clock time. Smaller block sizes, however, are not expected to improve locality as the increased frequency of SWAPs will trigger additional cache misses. The evaluation varied the number of qubits from 4 to 28, using single-precision floating-point numbers for the simulation. For executions involving 16 or more qubits, the block size was varied between 16 and n − 1 qubits (where n is the total number of qubits). The baseline for this benchmark is the
execution without dividing the quantum state. We swept across different block sizes to identify the optimal configuration. For the Apple M1 Pro system, cache miss data was not collected due to architectural limitations in reading the PMU registers on macOS. However, cache behavior in this system can be inferred by observing the optimal block size. Each benchmark configuration was executed three times and the median was recorded. A two-second sleep interval was introduced between executions to allow the processor to cool down. This interval is necessary because thermal throttling measurably impacts execution time, particularly on laptops, which are the primary focus of these experiments. C. Hardware We evaluated the proposed optimization on the four systems detailed in Table I. It is important to note that these systems feature processors from different generations and operate with varying thermal design powers (TDPs). Consequently, the purpose of this evaluation is not to conduct a direct performance comparison between hardware. Instead, our objective is to assess the efficacy and behavior of the optimization independently across a diverse set of consumer-grade architectures. We note that the hardware selection for this study was dictated by the most stringent of resource constraints: the immediate physical availability of the authors’ personal computers. Nevertheless, this ensemble of daily drivers effectively demonstrates the optimization’s performance across a diverse, if unintentional, variety of hardware ecosystems. V. R ESULTS AND D ISCUSSION This section analyzes the impact of the proposed optimization on the four systems detailed in Table I. Section V-A evaluates the baseline execution to establish the performance characteristics of the unoptimized simulation, providing context for the improvements achieved by the proposed state partitioning method discussed in Section V-B. A. Baseline Figure 4 presents the execution times for both CPU- and GPU-accelerated simulations. In the baseline case (without state division), the expected behavior is observed across all systems: once the GPU kernel launch overhead is amortized, the GPU outperforms the CPU. This crossover typically occurs at approximately 19 qubits. Note that the experiments were performed with minimal background processes running (e.g., on Linux systems, the desktop environment and network manager were stopped) to reduce measurement noise. Under a fully loaded system, observations shows the GPU-accelerated simulation outperforming the CPU at smaller qubit counts. Figure 6 presents the speedup of the GPU-accelerated simulation relative to the CPU execution. A notable trend across all systems is a substantial decrease in the speedup factor at approximately 25 qubits. This performance degradation indicates that the simulation becomes bandwidth-bound. The memory access pattern in the state vector algorithm (Algorithm 1) is non-sequential; the inner loop reads and writes to distant
memory addresses. Because every element of the 2n state vector must be accessed during each quantum gate application, the algorithm exhibits poor spatial locality. The CPU architecture is generally better equipped to handle this lack of spatial locality. Because the iterations of the inner loop are independent, CPU features such as memory-level parallelism and out-of-order execution can partially hide cache miss latency. Conversely, on a GPU, a cache miss stalls the entire thread warp executing on a Streaming Multiprocessor (SM). Due to the poor spatial locality, multiple warps may stall simultaneously while waiting for main memory accesses, thereby reducing GPU occupancy and overall throughput. In the case of the Intel Core i5-1340P, the GPU execution time exceeds that of the CPU for the 28-qubit simulation, and a general reduction in GPU speedup is observed across all evaluated systems at larger qubit counts. B. Optimized The objective of the proposed optimization is to improve cache locality by maximizing the number of operations performed within a single state partition before transitioning to the next. This approach aims to retain the active block in the cache as long as possible. Because there are no Performance Monitoring Unit (PMU) registers readily available to directly record GPU cache misses on the evaluated integrated platforms, the L3 cache miss rate of the CPU execution is used as a proxy metric. This substitution is viable because the integrated GPU and CPU share the last-level cache (LLC). Figure 5 illustrates the cache miss rate for CPU execution of a 27-qubit QPE simulation across various block sizes. Each processor exhibits distinct cache behavior, which subsequently influences the performance gains yielded by the optimization. The results for each architecture are analyzed individually: 1) Intel Core i5-1340P: For the 27-qubit QPE simulation, the baseline cache miss rate is 48.80%. A clear reduction in the miss rate is observed as the block size decreases. At a block size of 20 qubits, the point where the cache miss rate cross with the SWAP count metric, the miss rate drops to 17.89%. It is important to note that only the miss rate of the performance cores was recorded, as these cores primarily dictate the execution time. Regarding the GPU execution time, the shortest durations are observed at block sizes of 19 and 20 qubits, measuring 25.02s and 25.08s, respectively. Assuming single-precision complex numbers (8 bytes per amplitude), a 20-qubit block requires exactly 8 MB of memory, which fits within the processor’s 12 MB L3 cache. Conversely, a 21-qubit block requires 16 MB, exceeding the L3 capacity. Analyzing the optimized execution in Figure 4 confirms that the optimal block size is around 20 qubits. Furthermore, Figure 6 shows that the proposed optimization mitigates the speedup degradation observed beyond 22 qubits. For the 28-qubit simulation, the GPU speedup recovers from 0.95× (a performance deficit) in the baseline to 1.89× with the optimization. 2) Intel Core Ultra 7 258V: Despite featuring a 12 MB L3 cache similar to the i5-1340P, the Core Ultra 7 258V exhibits a higher overall cache miss rate. In the baseline 27-qubit
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Fig. 4. Execution times for the QPE simulation on CPU versus integrated GPU. The top row (a–d) shows the baseline, while the bottom row (e–h) displays the execution times using the optimal state partitioning. The y-axis represents the wall-clock time in seconds on a logarithmic scale, and the x-axis indicates the number of simulated qubits. Executions range from 4 to 28 qubits, except for the AMD system (c, g), which is limited to a maximum of 27 qubits. In the optimized plots (e–h), the numbers annotated below the data points indicate the optimal block size yielding the shortest execution time.
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(e) Intel Core i5-1340P (GPU).
(f) Intel Core Ultra 7 258V (GPU).
(g) AMD Ryzen 5 5500U (GPU).
(h) Apple M1 Pro (GPU).
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Fig. 5. Performance analysis of a 27-qubit QPE simulation on CPU and integrated GPU. The top row (a–d) displays the CPU execution, while the bottom row (e–h) shows the GPU execution. The plots illustrate execution time (left y-axis), cache miss percentage (red bars, right y-axis), and SWAP count (green bars, right y-axis) for block sizes ranging from 16 to 27. Cache miss data is not available GPU executions and Apple M1 Pro CPU execution (d).
simulation, the performance cores experience a 66.18% miss rate. The minimum recorded miss rate is 43.53% at a block size of 21 qubits. Decreasing the block size further results in an increased miss rate, an expected outcome due to the higher frequency of required SWAP operations. Unlike the i5 processor, the optimization yields only a modest improvement in cache locality for the Ultra 7. Consequently, the reduction in GPU execution time only appears at 26 qubits and above. Nevertheless, for the 28-qubit simulation, the optimization yields a notable improvement in the GPU speedup factor, increasing from 2.23× in the baseline to 4.48×.
3) AMD Ryzen 5 5500U: The Ryzen 5 processor demonstrated the smallest relative impact from the proposed optimization. Interestingly, despite having the smallest L3 cache among the tested systems (8 MB), it maintained the minimum baseline cache miss rate. For the 27-qubit QPE simulation, the baseline miss rate is 16.96%, which decreases to 14.67% at the optimal block size of 20 qubits. As previously established, a 20-qubit block requires exactly 8 MB of memory. Corresponding to this modest reduction in cache misses, the GPU simulation exhibits a similarly modest performance gain. For the 27-qubit simulation, the optimization increases the GPU
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(c) AMD Ryzen 5 5500U.
(d) Apple M1 Pro.
Fig. 6. Speedup factor of the integrated GPU relative to the CPU for the QPE simulation. The y-axis represents the relative speedup, where a value greater than 1 indicates faster execution on the GPU. The x-axis denotes the number of simulated qubits. The red line (Base Speedup) shows the relative performance without state partitioning, while the green line (Optimized Speedup) shows the performance with the proposed optimization (optimal block size).
speedup factor from 1.92× to 2.44×. 4) Apple M1 Pro: Cache miss rates could not be recorded for the Apple M1 Pro. The M1 architecture differs fundamentally from the x86 64 processors tested; its last-level cache, referred to as the System Level Cache (SLC), is dynamically shared among the CPU, GPU, and other coprocessors. This architecture prevents the isolation and computation of miss rates for an individual process such as the simulator. However, the M1 Pro demonstrated a consistent performance gain across circuit sizes. For simulations of 23 qubits and larger, the optimal block size was consistently identified as 22 qubits, which requires 32 MB of memory. This correlates with the hardware specifications of the processor, which features 24 MB of L2 cache for the performance cores and a 24 MB SLC. For the 28qubits simulation, the optimization increases the GPU speedup from 3.71× to 5.88×. While the impact varies across the evaluated systems, the proposed optimization successfully reduced execution times on all platforms. This improvement is primarily attributed to enhanced cache locality; the system that exhibited the largest reduction in cache miss rate (the i5-1340P) also demonstrated the most substantial decrease in execution time relative to its
baseline. Conversely, the optimization did not yield performance gains for pure CPU executions. This result suggests that the latency incurred by cache misses on the CPU is already effectively mitigated by hardware-level memory parallelism and out-of-order execution, rendering the software-level state partitioning redundant for CPU-only simulations on these specific architectures. VI. F INAL R EMARKS In this paper, we presented how state division strategies, typically applied to distributed quantum simulation, can be employed to improve cache spatial locality, which positively impacts the execution time of quantum simulations on integrated GPUs. The experimental results demonstrate that, while the CPU can effectively mitigate cache miss latency via memorylevel parallelism and out-of-order execution, the integrated GPU is significantly more affected by the poor spatial locality inherent to the state vector simulation algorithm. The development of this GPU-accelerated simulator was motivated by the objective of maximizing the use of computational resources of consumer-grade laptops. Although several GPU-accelerated simulators are currently available, most rely
on vendor-specific frameworks, targeting exclusively NVIDIA CUDA, AMD ROCm, or Apple Metal. This fragmentation motivated our adoption of CubeCL, a vendor-agnostic framework, that utilizes the graphics library wgpu to ensure broad hardware compatibility. Although the initial implementation, which lacked state partitioning, provided measurable improvements over the CPU execution, the decline in relative speedup observed near the 27-qubit mark prompted further investigation. The hypothesis that the memory access pattern of the simulator was the primary performance bottleneck motivated the exploration of techniques to enhance cache locality. As demonstrated by our results, implementing a state partitioning strategy tailored to the processor’s last-level cache successfully reduced cache miss rates. This optimization mitigated the performance degradation at larger qubit counts, yielding consistent execution time improvements across the evaluated integrated GPUs. Despite these positive outcomes, due to hardware availability constraints, this evaluation was limited to four distinct systems. For future work, a controlled comparison of contemporaneous processors from competing vendors, specifically those from the same release cycle and with equivalent thermal design power (TDP), would be valuable to determine which architectures are most suitable for quantum simulation workloads. Such an analysis could inform the procurement decisions of quantum computing research groups when upgrading their infrastructure. Furthermore, the current testing was restricted to integrated GPUs, and this analysis does not directly translate to discrete GPUs, which possess different memory hierarchies and bandwidth capabilities. Therefore, evaluating this state partitioning optimization on discrete GPUs from vendors such as Intel, NVIDIA, and AMD remains a subject for future research. ACKNOWLEDGMENT This work was executed under the TIC26 – Brazil Quantum Camp project, funded within the scope of the Prioritized Informatics Programs and Projects (PPI), Process No. 01245.008254/2025-22, under the responsibility of the Ministry of Science, Technology and Innovation (MCTI), with operational coordination by the Association for the Promotion of Brazilian Software Excellence (SOFTEX), and executed by CESAR and the Instituto de Pesquisas Eldorado. Artificial Intelligence (AI) tools, specifically Google’s Gemini 3.1 Pro, were utilized for editing and grammar enhancement during the preparation of this manuscript. The authors adopted a methodology in which all sections were initially drafted without AI assistance, followed by iterative refinement and proofreading using the model. In the software development phase, Gemini was employed to identify potential bugs within the simulator’s source code. Furthermore, the scripts used to automate the benchmarks and generate the plots were initially drafted by the AI, followed by comprehensive human validation and verification.
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