QT-PUF: Quantum Tunneling Leakage Based PUF for Implantable IoMT Devices , Vivek Mohan*†1,2 , Chip Hong Chang2 , Emmanuel M. Drakakis1 1 Imperial College London, Imperial Global Singapore 2 Nanyang Technological University 3 Technical University of Munich
arXiv:2605.22113v1 [cs.CR] 21 May 2026
Yueqi Ma*1,2,3
Abstract—The Internet of Medical Things (IoMT) marks a shift toward decentralized healthcare, enabling continuous monitoring and personalized care through connected wearable and implantable devices. However, ensuring the trust and integrity of these devices themselves remains a major challenge, as physical compromise or counterfeiting can directly endanger patient safety, privacy, and data integrity. This work presents QTPUF, a gate-tunneling-leakage-based physical unclonable function (PUF) that leverages quantum-mechanical gate leakage resulting from process-induced variations in standard CMOS devices. A differential readout circuit with a pseudo-resistor I-to-V frontend is proposed to convert the picoampere-level leakage variations into digital responses. Unlike existing PUFs such as those based on memory, ring oscillators, or arbiters, which are less suitable for ultralow-power IoMT devices (due to additional circuitry, power overhead, or poor stability), QT-PUF requires no external excitation or stabilization and operates under static bias. Simulation-based measurements for a 65 nm CMOS process demonstrate an entropy of 0.9999998, an FHD of 0.5001, and an average power (energy) consumption of 96.04 nW/bit (19.21 fJ/bit, respectively) at 1.2 V and 35 ◦ C for the proposed PUF. It operates reliably across 0.9–1.3 V and 0–100 ◦ C with an average BER below 0.000163 across 1.0–1.3 V and 10–70 ◦ C within the operating conditions of typical implantable devices. Index Terms—Physical Unclonable Functions (PUF), IoMT Security, Quantum Tunneling, Gate Leakage, Hardware Security.
I. I NTRODUCTION The Internet of Medical Things (IoMT) is reshaping modern healthcare by enabling continuous and decentralized monitoring of patients through wearable and implantable devices. These systems collect and transmit biomedical data in real time for remote diagnosis or on-device processing for therapeutic actions, reducing hospital loads and healthcare costs [1]–[6]. However, operating outside controlled clinical environments exposes sensitive physiological data to unauthorized access, potentially compromising patient safety and privacy [7]–[10]. Conventional cryptographic mechanisms, relying on stored keys, are often vulnerable to invasive, non-invasive, and side-channel attacks [11], and are unsuitable for ultra-lowpower implantable electronics. Physical Unclonable Functions (PUFs) have emerged as lightweight alternatives, leveraging inherent manufacturing variations to generate unique, tamperresistant responses without stored keys, enabling low-power, on-demand authentication and key generation [11]. Existing * Co-first authors. This work was supported by the National Research Foundation, Prime Minister’s Office, Singapore under its Campus for Research Excellence and Technological Enterprise (CREATE) - IN-CYPHER programme. † Corresponding author email: [email protected]
PUF designs, including arbiter, ring oscillator (RO), SRAM, optical, quantum, and hybrid approaches [12]–[18], face limitations that make them unsuitable for IoMT devices. For example, arbiter and RO PUFs exhibit high dynamic power consumption [12], [13]; SRAM PUFs rely on reading the initial SRAM state at each power-on, but their reliability degrades after long dormancy or power loss and they remain susceptible to environmental fluctuations [14]; while Optical and Quantum PUFs require bulky external components incompatible with compact implantable systems [15]–[17]. Leakage-based PUFs are promising for IoMT security due to their static operation, ultra-low power, and CMOS compatibility, with several designs demonstrating good stability [19]–[22]. However, subthreshold-leakage-based PUFs [19], [22] suffer from high temperature sensitivity, limited process randomness, and predictable leakage–parameter relationships that compromise uniqueness and modeling resistance, owing to thermally activated leakage that increases exponentially with temperature. In contrast, gate-tunneling-leakage PUFs offer high stability, entropy, and energy efficiency. The tunneling current, resulting from quantum-mechanical carrier transmission through the gate oxide, exhibits minimal temperature dependence [23]–[25], while its strong nonlinearity with oxide thickness, doping, and interface traps enhances uniqueness and modeling resistance. Operating at picoampere-to-nanoampere static bias, these PUFs enable ultra-low-power, stable operation ideal for implantable IoMT devices. In this work we introduce a PUF implemented in standard CMOS, paired with a differential readout circuit suitable for IoMT applications, and make the following contributions: We propose QT-PUF, a gate-tunneling-leakage array PUF composed of four-transistor cells, where two larger transistors generate measurable quantum gate leakage currents, providing ultra-low-power (96.04 nW/bit), static, and stable operation for implantable IoMT devices. • We present a pseudoresistor-based I-V converter, and differential amplifier readout circuit that reliably converts gate-leakage variations into digital responses via a comparator circuit with high entropy (0.9999998) and low BER (0.000163). • We validate the overall design through simulations in 65 nm CMOS process, demonstrating strong uniqueness and robustness across voltage and temperature variations, as reflected in the inter-array FHD of 0.5001. •
Fig. 1. Schematic of QT-PUF system architecture composed of: (a-1) cell selection logic (CS and RS are the column and row select signals) and (a-2) QT-PUF Cell that are arranged into a (b) 4096-bit QT-PUF Array, and (c) readout circuit featuring (d) a pair of pseudo-resistor for I to V conversion, followed by amplifier and comparator stages to convert the intrinsic quantum gate leakage variations into digital response (BOUT ).
Fig. 2. Schematic illustrating the five gate leakage components in NMOS devices with ultrathin gate oxide layers: Igs , Igd , Igcs , Igcd , and Igb . STI: Shallow Trench Isolation.
II. M ETHODOLOGY This section outlines the principles of quantum gatetunneling leakage as an entropy source, the PUF cell and array design, readout circuitry, and challenge–response (CRP) generation. QT-PUF (Fig. 1) integrates five functional modules that collectively convert physical randomness into a digital response, implemented in standard 65 nm CMOS and optimized for ultra-low-power, stable operation in implantable IoMT devices. A. Gate Leakage The primary gate-leakage mechanisms in MOS devices with ultrathin silicon dioxide are Fowler–Nordheim tunneling (FNT), quantum mechanical direct tunneling (QMDT), and trap-assisted tunneling (TAT) [26]–[29]. Net gate leakage is the superposition of these mechanisms: FNT dominates at high gate voltages, QMDT in thin oxides under normal operation, and TAT under low-bias or high-defect conditions, as shown in Fig. 2. Ultra-thin gate oxides give rise to five main leakage components: gate-source (Igs ), gate-drain (Igd ), gate-channel-source (Igcs ), gate-channel-drain (Igcd ), and gatesubstrate (Igb ) currents [27], [30], [31]. B. QT-PUF Cell Design In this work, QMDT is exploited as the primary entropy source and therefore, in our proposed PUF cell design, a
voltage V2 ≈ 1.2 V is applied to the gate terminal of the tunneling device, lower than typical FNT (> 3 V) and higher than biasing conditions for TAT. The fundamental building block of the proposed PUF system is the PUF cell designed as shown Fig. 1(a-2). It is composed of two NMOS transistors (M1, M2) whose drain, source, and substrate are grounded, thereby acting as a gate leakage sources, and control transistors (M3 and M4) in each branch which allow the leakage current to flow to outputs IO1 and IO2 . When the gate bias of M1 and M2 exceeds approximately 0.9 V, an inversion layer is established near the Si–SiO2 interface, leading to quantum confinement of carriers that travel laterally along the interface with minimal substrate injection [27], [32]. Due to limited lateral diffusion overlap, Igs and Igd remain small, whereas Igcs and Igcd dominate the total gate tunneling current. These leakage variations provide a stable, unique and unclonable entropy source for each cell. C. QT-PUF Array Architecture As shown in Fig. 1(b), the system core comprises a 64 × 64 PUF cell array (4, 096 cells in total), each exhibiting a unique leakage pattern from process-induced variations such as oxide thickness and doping differences. An applied challenge is decoded into row and column signals via row and column address decoders, respectively, to select target cells (via V1) while suppressing interference from unselected cells. The picoampere level leakages of the selected cells (IO1 and IO2 ) are routed to a readout circuit that converts them into stable digital response. Each cell’s distinct leakage ensures high uniqueness and entropy across the array. D. Address Decoding and Cell Selection Row and column decoders convert input address codes of a challenge into row (RS) and column (CS) select signals. The selection logic, shown in Fig. 1(a-1), ensures only the targeted cell contributes to the readout, preventing crosstalk. PseudoNMOS devices in the selection circuit control the differential
Fig. 3. CRP generation workflow: a challenge with address and response length n triggers current comparisons in selected cells to generate n concatenated response bits.
Fig. 4. (a) Distribution of differential leakage currents: the mean value is 28.1986 pA, and the standard deviation is 8411.84 pA; (b) Uniqueness is evaluated over 190 inter-array comparisons generated by 20 arrays (19+18+ ... + 2 + 1) using 4096 bits of data each, yielding an average FHD of 0.5001 and a standard deviation of 0.008002.
input pair MA and MB to enable or disable current paths for each cell. E. Readout Circuitry The readout circuit converts the picoampere-level leakage current from the selected cell into a stable digital bit. First, a pair of tunable pseudo-resistors (shown in Fig. 1(d)) transform the leakage current (IO1 and IO2 ) into a voltage according to the relation: VO1(O2) = V3 − IO1(O2) × Rpseudo , where V3 is the biasing voltage, and Rpseudo is the effective resistance (in the order of GΩ). This converted differential voltage (∆V = VO1 − VO2 ) is then amplified by a fully differential operational amplifier with a gain of 30 dB to suppress noise and ensure signal integrity (resulting in ∆V′ ), before being digitized by a comparator to produce a stable and unique output bit (Bout ) as shown in Fig. 1(c).
Fig. 5. PUF waveforms of 1500 samples obtained from simulation with one highlighted as an example. Due to process-related randomness, the 1500 differential leakage current waveforms are all different. The input challenges are applied at the rate of 1 MHz.
F. Challenge–Response Pair (CRP) Generation A challenge C consists of n address codes corresponding to the desired response length ‘n’. For each address code (split into row and column addresses) of a challenge C, the readout circuit compares the voltage-converted leakage currents corresponding to the two branches of the selected cell. The comparison result is latched as a 1-bit response (0 or 1), where the dominant branch determines the output state. Concatenating n such response bits for n address codes of a challenge results in an n-bit PUF response R as illustrated in Fig. 3, which is repeatable for the same challenge and PUF unit, unique and unclonable for each PUF unit. III. R ESULTS The proposed gate-leakage PUF is prototyped in a 65 nm CMOS process. We first verified and evaluated a small-scale PUF array before scaling to a 4096-cell PUF. A comparison with state-of-the-art designs is summarized in Table II. A. 16-cell PUF Array Test Monte Carlo simulations were first performed on a single cell to evaluate process-induced variations. As shown in Fig. 4(a), the distribution of differential leakage currents exhibits a mean of 28.1986 pA and a standard deviation of 8.41184 nA, validating the expected quantum tunneling based leakage current variability.
Fig. 6. Logical speckle figure of measured PUF output from 20 arrays: Black[1]-50.02%, White[0]-49.98% TABLE I R ESULTS OF NIST R ANDOMNESS T ESTS ON 700 A RRAYS Test Monobit Test Frequency in a Block Test Runs Test Longest Run of 1s in a Block Test DFT Test Serial Test NIST Approximate Entropy Test Cumulative Sums Test
Average p-value 0.7524 0.5356 0.4886 0.5579 0.4956 0.9996 0.5886 0.9899
Pass Rate (%) 100 99.43 98.57 99.43 98.43 100 99.43 100
For array-level measurement, 16 PUF cells were sampled over 1500 cycles each. Representative waveforms are illustrated in Fig. 5. Due to random oxide thickness and channel variations, the differential leakage current (first row) may appear as positive or negative across cells. This signal is processed through a current comparator to produce a binary output bit (last row). The intermediate voltage waveform after current-to-voltage conversion and filtering (second row) effectively suppresses noise and transient glitches before amplification (third row), ensuring bit stability across samples.
TABLE II C OMPARISON OF THE PROPOSED QT-PUF WITH THE STATE OF THE ART Area per Stabilization InterBER (%) Required Array FHD bit (F2 ) JSSC 2019 [21] 40 Soft Oxide Breakdown 0.9998 1875 NO 0.496 0.02 ISSCC 2020 [33] 28 (FDSOI) NAND 0.9999999 3698.97 YES 0.4978 0.089 / 1.41e-64h JSSC 2020 [34] 28 Ring Oscillator 0.99986 33163 YES 0.4994 0.156 JSSC 2021 [19] 180 Sub-threshold Leakage N/Ga 354 YES 0.4946 0.0073 TCAS 2022 [35] 65 SRAM 0.9999965 307.69 NO 0.4947 3 TCAS 2023 [36] 28 Arbiter 0.9999927 5143 YES 0.502 0.0016 a IOTJ 2024 [20] 55 Gate-oxide Leakage N/G 3239.67 NO 0.500 3 Nature 2025 [37] N/Ab Carbon Nanotubes 0.7–0.95 N/Ga YES 0.48 0.55–0.98 TCAS 2025 [38] 45 SRAM N/Ga 46419.75d YES 0.4937–0.4989 0 ISSCC 2025 [39] 28 Eye-Opening Arbiter 0.99906 44438.78 YES 0.4999 3.49 / 2e-6h QT-PUF (This work) 65 Gate Tunneling Leakage 0.9999998 9151.95 NO 0.5001 0.0163 N/Ga : Information not given in the paper; N/Ab : Not Applicable; d 4 CRPs; e Increasing #challenges (N ) raises overall consumption; h After stabilization. Reference
Process (nm)
Topology
Entropy
Power/Energy per bit 51.2 fJ 0.38 mW 2150 fJ 465000 fJ 0.324 mW / 81 fJ 1.486 mW N/Ga N/Ga ∝ Ne 259 fJ 96.04 nW / 19.21 fJ
B. 64×64 PUF Array Evaluation A 64 × 64 PUF array was further tested to assess largescale randomness and uniqueness. The logical speckle pattern in Fig. 6 demonstrates a near-ideal balance between ‘0’ and ‘1’ responses, with probabilities of 0.4998 and 0.5002, respectively. The corresponding Shannon entropy, calculated using Eq. 1, is 0.9999998, approaching the theoretical maximum for random binary sequences. E = − [plog2 p + (1 − p) log2 (1 − p)]
(1)
The uniqueness of twenty arrays is evaluated using interarray fractional Hamming distance (FHD), calculated across 190 PUF array/unit pairs (each with 4096 bits response). The histogram in Fig. 4(b) shows a mean FHD of 0.5001 and a standard deviation of 0.008002, indicating high uniqueness and independence among arrays. Randomness was further verified using the NIST SP 800-22 suite across 700 arrays as summarized in Table I, along with array pass percentage and corresponding mean p-values for each sub-test. Statistical analysis predicts that at a significance level of 0.001, at least 99.41% of arrays will satisfy all sub-test criteria. Reliability under voltage and temperature variations is shown in Fig. 7. The worst-case BER occurs at 100◦ C and 1.2 V (0.003418), and at 0.9 V and 35◦ C (0.049316). Averaged over the range of 10–70◦ C and 1.0–1.3 V, which sufficiently covers typical implantable IoMT operating conditions, the BER remains below 0.000163. The average power consumption per bit is 96.038 nW at 1.2 V and 35◦ C, making the proposed design suitable for ultra-low-power embedded and implantable operation. C. Comparison and Discussion Table II summarizes a comparison between the proposed gate-tunneling-leakage PUF and prior state-of-the-art designs. The proposed PUF achieves a near-ideal entropy of 0.9999998 and an inter-array FHD of 0.5001, demonstrating excellent randomness and uniqueness. In contrast to many stabilizationbased implementations [19], [33], [34], [36]–[39], the proposed design operates reliably without requiring additional calibration or error correction. Although its area per cell is slightly larger than that of deep-submicron SRAM or NAND PUFs, the circuit features a simple structure and inherently
Fig. 7. Measured BER of the proposed PUF under (a) temperature variation and (b) supply voltage (VDD) variation. The standard operating condition is 1.2 V and 35◦ C.
stable operation. Moreover, it attains a low BER of 0.000163 without any post-processing and a power (energy) consumption of 96.038 nW/bit (19.207 fJ/bit, respectively), surpassing most recent CMOS-based PUF implementations. Overall, the proposed PUF achieves a favorable balance among reliability, uniqueness, and energy efficiency, making it well-suited for ultra-low-power implantable/wearable IoMT applications. IV. C ONCLUSION This work presents a quantum tunneling leakage-based PUF that leverages intrinsic gate leakage in standard CMOS for hardware security in implantable IoMT devices. By exploiting the nonlinear and temperature-insensitive characteristics of quantum mechanical tunneling, the proposed design achieves high entropy (0.9999998), excellent uniqueness (FHD = 0.5001), and low BER (0.000163) under operating conditions of typical implantable devices without additional stabilization or error correction. Using 65 nm CMOS, it operates reliably across voltage and temperature ranges (0.9–1.3 V and 0–100◦ C) with an ultra-low power cost of 96.038 nW/bit, outperforming many existing CMOS PUFs. These results demonstrate that gate-tunneling leakage can serve as a robust, low-power, and scalable entropy source, offering a promising pathway towards secure and energy-efficient hardware primitives for next-generation implantable IoMT systems. Future work will focus on optimizing the QT-PUF cell, performing hardware measurements, and exploring security applications such as mutual authentication protocols utilizing QT-PUF integrated on IoMT devices.
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