arXiv CSopen access

A Methodology to Assess Power Modeling in Energy-Aware Federated Learning on Heterogeneous Mobile Devices

A Methodology to Assess Power Modeling in Energy-Aware Federated Learning on Heterogeneous Mobile Devices Chaimae Jallouli1

Karim Boubouh2

Robert Basmadjian1

arXiv:2605.27601v1 [cs.DC] 26 May 2026

May 28, 2026 1

Mohammed VI Polytechnic University, Benguerir, Morocco 2 Khalifa University, Abu Dhabi, UAE Abstract

Estimating CPU power on heterogeneous ARM-based commodity devices is challenging due to limited access to CPU’s voltage domains. As a result, state-of-the-art energy-aware Federated Learning (FL) frameworks typically rely on simplified approximate power models to estimate computation energy, rather than the more accurate analytical CMOS-based model. To bridge this gap, we propose a reproducible CPU power estimation methodology combined with a railto-cluster mapping technique to retrieve cluster-level supply voltage. We evaluate our approach on two commodity Android devices and show that the analytical model predicts CPU power with errors below 10%, whereas the approximate model incurs errors of up to 959%. Using AnycostFL, a state-of-the-art energy-aware FL framework, we show that the analytical model achieves the same 80% model accuracy while consuming 1.4× less energy than the approximate model. These results highlight that approximate models can severely misestimate computation energy and lead to suboptimal decisions. This work facilitates the use of analytical CPU power models on heterogeneous multi-cluster ARM-based mobile SoCs without additional hardware support or external power measurement tools.

1

Introduction

Green computing has shifted toward energy-aware solutions [35]. As ARM-based devices gain compute power, they are replacing x86 architectures due to superior performance-per-watt [24] and are increasingly hosting on-device Machine Learning (ML) tasks [19]. Unlike x86 processors, which offer OS-accessible metrics like RAPL [39], ARM processors typically only expose frequency. This limited observability hinders analytical CMOS-based power models common for x86 [12], with direct implications for battery-powered devices where maintaining performance under tight energy budgets requires accurate power estimation [44]. Since on-device ML is CPU-dominated [42], modeling inaccuracies directly impact energy-aware optimization and the reliability of on-device frameworks. At the same time, a new generation of on-device ML appeared [11], such as Federated Learning (FL) [34], a distributed paradigm that allows devices to collaboratively train a shared model while keeping data local. By shifting training to end devices, FL places local computation, and 0 This version of the contribution has been accepted for publication, after peer review, but is not the Version of Record and does not reflect post-acceptance improvements, or any corrections. The Version of Record will be available online at: https://doi.org/[DOI~to~appear] once published in the proceedings of Networked Systems (NETYS 2026), Springer Nature. Use of this Accepted Version is subject to the publisher’s Accepted Manuscript terms of use: https://www.springernature.com/gp/open-research/policies/accepted-manuscript-terms

1

consequently energy consumption, at the center of system performance constraints. The energyaware FL frameworks use techniques such as client selection, pruning, sparsification, and dynamic resource allocation to optimize training energy [32, 48, 42, 49]. These methods require an accurate estimation of computation energy, making power modeling accuracy central. In practice, however, most existing state-of-the-art FL frameworks use approximate CPU power models, that estimate CPU power from frequency alone, due to the scarcity of the processor’s voltage readings. While convenient, such approximations assume linear voltage-frequency scaling and homogeneous cores neglecting key physical parameters and architectural heterogeneity that drive power demand under CPU-intensive workloads. This limitation is worsened on modern mobile SoCs, with multi-cluster CPU architectures [5], where multiple clusters have distinct performance and energyefficiency use cases, with appropriate frequency and voltage ranges. Approximate, cluster-agnostic models fail to capture this heterogeneity and misestimate power demand which consequently degrades their optimization strategies. This paper addresses this apparent gap and presents a reproducible methodology for estimating the dynamic power of heterogeneous multi-cluster ARM-based CPUs by adopting the analytical CMOS-based model. Our approach accounts for cluster heterogeneity and resolves the lack of voltage observability through a rail-to-cluster mapping technique to extract per-cluster supply voltages across operating frequencies. This enables accurate power modeling on commodity mobile devices without additional hardware support or external measurement tools. The key contributions of this paper are: • Estimating CPU dynamic power using the analytical CMOS-based model, accounting for cluster-level heterogeneity in modern ARM-based mobile SoCs. • Extracting per-cluster supply voltage across frequencies, despite the absence of hardware documentation or direct voltage readings. • Demonstrating that analytical modeling achieves errors below 10%, while approximate models incur errors of up to 959%. • Highlighting the impact of the power model on the optimization strategy of AnycostFL [32] as a case study. We showed that the analytical model reached target accuracies (80% and 90%) using approximately 1,000 J and 2,500 J respectively, compared to 5,000 J using the approximate model. The rest of this paper is organized as follows: Section 2 frames the problem and research questions. Section 3 and 4 outline the methodology and implementation. Section 5 validates the approach against approximate methods and demonstrates its impact on AnycostFL. Finally, Section 6 reviews relevant literature, and Section 7 concludes the paper.

2

Problem Statement and Research Questions

In CMOS-based processors, the power draw originates from three main sources: dynamic power due to switching between charging-discharging of capacitance, short-circuit power caused by transient current paths during switching, and leakage power, a static loss consumed even with no switching activity. The integrated power equation is given by [10]: Ptotal = Pdyn + Pshort_circuit + Pleakage

2

(1)

Table 1: Workstation evaluation: Analytical vs. Approximate power models compared to RAPL ground truth. Model

Freq [Hz]

Param

Pdyn [W]

P̂dyn [W]

Err [%]

Analytical Approximate

1.2 × 109 1.2 × 109

Ceff = 8.2 × 10−9 F ϵ = 1.91 × 10−27

5.57 5.57

5.62 3.31

0.94 40.6

Analytical Approximate

3.6 × 109 3.6 × 109

Ceff = 8.2 × 10−9 F ϵ = 1.91 × 10−27

28.21 28.21

27.95 89.3

0.95 217

Dynamic power dominates [15] and depends on frequency f , voltage V , and effective capacitance Ceff = αC. The analytical model is: Pdyn = Ceff V 2 f (2) For full workload, Ceff is approximately constant, making this model physically grounded [10, 16]. In contrast, many energy-aware FL frameworks [32, 48, 42, 49] assume V ∝ f and use: Pdyn ≈ ϵf 3

(3)

However, even if ϵ captures voltage scaling and workload effects, it must be re-derived per frequency, limiting generalization and oversimplifying Equation (2). A preliminary validation on an Intel Xeon W-2123 [27] (Table 1) shows that the analytical model achieves errors lower than 1%, while the approximate model yields errors of 40.6% and 217%, highlighting the limitations of the V ∝ f assumption, especially for heterogeneous mobile systems. This paper addresses the following research questions: • What is the accuracy of the approximate model compared to the analytical CMOS-based model on heterogeneous multi-cluster mobile devices? • How do approximate power models affect energy estimation and optimization decisions in energy-aware FL frameworks? We address these by proposing a cluster-aware power estimation methodology (Section 3), evaluating model accuracy on a real-world testbed and investigating implications for AnycostFL (Section 5.2.3).

3

Methodology

Processors based on x86 and ARM technologies differ fundamentally in their architecture and system-level capabilities. While x86 platforms provide direct CPU power access via the RAPL interface [40], ARM devices expose only battery-level power through the fuel gauge [4]. This together with differences in voltage visibility, core isolation, and thermal behavior necessitate a dedicated methodology for ARM-based mobile devices. Modern ARM SoCs are built with multiple heterogeneous clusters. A common architecture follows ARM’s big.LITTLE technology [5], where LITTLE cores are destined for energy-efficiency, while big cores handle demanding workloads. A more advanced architecture employs a tri-cluster CPU configuration (e.g., Google Tensor SoCs), with additional ultra-performance cores. Each cluster is a computational unit, with independent voltage and frequency values, and can operate simultaneously or powered off when needed, allowing for per-cluster power measurements. 3

Figure 1: Main pipeline for computing CPU dynamic power on heterogeneous ARM-based mobile devices. (a) Controlled conditions and core isolation techniques applied on two Core/Cluster acti(i) vation strategies (e.g., Per-cluster and Single) to measure per-cluster dynamic power Pdyn (f ) , (b) Rail-to-cluster mapping to extract voltage ranges (Vmin , Vmax ) per operating-frequency. To the best of our knowledge, this is the first attempt to provide such a fine-grained methodology for modern mobile and IoT devices with heterogeneous multi-cluster CPUs. Figure 1 depicts our proposed methodology built on two components: (i) cluster-aware activation-based power measurement strategies to measure dynamic power (see Section 3.2), and (ii) a rail-to-cluster mapping technique to extract per-cluster supply voltages (see Section 3.3), enabling the analysis and validation of the analytical power model in Equation (2).

3.1

Battery-to-CPU Power Approximation

Tools and interfaces for fine-grained CPU power measurements in mobile and IoT devices are not yet standardized [46] and often rely on external hardware, as recommended by the Android platform for component-level power analysis [3]. Consequently, many prior studies use external power analyzers such as Monsoon [14] and BattOR [41]. While these tools produce high-precision rail-level power measurements, they call for invasive procedures and non-portable physical setup with limited scalability. In light of these constraints, software-based power monitoring represents an accessible and inexpensive alternative for power measurement on mobile phones. Battery power reflects the power drawn by the device’s components such as CPU, display, radios, DRAM, etc., given by: Pbatt = PCPU + Pdisp + Pradio + Pmisc (4) where Pdisp , Pradio and Pmisc denote the power demand of the display subsystem, wireless interfaces and other components respectively. According to prior works [17, 37], the display, connectivity interfaces and CPU dominate the device’s overall power draw. By minimizing the contribution of dominant non-CPU components, conducting CPU-bound benchmarks, and assuming remaining components to be static, measured battery variations can be attributed chiefly to CPU activities (PCPU ≈ Pbatt ). Battery power Pbatt can be expressed in terms of the battery supply voltage and current, both 4

Table 2: CPU dynamic power measurement protocol at minimum and maximum frequencies.

Phase

Freq/Governor

State

Output

idle_min stress_min idle_max stress_max

powersave / fmin powersave / fmin performance / fmax performance / fmax

Idle ∼100% load Idle ∼100% load

Pidle (fmin ) Pload (fmin ) Pidle (fmax ) Pload (fmax )

Dynamic power: Pdyn (f ) = Pload (f ) − Pidle (f ), f ∈ {fmin , fmax }. exposed by the fuel gauge: Pbatt = Vbatt · Ibatt

(5)

The Power Profiler [13] tool is used to compute average battery power demand using Equation (5). While this approach provides device-level power, it does not account for individual clusters within heterogeneous mobile SoCs. Thus, next we introduce our proposed cluster-aware dynamic power estimation approach.

3.2

Cluster-aware Dynamic Power

Dynamic power is defined as the difference between the power drawn by a loaded CPU and an idle baseline. For each considered frequency point f , we assume two phases: an idle phase, measuring the average power of online but unloaded core(s), denoted Pidle (f ), and a loaded phase, where CPU core(s) are fully stressed using stress-ng [29], denoted Pload (f ). We select two operating points: the minimum frequency under the powersave governor and the maximum frequency under the performance governor. Table 2 shows four measurement phases. Each phase is run for a sufficient duration and repeated multiple times, from which average values are reported. On multi-cluster CPUs, we record the average battery power while activating a target (i) cluster Cli , and treat it as an estimate of that cluster’s dynamic power, Pdyn (f ). We propose two strategies for the activation of core(s) to isolate dynamic power. 3.2.1

Per-cluster Activation

This strategy (Algorithm 1) isolates the dynamic power of a target cluster Cli by keeping it online while all other clusters are switched off. This controlled setup attributes any power variation to the target cluster. During the loaded phase, all cores in the cluster are driven to full utilization, except for the housekeeping core (e.g., core 0), which is reserved for system tasks. The dynamic power contribution of cluster Cli is: (i) (i) (i) Pdyn (f ) = Pload (f ) − Pidle (f ). (6) The total power demand of the CPU then becomes: PCP U (f ) =

|Cl| X

(i)

Pdyn (f )

(7)

i=1

3.2.2

Single Activation

The Single activation strategy (Algorithm 2) captures fine-grained dynamic power contribution of individual cores. Within the target cluster, only one core k and the housekeeping core are kept 5

online at a time. The dynamic power contribution of an individual core k is: i h k0 +k k0 k k (f ) − Pidle (f ), Pcore (f ) = Pload (f ) + Pidle

(8)

k0 +k k (f ) is the power of core k when fully where Pidle (f ) denotes the idle power of both cores, and Pload loaded. This iterates through each core k in a cluster, deducing its dynamic power as: X (i) k Pcore (f ). (9) Pdyn (f ) = k̸=k0

3.3

Rail-to-cluster Voltage Mapping

Analytical power modeling requires (V, f ) pairs, yet on heterogeneous multi-cluster architectures, the frequency-voltage relationship is not linear nor consistent across clusters. We propose a railto-cluster voltage mapping procedure to retrieve per-cluster supply voltage. In modern SoCs, each cluster is powered by a dedicated rail, but these lack public documentation. We reverse-engineered DVFS by monitoring regulator rails exposed by the Linux kernel while activating clusters at different frequencies and workloads. For each cluster, a CPU-bound workload is pinned to all its cores while remaining clusters are kept idle. By logging regulator voltage, we track the rails whose voltage increases when the target cluster is activated. Repeating this across all clusters enables mapping each rail to its cluster and identifying associated voltage ranges. Each voltage spike corresponds to the activation of a specific cluster, allowing direct mapping of minimum and maximum supply voltages (Vmin , Vmax ).

3.4

Power Model Validation

Once dynamic power Pdyn (f ) is measured supply voltages are obtained the effective capacitance Ceff can be derived by: Pdyn (f ) Ceff (f ) = (10) f.V 2 For the approximate model, ϵ is derived by reversing Equation (3): ϵ(f ) ≈

Pdyn (f ) f3

(11)

With the analytical model, Ceff is expected to remain constant for a given micro-architecture and 100% workload (e.g., α = 1), besides measurement noise at minimum and maximum frequency. For the approximate model, the difference between ϵ(fmin ) and ϵ(fmax ) is typically significant; therefore, we define a single representative value of ϵ as the arithmetic mean: ϵ(fmin ) + ϵ(fmax ) . (12) 2 With Ceff , ϵ, operating frequencies and their corresponding supply voltages available, power can be estimated using the analytical and approximate models in Equations (2) and (3). We follow a validation procedure to evaluate accuracy using the relative prediction error: ϵ=

Error =

P̂dyn (f ) − Pdyn (f ) × 100% Pdyn (f )

(13)

Lower prediction error reflects agreement between model predictions and CMOS circuit behavior. We consider errors below 5% acceptable, as measurements are prone to noise and thermal fluctuations. 6

4

Implementation

4.1

System Configuration

Rail-to-cluster mapping and fine-grained power measurements share common setup steps: frequency and governor configuration, cluster/core isolation, and workload execution. Direct sysfs control is typically restricted by SELinux; therefore, we use the EX Kernel Manager (EXKM) [21] to set percluster frequencies and switch between powersave and performance governors. To disable DVFS (Dynamic Voltage and Frequency Scaling), minimum and maximum frequencies are set to identical values before each phase. Isolation is achieved via Linux kernel mechanisms: cpuset cgroups shield the SYSTEM_CORE (core 0) from background tasks; cores are toggled via /sys/devices/system/cpu/cpuX/online; and workloads are bound to target cores using taskset: taskset -c k stress-ng --cpu 1 --timeout T where -c k pins the stress-ng worker to core k for duration T. All scripts for configuration, isolation, and mapping are available in our public repository [6].

4.2

Power Measurement Setup

Loaded phases employ stress-ng with the –cpu-method all option to ensure workload-independent stress. Experiments are executed via the Termux terminal emulator [43]. Battery-level power is logged using Power Profiler [13], which samples Vbatt , Ibatt , frequency, utilization, and temperature every 0.5 s. To mitigate thermal throttling bias, we enforce a target CPU temperature of 30 ◦ C [33]. If the temperature deviates, we employ dynamic warming (multi-core stress) or cooling (core off-lining and idling). To ensure stability, each 10-minute phase is repeated 5 times. An idle-before-load order is maintained, with consistent thermal management between runs. Results are reported as the mean across runs, with variability indicated by min–max ranges or standard deviation.

4.3

Activation Strategies

We introduce two activation strategies to isolate cluster-level dynamic power. Per-cluster Activation: Algorithm 1 performs the per-cluster activation procedure by offlining non-target clusters, measuring power in idle and loaded states, then extracting the per-cluster dynamic power as their difference [7]. Single Activation: Algorithm 2 isolates per-core dynamic power by measuring one core at a time while keeping the SYSTEM_CORE k0 online for OS activities. It alternates idle and loaded phases for each target core and computes the cluster dynamic power as the sum of per-core contributions [8].

5

Evaluation

This section introduces the hardware specifications of our experimental testbed, then addresses the research questions in Section 2 by evaluating the cluster-aware power measurement methodology presented in Section 3.

7

Algorithm 1 Per-cluster Activation Require: Target cluster Cli , frequency f , SYSTEM_CORE k0 (i) Ensure: Pdyn (f ) 1: Offline all clusters except Cli ; keep all cores in Cli online 2: Pin Cli to frequency f ; shield system tasks on k0 (i) 3: Pidle (f ) ← MeasureAvgPower() 4: Pin stress-ng to all cores k ∈ Cli where k ̸= k0 (i) 5: Pload (f ) ← MeasureAvgPower() (i) (i) (i) (i) 6: Pdyn (f ) ← Pload (f ) − Pidle (f ); return Pdyn (f ) Algorithm 2 Single Activation Require: Target cluster Cli , frequency f , SYSTEM_CORE k0 (i) k (f )} Ensure: Pdyn (f ), {Pcore 1: Offline clusters except Cli ; pin f ; keep only k0 online and shielded (i) 2: Pdyn (f ) ← 0 3: for all k ∈ Cli , k ̸= k0 do k0 +k 4: Bring core k online; Pidle (f ) ← MeasureAvgPower() k 5: Pin stress-ng i ) ← MeasureAvgPower() h to core k; Pload (f 6:

k (f ) ← P k (f ) + P k0 (f ) − P k0 +k (f ) Pcore load idle idle (i)

(i)

k (f ); Offline core k Pdyn (f ) ← Pdyn (f ) + Pcore 8: end for (i) 9: return Pdyn (f )

7:

Table 3: Hardware specifications of the Android devices used in our experiments. Device Google Pixel 8 Pro Samsung A16

5.1

SoC

Clusters

RAM

Operating System

Google Tensor G3 MediaTek Helio G99

LITTLE + big + Prime LITTLE + big

12 GB 8 GB

Android 14 Android 14

Hardware Configuration

To analyze cluster-specific dynamic power on ARM-based mobile platforms, two Android devices hosted the experiments, and whose hardware and software configuration are summarized in Table 3. The Google Pixel 8 Pro integrates a Google Tensor G3 SoC with a heterogeneous tri-cluster CPU (LITTLE, big and Prime), representing upper-tier mobile platforms. The Samsung A16, powered by Mediatek Helio G99 SoC, adopts a big.LITTLE CPU design and is representative of lower-cost devices with more modest computational capabilities. Both devices reflect the heterogeneity of modern commodity devices in terms of performance, architecture and energy characteristics. We obtained the minimum and maximum operating voltages of each CPU cluster at corresponding operating frequencies using the rail-to-cluster mapping presented in Section 3.3. Table 4 presents the voltage ranges for both Google Pixel 8 Pro and Samsung A16.

8

Table 4: Measured per-cluster operating ranges (frequency and voltage) for two mobile SoCs used in our experiments. Device

Cluster

Cores

fmin [Hz]

fmax [Hz]

Vmin [V]

Vmax [V]

Google Pixel 8 Pro (Tensor G3)

LITTLE big Prime

4 4 1

3.24 × 108 4.02 × 108 5.00 × 108

1.70 × 109 2.37 × 109 2.91 × 109

0.56 0.55 0.53

0.85 1.13 1.20

Samsung A16 (MediaTek Helio G99)

LITTLE big

6 2

5.00 × 108 7.25 × 108

2.00 × 109 2.20 × 109

0.55 0.55

0.81 0.76

Table 5: Analytical model accuracy across activation strategies. Pdyn is the measured dynamic power (± standard deviation). Predicted power P̂ is computed using the averaged Ceff . Bolding indicates the strategy with the lowest absolute error for each cluster. Device

Samsung A16

Activation Strategy

Cluster

Min frequency Pdyn [W] P̂ [W] Err [%]

Max frequency Pdyn [W] P̂ [W] Err [%]

Per-cluster

LITTLE big

0.182 ±0.087 0.189 ±0.062

0.099 0.198

8.5 4.8

0.549 ±0.074 0.806 ±0.042

0.825 0.787

-7.3 -4.4

Single

LITTLE big

0.100 ±0.045 0.206 ±0.037

0.102 0.211

1.6 2.5

0.859 ±0.143 0.862 ±0.081

0.846 0.841

-1.5 -2.4

Per-cluster

LITTLE big Prime

0.146 ±0.041 0.142 ±0.095 0.100 ±0.065

0.135 0.157 0.102

-8.0 10.2 2.0

0.995 ±0.097 4.267 ±0.101 3.114 ±0.063

1.090 3.910 3.050

9.6 -8.5 -2.0

Single

LITTLE big Prime

0.142 ±0.070 0.199 ±0.107 0.100 ±0.021

0.136 0.193 0.103

-3.9 -3.1 3.1

1.056 ±0.167 4.639 ±0.153 3.178 ±0.092

1.100 4.790 3.080

4.3 3.3 -2.9

Pixel 8 Pro

5.2

Experimental Results

5.2.1

Activation Algorithm Validation

In Section 3.2, we proposed two activation strategies against ground-truth measurements at the lowest and highest supported frequencies. Overall, both strategies yield reasonable estimates with low relative errors, while the Single strategy outperforms the Per-cluster strategy and achieves errors below 5% across all clusters and frequencies. For the Samsung A16, the Single strategy achieves an error of only 1.5% for the LITTLE cluster at maximum frequency, while the Per-cluster strategy reaches errors up to 8.5%. Due to the high granularity of the Single strategy, it requires long per-core configurations. Nevertheless, it is more robust against inter-cluster power interference and thermal throttling. While Per-cluster strategy shows larger errors, between 7% and 10%, likely due to noise caused by simultaneous cluster activation and shared voltage noise on commodity heterogeneous SoCs. Since Single outperforms Per-cluster by achieving lower errors and better repeatability, we adopt it for the remainder of this paper and subsequent experiments. 5.2.2

Analytical vs. Approximate Model Accuracy

Our first research question, presented in Section 2, relates to the accuracy of the analytical model of Equation (2) in contrast to the approximate one of Equation (3). To compare, we use the same prior validation methodology explained in Section 3.4. Figure 2 clearly brings out the difference 9

Google Pixel 8 Pro Dynamic Power [W]

Dynamic Power [W]

Samsung A16

1.0

0.10

10.0

1.0

0.10 LITTLE

LITTLE

big

LITTLELITTLE big

big

Ground Truth

Analytical Model

big

Prime Prime

Approximate Model

Figure 2: Dynamic power prediction comparison across analytical and approximate models on Samsung A16 and Google Pixel 8 Pro devices. Bars show mean predicted across 5 runs: ground truth power, analytical power model and approximate power model. The analytical model closely tracks ground truth values across all clusters and frequency points, while the approximate model deviates from measured power by factors up to 2-5x. Table 6: Reported average values of ground truth (P ) versus predicted power (P̂ ) using analytical and approximate power models (Single Strategy). Relative error values represent mean ± std across runs. Device Cluster Freq. [Hz] P [W] Analytical Approximate

Samsung A16

Pixel 8 Pro

P̂ [W]

Err [%]

P̂ [W]

Err [%]

LITTLE

5.00 × 108 2.00 × 109

0.100 ±0.045 0.859 ±0.143

0.102 0.846

1.6 -1.5

0.057 3.630

-43.3 322.0

big

7.25 × 108 2.20 × 109

0.206 ±0.037 0.862 ±0.081

0.211 0.841

2.5 -2.4

0.118 3.310

-42.5 284.0

LITTLE

3.24 × 108 1.70 × 109

0.142 ±0.070 1.056 ±0.167

0.136 1.100

-3.9 4.3

0.077 11.200

-45.8 959.0

big

7.25 × 108 2.20 × 109

0.199 ±0.107 4.639 ±0.153

0.193 4.790

-3.1 3.3

0.111 22.600

-44.3 388.0

Prime

5.00 × 108 2.91 × 109

0.100 ±0.021 3.178 ±0.092

0.103 3.080

3.1 -2.9

0.058 11.500

-42.0 262.0

among both models at estimating power by comparing their estimations to ground truth measured power across all clusters and operating frequencies. The analytical model shows excellent power prediction behavior, agreeing with the measured values, maintaining prediction errors below 5%. In contrast, the approximate model deviates significantly from measured power, diverging by a scale of 3 to 10x. These poor predictions are reflected by high relative errors reaching 322.0% on Samsung A16 and 959.0% on the Google Pixel 8 Pro at maximum frequencies (See Table 6). These results demonstrate the unreliability of the approximate 10

(b) MNIST 1.0

0.9

0.9

0.8

0.8

0.7

0.7

Mean Accuracy

Mean Accuracy

(a) Fashion-MNIST 1.0

0.6 0.5 0.4 0.3

0.6 0.5 0.4 0.3

0.2

0.2 Analytical Model Approximate Model

0.1

Analytical Model Approximate Model

0.1

0.0

0.0 0

1000

2000

3000

4000

5000

6000

7000

0

500

Cumulative Energy [J]

1000

1500

2000

2500

3000

Cumulative Energy [J]

Figure 3: Cumulative computation energy vs. Accuracy of AnycostFL on (a) Fashion-MNIST and (b) MNIST using the analytical and the approximate model. For a given target accuracy, the analytical model showcases lower energy consumption compared to the approximate one, leading to suboptimal optimization decisions that affect model’s accuracy. model for power estimation compared to the analytical CMOS-based model. 5.2.3

Implications for Energy-Aware Federated Learning

Figure 3 reports accuracy versus energy tradeoffs of the AnycostFL framework, trained on FashionMNIST and MNIST datasets, when modeling computation energy using the analytical CMOS-based model in Equation (2) or with the approximate formulation commonly used in energy-aware FL frameworks in Equation (3). This figure highlights the paper’s main takeaway: the choice of power model shapes the optimization strategy and subsequent decisions of energy-aware FL (e.g., energy budgets, shrinking factors, resource allocation), and therefore impacts the attainable accuracy under a fixed energy budget. Technical details about the AnycostFL framework and its computation energy as well as the integration of analytical and approximate model are provided in Appendix B. Across both datasets, and for a target accuracy, the analytical model consumes less computation energy compared to the approximate model. The gap in terms of energy consumption is especially apparent on Fashion-MNIST, where the analytical model reaches 80% accuracy at roughly 1000J, whereas the approximate model requires more training rounds, consuming above 5000J to attain the same accuracy. On the easier MNIST dataset, both models show similar behavior and converge closely, with the analytical model still outperforming in terms of accuracy with less energy consumption. The same pattern is repeated with the analytical model consuming 600J to achieve a target accuracy of 90% while the approximate model consumes 1000J to attain the same accuracy.

5.3

Discussion

Figure 3 showcases the divergence between the analytical and approximate models in terms of estimating energy. Since the approximate model does not account for per-cluster voltage domains and effective capacitance, it tends to over-estimate this quantity. As explained in Appendix B, the max . If over-estimated, the shrinking factor αt,i is estimated based on the computation energy Et,i feasible range of ϕt,i becomes tighter, pushing αt,i towards smaller values and training overly small 11

models, leading to slower convergence. We call this phenomenon over-shrinking. The analytical model, within 5% from the ground truth, avoids this issue and reaches the same target accuracy with substantially less energy. This phenomenon is not specific to AnycostFL, instead, it is prominent on any FL framework basing its energy-aware decisions on computation energy constraints. The methodology is also relevant beyond FL, and can be extended to edge computing frameworks such as on-device inference scheduling, DVFS-aware task placement, etc. With the same pattern appearing on an upper-tier and a lower-cost mobile device (e.g., Google Pixel 8 Pro and Samsung A16), we conclude that ignoring per-cluster voltage domains and effective capacitance is a direct cause of this sensitivity, instead of attributing it to a SoC artifact. A natural concern arises when considering the scale of an FL deployment, where many heterogeneous devices are included in the training process. In practice, the characterization cost is correlated with performing the rail-to-cluster mapping and extracting effective capacitance only once. Moreover, extracting parameters needs to be performed once per-SoC, and then re-used for any devices built on it. For a non characterized device, a hybrid approach is possible: apply the analytical model when parameters are ready, and fall back to the approximate model otherwise. This enables potential improvements of power estimation accuracy, without requiring full upfront characterization.

6

Related Work

Power consumption of processors was firstly analyzed by Chandrakasan et al. [18], who established dynamic power as in Equation (2). Burd and Brodersen [15] presented an energy-saving framework through supply voltage reduction, demonstrating the high impact of voltage. However, these works only targeted homogeneous cores with uniform voltage domains. Energy efficiency has also been addressed at the architectural level. Kumar et al. [31] demonstrated significant energy savings (15-40%) by assigning different power-performance traits to cores. This design was later adopted by ARM in big.LITTLE [23] and DynamIQ tri-cluster architectures [36]. Under these technologies, heterogeneous clusters operate under distinct voltage-frequency points and lack methods to extract per-cluster supply voltage. Carroll and Heiser [17] conducted an early smartphone power study using external hardware, but considered homogeneous cores. Walker et al. [45] proposed a real-time model based on performance monitoring counters (PMCs) that is cluster-agnostic and data-driven. A CMOS-based model was presented in Baek et al. [9], which relies on invasive hardware instrumentation and doesn’t account for per-cluster voltage and capacitance variations. In addition to hardware-based measurement techniques, several studies proposed software-based power modeling techniques for power measurements. Pathak et al. [37] used system activity statistics to build a fine-grained energy accounting framework tested on Android and Windows Mobile. A similar approach named PowerTutor was proposed by Dong and Zhong [20] to estimate componentlevel energy consumption using information from the operating system and the battery. These approaches were able to estimate power without external hardware, yet their prime focus is on system level energy consumption instead of analytical CPU power modeling. Moreover, these studies don’t account for heterogeneous multi-cluster SoCs present in modern mobile processors, or consider cluster-level power parameters such as supply voltage and effective switching capacitance, both required to apply the CMOS-based analytical model. Despite extensive work on CPU power modeling, existing analytical formulations remain difficult to apply on commodity smartphones, mainly due to the absence of per-cluster voltage observability. 12

Consequently, most prior studies either rely on external hardware instrumentation or employ datadriven approximations that remain unaware of heterogeneous cluster-level operating points. To the best of our knowledge, no prior work proposes a reproducible methodology enabling fine-grained analytical modeling of dynamic CPU power demand on real multi-cluster mobile devices. In this work, we address these limitations by proposing the first comprehensive methodology to enable fine-grained analytical CPU power modeling on commodity heterogeneous mobile devices. Our approach introduces a rail-to-cluster mapping mechanism to retrieve per-cluster supply voltages and presents multiple activation strategies to capture dynamic CPU demand at different granularities. We validate the methodology across several Android smartphones without requiring external measurement equipment or hardware modifications.

7

Conclusion and Future Work

This work questions the prevalent reliance on approximate CPU power models in edge and mobile computing and highlights their shortcomings on modern heterogeneous ARM-based platforms. To address this gap, we present a reproducible methodology for estimating dynamic CPU power using the analytical CMOS-based modeling approach. Our methodology overcomes the challenge of unavailable voltage measurements by employing cluster-aware activation and a reverse-engineered mapping from rail to cluster voltages, enabling accurate power estimation without direct voltage observability. Our evaluations on two heterogeneous off-the-shelf Android devices showed that the analytical model produces stable, physically meaningful parameters and accurate power estimates, whereas the approximate models used by state-of-the-art energy-aware Federated Learning (FL) frameworks exhibit large errors and poor generalization. When integrated with AnycostFL, a state-of-the-art energy-aware FL framework, we showed that inaccurate approximate models lead to suboptimal energy allocation and poorer accuracy–energy trade-offs, while the analytical model enables more effective use of each device’s energy budget. This work faces several limitations. With our methodology focusing on dynamic CPU power, other contributors to total energy footprint of an FL workload on mobile devices remain unexplored. In practice, the CPU power contains additional power terms (See Equation 1), that can have significant impact on total power demand under realistic workloads. As part of our measurement protocol, we include steps to mitigate thermal throttling effects. While useful during the parameter extraction process, long-running FL deployments may experience more intense throttling regimes, altering the power-performance relationship altogether. Finally, the PCP U ≈ ∆Pbatt remains an under-validated assumption, with the power supply of the battery feeding into other non-CPU components (e.g., DRAM, voltage regulators and SoC interconnect). Inspired by these limitations, our future work focuses on extending the analytical model to capture the CPU leakage term, enabling thermal-aware CPU power modeling. We further plan to extend our testbed to include a broader set of SoCs, with ML inference workloads reflecting real-world scenarios, to assess the accuracy of the proposed model under realistic thermal regimes. Overall, this work lays a practical foundation for accurate, portable, and energy-optimal learning on heterogeneous mobile and edge devices.

References [1] Advanced Micro Devices. BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h Processors, 2013. Includes SVI2 voltage identification format. 13

[2] Advanced Micro Devices. AMD64 Architecture Programmer’s Manual: BIOS and Kernel Developer Guide for AMD Zen Processors, 2017. Details MSR_PSTATE registers and VID decoding for Zen architectures. [3] Android Open Source Project. Measure component power. https://source.android.com/ docs/core/power/component, 2026. Accessed: 2026-01-12. [4] Android Open Source Project. Measure device power. https://source.android.com/docs/ core/power/device, 2026. Accessed: 2026-01-12. [5] ARM Ltd. big.LITTLE Technology: The Future of Mobile, 2013. https://armkeil.blob.core.windows.net/developer/Files/pdf/white-paper/ big-little-technology-the-future-of-mobile.pdf.

URL

[6] Anonymous Authors. Arm-based power modeling repository. https://anonymous.4open. science/r/ARM-based-Power-04E8/README.md. Accessed: 2026-01-27. [7] Anonymous Authors. Per-cluster activation script (perclusterpower.sh), 2026. URL https:// anonymous.4open.science/r/ARM-based-Power-04E8/percluster_power.sh. Anonymized artifact repository. Accessed: 2026-01-29. [8] Anonymous Authors. Single activation script (singlepower.sh), 2026. URL https:// anonymous.4open.science/r/ARM-based-Power-04E8/single_power.sh. Anonymized artifact repository. Accessed: 2026-01-29. [9] In Hwan Baek and Xiangrui Liu. Power and energy analysis on odroid-xu+e and adaptive power models. In UCLA Engineering Technical Report, Los Angeles, CA, USA, 2015. University of California, Los Angeles. [10] In Hwan Baek and Xiangrui Liu. Power and energy analysis on odroid-xu+e and adaptive power model. Technical report, University of California Los Angeles, Los Angeles, CA, USA, 2017. [11] Robert Basmadjian, Karim Boubouh, Amine Boussetta, Rachid Guerraoui, and Alexandre Maurer. On the advantages of p2p ml on mobile devices. In Proceedings of the thirteenth ACM international conference on future energy systems, pages 338–353, 2022. [12] Yannick Becker and Stefan Naumann. Software-based estimation of software-induced energy dissipation with powerstat. In From Science to Society: The Bridge Provided by Environmental Informatics, pages 69–73. Shaker Verlag, 2017. [13] Karim Boubouh and Robert Basmadjian. Power profiler: Monitoring energy consumption of ml algorithms on android mobile devices. In Companion Proceedings of the 14th ACM International Conference on Future Energy Systems, e-Energy ’23 Companion, New York, NY, USA, 2023. ACM. doi: 10.1145/3599733.3600248. [14] Duc Hoang Bui, Yunxin Liu, Hyosu Kim, Insik Shin, and Feng Zhao. Rethinking energyperformance trade-off in mobile web page loading. In Proceedings of the 21st Annual International Conference on Mobile Computing and Networking, MobiCom ’15, pages 14–26, New York, NY, USA, 2015. ACM. doi: 10.1145/2789168.2790090. [15] Thomas D. Burd and Robert W. Brodersen. Energy efficient cmos microprocessor design. IEEE Journal of Solid-State Circuits, 30(2):118–125, February 1995. doi: 10.1109/4.350185. 14

[16] Thomas D. Burd and Robert W. Brodersen. Processor design for portable systems. Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, 13(2-3):203–221, 1996. doi: 10.1007/BF01130406. [17] Aaron Carroll and Gernot Heiser. An analysis of power consumption in a smartphone. In Proceedings of the 2010 USENIX Annual Technical Conference, USENIX ATC ’10, pages 271– 284, Berkeley, CA, USA, 2010. USENIX Association. [18] Anantha P. Chandrakasan, Samuel Sheng, and Robert W. Brodersen. Low-power cmos digital design. IEEE Journal of Solid-State Circuits, 27(4):473–484, 1992. doi: 10.1109/4.126534. [19] Sauptik Dhar, Junyao Guo, Jiayi Liu, Samarth Tripathi, Unmesh Kurup, and Mohak Shah. A survey of on-device machine learning: An algorithms and learning theory perspective. ACM Transactions on Internet of Things, 2(3), 2021. [20] Mingjun Dong and Lin Zhong. Self-constructing energy models for mobile devices. In Proceedings of the 9th International Conference on Mobile Systems, Applications, and Services (MobiSys), pages 335–348. ACM, 2011. [21] flar2. Ex kernel manager, August 2024. URL https://play.google.com/store/apps/ details?hl=en-US&id=flar2.exkernelmanager. Android app. Accessed: 2025-12-09. [22] GNOME Foundation. Gnome desktop environment. https://www.gnome.org/, 2025. Accessed: 2025-02-14. [23] Peter Greenhalgh. ARM big.LITTLE Processing with ARM Cortex-A15 and Cortex-A7. ARM Ltd., September 2011. [24] Khushi Gupta and Tushar Sharma. Changing trends in computer architecture: A comprehensive analysis of arm and x86 processors. International Journal of Scientific Research in Computer Science, Engineering and Information Technology, 7:619–631, 2021. [25] i3wm. i3 window manager. https://i3wm.org/, 2025. Accessed: 2025-02-14. [26] Intel Community. How to determine cause of processor frequency scale down to 200 mhz, 2019. URL https://community.intel.com/t5/Software-Tuning-Performance/ How-to-determine-cause-of-processor-frequency-scale-down-to-200/m-p/1137067. Accessed: 2025-11-25. [27] Intel Corporation. Intel® xeon® w-2123 processor (8.25m cache, 3.60 ghz) specifications, 2017. URL https://www.intel.com/content/www/us/en/products/sku/125036/ intel-xeon-w2123-processor-8-25m-cache-3-60-ghz/specifications.html. Accessed: 2025-11-28. [28] Intel Corporation. Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 4: Model-Specific Registers. Intel Corporation, order number 335592 edition, 2023. URL https://kib.kiev.ua/x86docs/Intel/SDMs/252046-048.pdf. Accessed: 2025-11-25. [29] Colin Ian King. stress-ng, October 2020. URL https://wiki.ubuntu.com/Kernel/ Reference/stress-ng. Ubuntu Wiki. Accessed: 2025-11-28. [30] Colin Ian King. powerstat. https://github.com/ColinIanKing/powerstat, 2025. Accessed: 2025-02-14. 15

[31] Rakesh Kumar, Dean M. Tullsen, Parthasarathy Ranganathan, Norman P. Jouppi, and Keith I. Farkas. Single-isa heterogeneous multi-core architectures for multithreaded workload performance. ACM SIGARCH Computer Architecture News, 31(2):64–75, 2003. doi: 10.1145/871656.859629. [32] Peichun Li, Guoliang Cheng, Xumin Huang, Jiawen Kang, Rong Yu, Yuan Wu, and Miao Pan. Anycostfl: Efficient on-demand federated learning over heterogeneous edge devices. In Proceedings of the IEEE INFOCOM 2023 - IEEE Conference on Computer Communications, pages 1–10, New York, NY, USA, 2023. IEEE. doi: 10.1109/INFOCOM53939.2023.10228888. [33] Zhaoxia Luo, Hyejung Cho, Xiaobing Luo, and Kyung-il Cho. System thermal analysis for mobile phone. Applied Thermal Engineering, 28(14-15):1889–1895, 2008. [34] Brendan McMahan, Eider Moore, Daniel Ramage, Seth Hampson, and Blaise Agüera y Arcas. Communication-efficient learning of deep networks from decentralized data. In Proceedings of the 20th International Conference on Artificial Intelligence and Statistics, volume 54 of PMLR, pages 1273–1282, Fort Lauderdale, FL, USA, 2017. PMLR. [35] San Murugesan. Harnessing green it: Principles and practices. IT Professional, 10(1):24–33, 2008. doi: 10.1109/MITP.2008.10. [36] Mahesh Navada, Sanjay Saikia, and Abhijit Bhattacharyya. Power and performance analysis of dynamiq-based multi-core processors. In Proceedings of the 2019 IEEE 37th International Conference on Computer Design (ICCD), pages 478–481. IEEE, 2019. doi: 10.1109/ICCD46524.2019.00071. [37] Abhinav Pathak, Y. Charlie Hu, and Ming Zhang. Fine-grained power modeling for smartphones using system call tracing. In Proceedings of the Sixth European Conference on Computer Systems (EuroSys), pages 153–168. ACM, 2011. [38] Ryan Piersma, Tawhid Bhuiyan, Tanvir Ahmed Khan, and Simha Sethumadhavan. Reverse engineering dvfs mechanisms. In Proceedings of the 2025 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pages 111–122, Tysons Corner, VA, USA, 2025. IEEE. doi: 10.1109/HOST55342.2025.00000. [39] Guillaume Raffin and Denis Trystram. Dissecting the software-based measurement of cpu energy consumption: A comparative analysis. arXiv preprint arXiv:2401.15985, 2024. [40] Guillaume Raffin and Denis Trystram. Dissecting the software-based measurement of cpu energy consumption: A comparative analysis, 2024. [41] Aaron Schulman, Daniel Levin, Neil Spring, Bobby Bhattacharjee, and Patrick Levis. Demo: Phone power monitoring with battor. In Proceedings of the 17th Annual International Conference on Mobile Computing and Networking, MobiCom ’11, pages 113–114, New York, NY, USA, 2011. ACM. doi: 10.1145/2030613.2030667. [42] Dian Shi, Liang Li, Rui Chen, Pavana Prakash, Miao Pan, and Yuguang Fang. Toward energyefficient federated learning over 5g+ mobile devices. IEEE Wireless Communications, 29(5): 44–51, 2022. [43] Termux Project. Termux. https://termux.dev/, 2026. Accessed: 2026-01-21.

16

[44] Matthew J. Walker, Stephan Diestelhorst, Andreas Hansson, Anup K. Das, Sheng Yang, Bashir M. Al-Hashimi, and Geoff V. Merrett. Accurate and stable run-time power modeling for mobile and embedded cpus. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 36(1):106–119, 2017. doi: 10.1109/TCAD.2016.2562920. [45] Matthew J. Walker, Stephan Diestelhorst, Andreas Hansson, Anup K. Das, Sheng Yang, Bashir M. Al-Hashimi, and Geoff V. Merrett. Accurate and stable run-time power modeling for mobile and embedded cpus. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 36(1):106–119, 2017. doi: 10.1109/TCAD.2016.2562920. [46] Genc-Alban Wilke, Aniko Hegedus, et al. Measuring power consumption in mobile devices for energy sustainable computing: Review of power measuring tools. Sustainable Computing: Informatics and Systems, 32:100627, 2021. doi: 10.1016/j.suscom.2021.100627. [47] Winbond Electronics Corporation. W83627HF Hardware Monitor Datasheet, 2002. Documents VCORE voltage monitoring via Super I/O hardware interface. [48] Zhaohui Yang, Mingzhe Chen, Walid Saad, Choong Seon Hong, and Mohammad Shikh-Bahaei. Energy efficient federated learning over wireless communication networks. IEEE Transactions on Wireless Communications, 20(3):1935–1949, 2021. doi: 10.1109/TWC.2020.3037554. [49] Yifan Zeng, Mingzhe Chen, and Walid Saad. Resource-aware federated learning for mobile edge computing. IEEE Transactions on Wireless Communications, 2023.

17

A

x86-based Workstations

Whether deployed as commodity desktop devices or as servers in a data center environment, most workstations rely on x86-based processors. Our goal in this section is therefore to present a robust methodology for reliably capturing power measurements on such devices, and access the supply voltages readable through model-specific registers.

A.1

Hardware and Software Details

In this study, a preliminary validation experiment was conducted on a x86-based Intel workstation, while our proposed methodology was tested on ARM-based mobile devices. The hardware and software specifications for both types of devices are details in what follows. We conducted our preliminary validation experiment on a workstation equipped with a CPU Intel Xeon W-2123 containing 4 physical cores, with one hardware thread each and a single-socket x86 architecture with RAPL (Running Average Power Limit) support. The processor frequencies range from 1.2 GHz to 3.6 GHz. The system runs Ubuntu 24.04.3, a Linux distribution released on 2024. By extracting the VID at both operating points (e.g. minimum and maximum frequency) following the steps in section A.3, we deduce the corresponding CPU voltage values of the x86 workstation presented in Table 7. Table 7: CPU voltage at fixed operating frequencies on the Intel Xeon W–2123 workstation.

A.2

Corner

Frequency [GHz]

VID

VCPU [V]

Min Max

1.20 3.60

6193 7971

0.756 0.973

Power Measurement Protocol

On the workstation, the open-source software package powerstat [30] is used to extract power demand readings on Linux operating systems, and retrieve additional system statistics such as CPU usage, as well as frequency and temperature values [12]. To minimize uncontrolled CPU tasks and retrieve a clean and reliable baseline power measurements, a lightweight keyboard-centric window manager named i3 [25] is used instead of GNOME [22], the default desktop environment of Ubuntu. To reduce measurement noise and instability, CPU shielding and CPU pinning mechanisms were implemented. Shielding prevents operating system routines and background tasks from running on experimental shielded cores by confining them to a dedicated SYSTEM_CORE, while pinning fixes the synthetic workload (e.g., stress-ng) on the set of assigned cores. This pinning-and-shielding setup yields more reliable and coherent power measurements, and ensure that power variation is a result of workload rather than noisy OS tasks.

A.3

Core Voltage Retrieval

In early x86 platforms (mid-1990s through 2012), CPU Vcore was traditionally accessible through external hardware monitoring chips (e.g., Winbond/Nuvoton W83627, ITE IT87xx) [47]. In modern processors, the CPU supply voltage is not exposed through standard OS interfaces such as lm_sensors or hwmonitor which report this information as unavailable.

18

Intel Processors According to Intel® 64 and IA-32 architectures software developer’s manual (vol. 4, MSR reference) [28], the CPU voltage is encoded as a VID field in an internal voltage–frequency table and can be retrieved from the IA32_PERF_STATUS (MSR 0x198) register, precisely in the slice 47:32, scaled by a factor of 1/8192 [38, 26]. The CPU voltage can be computed as: VCPU = M SR_P ERF _ST AT U S[47 : 32] × 2−13 (14) where MSR_PERF_STATUS[47:32] is the VID entry in the register IA32_PERF_STATUS, and the factor 2−13 converts this fixed-point VID code into a voltage value in volts. AMD processors In AMD processors, voltage information is also encoded as a VID, but exposed differently through P-states in MSR_PSTATE_n registers (typically MSR 0xC0010064 through 0xC001006B). Each P-state entry contains a VID field containing the AMD’s Serial Voltage Identification encoding. The supply voltage is found through the conversion of the SVI2 formula defined in the AMD BIOs [1] and the Kernel Developer’s Guide (BKDG) [2] as follows: VCPU = Voffset − k · VID

(15)

The generation-dependent constants in Equation (15) are available through the BKDG documentation.

B

AnycostFL: Energy-Aware FL Case Study

AnycostFL [32] is a state-of-the-art on-demand Federated Learning framework that reduces computation energy using a model-shrinking strategy and allows to train the same network at different widths according to a shrinking factor α. In other words, during each local training round, each peer selects its model size according to its resource constraints. This approach balances accuracy and energy among peers with heterogeneous performance ranges and constitutes a solid energy-aware FL framework on mobile and edge devices. To illustrate the gap between analytical and approximate models and their impact on energyaware Federated Learning (FL), we adopt the AnycostFL framework’s computation model for time and energy on our experimental devices (see Section 5.1). For comparison, we compute the energy model twice: once with the widely adopted approximation model of Equation (3) by the energyaware FL frameworks, and once with our proposal of using the analytical model of Equation (2). More precisely, for each model, we measure computational energy consumed by peer i at round t, given a CPU frequency ft,i . Using the analytical dynamic-power model in Equation (2), the computation energy is given by: (i) cmp Et,i = Ceff Vi (ft,i )2 Wt,i , (16) (i)

where Ceff is the effective switching capacitance of peer i and Vi (ft,i ) is the supply voltage corresponding to ft,i . Similarly to Equation (16), the approximate energy is modeled as: cmp 2 Et,i = ϵi ft,i Wt,i ,

(17)

where ϵi is a device-dependent hardware coefficient. The local compute workload is defined as Wt,i ≜ τ |Di | αt,i Wsample

(18)

with τ the number of local epochs per round, |Di | the size of peer i’s dataset, αt,i ∈ [0, 1] the fraction of samples processed at round t, and Wsample the average number of CPU cycles required to process one training sample on the target platform. 19