Unlocking the performance limits of 2T0C DRAM with Ω-shaped-gated single-crystal In(2)O(3) FETs.

Unlocking the performance limits of 2T0C DRAM with Ω-shaped-gated single-crystal In2O3 FETs - PMC Skip to main content An official website of the United States government Here's how you know Here's how you know Search Log in Primary site navigation Search Log in Search PMC Full-Text Archive Search in PMC Journal List User Guide As a library, NLM provides access to scientific literature. Inclusion in an NLM database does not imply endorsement of, or agreement with, the contents by NLM or the National Institutes of Health. Learn more: PMC Disclaimer | PMC Copyright Notice Sci Adv . 2026 May 29;12(22):eaec3934. doi: 10.1126/sciadv.aec3934 Unlocking the performance limits of 2T0C DRAM with Ω-shaped-gated single-crystal In 2 O 3 FETs Shiyue Zuo 1, 2, † , Zhengdao Xie 1, † , Xu Zhao 2, † , Lin Tang 1 , Yidan Zhao 1, 2 , Yu Zeng 1 , Wencheng Niu 1 , Sen Liu 3 , Qingjiang Li 3 , Guanhua Yang 4 , Ling Li 4 , Zhipeng Wei 5 , Cong Ye 6 , Xuming Zou 1 , Xingqiang Liu 1, * , Lei Liao 1, * , Penghui He 1, * Author information Article notes Copyright and License information 1 State Key Laboratory of Chemo and Biosensing, Engineering Research Center of Advanced Semiconductor Technology and Application of Ministry of Education, College of Semiconductors (College of Integrated Circuits), Hunan University, Changsha, China. 2 School of Physics, Henan Normal University, Xinxiang, China. 3 College of Electronic Science and Technology, National University of Defense Technology, Changsha, China. 4 Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China. 5 School of Physics, Changchun University of Science and Technology, Changchun, China. 6 School of Microelectronics, Hubei University, Wuhan, China. * Corresponding author. Email: liuxq@hnu.edu.cn (X.L.); * Corresponding author. Email: liaolei@whu.edu.cn (L.L.); * Corresponding author. Email: hepenghui@hnu.edu.cn (P.H.) † These authors contributed equally to this work. Roles Shiyue Zuo : Conceptualization, Data curation, Formal analysis, Investigation, Methodology, Validation, Visualization, Writing - original draft, Writing - review & editing Zhengdao Xie : Conceptualization, Data curation, Formal analysis, Methodology, Validation, Visualization, Writing - original draft, Writing - review & editing Xu Zhao : Data curation, Investigation, Writing - original draft, Writing - review & editing Lin Tang : Investigation Yidan Zhao : Investigation Yu Zeng : Investigation Wencheng Niu : Investigation Sen Liu : Conceptualization, Data curation, Formal analysis, Funding acquisition, Investigation, Methodology, Project administration, Resources, Software, Supervision, Validation, Visualization, Writing - original draft, Writing - review & editing Qingjiang Li : Conceptualization, Data curation, Validation, Writing - review & editing Guanhua Yang : Formal analysis Ling Li : Formal analysis Zhipeng Wei : Resources, Supervision Cong Ye : Formal analysis, Methodology Xuming Zou : Conceptualization Xingqiang Liu : Conceptualization, Funding acquisition, Project administration, Resources, Supervision, Validation, Writing - review & editing Lei Liao : Conceptualization, Funding acquisition, Methodology, Project administration, Supervision, Validation, Writing - original draft, Writing - review & editing Penghui He : Conceptualization, Funding acquisition, Investigation, Methodology, Project administration, Supervision, Validation, Writing - original draft, Writing - review & editing Received 2025 Sep 18; Accepted 2026 Apr 21; Collection date 2026 May 29. Copyright © 2026 The Authors, some rights reserved; exclusive licensee American Association for the Advancement of Science. No claim to original U.S. Government Works. Distributed under a Creative Commons Attribution NonCommercial License 4.0 (CC BY-NC). This is an open-access article distributed under the terms of the Creative Commons Attribution-NonCommercial license , which permits use, distribution, and reproduction in any medium, so long as the resultant use is not for commercial advantage and provided the original work is properly cited. PMC Copyright notice PMCID: PMC13220857  PMID: 42213832 Abstract This study demonstrates high performance Ω-shaped-gated single-crystal In 2 O 3 field-effect transistors (Ω-SC In 2 O 3 FETs), which push the performance boundaries of oxide-based electronics. To showcase these capabilities in a demanding application, a capacitorless two-transistor (2T0C) dynamic random-access memory (DRAM) cell is fabricated based on Ω-SC In 2 O 3 FETs. Specifically, a high average field-effect mobility of 321.7 cm 2 /V·s with an on-off ratio above 10 9 and a steep subthreshold swing (SS) of 64.6 mV/dec are obtained for Ω-SC In 2 O 3 FETs due to the single-crystal In 2 O 3 channel as well as effectively enhanced electrostatic control of the Ω-shaped gate structure. The robust gate bias temperature stress stabilities, including positive and negative bias-temperature stresses, are achieved with a threshold voltage ( V TH ) shift value of −121 and 41 mV for 10 4 s, respectively, which is attributed to low defect density. Moreover, the high-performance capacitorless 2T0C DRAM cell based on Ω-SC In 2 O 3 FETs is constructed, which presents long data retention of 10 5 s, ultrafast access speed of 5 ns, endurance of 10 12 cycles, and storage of 3 bits. Ω-shaped-gated single-crystal In 2 O 3 FETs with record-high performance push the boundaries of 2T0C DRAM. INTRODUCTION Oxide semiconductors have wide bandgaps (>3.0 eV), enabling field-effect transistors (FETs) with extremely low leakage currents (<10 −21 A/μm), which have emerged as a promising alternative for low-power-consumption dynamic random-access memory (DRAM) applications ( 1 – 7 ). Moreover, oxide semiconductors exhibit excellent back-end-of-line (BEOL) compatibility ( 8 – 10 ). To leverage these advantages, circuit design optimization can eliminate the reliance on capacitor components, thereby realizing capacitorless 2T0C DRAM cells suitable for applications requiring long data retention time and low power consumption. This capacitorless architecture holds great potential for resolving a series of problems caused by excessive leakage currents in conventional 1T1C DRAM ( 11 – 16 ). The first oxide-based DRAM cell based on c -axis-aligned crystalline InGaZnO FETs presents a theoretically estimated retention time of 1000 s ( 17 ). Subsequently, various oxide FETs have been used to fabricate capacitorless 2T0C DRAM cells experimentally, such as planar FETs ( 18 – 22 ), double-gate FETs ( 23 ), ultrathin oxide FETs ( 24 , 25 ), channel-all-around FETs and so on ( 26 – 28 ). To date, a write speed of 10 ns and a retention time of 30,000 s have been achieved individually for different 2T0C DRAM cells, while an output current of 1500 μA/μm and a mobility of 55.0 cm 2 /V·s are achieved for FETs ( 18 , 28 ). However, the performance boundaries of 2T0C DRAM remain largely unexploited due to limitations in the electrical properties of oxide FETs, particularly in terms of carrier mobility and operational stability. A high field-effect mobility (μ FE ) is essential to provide efficient carrier transport and charge/discharge capability, enabling ultrafast read and write operations for 2T0C DRAM cells ( 29 , 30 ). In addition, since the write transistor operates predominantly under negative gate bias, this operating condition can lead to a negative shift in the threshold voltage ( V TH ) and an increase in off-state current, thereby accelerating the leakage of stored charge and reducing retention time. Meanwhile, under positive bias stress (PBS), oxide FETs exhibit a positive V TH shift (Δ V TH ), which reduces the read transistor current and correspondingly diminishes the extracted storage node voltage, further degrading retention performance ( 31 , 32 ). These degradation behaviors are attributed to the redistribution of oxygen vacancy defects in oxide semiconductors, as well as the increased interface state density causing the trapping of charges under the influence of an electric field and thermal energy ( 33 ). However, reducing oxygen vacancy concentration in oxide semiconductors may improve stability but at the expense of reduced mobility ( 34 , 35 ). Here, we develop Ω-shaped-gated single-crystal (Ω-SC) In 2 O 3 FETs that exhibit high mobility, high current density, and robust stability, and explore the performance boundaries of 2T0C DRAM cells based on Ω-SC In 2 O 3 FETs. The single-crystal structure of the In 2 O 3 channel could minimize deep-level defects, enabling high carrier mobility and stability simultaneously, which are approaching their theoretical limits. On the basis of Ω-shaped-gated architecture with simplified processes, the Ω-SC In 2 O 3 FETs present ultrahigh current density, robust gate bias temperature stress stability, and superior gate modulation capability. Therefore, the capacitorless DRAM cells based on Ω-SC In 2 O 3 FETs generate performances with long retention time, ultrafast speeds, and robust endurance. RESULTS Electrical performance of Ω-SC In 2 O 3 FETs Figure 1A shows the schematic diagram of Ω-SC In 2 O 3 FETs with a top-gate device structure. The single-crystal In 2 O 3 nanowires with a diameter of 50.0 nm grown by chemical vapor deposition (CVD) are used as channel, while the Al 2 O 3 is deposited as the gate dielectric by atomic layer deposition (ALD). Ni films are used as contact and gate electrodes, in which the Ω-shaped gate structure is realized via a tilted and rotated thermal evaporation process (fig. S1). After the transfer of presynthesized nanowires, the subsequent device fabrication is BEOL compatible, using only low-temperature processes. The detailed fabrication process is shown in figs. S2 and S3. The Ω-shaped gate structure is constructed via a simple process to enhance gate modulation, offering a superior balance between performance and manufacturability. It achieves electrostatic control close to that of a gate-all-around (GAA) structure while maintaining the process simplicity and cost-effectiveness of a planar gate. Figure S4 presents a basic Silvaco TCAD simulation comparing the electrostatic potential and carrier concentration distribution in the channel for the structures of Ω-shaped gate FETs, planar top-gate FETs, and ideal GAA FETs. The simulation results clearly demonstrate that the Ω-gate provides a potential profile much closer to that of GAA than to the planar gate, confirming enhanced gate control. Figure 1 (B and C) shows the high-angle annular dark-field scanning transmission electron microscopy image and the element distribution maps of Ω-SC In 2 O 3 FETs, respectively. Sharp interfaces are observed between the functional layers, indicating low interface defects. Notably, a single-crystal grain spanning the entire cross section is observed, as illustrated in the inset of Fig. 1B as well as in fig. S5. The scanning electron microscopy (SEM) and energy-dispersive spectrometry (EDS) images of single-crystal In 2 O 3 nanowire demonstrate uniform diameter and homogeneous elemental distribution along its axial direction (fig. S6). To further investigate the defect characteristics in the In 2 O 3 nanowires, x-ray photoelectron spectroscopy analysis is performed, as shown in fig. S7. Deconvolution of the O 1 s spectrum for the In 2 O 3 nanowires reveals three components, assigned to lattice oxygen (529.6 eV), oxygen vacancies (530.9 eV), and surface hydroxides (531.9 eV). The oxygen vacancy concentration is quantified at 17.31%, which acts as intrinsic donors for charge carriers. Fig. 1. Device structure and electrical performances of Ω-SC In 23 FETs. Open in a new tab ( A ) Schematic image of Ω-SC In 2 O 3 FETs using a top-gate device structure. ( B ) Transmission electron microscopy (TEM) image and ( C ) the elements distributions of Ω-SC In 2 O 3 FETs. ( D ) Typical output characteristics and ( E ) transfer characteristics of Ω-SC In 2 O 3 FETs with a channel length ( L CH ) of 3 μm. ( F ) Transfer characteristics of Ω-SC In 2 O 3 FETs with L CH scaling from 3 μm to 200 nm. ( G ) Output characteristics of Ω-SC In 2 O 3 FETs with an L CH of 200 nm. Benchmark of ( H ) I on , ( I ) mobility, and SS for previously reported oxide FETs and this work. The Ω-SC In 2 O 3 FETs demonstrates high mobility and on-state current ( I ON ) among oxide-based FETs for 2T0C DRAM applications. The concurrent 2T0C DRAM requirements of long retention time, high write speed, and low static power consumption, necessitate optimizing the write and read transistor for simultaneously low off-state current, high current driving capacity, and appropriate V TH with high stability ( 36 ). For comparison, the bottom-gate transistors based on single-crystal In 2 O 3 (BG-SC In 2 O 3 FETs) are fabricated on 100-nm-thick SiO 2 substrates to investigate the electrical properties of single-crystal In 2 O 3 channel, as shown in fig. S8. A drain output current of 200 μA/μm is obtained when V GS and V DS are 20 and 1 V, respectively (fig. S8C). The transfer characteristics of BG-SC In 2 O 3 FETs are carried out as the gate voltage sweeps from −50 to 50 V at a constant V DS of 0.1 V (fig. S8D). A negative V TH (defined as the V GS at an I DS of 1 nA/μm) of −22.8 V is extracted, due to that the planar gate structure has a weak electric field modulation ability. It is worth noting that the BG-SC In 2 O 3 FETs exhibit a hysteresis window as large as 10 V. This is primarily attributed to that the abundant dangling bonds on the surface of the single-crystalline In 2 O 3 , resulting from its well-ordered crystal structure, adsorb a substantial number of water and oxygen molecules, and their adsorption/desorption processes cause the trap/release of electrons during device operation. Figure 1D shows typical output characteristics of Ω-SC In 2 O 3 FETs with a channel length ( L CH ) of 3 μm. The output current of the device is as high as 800 μA/μm at V DS = 1.0 V, which is four times that of the BG-SC In 2 O 3 FETs. In addition, the output characteristics at various V DS are measured to clearly demonstrate channel saturation, as shown in fig. S9. A stable current saturation without noticeable degradation at high V DS indicates the absence of appreciable self-heating effects, while an obvious linear region without any current crowding at low V DS suggests good contact properties between single-crystal In 2 O 3 and Ni with the potential for further scaling. A contact resistance of 1216 Ω·μm at 300 K is extracted by the four-probe method (fig. S10). The transfer characteristics of the Ω-SC In 2 O 3 FETs are measured ( Fig. 1E ), in which the off-state current ( I OFF ) is lower than 30 fA/μm that is below the measurement limit, accompanying an on-off ratio of 10 9 with a V TH of −0.8 V. These results indicate that the Ω-shaped gate structure can effectively enhance the modulation ability of the gate electric field on the channel, achieving large output current and V TH close to 0 V (fig. S11). A hysteresis as small as 4 mV is obtained, which is attributed to high-quality single-crystal structure of In 2 O 3 channel causing low bulk defect density, as shown in the inset of Fig. 1E . Moreover, the prolonged oxygen plasma treatment, in combination with the uniform coverage of an Al 2 O 3 dielectric layer, effectively passivates the dangling bonds on the nanowire surface ( 37 ). As the L CH scales down to 200 nm, the on-state current ( I ON ) of the device gradually increases, while the V TH and I OFF are negligibly changed ( Fig. 1F ), resulting from robust gate modulation of Ω-SC structures. Impressively, the maximum transconductance ( G m ) of 1800 μS/μm and the maximum I ON of 4000 μA/μm are simultaneously obtained at V DS = 1 V for Ω-SC In 2 O 3 FETs with L CH = 200 nm ( Fig. 1, F and G ). Figure S12A shows the transfer characteristics of the planar BG-SC In 2 O 3 FETs and Ω-SC In 2 O 3 FETs with the same channel length. In the V GS scan range from −2 to 2 V, the planar BG-SC In 2 O 3 FETs are difficult to turn-off and have more negative V TH (−4 V) and smaller on-state currents than Ω-SC In 2 O 3 FETs, exhibiting weaker gate control capability. The subthreshold swing (SS) remains consistently near the thermal limit (63 to 74 mV/dec) as L CH scales from 3 μm down to 200 nm (fig. S12B). Figure S12C shows the transfer characteristics of the Ω-SC In 2 O 3 FETs with L CH = 200 nm at different V DS , and the drain-induced barrier lowering is less than 72 mV/V, demonstrating robust immunity to short-channel effects. In addition, the transfer characteristics of Ω-SC In 2 O 3 FETs applied a series of bottom-gate voltage ( V BG ) on heavily doped silicon is performed (fig. S13). The V TH remains remarkably stable with elevating V BG , indicating strong electric field modulation capability of Ω-shaped gate electrode. Figure 1 (H and I) summarizes the performance boost achieved in this work. Channel length scaling enables higher I ON while maintaining comparably low I OFF . Compared to various oxide-based transistors in previous reports, such as InGaZnO-, In 2 O 3 -, and InSnO-based transistors, our Ω-SC In 2 O 3 FETs exhibit a high average μ FE of 321.7 cm 2 /V·s and a high output current of 4000 μA/μm with an L CH of 200 nm, and features a more straightforward fabrication process than GAA transistors ( 4 , 5 , 7 , 13 , 14 , 16 – 18 , 20 , 22 , 24 , 26 , 28 , 38 – 47 ). In addition, a SS of 64.6 mV/dec, which is close to the theoretical limit, is extracted ( Fig. 1I ). The performance metrics of the representative devices are summarized in table S1 ( 38 – 55 ). This indicates that single-crystal In 2 O 3 provides high-speed electron transport paths while minimizing interface defects. Therefore, the Ω-SC In 2 O 3 FETs can meet the requirements outlined in the 2024 International Roadmap for Devices and Systems for both high-performance electronics and low-power electronics. Stability of Ω-SC In 2 O 3 FETs The temperature reliability and gate bias stress stability of the fabricated Ω-SC In 2 O 3 FETs are evaluated. Figure 2A records the changes in the transfer curves of FETs from 77 to 450 K, exhibiting a slight temperature dependence. As the temperature increases, the device transfer curves exhibit a slight negative shift with a Δ V TH of −141 mV, which is primarily attributed to the upward shift of the Fermi edge caused by an increase in carrier concentration. In the elevated temperature range from room temperature to 450 K, the V TH shift is limited to 29 mV, while the change in I ON remains below 8%, as shown in Fig. 2B . The μ FE of the Ω-SC In 2 O 3 FETs decreases as the temperature decreases, which is primarily dominated by contact resistance. The contact resistance, extracted via a four-probe method (fig. S10), increases at lower temperatures. Consequently, the estimated intrinsic mobility ( μ int = μ EF R total R total − 2 R C , R total is the total resistance) of the Ω-SC In 2 O 3 FETs after deducting the contribution of contact resistance, is observed to increase as temperature decreases, revealing a high-quality crystal structure where phonon scattering dominates. In addition, fig. S14 presents the leakage current characteristics of Ω-SC In 2 O 3 FETs measured over a wide temperature range from 77 to 450 K. The leakage current exhibits negligible dependence on temperature, which can be attributed to Fowler-Nordheim (F-N) tunneling. The corresponding F-N plots [ ln ( I GS / V GS 2 ) versus 1/ V GS ] are shown in fig. S15. These results confirm that the dielectric layer is of high quality, ensuring reliable device performance operation over a wide temperature range. Fig. 2. Electrical performance and stability of Ω-SC In 23 FETs. Open in a new tab ( A ) The changes in the transfer curves of Ω-SC In 2 O 3 FETs from 77 to 450 K. ( B ) extracted Δ V TH , I ON , and mobility. ( C ) PBS (room temperature), ( D ) NBTS, and ( E ) PBTS stability of the devices combined ±2 V V GS with a temperature of 60°C. ( F ) The corresponding V TH extracted from the transfer curves under different stress times. A slightly negative shift of 41 and −121 mV is observed under NBTS and PBTS for 10 4 s, respectively, while negligible change in SS is observed. Figure 2C and fig. S16 show the negative bias stress (NBS) and PBS (room temperature) stability of the Ω-SC In 2 O 3 FETs with a V GS of ±2 V, in which the drift values of V TH are −64 and −94 mV for 10 4 s, respectively. In addition, the negative bias temperature stress (NBTS) and positive bias temperature stress (PBTS) stability of the devices are measured, and a V GS of ±2 V combined with a temperature of 60°C is applied ( Fig. 2, D and E ). The corresponding V TH extracted from the transfer curves under different stress times is plotted in Fig. 2F . Slight Δ V TH values of 41 mV and −121 mV are observed under NBTS and PBTS for 10 4 s, respectively, while negligible change in SS is observed. The slightly negative shift of V TH under PBTS is primarily attributed to the further diffusion of H ions from the ALD Al 2 O 3 dielectric layer into single-crystal In 2 O 3 donating electrons to the conduction band of In 2 O 3 and the stability of O in Al 2 O 3 can suppress the migration of oxygen vacancies in In 2 O 3 . Conversely, the synergistic effect of the electric field and temperature can drive the migration of hydrogen ions from the In 2 O 3 nanowire into the dielectric layer under NBTS, thereby giving rise to a reduction in the channel carrier concentration. To further confirm the influence of hydrogen on the performance of the Ω-SC In 2 O 3 FETs, the devices are annealed at 200°C for 10 min in vacuum and in oxygen atmosphere, respectively. As illustrated in fig. S17, all devices exhibit negative shifts in their transfer curves following annealing in both environments. This shift can be attributed to the enhanced diffusion of hydrogen at elevated temperatures, which affects the carrier concentration and electrical characteristics of the FETs. In this work, the ALD Al 2 O 3 dielectric layer is grown using H 2 O as an oxidant, resulting in hydrogen residue and doping, while hydrogen is widely recognized as an electron donor in oxide semiconductors inducing a highly conductive state ( 56 ). In brief, the Ω-SC In 2 O 3 FETs exhibit robust stability against both thermal and electrical bias stress, owing to their high-quality crystalline channel and a reasonable device design. 2T0C DRAM cell based on Ω-SC In 2 O 3 FETs Figure 3 (A to C) presents the equivalent circuit diagram, schematic diagram, and SEM image of a 2T0C DRAM cell based on Ω-SC In 2 O 3 FETs, respectively, in which the drain of the write transistor connects to the gate of read transistor, using latter’s gate capacitance for charge storage. The data retention time is determined by the I OFF of the write transistor and the leakage current of read transistor, while write speed depends on I ON of write transistor. Figure 3D details the write and read timing diagrams, highlighting the decoupled nature of these operations. The memory state is read nondestructively by monitoring the current of read bit line ( I RBL ), without disturbing the charge stored at the storage node (SN), a key distinction from the traditional 1T1C architecture. The retention time can be extracted by monitoring the losses of voltage at SN ( V SN ), which can be deduced from the transfer curve of read transistor, as shown in Fig. 3E . Fig. 3. Performances of 2T0C DRAM cell based on Ω-SC In 23 FETs. Open in a new tab ( A ) Equivalent circuit diagram, ( B ) schematic image of the 2T0C DRAM cell. ( C ) Corresponding scanning electron microscopy (SEM) image of a 2T0C DRAM cell based on Ω-SC In 2 O 3 FETs. ( D ) Write and read timing diagrams, highlighting the decoupled nature of these operations. ( E ) Voltage at SN deduced from the transfer curve of read transistor. ( F ) I RBL retention time curves after writing “1” with pulse width ranging from 5 to 200 ns. ( G ) Dependence of the I RBL on the pulse width for the 2T0C DRAM cell. ( H ) V SN -time characteristic of the 2T0C DRAM. ( I ) I ON / I OFF maintains larger than 10 6 after 10 12 pulse cycles. ( J ) Benchmark of retention and access speed for reported 2T0C DRAM cell based on oxide FETs. Figure 3 (F and G) exhibits the writing speed of the 2T0C DRAM. The read current increases with longer write time and saturates after 150 ns, because the charge stored at the SN under a constant write-bit-line voltage ( V WBL ) is determined by the product of the I ON of write transistor and pulse duration. The 2T0C DRAM achieves 5-ns write speed (limited by test equipment), delivering a read current of 27 μA/μm at a V RBL of 0.1 V. This performance stems from the high carrier mobility and superior gate control capability of the Ω-SC In 2 O 3 FETs. In addition, the data retention of the 2T0C DRAM is characterized by monitoring the temporal evolution of V SN derived from I RBL , as shown in Fig. 3H and fig. S18. After writing data “1” with a 0.5 V V WBL pulse, I RBL remains at 30 μA/μm even after 10 5 s with a change of V SN (Δ V SN ) < 0.1 V. Furthermore, fig. S19 presents the Δ V SN over time for six independently fabricated DRAM cells. All devices show a Δ V SN of less than 0.1 V after 10 5 s, demonstrating the uniformity and reproducibility of the long retention characteristic. This outstanding retention characteristic is due to superior gate modulation of Ω-gate structure, which ensures a very low I OFF in the Ω-SC In 2 O 3 FETs. The endurance of DRAM based on Ω-SC In 2 O 3 FETs is evaluated using continuous pulse cycles with a period of 100 ns, as shown in Fig. 3I and fig. S20. The combination of low-frequency continuous current monitoring and high-frequency intermittent waveform verification provides a robust and comprehensive assessment of endurance. The I RBL is monitored by sampling at a rate of one point per 0.1 s throughout the 10 12 -cycle test. The DRAM exhibits negligible degradation after 10 12 endurance cycles. Figure S21 records the transfer characteristics of the Ω-SC In 2 O 3 FETs and the on/off performance of DRAM cell across different cycle numbers. As a comparison, Fig. 3J and Table 1 summarize the key parameters of previously reported capacitorless DRAM cells based on oxide transistors ( 4 , 5 , 7 , 13 , 14 , 16 – 18 , 20 – 22 , 26 , 28 , 57 – 60 ), showing an obvious performance advantage of the Ω-SC In 2 O 3 FETs with ultrafast write speed, extended data retention, exceptional on/off ratio, and low-power operation. Table 1. Benchmark of reported oxide FETs and 2T0C DRAM cell. Ref. L CH (μm) μ (cm 2 /Vs) NBS (mV) PBS (mV) I ON (μA/μm) Write time Retention (s) This work 0.2 321.7 −64 −94 4000 5 ns >100,000 ( 4 ) 20 17.54 1110 710 108 0.2 s >10,000 ( 7 ) 10 35.2 – – 23 0.1 s 10,000 ( 13 ) 0.4 – – – 150 10 ns 5000 ( 14 ) 1 55 – 13.6 67 100 ns 1360 ( 18 ) 0.1 30 – – 40 10 ns >30,000 ( 20 ) 1 8 80 30 0.9 100 ns >30,000 ( 26 ) 0.05 – −25 −20 4.07 2 s 190 Open in a new tab In addition, the multibit writing operation of the 2T0C DRAM based on Ω-SC In 2 O 3 FETs is demonstrated. Figure 4A illustrates the measurement configuration, where the V WBL varies from −0.1 to 2.0 V with a step of 0.3 V, thereby enabling the write pulse to induce eight-level memory states. Figure 4B shows the temporal evolution of the eight V SN levels over the retention period, demonstrating clear maintenance of distinct separation. Figure 4 (C and D) presents the statistical distribution of the V SN for all eight states of the 2T0C DRAM over the retention period, showing no measurable overlap between adjacent levels. The V SN values for each state cluster around their respective mean (μ) and are well described by a Gaussian distribution with a corresponding SD (σ). All eight states exhibit narrow distributions with σ values below 10 mV (fig. S22). Using the 3σ criterion for distinguishability, the difference between the mean values of any two adjacent levels exceeds three times the sum of their SDs, satisfying the condition μ 2 − μ 1 > 3(σ 2 + σ 1 ) (where the subscripts represent the state indices). This result quantitatively confirms the robust separability and reliability of the multilevel storage operation. Furthermore, multiple cyclic operation tests of eight-state storage are conducted on the same device, which exhibits superior operational stability, with the test results presented in Fig. 4E . Last, to verify the device-to-device reproducibility, the 3-bit operational characteristics of six independently fabricated DRAM cells are characterized. The linear relationship and statistical distribution of V WBL - V SN for each corresponding storage state are shown in Fig. 4F , exhibiting good uniformity of the devices and robust 3-bit storage capability in the 2T0C DRAM based on the Ω-SC In 2 O 3 FETs. Fig. 4. Multibit writing operations of the 2T0C DRAM cell. Open in a new tab ( A ) Measurement configuration of multibit writing operation of the 2T0C DRAM cell where the V WWL is fixed at 1 V, while the V WBL varies from −0.1 to 2.0 V with a step of 0.3 V. ( B ) I RBL retention time of the 2T0C DRAM cell with the V WBL varying from −0.1 to 2.0 V. ( C ) Cumulative distribution (CDF) and ( D ) statistical distribution of the 3-bit V SN . ( E ) Repeated measurements are performed of I RBL of the 3-bit operation as a linear function of V WBL . ( F ) Linear relationship between SN voltage and V WBL for multibit writing operations of six 2T0C DRAM cells. DISCUSSION In summary, the Ω-SC In 2 O 3 FETs exhibit large current transport and superior gate modulation, which achieve an ultrahigh μ FE of 321.7 cm 2 /V·s, an I ON / I OFF above 10 9 and a steep SS of 64.6 mV/dec. In addition, robust PBTS and NBTS stability with small V TH shifts are obtained, due to the high-quality single-crystal of In 2 O 3 semiconductor channel, which affords low bulk defects and interface defects. Furthermore, on the basis of Ω-SC In 2 O 3 FETs with high I ON , low I OFF , and superior stability, the developed 2T0C DRAM pushes the performance boundaries toward a retention of 10 5 s, an ultrahigh access speed of 5 ns, endurance of 10 12 cycles, and 3-bit multilevel storage capability. MATERIALS AND METHODS Synthesis of In 2 O 3 nanowires The single-crystal In 2 O 3 nanostructures were synthesized via a conventional CVD process in a horizontal tube furnace. A mixture of In 2 O 3 powder and graphite powder at a weight ratio of 1:2 was loaded into a quartz boat. Silicon substrates with a predeposited 1-nm-thick gold catalyst layer were positioned directly above the evaporation source. The entire assembly was then introduced into a quartz tube reactor. The source material was heated to 1000°C and maintained at this temperature for 1 hour under a constant gas flow (Ar/O 2 = 100/6) at a total rate of 200 sccm. After the system cooled down to room temperature, a high density of nanowires was deposited on the silicon substrates. Preparation of Ω-SC In 2 O 3 FETs Single-crystal In 2 O 3 nanowires were physically transferred onto highly doped p-type silicon substrates coated with a 100-nm thermal SiO 2 layer to serve as the channel material. After 10 min of oxygen plasma treatment, 50-nm Ni electrodes were patterned by electron beam lithography and deposited by e-beam evaporation with lift-off processes, as source/drain contact. A 10-nm Al 2 O 3 was deposited as the gate dielectric by ALD. Thereafter, 50-nm Ni was deposited as gate electrodes in the channel range and connected to DRAM cell. Last, 2-min Ar-plasma treatment was performed to reduce the contact resistance. Please see the Supplementary Materials for more details. Electrical measurement Electrical measurements were performed by a Keysight B1500A semiconductor parameter analyzer with a Lake Shore TTPX probe station. The captured data were recorded by an Keysight B1500A semiconductor parameter analyzer, while the pulse voltage was applied by the Keysight 33612A Waveform Generator. The cross-sectional high-resolution transmission electron microscopy (JIB-4501, JEOL) with an EDS analyzer was carried out to confirm the structure of the device. Moreover, the mobility is estimated using the equation in the linear operation regime μ FE = G m L CH C g WV DS where G m = d I DS / d V GS is the transconductance, C g is the capacitance of dielectric, and W is the effective channel width normalized by the area of the gate electrode covering the nanowires. During the write operation, a pulse of 0.3 V is applied to the WBL of the write transistor. Concurrently, another pulse of 0.5 V (write pulse) is applied to the write word line (WWL), turning on the write transistor and enabling charge transfer to the SN. During the read operation, the WWL is held at a voltage of −1.5 V to turn off the write transistor, preserving the charge stored at SN that slowly discharges majorly due to the off-state current of the write transistor. A read voltage of 0.1 V is then applied to the RBL, and the output current of the read transistor is measured to calculate the V SN . The retention time is defined as the duration for which the Δ V SN remains below 0.1 V after writing. Acknowledgments Funding: This work is supported by the National Key Research and Development Program of Ministry of Science and Technology (2024YFB3614200 to L.Lia.), the National Natural Science Foundation of China (62305110 to P.H., 62374054 to X.Zh., and 62474061 to X.L.), the Natural Science Foundation of Hunan Province, China (2023JJ40164 to L.Lia. and 2025JK2017 to X.L.), and the Ministry of Human Resources and Social Security of China (No. B25033 to L.Lia). Author contributions: S.Z., Z.X., and X.Zh. contributed equally to this work. P.H., L.Lia., and X.L. designed the research. S.Z., Z.X., Y.Zh., Y.Ze., and W.N. prepared and characterized the materials and related devices. L.T., X.Zo., S.L., and Q.L. participated in the experiments. G.Y., L.Li., X.Zo., C.Y., and Z.W. discussed the experiments and provided suggestions. S.Z., Z.X., X.Zh., X.L., L.Lia., and P.H. co-wrote the manuscript with inputs from all of the authors. All authors discussed the results and commented on the manuscript. Competing interests: The authors declare that they have no competing interests. Data, code, and materials availability: All data and code needed to evaluate and reproduce the results in the paper are present in the paper and/or the Supplementary Materials. This study did not generate new materials. Supplementary Materials This PDF file includes: Figs. S1 to S22 Table S1 References sciadv.aec3934_sm.pdf (2.8MB, pdf) REFERENCES 1. Salahuddin S., Ni K., Datta S., The era of hyper-scaling in electronics. Nat. Electronics 1, 442–450 (2018). [ Google Scholar ] 2. Cao W., Bu H., Vinet M., Cao M., Takagi S., Hwang S., Ghani T., Banerjee K., The future transistors. Nature 620, 501–515 (2023). [ DOI ] [ PubMed ] [ Google Scholar ] 3. Kato K., Shionoiri Y., Sekine Y., Furutani K., Hatano T., Aoki T., Sasaki M., Tomatsu H., Koyama J., Yamazaki S., Evaluation of off-state current characteristics of transistor using oxide semiconductor material, indium-gallium-zinc oxide. Jpn. J. Appl. Phys. 51, 021201 (2012). [ Google Scholar ] 4. Park J.-M., Lee S., Lee J., Kwon J.-Y., ITZO-based self-aligned top gate thin-film transistor with minimum parasitic capacitance for long-retention 2T0C DRAM. ACS Omega 10, 1006–1011 (2025). [ DOI ] [ PMC free article ] [ PubMed ] [ Google Scholar ] 5. Zhu S., Hu Q., Li Q., Yan S., Liu H., Liu R., Wu Y., First demonstration of deeply scaled 2T0C DRAM with record data retention and fast write speed. IEEE Electron Dev. Lett. 46, 405–408 (2025). [ Google Scholar ] 6. Bao Y., Yan G., Cao L., Niu C., Li Q., Sang G., Li L., Wei Y., Zhang X., Luo J., Yang Y., Xu G., Yin H., Partially isolated dual work function gate IGZO TFT with obviously reduced leakage current for 3D DRAMs. IEEE J. Electron Dev. Soc. 12, 637–644 (2024). [ Google Scholar ] 7. Wang Z., Zheng L., Lin Z., Zhao J., Tang W., Feng L., Liu Z., Li X., Guo X., Si M., CMOS logic and capacitorless DRAM by stacked oxide semiconductor and poly-Si Transistors for monolithic 3-D integration. IEEE Trans. Electron Dev. 71, 4664–4669 (2024). [ Google Scholar ] 8. Hirose T., Okamoto Y., Komura Y., Mizuguchi T., Saito T., Ito M., Kimura K., Inoue H., Onuki T., Ando Y., Sawai H., Murakawa T., Kunitake H., Kimura H., Matsuzaki T., Ikeda M., Yamazaki S., 1-Mbit 3-D DRAM using a monolithically stacked structure of a Si CMOS and heterogeneous IGZO FETs. IEEE J. Electron Dev. Soc. 12, 236–242 (2024). [ Google Scholar ] 9. Liang J., Yuan P., Yu Y., Xiang J., Zhu Z., Zhou M., Shao F., Lu Y., Dai J., Yi S., Wang G., Zhang J., Kang B., Zhao C., A design methodology for highly reliable operation for 2T0C dynamic random access memory application based on IGZO channel-all-around ferroelectric field-effect transistors. Jpn. J. Appl. Phys. 63, 06SP05 (2024). [ Google Scholar ] 10. Ryu S., Kang M., Cho K., Kim S., Capacitorless two-transistor dynamic random-access memory cells comprising amorphous indium–tin–gallium–zinc oxide thin-film transistors for the multiply–accumulate operation. Adv. Mater. Technol. 9, 2302209 (2024). [ Google Scholar ] 11. Yan S., Cong Z., Lu N., Yue J., Luo Q., Recent progress in InGaZnO FETs for high-density 2T0C DRAM applications. Sci. China Inf. Sci. 66, 200404 (2023). [ Google Scholar ] 12. F. F. Athena, E. Ambrosi, K. Jana, C. H. Wu, J. Hartanto, Y. M. Lee, C. C. Kuo, S. Liu, B. Saini, C. C. Wang, C. F. Hsu, G. Zeevi, X. Wang, J. Kang, E. Pop, T. Y. Lee, P. C. McIntyre, H. S. P. Wong, X. Y. Bao, First demonstration of an N-P oxide semiconductor complementary gain cell memory, in Proceeding of the 2024 IEEE International Electron Devices Meeting (IEDM) (IEEE, 2024), pp. 1–4. [ Google Scholar ] 13. M. Liu, Z. Li, W. Lu, K. Chen, J. Niu, F. Liao, Z. Wu, C. Lu, W. z. Li, D. Geng, N. Lu, C. Dou, G. Yang, L. Li, M. Liu, First demonstration of monolithic three-dimensional integration of ultra-high density hybrid IGZO/Si SRAM and IGZO 2T0C DRAM achieving record-low latency (< 10 ns), record-low energy (< 10 fJ) of data transfer and ultra-long data retention (> 5000 s), in Proceeding of the 2024 IEEE Symposium on VLSI Technology and Circuits (IEEE, 2024), pp. 1–2. [ Google Scholar ] 14. Gu C., Hu Q., Zhu S., Li Q., Zeng M., Kang J., Tong A., Wu Y., First experimental demonstration of 3D-stacked 2T0C DRAM cells based on indium tin oxide channel. IEEE Electron Dev. Lett. 45, 1764–1767 (2024). [ Google Scholar ] 15. Xiao K., Wan J., Xie H., Zhu Y., Tian T., Zhang W., Chen Y., Zhang J., Zhou L., Dai S., Xu Z., Bao W., Zhou P., High performance Si-MoS 2 heterogeneous embedded DRAM. Nat. Commun. 15, 9782 (2024). [ DOI ] [ PMC free article ] [ PubMed ] [ Google Scholar ] 16. Z. Zhao, J. Gomez, H. Ye, M. Imani, X. Yin, S. Deng, B. Melanson, J. Zhang, X. Gong, A. Abusleme, S. Datta, K. Ni, Computational associative memory based on monolithically integrated metal-oxide thin film transistors for update-frequent search applications, in Proceeding of the 2021 IEEE International Electron Devices Meeting (IEDM) (IEEE, 2021), pp. 37.6.1–37.6-4. [ Google Scholar ] 17. M. Oota, Y. Ando, K. Tsuda, T. Koshida, S. Oshita, A. Suzuki, K. Fukushima, S. Nagatsuka, T. Onuki, R. Hodo, T. Ikeda, S. Yamazaki, 3D-stacked CAAC-In-Ga-Zn oxide FETs with gate length of 72 nm, in Proceeding of the IEEE International Electron Devices Meeting (IEDM) (IEEE, 2019), pp. 3.2.1–3.2.4. [ Google Scholar ] 18. Hu Q., Gu C., Li Q., Zhu S., Liu S., Li Y., Zhang L., Huang R., Wu Y., True nonvolatile high-speed DRAM cells using tailored ultrathin IGZO. Adv. Mater. 35, e2210554 (2023). [ DOI ] [ PubMed ] [ Google Scholar ] 19. Jang J., Kim S., Park S., Kim S., Kim S., Cho S., Leaky 2T dynamic random-access memory devices based on nanometer-thick indium–gallium−zinc-oxide films for reservoir computing. ACS Appl. Nano Mater. 7, 22430–22435 (2024). [ Google Scholar ] 20. Xiong W., Luo B., Meng W., Wu X., Zhu B., Ding S.-J., Atomic-layer-deposited ultrathin InAlZnO FETs-based 2T0C DRAM cells with long data retention and multilevel storage. IEEE Trans. Electron Dev. 71, 2393–2398 (2024). [ Google Scholar ] 21. Yang L., Luo B., Chen X., Xiong W., Yang M., Meng W., Teng J., Zhu B., Ding S.-J., Wu X., Fluorine-treated top-gate InAlZnO TFT for 2T0C DRAM with long data retention at V hold = 0 V. IEEE Trans. Electron Dev. 72, 2305–2311 (2025). [ Google Scholar ] 22. Lin Z., Wang Z., Zhao J., Li X., Si M., A low-leakage zinc oxide transistor by atomic layer deposition. IEEE Electron Dev. Lett. 44, 536–539 (2023). [ Google Scholar ] 23. H. Ye, J. Gomez, W. Chakraborty, S. Spetalnick, S. Dutta, K. Ni, A. Raychowdhury, S. Datta, Double-gate W-doped amorphous indium oxide transistors for monolithic 3D capacitorless gain cell eDRAM, in Proceeding of the IEEE International Electron Devices Meeting (IEDM) (IEEE, 2020), pp. 28.3.1–28.3.4. [ Google Scholar ] 24. E. Sarkar, C. Zhang, D. Chakraborty, F. G. Waqar, S. Kirtania, K. A. Aabrar, H. Park, J. Shin, M. Tian, A. I. Khan, S. Yu, S. Datta, First demonstration of W-doped In2O3 gate-all-around (GAA) nanosheet FET with improved performance and record threshold voltage stability, in Proceeding of the 2024 IEEE International Electron Devices Meeting (IEDM) (IEEE, 2024), pp. 1–4. [ Google Scholar ] 25. Hu Q., Gu C., Zhu S., Li Q., Tong A., Kang J., Huang R., Wu Y., Capacitorless DRAM cells based on high-performance Indium-Tin-Oxide transistors with record data retention and reduced write latency. IEEE Electron Dev. Lett. 44, 60–63 (2023). [ Google Scholar ] 26. C. Chen, X. Duan, G. Yang, C. Lu, D. Geng, L. Li, M. Liu, Inter-layer dielectric engineering for monolithic stacking 4F 2 -2 T0C DRAM with channel-all-around (CAA) IGZO FET to achieve good reliability (> 10 4 s bias stress, > 10 12 cycles endurance), in Proceeding of the 2022 International Electron Devices Meeting (IEDM) (IEEE, 2022), pp. 26.5.1–26.5.4. [ Google Scholar ] 27. Duan X., Huang K., Feng J., Niu J., Qin H., Yin S., Jiao G., Leonelli D., Zhao X., Wang Z., Jing W., Wang Z., Wu Y., Xu J., Chen Q., Chuai X., Lu C., Wang W., Yang G., Geng D., Li L., Liu M., Novel vertical channel-all-around (CAA) In-Ga-Zn-O FET for 2T0C-DRAM with high density beyond 4F2 by monolithic stacking. IEEE Trans. Electron Dev. 69, 2196–2202 (2022). [ Google Scholar ] 28. W. Lu, Z. Zhu, K. Chen, M. Liu, B.-M. Kang, X. Duan, J. Niu, F. Liao, W. Dan, X.-S. Wu, J. Son, D.-Y. Xiao, G.-L. Wang, A. Yoo, K.-Y. Cao, D. Geng, N. Lu, G. Yang, C. Zhao, L. Li, M. Liu, First demonstration of dual-gate IGZO 2T0C DRAM with novel read operation, one bit line in single cell, I ON = 1500 μA/μm@V DS = 1 V and retention time > 300 s, in Proceeding of the 2022 International Electron Devices Meeting (IEDM) (IEEE, 2022), pp. 26.4.1–26.4.4. [ Google Scholar ] 29. Shiah Y.-S., Sim K., Shi Y., Abe K., Ueda S., Sasase M., Kim J., Hosono H., Mobility–stability trade-off in oxide thin-film transistors. Nat. Electron. 4, 800–807 (2021). [ Google Scholar ] 30. J. Zhang, Z. Zhang, H. Dou, Z. Lin, K. Xu, W. Yang, X. Zhang, H. Wang, P. D. Ye, Fluorine anion-doped ultra-thin InGaO transistors overcoming mobility-stability trade-off, in Proceeding of the 2023 International Electron Devices Meeting (IEDM) (IEEE, 2023), pp. 1–4. [ Google Scholar ] 31. Zhang X., Xu L., Liang R., Zong S., Li J., Zhu Z., Luo S., Song Z., Liu X., Improved environmental stability of InSnO thin-film transistor by interface engineering. IEEE Trans. Electron Dev. 71, 3015–3019 (2024). [ Google Scholar ] 32. Jiang Z., Wei J., Lv Y., Wei Y., Wang Y., Lu J., Liu H., Feng Z., Zhou H., Zhang J., Xu G., Long S., Luo X., Nonuniform mechanism for positive and negative bias stress instability in β-Ga 2 O 3 MOSFET. IEEE Trans. Electron Dev. 69, 5509–5515 (2022). [ Google Scholar ] 33. Wang Z., Shi Y., Zhang Z., Dong Y., Liu G., Shan F., Solution-processed oxide TFT based on bilayer channels with graded oxygen vacancy. IEEE Electron Dev. Lett. 44, 1636–1639 (2023). [ Google Scholar ] 34. Park J. H., Kim Y.-g., Yoon S., Hong S., Kim H. J., Simple method to enhance positive bias stress stability of In–Ga–Zn–O thin-film transistors using a vertically graded oxygen-vacancy active layer. ACS Appl. Mater. Interfaces 6, 21363–21368 (2014). [ DOI ] [ PubMed ] [ Google Scholar ] 35. Jeong H.-S., Cha H.-S., Hwang S.-H., Lee D.-H., Song S.-H., Kwon H.-I., Effects of oxygen content on operational characteristics and stability of high-mobility IGTO thin-film transistors during channel layer deposition. Coatings 11, 698 (2021). [ Google Scholar ] 36. Kruv A., Van Setten M. J., Dekkers H. F. W., Lorant C., Verreck D., Smets Q., Venkataramana B. Y., Belmonte A., Subhechha S., Chasin A. V., Delhougne R., Kar G. S., The impact of IGZO channel composition on DRAM transistor performance. IEEE Trans. Electron Dev. 70, 4674–4679 (2023). [ Google Scholar ] 37. Tien T.-C., Hsieh T.-E., Lee Y.-S., Wang Y.-H., Lee M.-L., Electrical and hysteresis characteristics of top-gate InGaZnO thin-film transistors with oxygen plasma treatment prior to TEOS oxide gate dielectrics. Coatings 12, 383 (2022). [ Google Scholar ] 38. Z. Lin, Z. Zhang, C. Niu, H. Dou, K. Xu, M. Islam, J. Y. Lin, C. Sung, M. Hong, D. Ha, H. Wang, M. A. Alam, P. D. Ye, Highly robust all-oxide transistors with ultrathin In 2 O 3 as channel and thick In 2 O 3 as metal gate towards vertical logic and memory, in Proceeding of the 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (IEEE, 2024), pp. 1–2. [ Google Scholar ] 39. J. Chiu, E. Sarkar, Y. Liu, Y. Chen, Y. Fan, C. W. Liu, First demonstration of a-IGZO GAA nanosheet FETs featuring achievable SS = 61mV/dec, I off < 10 −7 μA/μm, DIBL = 44 mV/V, positive VT, and process temp. of 300°C, in Proceeding of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (IEEE, 2023), pp. 1–2. [ Google Scholar ] 40. J. Zhang, Z. Zhang, Z. Lin, K. Xu, H. Dou, B. Yang, X. Zhang, H. Wang, P. D. Ye, First demonstration of BEOL-compatible atomic-layer-deposited InGaZnO TFTs with 1.5 nm channel thickness and 60 nm channel length achieving ON/OFF ratio exceeding 10 11 , SS of 68 mV/dec, normal-off operation and high positive gate bias stability, in Proceeding of the 2023 IEEE Symposium on VLSI Technology and Circuits (IEEE, 2023), pp.1–2. [ Google Scholar ] 41. Z. Zhang, Z. Lin, C. Niu, M. Si, M. A. Alam, P. D. Ye, Ultrahigh bias stability of ALD In 2 O 3 FETs enabled by high temperature O 2 annealin, in Proceeding of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (IEEE, 2023), pp. 1–2. [ Google Scholar ] 42. D. Zheng, A. Charnas, J. Lin, J. Anderson, D. Weinstein, P. D. Ye, Ultrathin atomic-layer-deposited In 2 O 3 radio-frequency transistors with record high f T of 36 GHz and BEOL compatibility, in Proceeding of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (IEEE, 2023), pp. 1–2. [ Google Scholar ] 43. S. Liu, K. Jana, K. Toprasertpong, J. Chen, Z. Liang, Q. Jiang, S. Wahid, S. Qin, W.-C. Chen, H. S. P. Wong, Gain cell memory on logic platform device guidelines for oxide semiconductor transistor materials development, in Proceeding of the 2023 IEEE International Electron Devices Meeting (IEDM) (IEEE, 2023), pp. 1–4. [ Google Scholar ] 44. Q. Lin, N. Safron, D. Zhong, G. Arutchelvan, C. Gilardi, C. Yoo, J. Hartanto, B. Saini, S.-C. Lai, G. Pitner, G. Chen, M. M. F. Chang, Y.-M. Lin, W. Tsai, P. C. McIntyre, I. P. Radu, Enhancement-mode atomic layer deposited W-doped In 2 O 3 transistor at 55 nm channel length by oxide capping layer with improved stability, in Proceeding of the 2024 IEEE International Electron Devices Meeting (IEDM) (IEEE, 2024), pp. 1–4. [ Google Scholar ] 45. B. Tang, Z. Fang, R. Wan, S. Hooda, J. F. Leong, Q. Wan, C.-K. Chen, E. Zamburg, J.-s. Kim, A. V. Y. Thean, 1T1R and 2T0C1R IGZO-MoS 2 all-BEOL 3D memory cells, in Proceeding of the 2024 IEEE International Electron Devices Meeting (IEDM) (IEEE, 2024), pp. 1–4. [ Google Scholar ] 46. J.-Y. Lin, C. Niu, Z. Lin, T. Kim, B. Park, H. Jang, C. Jeong, P. D. Ye, Quantum confinement controlled positive to negative schottky barrier conversion in ultrathin In 2 O 3 transistor contacts, in Proceeding of the 2024 IEEE International Electron Devices Meeting (IEDM) (IEEE, 2024), pp. 1–4. [ Google Scholar ] 47. J. Y. Lin, Z. Zhang, S. Alajlouni, P. Y. Liao, Z. Lin, C. Niu, A. Shakouri, P. D. Ye, First determination of thermal resistance and thermal capacitance of atomic-layer-deposited In 2 O 3 transistors, in Proceeding of the 2023 IEEE International Electron Devices Meeting (IEDM) (IEEE, 2023), pp. 1–4. [ Google Scholar ] 48. Y. Wu, Y. Liu, H. Sung, R. Ma, J. Gracia, H. Fujiwara, K. Lu, C. W. Liu, First demonstration of 2-floor GAA In 2 O 3 nanosheet FET enabled by TiN sacrificial layers and fluorine passivation, in Proceeding of the 2025 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (IEEE, 2025), pp.1–2. [ Google Scholar ] 49. J. Wang, Z. Bai, K. Zhang, Z. Wu, D. Geng, Y. Xu, N. You, Y. Li, G. Yang, L. Li, S. Wang, M. Liu, Ge-doped In 2 O 3 : First demonstration of utlizing Ge as oxygen vacancy consumer to break the mobility/reliability tradeoff for high performance oxide TFTs, in Proceeding of the 2024 IEEE Symposium on VLSI Technology and Circuits (IEEE, 2024), pp. 1–2. [ Google Scholar ] 50. Q. Li, W. Zhao, Q. Hu, C. Gu, S. Zhu, H. Liu, R. Huang, Y. Wu, First demonstration of sequential integration for stacked gate-all-around a-IGZO nanosheet transistors with record I d = 2.05 mA/μm, g m = 1.13 mS/μm and ultralow SS = 66 mV/dec, in Proceeding of the 2023 IEEE International Electron Devices Meeting (IEDM) (IEEE, 2023), pp.1–4. [ Google Scholar ] 51. W. Zhao, W. Cui, L. Kang, S. Lu, W. Yuan, H. Wang, S. Zhan, Y. Wang, Y. Yin, K. Kaneko, L. Xing, X. Sang, Y. Shao, Z. Lin, H. Shen, X. Cui, Y. Wu, J. Xu, High-performance vertical gate-all-around oxide semiconductor transistors with 6 nm ALD IGZO channel and scaled contact CD down to 28 nm, in Proceeding of the 2024 IEEE International Electron Devices Meeting (IEDM) (IEEE, 2024), pp.1–4 . [ Google Scholar ] 52. S. Miyata, K. Furutani, Y. Komura, Y. Ando, S. Saito, T. Hirose, F. Isaka, H. Miyairi, H. Komagata, H. Katagiri, T. Matsuzaki, T. Onuki, S. Yamazaki, Vertical-channel crystalline In 2 O 3 FET with a pulled-up gate, monolithically stacked on Si CMOS, achieving 112.2 μA/μm on-state current, in Proceeding of the 2024 IEEE International Electron Devices Meeting (IEDM) (IEEE, 2024), pp. 1–4. [ Google Scholar ] 53. W. Zhao, S. Zhu, Q. Li, Q. Hu, H. Liu, A. Tong, M. Zeng, R. Huang, Y. Wu, First demonstration of double-gate IGZO transistors with ideal subthreshold swing of 60 mV/dec at room temperature and 76 mV/dec at 380 K over 5 decades and g m exceeding 1 mS/μm with contact length scaling, in Proceeding of the 2024 IEEE International Electron Devices Meeting (IEDM) (IEEE, 2024), pp. 1–4. [ Google Scholar ] 54. Y. Shao, J. C. C. Huang, E. R. Borujeny, T. E. Espedal, D. A. Antoniadis, J. A. Del Alamo, Highly-scaled BEOL e-mode transistor and discrete-domain ferroelectric memory platform enabled by PEALD In 2 O 3 , in Proceeding of the 2024 IEEE International Electron Devices Meeting (IEDM) (IEEE, 2024), pp. 1–4. [ Google Scholar ] 55. G. Yan, Y. Luo, J. Wang, Z. Song, C. Niu, S. Yang, G. Tian, J. Yao, X. Ma, Q. Zhang, J. Xiang, N. Zhou, G. Wang, G. Xu, Z. Wu, J. Bi, C. Zhao, J. Luo, H. Yin, First demonstration of true 4-bit memory with record high multibit retention > 10 3 s and read window > 10 5 by hydrogen self-adaptive-doping for IGZO DRAM arrays, in Proceeding of the 2023 IEEE International Electron Devices Meeting (IEDM) (IEEE, 2023), pp. 1–4. [ Google Scholar ] 56. Lin J., Ji H., Swift M. W., Hardy W. J., Peng Z., Fan X., Nevidomskyy A. H., Tour J. M., Natelson D., Hydrogen diffusion and stabilization in single-crystal VO 2 micro/nanobeams by direct atomic hydrogenation. Nano Lett. 14, 5445–5451 (2014). [ DOI ] [ PubMed ] [ Google Scholar ] 57. Hu X., Li Z., Feng T., Meng J., Li Q., Zhu H., Sun Q., Zhang D. W., Chen L., Flexible organic field-effect transistor (OFET) based 2T0C DRAM cells with 2-Bit operation and extended retention. Adv. Sci. 12, e2500300 (2025). [ DOI ] [ PMC free article ] [ PubMed ] [ Google Scholar ] 58. Chen K., Lu W., Niu J., Liu M., Liao F., Zhang X., Li Z., Mao N., Zhang K., Lu C., Kang B.-M., Wang J., Geng D., Lu N., Wang G., Zhu Z., Yang G., Zhao C., Nathan A., Li L., Liu M., IGZO 2T0C DRAM with V TH compensation technique for multi-bit applications. IEEE J. Electron Dev. Soc. 13, 439–443 (2025). [ Google Scholar ] 59. Ko S. H., Yoon S. M., Interface-engineered HfO 2 /Al 2 O 3 nanolaminate gate insulators for InGaZnO thin-film transistors and 2T0C DRAM applications. ACS Appl. Electron. Mater.‌ 7, 8100–8107 (2025). [ Google Scholar ] 60. Lee Y., Lee S. Y., Choi J., Ghenzi N., Han J. K., Hwang C. S., Heterogeneous capacitor-less two-transistor dynamic random access memory cell with long retention time and high sensing current supporting 5-bit multilevel operation. Phys. Status Solidi RRL 19, 2500131 (2025). [ Google Scholar ] Associated Data This section collects any data citations, data availability statements, or supplementary materials included in this article. Supplementary Materials Figs. S1 to S22 Table S1 References sciadv.aec3934_sm.pdf (2.8MB, pdf) Data Availability Statement All data and code needed to evaluate and reproduce the results in the paper are present in the paper and/or the Supplementary Materials. This study did not generate new materials. Articles from Science Advances are provided here courtesy of American Association for the Advancement of Science ACTIONS View on publisher site PDF (1.5 MB) Cite Collections Permalink RESOURCES Similar articles Cited by other articles Links to NCBI Databases Follow NCBI NCBI on X (formerly known as Twitter) NCBI on Facebook NCBI on LinkedIn NCBI on GitHub NCBI RSS feed Connect with NLM NLM on X (formerly known as Twitter) NLM on Facebook NLM on YouTube National Library of Medicine 8600 Rockville Pike Bethesda, MD 20894 Web Policies FOIA HHS Vulnerability Disclosure Help Accessibility Careers NLM NIH HHS USA.gov Back to Top

Related documents

• Tunable Enhancement of Magnetization Dynamics by Crystal Cut at Interface Exchange Coupled $α$-Fe$_2$O$_3$/NiFe Heterostructures#141683
• Ising superconductivity in noncentrosymmetric bulk NbSe2#124585
• Radiation shielding performance of PbO–B_2O_3–SiO_2 glass–ceramics: insights from molecular dynamics, theoretical analyses, and Monte Carlo simulations#150700
• Design of altermagnetism in oxide superlattices exploiting interface effects and quantum confinement#616904
• Design of altermagnetism in oxide superlattices exploiting interface effects and quantum confinement#616404