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Learn more: PMC Disclaimer | PMC Copyright Notice ACS Nano . 2026 Mar 31;20(14):10905–10918. doi: 10.1021/acsnano.5c16255 Search in PMC Search in PubMed View in NLM Catalog Add to search Sub‑2 nm Equivalent-Oxide-Thickness Ferroelectric Transistors for Cryogenic Memory and Computing Apu Das Apu Das † College of Semiconductor Research (CoSR), National Tsing Hua University (NTHU), Hsinchu 300044, Taiwan Find articles by Apu Das † , Asim Senapati Asim Senapati † College of Semiconductor Research (CoSR), National Tsing Hua University (NTHU), Hsinchu 300044, Taiwan Find articles by Asim Senapati † , Gautham Kumar Gautham Kumar † College of Semiconductor Research (CoSR), National Tsing Hua University (NTHU), Hsinchu 300044, Taiwan Find articles by Gautham Kumar † , Zhao-Feng Lou Zhao-Feng Lou ‡ Graduate Institute of Electronics Engineering (GIEE), National Taiwan University (NTU), Taipei 106319, Taiwan Find articles by Zhao-Feng Lou ‡ , Jonas Müller Jonas Müller § Laboratory for Analysis and Architecture of Systems (LAAS-CNRS), Université de Toulouse, 31031 Toulouse, France Find articles by Jonas Müller § , Jaskirat Singh Maskeen Jaskirat Singh Maskeen ∥ Department of Computer Science and Engineering, Indian Institute of Technology Gandhinagar, Palaj, Gujarat 382055, India Find articles by Jaskirat Singh Maskeen ∥ , Yii-Tay Chang Yii-Tay Chang ‡ Graduate Institute of Electronics Engineering (GIEE), National Taiwan University (NTU), Taipei 106319, Taiwan Find articles by Yii-Tay Chang ‡ , Mohit Tewari Mohit Tewari ⊥ Department of Electrical Engineering, Indian Institute of Technology Gandhinagar, Palaj, Gujarat 382055, India Find articles by Mohit Tewari ⊥ , Ankit Agarwal Ankit Agarwal # Department of Electrical Engineering, National Cheng Kung University (NCKU), Tainan 70101, Taiwan Find articles by Ankit Agarwal # , Agniva Paul Agniva Paul † College of Semiconductor Research (CoSR), National Tsing Hua University (NTHU), Hsinchu 300044, Taiwan Find articles by Agniva Paul † , Yannick Raffel Yannick Raffel ∇ Fraunhofer Institute for Photonic Microsystems IPMSCenter Nanoelectronic Technologies, 01109 Dresden, Germany Find articles by Yannick Raffel ∇ , Siddheswar Maikap Siddheswar Maikap ○ Department of Electronic Engineering, Chang Gung University (CGU), Taoyuan 333323, Taiwan Find articles by Siddheswar Maikap ○ , Kuo-Hsing Kao Kuo-Hsing Kao # Department of Electrical Engineering, National Cheng Kung University (NCKU), Tainan 70101, Taiwan Find articles by Kuo-Hsing Kao # , Tarun Agarwal Tarun Agarwal ⊥ Department of Electrical Engineering, Indian Institute of Technology Gandhinagar, Palaj, Gujarat 382055, India Find articles by Tarun Agarwal ⊥ , Sandip Lashkare Sandip Lashkare ⊥ Department of Electrical Engineering, Indian Institute of Technology Gandhinagar, Palaj, Gujarat 382055, India Find articles by Sandip Lashkare ⊥ , Darsen Lu Darsen Lu # Department of Electrical Engineering, National Cheng Kung University (NCKU), Tainan 70101, Taiwan Find articles by Darsen Lu #, * , Guilhem Larrieu Guilhem Larrieu § Laboratory for Analysis and Architecture of Systems (LAAS-CNRS), Université de Toulouse, 31031 Toulouse, France Find articles by Guilhem Larrieu §, * , Min-Hung Lee Min-Hung Lee ‡ Graduate Institute of Electronics Engineering (GIEE), National Taiwan University (NTU), Taipei 106319, Taiwan Find articles by Min-Hung Lee ‡, * , Sourav De Sourav De † College of Semiconductor Research (CoSR), National Tsing Hua University (NTHU), Hsinchu 300044, Taiwan Find articles by Sourav De †, * Author information Article notes Copyright and License information † College of Semiconductor Research (CoSR), National Tsing Hua University (NTHU), Hsinchu 300044, Taiwan ‡ Graduate Institute of Electronics Engineering (GIEE), National Taiwan University (NTU), Taipei 106319, Taiwan § Laboratory for Analysis and Architecture of Systems (LAAS-CNRS), Université de Toulouse, 31031 Toulouse, France ∥ Department of Computer Science and Engineering, Indian Institute of Technology Gandhinagar, Palaj, Gujarat 382055, India ⊥ Department of Electrical Engineering, Indian Institute of Technology Gandhinagar, Palaj, Gujarat 382055, India # Department of Electrical Engineering, National Cheng Kung University (NCKU), Tainan 70101, Taiwan ∇ Fraunhofer Institute for Photonic Microsystems IPMSCenter Nanoelectronic Technologies, 01109 Dresden, Germany ○ Department of Electronic Engineering, Chang Gung University (CGU), Taoyuan 333323, Taiwan * E-mail: [email protected] . * E-mail: [email protected] . * E-mail: [email protected] . * E-mail: [email protected] . Received 2025 Sep 20; Accepted 2026 Mar 17; Revised 2026 Mar 14; Collection date 2026 Apr 14. © 2026 The Authors. Published by American Chemical Society This article is licensed under CC-BY 4.0 PMC Copyright notice PMCID: PMC13085857 PMID: 41914654 Abstract Ferroelectric hafnia-based field-effect transistors are promising candidates for nonvolatile memory and in-memory computing. However, their operation principle under deep-cryogenic conditions at aggressively scaled gate stacks remains underexplored, especially for bulk silicon technology. This work presents an experimental demonstration of front-end-of-line bulk silicon-channel ferroelectric field-effect transistors featuring sub-2 nm equivalent-oxide-thickness gate stacks with ≃5 nm hafnium–zirconium oxide, exhibiting robust switching at 10 K. Key metrics include memory windows exceeding 1 V, tightly distributed threshold voltages (standard deviation ≲ 40 mV), endurance surpassing 10 7 cycles, and retention projections consistent with decade-scale stability. Correlative four-dimensional scanning transmission electron microscopy phase mapping reveals an increased orthorhombic ferroelectric fraction following electrical wake-up at cryogenic temperatures, correlated with enhanced polarization stability and strengthened oxygen–metal coordination. We hypothesize that suppressed trapping-related instability, along with a higher orthorhombic phase, jointly contribute to this effect. Current–voltage sweeps define an operational design window, with memory-window saturation beyond ±5 V programming voltages and ≳900 ns pulse widths, consistent with nucleation-limited reversal kinetics in ultrathin films. A spiking neural network implemented at 10 K achieves >92% classification accuracy on MNIST and 73.8% accuracy on NMNIST data sets, demonstrating practical utility. These findings provide materials- and device-level insights into scaled hafnia FeFETs for energy-efficient cryogenic applications, including potential integration in quantum–classical systems. Keywords: FeFETs, HZO, cryogenic electronics, nonvolatile memory, neuromorphic computing, 4D-STEM, XPS Nonvolatile ferroelectric field-effect transistors (FeFETs) based on hafnia have re-emerged as promising contenders for embedded nonvolatile memory and in-memory computing. Their appeal lies in the unique combination of CMOS compatibility, voltage-driven programming, and low-energy readout, all realized in a simple one-transistor cell. − Despite rapid progress at room temperature (RT), two frontiers remain insufficiently resolved for system integration at advanced nodes and in extreme environments. The first is gate-stack scaling toward sub-2 nm effective-oxide thickness (EOT), where depolarization, interfacial dipoles, and leakage through the interfacial oxide (IL) can undermine retention and variability. The second is deep-cryogenic operation ( T ≲ 10–77 K), increasingly relevant for cryo-CMOS controllers of quantum processors, superconducting logic, and low-noise sensing pipelines. Achieving robust, reproducible ferroelectric switching under both constraints is essential if FeFETs are to provide dense cryogenic memory and synaptic primitives in the quantum–classical stack. ,,− FeFET is particularly attractive at advanced nodes because its noncentrosymmetric orthorhombic phase (Pca2 1 ) persists in nanometric films and can be stabilized through stress, grain-size engineering, oxygen-vacancy control, and electrode work-function tuning. ,,,− ,− Yet pushing the gate stack to sub-2 nm EOT magnifies the influence of the IL and depolarization field, increases sensitivity to charge-trapping, and fixed-charge fluctuations. − Although prior studies at low temperature report steeper subthreshold slopes and improved carrier mobility in Si-FeFETs, and highly stable endurance and retention in amorphous metal-oxide channel-based FeFETs. , A mechanistic connection linking cryogenic switching, wake-up, polarization kinetics in ultrathin HZO, and device reliability remains incomplete and requires further investigation. ,,,,,− Here we address this gap by engineering FeFETs that combine sub-2 nm EOT stacks with ∼5 nm HZO and mapping their electrical and physical behavior down to 10 K. Cross-sectional transmission electron microscopy (TEM) confirms the TaN/HZO/SiO 2 /p-Si stack geometry and thickness control, while four-dimensional scanning TEM (4D-STEM) with automated crystallography mapping (ACOM) resolves the monoclinic/orthorhombic distribution. These measurements reveal a cryogenic electrical “wake-up” that increases the orthorhombic fraction, correlating with enhanced polarization stability and narrower device-to-device threshold-voltage ( V th ) distributions at 10 K. The 4D-STEM data indicate a higher fraction of the ferroelectric phase following wake-up at cryogenic temperature (10 K). We hypothesize that this enhancement originates from a reduction in internal bias due to suppressed trapping-related instability at low temperature; however, a more detailed investigation is required to validate this mechanism conclusively. The increased ferroelectric phase fraction consequently amplifies the polarization-induced surface-potential shift at the HZO/SiO 2 interface, thereby improving MW stability without inducing excess leakage through the interfacial layer. Under program/erase (PG–ER) pulses of ±5 V and t pw = 500 ns, devices exhibit MW > 1 V at 10 K with tight V th statistics. Increasing the programming amplitude V P or pulse width t pw expands the MW but saturates beyond V P ≳ 5 V and t pw ≳ 900 ns, consistent with nucleation-limited reversal and domain-wall creep kinetics in the ultrathin ferroelectrics in the cryogenic regime. Band-diagram analysis with a common Fermi level across TaN/HZO/SiO 2 /p-Si clarifies the mechanism: polarization charge (±σ p ) at the HZO/SiO 2 interface introduces an additional drop Δϕ ≈ σ p t HZO /(ε 0 ε HZO ) that modulates the Si surface potential. Retention projections exceed a decade at 10 K, and endurance surpasses 10 7 cycles within the same PG–ER scheme. Prior cryogenic FeFET demonstrations, such as the back-end-of-line-compatible oxide-channel device reported in ref , have achieved remarkable endurance exceeding 10 10 cycles with no observable degradation and highly stable retention at 77 and 5 K. This outstanding performance underscores the potential of cryogenic operation to suppress thermally activated defect generation and interface trapping, enabling effective ”unlimited” cycling endurance in ferroelectric memories suitable for last-level cache applications in high-performance computing systems. Beyond device-level metrics, it is equally important to understand the atomistic origins of the stability of FeFETs with ultrathin EOT at low temperature. Our complementary density functional theory-molecular dynamics (DFT–MD) analysis of the SiO 2 /HZO interface demonstrates that cooling from 300 to 10 K reduces interface trap states and strengthens polarization coupling across the interfacial layer simultaneously. This microscopic suppression of traps provides a clear rationale for the experimentally observed tightening of V th distributions and the improved separation of high-threshold-voltage (HVT)/low-threshold-voltage (LVT) states at cryogenic temperature (10 K). By explicitly linking trap energetics, band alignment, and polarization screening to macroscopic MW retention, the atomistic study furnishes a materials-level foundation for the design rules we establish in this work. Finally, we evaluate system-level relevance through a device-aware neuromorphic demonstration at 10 K. FeFET synaptic weights are encoded by programmable V th states and read at low V DS . A spiking neural network (SNN) trained and inferred on Modified National Institute of Standards and Technology (MNIST) and Neuromorphic Modified National Institute of Standards and Technology (N-MNIST) data sets, parametrized by measured cryogenic switching curves and state distributions, achieves >92% and 73.8% test accuracy, respectively, while adhering to endurance cycling limits. In summary, we have demonstrated FeFETs with sub-2 nm EOT that operate reliably at 10 K. These devices exhibit robust switching, achieving memory windows exceeding 1 V with V th variations below 40 mV across devices and cycles. They sustain endurance of 10 7 cycles under moderate program–erase stress and show retention characteristics that enable reliable decade-long projections, supported by stable V th evolution over 10 4 s measurements at 10 K. Furthermore, 4D-STEM reveals an increased fraction of the orthorhombic ferroelectric phase, and we successfully demonstrate SNN inference at 10 K with accuracy better than room-temperature benchmarks. Collectively, these findings establish clear materials and operational guidelinesincluding ultrathin HZO layers, sub-2 nm EOT gate stacks, and optimized program–erase schemes,for integrating hafnium-based FeFET macros and neuromorphic elements into cryo-CMOS, quantum–classical interfaces, and other extreme-environment applications. Results Structural Analysis To identify the microscopic origin of the improved ferroelectric (FE) behavior at low temperature, we combined cross-sectional transmission electron microscopy (TEM), four-dimensional scanning transmission electron microscopy (4D-STEM) with automated crystal-orientation mapping (ACOM), X-ray diffraction ( Figure S1 ) and X-ray photoelectron spectroscopy, XPS, ( Figure ) on the ultrathin (∼5 nm) HZO layers used in our FeFETs. Conventional TEM verifies the structural integrity of the gate stack and the thickness control of the FE film, yielding 5.3 nm across FeFETs ( Figure a). No voids, delamination, or interfacial roughening are observed at the TaN/HZO and HZO/SiO 2 boundaries, ruling out obvious morphological causes for the temperature trends discussed below. Phase identification and quantification were performed by 4D-STEM ACOM ( Figure c,d). In this approach, a nanobeam diffraction pattern is recorded at each scan pixel and indexed against crystallographic libraries to assign a local phase with a confidence metric; pixels with low confidence (diffuse patterns, grain boundaries) are masked to avoid bias. The maps unambiguously resolve the monoclinic ( m , P 2 1 / c ) and polar orthorhombic ( o , Pca 2 1 ) regions in the ultrathin HZO, consistent with prior observations that solid-solution hafnia–zirconia near 1:1 composition stabilizes multiple polymorphs under the combined influence of interfacial fields and strain. Importantly, correlative measurements before and after electrical wake-up at 10 K show a systematic increase in the orthorhombic fraction: the area fraction assigned to the o -phase rises from 21.4% at 300 K to 34.9% after low-temperature wake-up ( Figure S2 ). Because the acquisition and indexing parameters are kept identical across temperatures, this change reflects a genuine redistribution of phase content rather than an analysis artifact. 2. Open in a new tab Temperature- and cycling-dependent O 1s chemistry in ultrathin HZO. (a–b) Post–wake-up high-resolution O 1s XPS spectra at 300 and 10 K, each fit with identical components: lattice oxygen (M–O), defect/oxygen-vacancy–related oxygen ( V O /suboxide), and adsorbates. (c) Quantified oxygen state fractions extracted from XPS peak fitting, showing increased lattice oxygen and reduced defect oxygen at 10 K, consistent with enhanced metal–oxygen coordination and cryogenic stabilization of the ferroelectric phase. 1. Open in a new tab Device stack, process flow, and structural analysis of ultrathin-HZO FeFETs. (a) Fabrication overview and gate-stack (TaN/HZO/SiO 2 /Si). The flow comprises field-oxide patterning, interfacial SiO 2 formation, atomic-layer deposition (ALD) of Hf 0.5 Zr 0.5 O 2 (HZO), TaN gate deposition and anisotropic etch, source/drain implantation and activation, and backend metallization. The ultrathin HZO is placed directly above the interfacial SiO 2 to minimize depolarization and maintain sub-2 nm (1.68 nm) EOT while preserving ferroelectric switching. (b) Cross-sectional TEM confirming uniform layer formation and precise thickness control in representative capacitors/FeFETs: HZO thickness t HZO = 5.3 nm and interfacial SiO 2 thickness t IL = 0.85 nm (values from local metrology), evidencing a clean, abrupt TaN/HZO/SiO 2 /Si stack without observable intermixing. (c) 4D-STEM with automated crystal-orientation mapping (ACOM) performed on the 5 nm HZO film. Phase-resolved indexing delineates monoclinic ( m , P 2 1 / c ) and ferroelectric orthorhombic ( o , Pca 2 1 ) regions at nanometric resolution; high phase-confidence segmentation confirms robust crystallographic discrimination within the scaled film. (d) Temperature- and stimulus-dependent phase-fraction comparison across three states: room temperature (RT, 300 K), cryogenic operation at 10 K following electrical “wake-up” (initial cycling that mobilizes pinned domains/defects), and the pristine state prior to wake-up. Quantitative mapping shows the o -phase fraction increasing from 21.4% at RT to 34.9% at 10 K postwake-up, indicating cryo-assisted stabilization of the polar phase. Although the 4D-STEM analysis probes a localized region of the film, its role in this work is to establish the presence, stability, and spatial continuity of the orthorhombic ferroelectric phase after cryogenic wake-up, rather than to claim enhanced intrinsic ferroelectric switching. Although the 4D-STEM analysis probes a localized region of the film, its role here is to establish the presence and spatial continuity of the orthorhombic ferroelectric phase after cryogenic wake-up, rather than to claim enhanced intrinsic switching strength. Complementary global electrical measurements (PUND, switching-current, and cryogenic C – V , discussed later) confirm that ferroelectric switching remains active across the full device area at 10 K; however, these data also show that intrinsic polarization and switching strength are not increased at cryogenic temperatures (10 K) within the same voltage range. We attribute the cryogenic increase in o -phase to field-assisted stabilization of pre-existing polar domains and/or transformation of marginal m -phase grains under reduced defect kinetics. At room temperature, oxygen vacancies (V O ) and other mobile point defects can screen the polarization and promote relaxation toward the centrosymmetric m -phase during cycling. Cooling to 10 K suppresses defect migration and detrapping, strengthening the local impact of applied electric field during wake-up to align dipoles and lower the free energy of polar variants relative to the m -phase without being counteracted by rapid defect reconfiguration. The ultrathin geometry further amplifies interfacial field and elastic boundary conditions that are known to favor Pca 2 1 in hafnia-based ferroelectrics. − , Independent chemical evidence from XPS supports this interpretation ( Figure a,b). High-resolution O 1s spectra, consistently deconvoluted into lattice oxygen (∼530.0 eV), vacancy/suboxide–related oxygen (∼531–532 eV), and adsorbates at higher binding energies, reveal a clear temperature-dependent redistribution of spectral weight. As the temperature decreases from 300 to 10 K, the lattice-oxygen component progressively intensifies while the defect-related contribution diminishes. This trend reflects strengthened metal–oxygen coordination and suppressed oxygen-vacancy activity under cryogenic conditions. Quantitative analysis of the fitted peak areas is summarized in Figure c. The lattice oxygen fraction increases from 57.4% at 300 K to 68.9% at 10 K, while the defect-related oxygen fraction decreases from 27.5% to 14.0%. These values were obtained by integrating the spectral intensity within defined binding-energy windows (529.5–530.5 eV for lattice oxygen, 531–532 eV for defect oxygen) and normalizing to the total O 1s envelope (528–533 eV). The observed redistribution supports the hypothesis that cryogenic wake-up stabilizes the polar orthorhombic phase by reducing suboxide formation and enhancing lattice ordering. Taken together, the structural (4D-STEM) and chemical (XPS) data establish a coherent understanding of the physical mechanism for the device-level improvements measured at 10 K. The larger o -phase fraction provides a bigger reservoir of switchable polarization, directly translating to a wider and more stable MW in the FeFET transfer characteristics. Suppressed defect mobility at cryogenic temperature (10 K) reduces both internal screening and back-switching, improving the V th distributions and slowing time-dependent drift. In summary, nanoscale phase mapping reveals that electrical wake-up at cryogenic temperature (10 K) increases the polar orthorhombic fraction from 21.4% (300 K) to 34.9% (10 K) in ∼5 nm HZO, while XPS indicates strengthening of metal–oxygen bonding and a reduction in defect-related oxygen signatures. These complementary observations provide direct, materials-level insights on the physical mechanism behind improved ferroelectric Pca 2 1 polymorph and suppresses defect activity at 10 K, thereby explaining the enhanced switching robustness, larger nonvolatile window, and improved state stability observed in our low-temperature FeFETs. Polarization Response of Ferroelectric Gate-Stack at 300 K and 10 K To directly probe the switching dynamics of the ferroelectric gate stack, we performed positive-up-negativ-down (PUND)-based electrical measurements at 300 and 10 K ( Figure ). The gate waveform and current response ( Figure a) enable extraction of the net switching current by subtracting nonswitching contributions: ( I P – I U ) for positive and ( I N – I D ) for negative polarization reversal. The corresponding switching polarization P SW is obtained via time-domain integration normalized to the device area. Temperature-dependent switching current density J SW ( Figure b) reveals a significant reduction in peak values at 10 K, consistent with suppressed domain-wall mobility, slower polarization kinetics ( J SW ∝ d P /d t ), and the freezing out of defect-assisted conduction pathways. The extracted polarization loops ( Figure c) show diminished remanence and narrowed hysteresis at 10 K, indicating incomplete domain reversal and stronger pinning. Additionally, the gate capacitance C G versus V G ( Figure d) exhibits reduced hysteresis and enhanced imprint at low temperature, further supporting the need for elevated operating fields to achieve full switching under cryogenic conditions. 3. Open in a new tab PUND-based electrical characterization of ferroelectric gate stack in FeFET. Gate voltage waveform applied to the ferroelectric gate stack with all terminals grounded, illustrating the extraction of switching currents. The total switching current is obtained as the time-series sum of ( I P – I U ) for positive-direction switching and ( I N – I D ) for negative-direction switching. The corresponding switching polarization is calculated as P N = 1 A ∫ t 1 t 2 I SW ( t ) d t , where A is the device area (b) temperature-dependent switching current density ( J SW ) versus gate voltage at 300 and 10 K. The reduced peak currents at cryogenic temperatures arise from suppressed domain-wall mobility, slower polarization kinetics ( I ∝ d P /d t ), and the freezing out of defect-assisted conduction pathways that contribute at room temperature. (c) Extracted switching polarization ( P SW ) from the negative loop, showing diminished remanence and narrowing of the hysteresis at 10 K. This reduction reflects incomplete domain reversal due to stronger pinning, alongside an increased coercive field requirement at low temperature, meaning higher voltages are needed to fully switch polarization. (d) Gate capacitance ( C G ) versus gate voltage under forward and reverse sweeps at 1 kHz, revealing dielectric nonlinearity and ferroelectric imprint. The narrowing of the capacitance hysteresis at 10 K supports the need for higher operating field under cryogenic conditions. PG/ER Operations of FeFETs at 300 K and 10 K We first assess the switching and memory behavior of the fabricated FeFETs at 300 K and 10 K ( Figure ). Transfer characteristics I D – V G measured by slowly varying V G from −0.5 to 2 V at V DS = 0.1 V after PG/ER operation, show a monotonic threshold shift as the program-pulse amplitude is increased from V P = 2 to 6 V (rectangular pulses, t pw = 500 ns). The extracted V th (constant-current criterion of 10 μA) moves from ∼0.1 V (LVT, 6 V) to ∼0.9 V (HVT, −6 V), yielding a MW of Δ V th = V th,HVT – V th,LVT approaching ∼0.8 V ( Figure a). The smooth evolution of V th with V P indicates reproducible polarization reversal in the ∼5 nm HZO film under room-temperature conditions. Programming-speed sweeps at fixed V P = 5 V identify a minimum effective pulse duration of t pw,min ≈ 900 ns for stable nonvolatile switching ( Figure b). For t pw < 900 ns the resulting Δ V th diminishes rapidly, consistent with nucleation-limited dynamics in ultrathin hafnia wherein incomplete domain growth and back-switching dominate when the field is not applied long enough to overcome interfacial depolarization and defect pinning. 4. Open in a new tab PG/ER Operation of FeFETs with ∼5 nm HZO at 300 K and 10 K. (a) Transfer characteristics I D ( V G ) following programming with gate-voltage amplitude V P = 2–6 V in steps of Δ V P = 0.25 V (rectangular pulses, t pw = 500 ns), showing a monotonic threshold-voltage modulation Δ V th consistent with ferroelectric polarization switching. (b) Programming-speed study at V P = 5 V: the minimum pulse width producing a stable, nonvolatile shift is t pw,min ≈ 900 ns, extracted from sweeps with t pw = 0.1–1.6 μs in steps of Δ t pw = 0.1 μs. (c) I D – V G characteristics after a program/erase (PG–ER) cycle with t pw = 500 ns rectangular pulses. Curves illustrate nonvolatile, polarization-controlled modulation of channel conductance; the memory window (MW), defined as Δ V th = V th,HVT – V th,LVT , exceeds 1 V under low read bias. Threshold voltages are extracted by a constant-current criterion ( Methods section). (d) Distributions of V th across n = 8 devices for both states at 10 K show a narrow spread and a clear separation, indicating low device-to-device variability of the polarization-set surface potential. (e) Programming-amplitude sweep: increasing the gate-pulse amplitude V P enlarges Δ V th until a saturation regime beyond ∼5 V, where additional field does not produce a proportionate gain, consistent with near-complete fer-roelectric switching within the 5 nm HZO. (f) Programming-speed sweep: MW grows with pulse width and saturates for t pw ≳ 900 ns, indicating that switching kinetics at 10 K are limited by field-assisted processes and that longer pulses yield diminishing returns. Incremental sequences in V P and t pw demonstrate reproducible, nonvolatile state placement without drift across repeated cycles, while also showing that moderately elevated V P (and subμs pulses near the saturation regime) provide the best trade-off between window size and stress under cryogenic operation. PG/ER experiments performed at 10 K establish that the ultrathin HZO FeFETs switch robustly and reproducibly under modest drive voltage. A single PG–ER operation with pulses of 5 V/–6 V and t pw = 500 ns produces well-separated LVT/HVT states, with a memory window MW = Δ V th > 1 V ( Figure c). The statistical quality of the FeFETs under cryogenic conditions is quantified in Figure d shows probability density functions (PDFs) of V th , compiled across devices, reveal narrow unimodal distributions for both LVT/HVT. The device-to-device (D2D) standard deviations are small for each state, yielding no overlap between the PDFs. Such tight distribution of V th at 10 K is consistent with a reduction (not complete elimination) in thermally assisted charge trapping in the ferroelectric/oxide stack: lower temperature suppresses emission from shallow traps and slows the redistribution of interfacial charge ( Figure S3 ), thereby stabilizing the polarization-set surface potential. Comprehensive amplitude and pulse width sweeps define the design window for cryogenic operation. In Figure e, the MW increases monotonically as the programming voltage V P is raised from 2 V and saturates for | V P | ≈ 5 V at a fixed pulse width of t pw = 500 ns, beyond which further gains are negligible. Similarly, Figure f show the pulse-width dependence at fixed | V P | = 5 V, where the MW increases with t pw = 500 from 1.6 μs and plateaus for t pw ≥ 0.9 μs. The joint saturation with amplitude and time is indicative of nucleation-limited polarization reversal in ultrathin hafnia films, where a finite density of activation sites and domain-wall pinning centers sets the rate and extent of switching at 10 K. Once a path of switchable domains is established, additional field or pulse time primarily drives subcritical wall motion that contributes little to the macroscopic V th shift. Taken together, the 10 K characterization yields clear biasing rules for reliable and energy-efficient operation, aligned with the measured polarization saturation and switching transients, and they reconcile the benefits of cryogenic operation (reduced trap activity, better electrostatics) with the realities of scaled EOT and short-channel effects. Reliability of FeFETs at 300 K and 10 K A comprehensive reliability screen at 10 K exposes endurance and retention boundaries that are set by trap-driven electrostatics rather than by intrinsic ferroelectric (FE) fatigue. Figure a shows the waveform for endurance and retention characteristics. Endurance measurements with symmetric stress of +5/–5 V, t pw = 500 ns (read at V DS = 0.1 V) show well-separated HVT/LVT states with MW > 0.5 V for ∼10 3 cycles ( Figure b). Beyond 10 4 cycles, the window contracts and the HVT state drifts toward the LVT state, behavior attributable to charge injection into HZO/SiO 2 traps and partial polarization screening. The endurance trend at 300 K therefore reflects a balance between robust ferroelectric switching and progressive trap-assisted degradation under repeated high-field pulsing. Room-temperature retention further exposes the role of defect kinetics: both V th,LVT and V th,HVT relax toward intermediate values on logarithmic time scales, with stable separation not sustained beyond ∼10 5 s ( Figure c). We attribute this to thermally activated trapping of holes and internal field screening, which promote slow back-switching. At 10 K, FeFETs sustain ∼10 7 PG–ER cycles while maintaining clearly resolvable low- and high-threshold states ( Figure d,e). The apparent endurance ceiling arises from measurement time and storage constraints, not from device degradation. Throughout cycling, both the low- and high-threshold voltages exhibit a monotonic decrease with increasing cycle count. This parallel negative drift is primarily indicative of net positive trapped charge accumulation (e.g., holes injected during negative pulses or donor-like defects) at the ferroelectric/interfacial layers. Contributions from polarization fatigue or built-in field relaxation may account for the narrowing of the MW. At cryogenic temperature (10 K), suppressed thermal detrapping prolongs charge retention, exacerbating the screening effect and symmetric degradation. The gradual V th evolution observed during endurance and retention measurements at 10 K does not indicate ferroelectric degradation or thickness-driven fatigue. Instead, it arises from cumulative interfacial charge trapping during repeated read operations. Because detrapping kinetics are strongly suppressed at cryogenic temperatures (10 K), injected charge accumulates and progressively shifts V th over time. These observations are consistent with the freezing of thermally activated depolarization and trap emission at low T , which slows the detrapping kinetics that typically erode the MW at 300 K. 5. Open in a new tab Reliability of FeFETs at 300 and 10 K. (a) Schematic of the test setup. (b) Endurance under symmetric stress of +5/–5 V, 500 ns pulses for 10 4 cycles; the MW narrows at RT, consistent with charge trapping and partial back-switching in thin films. (c) RT retention of programmed HVT/LVT states for sub-5 nm HZO FeFETs, showing drift in V th over time. (d, e) Transfer curves showing LVT (solid) and HVT (dashed) states during cyclic programming. The MW narrows gradually but remains clearly resolvable up to 10 7 cycles. (f, g) Retention characteristics : LVT/HVT states show minimal drift over logarithmic time after PG/ER operations. Extrapolation supports >10-year stability at 10 K, consistent with suppressed thermally activated depolarization and trap emission. (h) Band-diagram summary: Under gate bias, polarization in HZO points toward/outward the SiO 2 /p-Si interface, inducing mobile inversion electrons/accumulation holes in the p-Si channel. At room temperature, thermionic generation and trap emission can destabilize the polarization-set surface potential. In contrast, at 10 K, carrier freeze-out and suppressed trap kinetics stabilize the inversion layer, enabling robust readout. Atomistic Modeling of a-SiO 2 /HZO Interface The optimized structure, shown in Figure (a,b), was used as the input for molecular dynamics (MD) simulations conducted at 300 K for 0.5 ps. During this equilibration phase, both potential energy and temperature were stabilized using the MACE potential. , The equilibrated atomic configuration and its corresponding band diagram are presented in Figure (c),(d), respectively. Subsequently, the system was cooled to 10 K to emulate cryogenic conditions and simulated for an additional 10 ps. The final structure and its band diagram under cryogenic operation are shown in Figure (e),(f). 6. Open in a new tab Atomistic modeling of the a-SiO 2 /HZO interface. (a) Optimized structure of orthorhombic HZO with amorphous SiO 2 . (b) Local-density-of-states (LDOS) analysis and band diagram at 0 K obtained from DFT. (c) SiO 2 /HZO structure after MD equilibration at 300 K. (d) LDOS analysis and band diagram at 0 K obtained from DFT for the 300 K structure. (e) Final structure after cooling to 10 K via MD simulation. (f) Corresponding LDOS and band diagram at 10 K. Figure (g) compares the interface density of states (DOS) for the initial structure, after equilibration at 300 K, and after cooling to 10 K. A clear reduction in interface trap states is observed at cryogenic temperatures (10 K). This reduction is significant because interface traps play a crucial role in degrading the stability of ferroelectric polarization in HZO. At higher trap densities, the polarization is partially screened, which weakens the control of HZO over the HVT and LVT states. By lowering the temperature to 10 K, the suppression of these traps leads to stronger polarization coupling and improved separation between HVT and LVT. Moreover, interface traps are a well-known source of read disturbance in ferroelectric devices, as they facilitate charge trapping/detrapping during read operations. Their reduction at cryogenic temperatures (10 K) therefore results in diminished read disturbance, which is directly reflected in the improved transfer characteristics. Supporting measurements on Al 2 O 3 reference stacks (see Supporting Figure S4 ) confirm that the observed cryogenic stabilization is also possible for HZO-FeFETs with Al 2 O 3 interfacial layers. However, a detailed study on the physics is necessary to further understand the role of the interfacial layer’s chemistry on the reliability of the FeFETs. Cryogenic FeFET Synapses for Neuromorphic Inference We evaluated the suitability of FeFET synapses for neuromorphic inference using both static and event-driven benchmarks. A two-layer spiking neural network (SNN) was first trained on a five-class MNIST task using a device-aware FeFET synapse model directly parametrized from measured electrical characteristics ( Figure a). The network comprises 784 leaky-integrate-and-fire (LIF) input neurons, lateral inhibition in the output layer, and a winner-takes-all decision rule. Synaptic efficacy is encoded in discrete threshold-voltage states programmed via ±5 V pulses ( t pw ≈ 900 ns) and read at low drain bias to minimize read-disturb. Training is performed using spike-timing-dependent plasticity (STDP) with clipped multilevel weights, while device-to-device variability, cycle-to-cycle variation, and endurance constraints are explicitly incorporated. 7. Open in a new tab Cryogenic FeFET synapses for neuromorphic inference. (a) Schematic of the device–algorithm mapping used to evaluate FeFETs as nonvolatile synapses in a spiking neural network (SNN) on the MNIST and NMNIST digit-classification task. The synaptic weight is encoded by the FeFET threshold state set via program/erase (PG–ER) pulses, while readout is performed using a low-bias I D – V G transfer. Network-level simulations employ a device-aware model parametrized by measured cryogenic (10 K) switching curves and read characteristics ( Methods section), capturing the finite memory window, state drift, and device-to-device variability. (b, c) Training accuracy for MNIST and NMNIST data sets, considering endurance constrained, as a function of programming pulse width t pw and imposed device variation, showing >92% accuracy over a broad operating range. (d, e) Superior inference accuracy is observed under cryogenic operation due to lower device variation. Under endurance-limited conditions, the MNIST network converges reliably and maintains stable accuracy across training epochs ( Figure b). To assess performance on event-driven data, we extended the evaluation to the N-MNIST data set using a three-layer fully connected SNN implemented in snnTorch ( Figure d). Flattened 34 × 34 × 2 event streams (2312 input neurons) project to a hidden layer of 1000 LIF neurons and a 10-neuron output layer. Synaptic weights are mapped to analog FeFET threshold states, incorporating quantization and endurance-induced degradation calibrated from experimental measurements. The impact of programming pulse width and amplitude on classification accuracy is systematically examined. While the ideal software baseline converges to ∼83.1% accuracy, endurance degradation at room temperature reduces the best last-epoch accuracy to 66.8%, underscoring the sensitivity of event-based inference to synaptic reliability. In contrast, cryogenic operation at 10 K consistently enhances inference robustness across both benchmarks: MNIST accuracy exceeds 92% under endurance constraints ( Figure c), and N-MNIST accuracy recovers to 73.8% ( Figure e), representing a 7% improvement over room temperature. This cryogenic advantage arises from three key mechanisms: (i) a larger and more stable memory window, improving separability of discretized weights; (ii) superior endurance and retention; and (iii) tighter V th distributions, which suppress accumulated quantization noise. These results validate FeFET synapses as robust primitives for low-temperature, energy-efficient neuromorphic inference and highlight the importance of codesigning training protocols with experimentally measured cryogenic switching and reliability envelopes. Discussion This work presents a comprehensive experimental investigation of aggressively thickness-scaled FeFETs with sub-2 nm EOT gate stacks, focusing on their electrical behavior, reliability limits, and defect dynamics under cryogenic operation. Rather than positioning the devices as a fully optimized ferroelectric memory benchmark, our results provide a physics-based materials- and device-level study that elucidates how ultrathin HZO films, interfacial dielectric choice, and low-temperature defect kinetics jointly govern FeFET performance. A sub-2 nm equivalent-oxide-thickness (EOT) stack by integrating an ultrathin (∼5 nm) Hf 0.5 Zr 0.5 O 2 (HZO) layer within a high- k /metal-gate architecture, and evaluate device behavior down to 10 K. At this temperature, the transistors sustain a MW > 1 V, endurance >10 7 program/erase (PG–ER) cycles under low-disturb read bias, and projected retention >10 years. These figures-of-merit are achieved with modest programming conditionsrectangular pulses of ±5 V and t pw ≈ 500–900 nsso the total write energy remains in the subfemtojoule range per bit. The central enabling mechanism is a materials–bias codesign that stabilizes the ferroelectric orthorhombic phase ( Pca 2 1 ) at cryogenic temperature (10 K) while maintaining strong electrostatics in the aggressively scaled gate stack. Correlative structural analysis confirms this picture. Automated crystal orientation mapping (ACOM) on 4D-STEM data sets reveals an increase of the orthorhombic phase fraction after electrical “wake-up” at 10 K, relative to room temperature, and high-resolution X-ray photoelectron spectroscopy (XPS) shows a consistent strengthening of lattice-oxygen signatures. Together, these data point to a cryo-induced reduction in defect participation and a more stable polarization landscape in ultrathin HZO. On the device side, these structural changes manifest as tighter V th statistics across devices and cycles, steeper cumulative distribution functions, and an MW that is resilient to modest programming variations. Electrical characterization establishes practical operating recipes. First, switching saturates at ±5 V: increasing | V P | to ±7 V or extending t pw beyond ∼900 ns yields only marginal gains in Δ V th . A notable outcome of deep-cryogenic operation is the decoupling of several room-temperature trade-offs. Reduced thermal activation at 10 K suppresses stochastic charge exchange with shallow traps and slows emission from deeper levels, which in turn improves device-to-device V th spreads. At the same time, the sub-2 nm EOT stack retains strong gate control, so depolarization fields do not collapse the ferroelectric state despite the ultrathin interfacial layer. The combined effect is a window of operating conditions where MW, variability, and endurance are simultaneously favorablea prerequisite for large-array deployment near the quantum stack. Beyond immediate device metrics, these results have system-level implications. The FET-native read path enables nanosecond-class sensing without the current integration or destructive read inherent to many alternative memories, and the sub-fJ write energy minimizes heat deposition on cold stages. In cryogenic control electronicswhere wiring count, thermal budget, and calibration stability dominatethe ability to store state locally with negligible standby power is particularly attractive. Moreover, the device characteristics demonstrated here map naturally to in-memory compute primitives: small-signal charge-sharing or current-mode multiply–accumulate operations can be executed with low V DS to avoid disturb, leveraging the nonvolatility of the ferroelectric polarization to hold weights. The comparison table ( Table ) provides a comparative overview of recent cryogenic studies on HfO 2 -based ferroelectric devices, highlighting the diversity of experimental platforms and reported performance metrics. Our work on bulk Si FeFETs with a scaled HZO layer (∼5 nm, sub-2 nm EOT) demonstrates a memory window exceeding 1 V and endurance beyond 10 7 cycles over the temperature range from 300 K down to 10 K. These electrical characteristics are further supported by structural and low-frequency noise analyses, which elucidate the underlying switching behavior and trapping dynamics at cryogenic temperature (10 K). 1. Benchmarking of Representative Cryogenic HfO 2 -Based FeFETs Compared with This Work . metric this work VLSI 2023 TED 2024 APL 2020 IMW 2024 Device/Platform Bulk-Si FeFET W–In 2 O 3 FeFET (BEOL) FDSOI Si-FeFET FDSOI Si-FeFET FeFET CMOS compatibility HKMG on 200 mm/Si platform BEOL demonstrator FDSOI platform FDSOI platform – FE material HZO HZO HZO Si/HfO 2 Si/HfO 2 FE thickness ∼5 nm ∼10 nm 9 nm 10 nm 10 nm EOT/IL <2 nm EOT – – – – Temp range 300 K → 10 K 300 K → 77 K, 5 K 300 K → 5 K 300 K → 6.9 K 2.5 K → 358 K MW at cryo >1 V@10 K 1.63× (at 5 K) Multilevel MW ∼1 V increase 2.3 [email protected] K Endurance at cryo >10 7 @10 K ≥10 10 @5 K >10 5 @5 K – > 10 4 @2.5 K Key takeaway Sub-2 nm EOT bulk Si-FeFET functional at 10 K with >1 V MW and > 10 7 endurance Extreme endurance at 5 K (BEOL FeFET) Cryo multilevel operation Cryo MW increase (FDSOI) Operation down to 2.5 K Open in a new tab a “–” indicates not reported. In contrast, the Cold-FeFET reported at VLSI 2023 employs a W–In 2 O 3 channel in a BEOL-compatible architecture, achieving effectively unlimited endurance and fast write operation at 77 and 5 K. The TED 2024 study on FDSOI FeFETs with a 9 nm HZO layer emphasizes multilevel memory operation and stable retention down to 5 K, while earlier work reported in APL 2020 on Si/HfO 2 FDSOI devices observed an ∼1 V increase in memory window upon cooling to 6.9 K, attributed to an increase in the coercive field. Capacitor-level investigations have also demonstrated exceptional cryogenic reliability. For example, the JXCDC 2021 study established endurance beyond 3.5 × 10 10 cycles with negligible fatigue at 4 K, and the Advanced Electronic Materials 2024 report demonstrated analog ferroelectric operation with up to 20 reproducible states and polarization values reaching 75 μC cm –2 at 4 K. Most recently, IMW 2024 presented Si/HfO 2 FeFETs incorporating SiON/SiO 2 interfacial layers, achieving a 2.3 V memory window at 2.5 K, a low subthreshold swing of ∼40 mV dec –1 , and stable retention governed by trap dynamics. Taken together, the compact 4 F 2 footprint, sub-fJ energy per operation, competitive latency, high endurance under low-disturb read conditions, and excellent cryogenic stability position Si-based hafnia-based FeFETs as leading candidates for dense, energy-efficient memory and mixed-signal in-memory computing near the quantum stack. Conclusion In this work, we have systematically investigated the cryogenic behavior of ferroelectric field-effect transistors (FeFETs) based on ultrathin HZO layers, combining structural, chemical, electrical, and atomistic analyses with neuromorphic benchmarking. Cross-sectional TEM and 4D-STEM ACOM established the coexistence of monoclinic and orthorhombic polymorphs, with cryogenic wake-up driving a measurable increase in the polar orthorhombic fraction. Complementary XPS confirmed strengthened metal–oxygen coordination and reduced defect-related oxygen signatures at 10 K, highlighting suppressed vacancy activity and enhanced lattice ordering. Together, these materials-level insights explain the improved switching robustness and stability observed in device-level measurements. Electrical characterization using PUND, PG/ER sweeps, and reliability screens revealed that cryogenic operation suppresses defect-assisted conduction, reduces back-switching, and narrows V th distributions. Endurance and retention tests demonstrated that trap-driven degradation dominates at room temperature, whereas at 10 K the freezing of defect kinetics prolongs charge retention and stabilizes the nonvolatile window. Atomistic modeling of the SiO 2 /HZO interface further supported these findings, showing a reduction in interface trap states under cryogenic conditions, which mitigates read disturbance and strengthens polarization coupling. Finally, neuromorphic inference experiments using MNIST and N-MNIST benchmarks validated FeFET synapses as robust primitives for low-temperature spiking neural networks. Cryogenic operation consistently improved inference accuracy, sustained endurance-constrained training, and reduced variability, underscoring the synergy between device physics and algorithmic performance. Overall, this study provides a coherent framework linking cryogenic defect physics, phase stability, and interface trap suppression to enhanced FeFET reliability and neuromorphic functionality. These results not only advance the fundamental understanding of hafnia-based ferroelectrics at low temperature but also establish design rules for cryogenic memory and energy-efficient neuromorphic hardware, where robust polarization control and minimized variability are essential. Methods Fabrication and Characterization Solid–solution hafnia–zirconia (SS–HZO) gate dielectrics were grown by thermal atomic layer deposition (ALD) using alternating HfO 2 and ZrO 2 cycles on Si/SiO 2 substrates. Calibrated growth rates were 0.96 Å/cycle (HfO 2 ) and 0.92 Å/cycle (ZrO 2 ). The supercycle was balanced to achieve a 1:1 Hf/Zr cation composition, yielding a total physical thickness of 5 nm. The gate stack for all FeFETs was TaN/SS–HZO/SiO 2 /p–Si in a gate-first flow. SiO 2 was selected as the interfacial layer because it provides a chemically stable, nonreactive interface with HZO, minimizes oxygen scavenging, and maintains well-defined band offsets. Unlike alternative high-k ILs such as Al 2 O 3 or SiON, SiO 2 does not introduce additional dipoles or mobile ionic species or additional fixed charges, allowing the intrinsic ferroelectric and cryogenic properties of HZO to be isolated. To verify this choice experimentally, we fabricated and evaluated AlO-based FeFETs. Postdeposition rapid thermal annealing (RTA) in Ar was used both for dopant activation and to crystallize the SS–HZO. The process flow of fabrication is shown in Figure a. Cross-sectional transmission electron microscopy (TEM) confirmed layer continuity and thicknesses of the TaN/SS–HZO/SiO 2 stack ( Figure b). Phase distributions within the 5 nm SS–HZO were mapped by 4D scanning TEM with automated crystal-orientation mapping (ACOM), allowing spatial discrimination of monoclinic and orthorhombic polymorphs. X-ray photoelectron spectroscopy (XPS) was used to assess cation stoichiometry and oxygen coordination/chemical bonding before and after annealing. Quasi-static and pulsed measurements were performed using a Keysight B1500A analyzer and B1530A WGFMU, respectively. Unless stated otherwise, transfer characteristics I D – V G were recorded in the programmed (HVT) and erased (LVT) states at 300 and 10 K, using a low drain bias to minimize read-disturb. Endurance was evaluated with symmetric program/erase (PG/ER) stress of ±5 V, 500 ns rectangular pulses (B1530A), with periodic verification sweeps. The threshold voltage V th was extracted by the constant-current criterion at I D = 0.1 μA × ( W / L ), where W and L are the device width and length. The memory window was defined as Δ V th = V th,HVT – V th,LVT . Measurements at additional temperatures were also collected, but are not reported here for brevity. Atomistic Modeling The simulations were performed using the orthorhombic phase of HZO and amorphous SiO 2 . The amorphous SiO 2 structure was generated via the melt-and-quench technique within molecular dynamics (MD) simulations. Following structural construction and optimization, density functional theory (DFT) calculations were initially carried out. The optimized structure and the corresponding band diagram, obtained from the local density of states (LDOS) analysis in the QuantumATK framework, are shown in Figure (a),(b). The atomistic modeling presented here does not attempt to compute a full transistor-scale band diagram of the TaN/HZO/SiO 2 /p-Si stack due to limited time and resources available in academia. Instead, it provides local electronic-structure information at the HZO/SiO 2 interfaceincluding the interface density of states, local band-edge alignment, and trap-state behaviorthat governs tunneling pathways and polarization screening. Neural Network Simulation We evaluated classification performance using a current-based, spiking neural network (SNN) that consumes measured FeFET device data as the synaptic primitive. The network implements a fully connected, feedforward topology with global lateral inhibition at the output layer and a pair-based spike-timing-dependent plasticity (STDP) learning rule on excitatory synapses. The input layer comprises 784 afferents (flattened 28 × 28 pixels). The output layer size depends on the task: for five-class recognition, we use either 60 neurons (“Nonlinear Synapse”, device-aware FeFET) or 80 neurons (“Ideal Synapse”, linear reference); for ten-class recognition, we use 80 output neurons. Each input neuron connects excitatorily to every output neuron. Fixed lateral inhibitory synapses mutually couple output neurons to enforce a winner-takes-all (WTA) competition during each stimulus window. All neurons are leaky integrate-and-fire (LIF). The membrane potential V evolves as τ m d V d t = − ( V − V rest ) + R m I syn ( t ) 1 with threshold V th , reset to V reset , and absolute refractory τ ref . Pixels are normalized to [0, 1] and converted to inhomogeneous Poisson spike trains whose rates are proportional to intensity. For each image, spikes are presented for a fixed simulation window T img ; within that window, lateral inhibition implements WTA so that the most active output neuron dominates the response. V rest denotes the resting (leak) potential to which the membrane relaxes, τ m membrane time constant (s), with τ m = R m C m , R m Membrane resistance, and I syn ( t ) Net synaptic input current (A), i.e., excitatory minus inhibitory drive. Two synapse models are used. (i) Ideal Synapse (reference): weights w ∈ [ w min , w max ] follow symmetric, state-independent potentiation/depression with linear update steps; no device noise, drift, or endurance limits are applied. (ii) Nonideal Synapse (FeFET): each synapse instantiates a device-aware weight state whose evolution is constrained by measured FeFET characteristics at the target temperature ( T ). Device-to-device and cycle-to-cycle variability are injected as perturbations with mean and standard deviations calibrated from the experiment. An endurance budget N cyc is enforced per synapse; beyond this, the update probability is reduced, or the step magnitude is attenuated following the measured cycling trend at the corresponding T (endurance-constrained setting). All reads are performed at a fixed, low V DS consistent with the cryogenic reliability envelope to suppress read-disturb. Excitatory synapses follow a pair-based STDP Δ w = { η A + e − Δ t / τ + S + ( w ) if Δ t ≡ t post − t pre > 0 − η A − e Δ t / τ − S − ( w ) if Δ t < 0 2 where η is a learning-rate factor, ( A ± , τ ± ) are amplitude/time constants, and S ± ( w ) are state-dependent scaling terms. For Ideal Synapses, S ± ( w ) 1. For FeFET synapses, S ± ( w ) are set by the device’s measured potentiation/depression nonlinearity (equivalently, we sample Δ w directly from Δ w ± ( w ; ·) as noted above). After each update, w is clipped to [ w min , w max ]. Lateral inhibitory synapses are fixed and nonplastic. During training, each image elicits an output spike raster over T img . A soft/hard WTA mechanism (global inhibition) suppresses nonwinning units to prevent mode collapse and encourages specialization. After training, each output neuron is assigned the label for which it produced the highest cumulative spike count across the training set. Inference runs with learning disabled; the predicted class is the argmax of output spike counts over T img . To study temperature, variability, and endurance, we instantiate FeFET synapses with parameter sets drawn from the measured cryogenic (e.g., 10 K) and room-temperature data sets. Programming amplitude V P and pulse width t pw are chosen within the experimentally validated envelope (e.g., saturation beyond ∼5 V and ∼900 ns at 10 K); endurance-constrained experiments cap the cumulative number of potentiation/depression events per synapse according to the measured cycling budget. All read operations use a low V DS consistent with the reliability maps to minimize MW contraction due to lateral-field-assisted injection and DIBL. Unless otherwise stated, we train for a fixed number of epochs with a constant time step solver; homeostatic mechanisms (activity regularization and mild weight normalization) are applied to avoid dead units and maintain balanced competition. Reported accuracies are averaged over multiple random seeds (data order and initial weights). We compare (a) device-aware FeFET synapses at cryogenic temperature (10 K), (b) the same at room temperature, and (c) the ideal-synapse reference, under identical SNN hyperparameters and presentation time. In endurance-constrained scenarios, cryogenic FeFET synapses maintain separable states with fewer refreshes, yielding >92% accuracy on MNIST within conservative pulse budgets, whereas the room-temperature baseline degrades under the same update cap. Supplementary Material nn5c16255_si_001.pdf (270.4KB, pdf) Acknowledgments This work was partly funded by the National Science and Technology Council (NSTC), Taiwan, under grants NSTC 114-2222-E-007-001, NSTC 114-2221-E-007–144, and NSTC 114-2811-E-007-001, by the Taiwan Semiconductor Research Institute (TSRI) grant JDP114-Y1-002, JDP115-Y1-132, and by PSMC-114A0. S.L. acknowledges support from the Anusandhan National Research Foundation (ANRF) Inclusivity Research Grant (IRG) ANRF/IRG/2024/000139/ENS. We thank the Taiwan Semiconductor Research Institute (TSRI) for providing us with the nanofabrication platform, and Laas CNRS for access to the 4D-STEM facility. We also thank all team members for their discussions and assistance during measurements and analysis. The Supporting Information is available free of charge at https://pubs.acs.org/doi/10.1021/acsnano.5c16255 . X-ray diffraction (XRD) of the ultrathin HZO film (called out in the Structural Analysis section) (Figure S1); phase-composition summary from ACOM/4D-STEM (orthorhombic fraction comparison: RT vs 10 K vs pristine) (Figure S2); temperature-dependent low-frequency noise (SID vs frequency) at 2 K/20 K/300 K (γ slopes) (Figure S3), and Al 2 O 3 interfacial-layer reference-stack measurements supporting cryogenic stabilization (Figure S4) ( PDF ) ◆. A.D. served as the lead author and was primarily responsible for conducting the measurements, preparing figures, analyzing data, and curating results. A.S. and G.K. contributed equally to this work. Z.-F.L. carried out device fabrication. J.M. performed the 4D-STEM experiments and subsequent analysis. D.L. and K.-H.K. provided the cryogenic measurement facilities and technical support. T.A., M.T., J.S.M., and S.L. implemented and evaluated the neuromorphic simulations. G.L. supervised the 4D-STEM activities and facilitated access to the measurement infrastructure. M.-H.L. provided fabricated devices and process support. S.D. conceived and directed the project, secured funding, supervised the research activities, and led the manuscript preparation. S.D. is the lead author and lead correspondent.All authors discussed the results, contributed to the writing, and approved the final version of the manuscript. A preprint version of this work was previously posted on TechRxiv: Preprint version: A.S., A.D., G.K., et al. Sub-2 nm equivalent-oxide thickness ferroelectric transistors for cryogenic memory and computing. TechRxiv, November 14, 2025. DOI: 10.36227/techrxiv. 176315919.92028806/v1 (accessed March 13, 2026). The authors declare no competing financial interest. References Dünkel, S. ; Trentzsch, M. ; Richter, R. ; Moll, P. ; Fuchs, C. ; Gehring, O. ; Majer, M. ; Wittek, S. ; Müller, B. ; Melde, T. ; Mulaosmanovic, H. ; Slesazeck, S. ; Müller, S. ; Ocker, J. ; Noack, M. ; Löhr, D.-A. ; Polakowski, P. ; Müller, J. ; Mikolajick, T. ; Höntschel, J. . et al. In A FeFET Based Super-Low-Power Ultra-Fast Embedded NVM Technology for 22 nm FDSOI and Beyond; 2017 IEEE International Electron Devices Meeting (IEDM), IEEE, 2017; pp 19.7.1–19.7.4. [ Google Scholar ] Zeng B., Liao M., Peng Q., Xiao W., Liao J., Zheng S., Zhou Y.. 2-Bit/Cell Operation of Hf0.5Zr0.5O2 Based FeFET Memory Devices for NAND Applications. IEEE J. Electron Devices Soc. 2019;7:551–556. doi: 10.1109/JEDS.2019.2913426. [ DOI ] [ Google Scholar ] De S., Müller F., Laleni N., Lederer M., Raffel Y., Mojumder S., Vardar A., Abdu-lazhanov S., Ali T., Dünkel S., Beyer S., Seidel K., Kämpfe T.. Demonstration of Multiply-Accumulate Operation With 28 nm FeFET Crossbar Array. IEEE Electron Device Lett. 2022;43:2081–2084. doi: 10.1109/LED.2022.3216558. [ DOI ] [ Google Scholar ] De S., Müller F., Thunder S., Abdulazhanov S., Laleni N., Lederer M., Ali T., Raffel Y., Dünkel S., Mojumder S., Vardar A., Beyer S., Seidel K., Kämpfe T.. 28 nm HKMG-Based Current Limited FeFET Crossbar-Array for Inference Application. IEEE Trans. Electron Devices. 2022;69:7194–7198. doi: 10.1109/TED.2022.3216973. [ DOI ] [ Google Scholar ] Ali T., Polakowski P., Riedel S., Büttner T., Kämpfe T., Rudolph M., Pätzold B., Sei-del K., Löhr D., Hoffmann R., Czernohorsky M., Kühnel K., Steinke P., Calvo J., Zim-mermann K., Müller J.. High Endurance Ferroelectric Hafnium Oxide-Based FeFET Memory Without Retention Penalty. IEEE Trans. Electron Devices. 2018;65:3769–3774. doi: 10.1109/TED.2018.2856818. [ DOI ] [ Google Scholar ] Mueller S., Müller J., Hoffmann R., Yurchuk E., Schlösser T., Boschke R., Paul J., Gold-bach M., Herrmann T., Zaka A., Schröder U., Mikolajick T.. From MFM Capacitors Toward Ferroelectric Transistors: Endurance and Disturb Characteristics of HfO2-Based FeFET Devices. IEEE Trans. Electron Devices. 2013;60:4199–4205. doi: 10.1109/TED.2013.2283465. [ DOI ] [ Google Scholar ] Marchand, C. ; O’Connor, I. ; Cantan, M. ; Breyer, E. T. ; Slesazeck, S. ; Mikolajick, T. In FeFET Based Logic-in-Memory: An Overview, 2021 16th International Conference on Design Technology of Integrated Systems in Nanoscale Era (DTIS); IEEE, 2021; pp 1–6. [ Google Scholar ] Chakraborty W., Aabrar K. A., Gomez J., Saligram R., Raychowdhury A., Fay P., Datta S.. Characterization and Modeling of 22 nm FDSOI Cryogenic RF CMOS. IEEE J. Explor. Solid-State Comput. Devices Circuits. 2021;7:184–192. doi: 10.1109/JXCDC.2021.3131144. [ DOI ] [ Google Scholar ] De S., Müller F., Le H.-H., Lederer M., Yannick R., Ali T., Lu D., K̈ampfe T.. READ-Optimized 28nm HKMG Multi-bit FeFET Synapses for Inference-Engine Applications. IEEE J. Electron Devices Soc. 2022;10:637–641. doi: 10.1109/JEDS.2022.3195119. [ DOI ] [ Google Scholar ] Sk M. R., Senapati A., Kumar G., Raffel Y., Seidel K., Das A., Paul A., Lederer M., Chen C. C., Padovani A., Chakrabarti B., De S.. Trapping Dynamics and Endurance in HfO2-FeFETs: An Insight from Charge Pumping. IEEE Electron Device Lett. 2025;46:2014–2017. doi: 10.1109/led.2025.3612323. [ DOI ] [ Google Scholar ] De S., Mueller F., Laleni N., Lederer M., Raffel Y., Mojumder S., Vardar A., Abdu-lazhanov S., Ali T., Dünkel S.. et al. Demonstration of multiply-accumulate operation with 28 nm fefet crossbar array. IEEE Electron Device Lett. 2022;43:2081–2084. doi: 10.1109/LED.2022.3216558. [ DOI ] [ Google Scholar ] Parmar V., Müller F., Hsuen J.-H., Kingra S. K., Laleni N., Raffel Y., Lederer M., Var-dar A., Seidel K., Soliman T.. et al. Demonstration of Differential Mode FeFET-Array based IMC-Macro for realizing multi-precision mixed-signal AI accelerator. Adv. Intell. Syst. 2023;5:2200389. doi: 10.1002/aisy.202200389. [ DOI ] [ Google Scholar ] Müller J., Schröder U., Böscke T. S., Müller I., Böttger U., Wilde L., Sundqvist J., Lemberger M., Kücher P., Mikolajick T., Frey L.. Ferroelectricity in yttrium-doped hafnium oxide. J. Appl. Phys. 2011;110:114113. doi: 10.1063/1.3667205. [ DOI ] [ Google Scholar ] Müller, F. ; Lederer, M. ; Olivo, R. ; Ali, T. ; Hoffmann, R. ; Mulaosmanovic, H. ; Beyer, S. ; Dünkel, S. ; Müller, J. ; Müller, S. ; Seidel, K. ; Gerlach, G. In Current Percolation Path Impacting Switching Behavior of Ferroelectric FETs, International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA); IEEE, 2021; pp 1–2. [ Google Scholar ] Müller F., De S., Olivo R., Lederer M., Altawil A., Hoffmann R., Kämpfe T., Ali T., Dünkel S., Mulaosmanovic H.. et al. Multilevel operation of ferroelectric fet memory arrays considering current percolation paths impacting switching behavior. IEEE Electron Device Lett. 2023;44:757–760. doi: 10.1109/LED.2023.3256583. [ DOI ] [ Google Scholar ] Khan A. I., Keshavarzi A., Datta S.. The future of ferroelectric field-effect transistor technology. Nat. Electron. 2020;3:588–597. doi: 10.1038/s41928-020-00492-7. [ DOI ] [ Google Scholar ] Ma X., Deng S., Wu J., Zhao Z., Lehninger D., Ali T., Seidel K., De S., He X., Chen Y., Yang H., Narayanan V., Datta S., Kämpfe T., Luo Q., Ni K., Li X.. A 2-Transistor-2-Capacitor Ferroelectric Edge Compute-in-Memory Scheme With Disturb-Free Inference and High Endurance. IEEE Electron Device Lett. 2023;44:1088–1091. doi: 10.1109/LED.2023.3274362. [ DOI ] [ Google Scholar ] Wang P., Yu S.. Ferroelectric devices and circuits for neuro-inspired computing. MRS Commun. 2020;10:538–548. doi: 10.1557/mrc.2020.71. [ DOI ] [ Google Scholar ] Agarwal A., Walke A. M., Ronchi N., Popovici M. I., Ma W. C. Y., Su C. J., Kao K. H., Houdt J. V.. Yttrium Doped Hf.Zr.O Based Ferroelectric Capacitor Exhibiting Fatigue Free (>10 Cycles), Long Retention, and Imprint Immune Performance at 4 K. IEEE Electron Device Lett. 2025;46:1095–1098. doi: 10.1109/LED.2025.3562798. [ DOI ] [ Google Scholar ] Christensen D. V., Dittmann R., Linares-Barranco B., Sebastian A., Gallo M. L., Redaelli A., Slesazeck S., Mikolajick T., Spiga S., Menzel S., Valov I., Milano G., Ricciardi C., Liang S.-J., Miao F., Lanza M., Quill T. J., Keene S. T., Salleo A., Grollier J.. et al. 2022 roadmap on neuromorphic computing and engineering. Neuromorphic Comput. Eng. 2022;2:022501. doi: 10.1088/2634-4386/ac4a83. [ DOI ] [ Google Scholar ] Alam S., Hossain M. S., Aziz A.. A cryogenic memory array based on superconducting memristors. Appl. Phys. Lett. 2021;119:082602. doi: 10.1063/5.0060716. [ DOI ] [ Google Scholar ] Guarcello C., Bergeret F. S.. Cryogenic Memory Element Based on an Anomalous Josephson Junction. Phys. Rev. Appl. 2020;13:034012. doi: 10.1103/PhysRevApplied.13.034012. [ DOI ] [ Google Scholar ] Kirtania, S. G. ; Aabrar, K. A. ; Khan, A. I. ; Yu, S. ; Datta, S. In Cold-FeFET as Embedded Non-Volatile Memory with Unlimited Cycling Endurance, 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits); IEEE, 2023; pp 1–2. [ Google Scholar ] Paasio E., Ranta R., Majumdar S. A.. A Physics-Based Compact Model for Ferroelectric Capacitors Operating Down to Deep Cryogenic Temperatures for Applications in Analog Memory and Neuromorphic Architectures. Adv. Electron. Mater. 2025;11:2400840. doi: 10.1002/aelm.202400840. [ DOI ] [ Google Scholar ] Ko J.-S., Shearer A. B., Lee S., Neilson K., Jaikissoon M., Kim K., Bent S. F., Pop E., Saraswat K. C.. Achieving 1-nm-Scale Equivalent Oxide Thickness Top-Gate Dielectric on Monolayer Transition Metal Dichalcogenide Transistors With CMOS-Friendly Approaches. IEEE Trans. Electron Devices. 2025;72:1514–1519. doi: 10.1109/TED.2024.3466112. [ DOI ] [ Google Scholar ] Cheng C., Chou K., Chin A.. Achieving low sub-0.6-nm EOT in gate-first n-MOSFET with TiLaO/CeO2 gate stack. Solid-State Electron. 2013;82:111–114. doi: 10.1016/j.sse.2013.02.003. [ DOI ] [ Google Scholar ] Mulaosmanovic H., Breyer E. T., Mikolajick T., Slesazeck S.. Ferroelectric FETs With 20nm-Thick HfO2 Layer for Large Memory Window and High Performance. IEEE Trans. Electron Devices. 2019;66:3828–3833. doi: 10.1109/TED.2019.2930749. [ DOI ] [ Google Scholar ] Minor A. M., Denes P., Muller D. A.. Cryogenic electron microscopy for quantum science. MRS Bull. 2019;44:961–966. doi: 10.1557/mrs.2019.288. [ DOI ] [ Google Scholar ] Hessler, D. ; Olivo, R. ; Seidel, K. ; Hoffmann, R. ; De, S. ; Raffel, Y. In Dopant-Dependent Flicker Noise of Hafnium Oxide Ferroelectric Field Effect Transistor, IEEE Electron Devices Technology and Manufacturing Conference (EDTM); IEEE, 2024. [ Google Scholar ] Estandía S., Dix N., Gazquez J., Fina I., Lyu J., Chisholm M. F., Fontcuberta J., Sanchez F.. Engineering Ferroelectric Hf0.5Zr0.5O2 Thin Films by Epitaxial Stress. ACS Appl. Electron. Mater. 2019;1:1449–1457. doi: 10.1021/acsaelm.9b00256. [ DOI ] [ Google Scholar ] O’Connor, Halter M., Eltes F., Sousa M., Kellock A., Abel S., Fompeyrine J.. Stabilization of ferroelectric HfxZr1xO2 films using a millisecond flash lamp annealing technique. APL Mater. 2018;6:121103. doi: 10.1063/1.5060676. [ DOI ] [ Google Scholar ] Park M. H., Lee Y. H., Kim H. J., Kim Y. J., Moon T., Kim K. D., Müller J., Kersch A., Schroeder U., Mikolajick T., Hwang C. S.. Ferroelectricity and antiferroelectricity of doped thin HfO2-based films. Adv. Mater. 2014;27:1811–1831. doi: 10.1002/adma.201404531. [ DOI ] [ PubMed ] [ Google Scholar ] Raffel Y., De S., Lederer M., Olivo R., Hoffmann R., Thunder S., Pirro L., Beyer S., Chohan T., Kämpfe T.. et al. A Synergistic Approach of Interfacial Layer Engineering and READ-Voltage Optimisation in HfO2-Based FeFETs for In-Memory-Computing Applications. ACS Appl. Electron. Mater. 2022;4(11):5292–5300. doi: 10.1021/acsaelm.2c00771. [ DOI ] [ PMC free article ] [ PubMed ] [ Google Scholar ] Lederer, M. ; Müller, F. ; Hoffmann, R. ; Olivo, R. ; Raffel, Y. ; Yang, S. ; De, S. ; Potjan, R. ; Ostien, O. ; Altawil, A. . et al. In Enhanced Reliability and Trapping Behavior in Ferroelectric FETs under Cryogenic Conditions, 2024 IEEE International Memory Workshop (IMW); IEEE, 2024; pp 1–4. [ Google Scholar ] Das, D. ; Park, H. ; Wang, Z. ; Zhang, C. ; Ravindran, P. V. ; Park, C. ; Afroze, N. ; Hsu, P.-K. ; Tian, M. ; Chen, H. ; Chern, W. ; Lim, S. ; Kim, K. ; Kim, K. ; Kim, W. ; Ha, D. ; Yu, S. ; Datta, S. ; Khan, A. In Experimental Demonstration and Modeling of a Ferroelectric Gate Stack with a Tunnel Dielectric Insert for NAND Applications, 2023 International Electron Devices Meeting (IEDM); IEEE, 2023; pp 1–4. [ Google Scholar ] Das, D. ; Park, H. ; Wang, Z. ; Zhang, C. ; Ravindran, P. V. ; Park, C. ; Afroze, N. ; Hsu, P.-K. ; Tian, M. ; Chen, H. ; Chern, W. ; Lim, S. ; Kim, K. ; Kim, K. ; Kim, W. ; Ha, D. ; Yu, S. ; Datta, S. ; Khan, A. In Experimental Demonstration and Modeling of a Ferroelectric Gate Stack with a Tunnel Dielectric Insert for NAND Applications, 2023 International Electron Devices Meeting (IEDM); IEEE, 2023; pp 1–4. [ Google Scholar ] Das, D. ; Fernandes, L. ; Ravindran, P. V. ; Song, T. ; Park, C. ; Afroze, N. ; Tian, M. ; Chen, H. ; Chem, W. ; Kim, K. ; Woo, J. ; Lim, S. ; Kim, K. ; Kim, W. ; Ha, D. ; Yu, S. ; Datta, S. ; Khan, A. In Design Framework for Ferroelectric Gate Stack Engineering of Vertical NAND Structures for Efficient TLC and QLC Operation, 2024 IEEE International Memory Workshop (IMW); IEEE, 2024; pp 1–4. [ Google Scholar ] Ohta A., Murakami H., Hashimoto K., Makihara K., Miyazaki S.. Characterization of Chemical Bonding Features and Interfacial Reactions in Ge-MIS Structure with HfO2/TaGexOy Dielectric Stack. ECS Meet. Abstr. 2014;MA2014-02:1785. doi: 10.1149/MA2014-02/35/1785. [ DOI ] [ Google Scholar ] Teherani J. T., Chern W., Antoniadis D. A., Hoyt J. L.. Ultra-Thin, High Quality HfO2 on Strained-Ge MOS Capacitors with Low Leakage Current. ECS Meet. Abstr. 2014;MA2014-02:1788. doi: 10.1149/MA2014-02/35/1788. [ DOI ] [ Google Scholar ] Hoffmann M., Salahuddin S.. Ferroelectric gate oxides for negative capacitance transistors. MRS Bull. 2021;46:930–937. doi: 10.1557/s43577-021-00208-y. [ DOI ] [ Google Scholar ] Lee, T.-E. ; Su, Y.-C. ; Lin, B.-J. ; Chen, Y.-X. ; Yun, W.-S. ; Ho, P.-H. ; Wang, J.-F. ; Su, S.-K. ; Hsu, C.-F. ; Mao, P.-S. ; Chang, Y.-C. ; Chien, C.-H. ; Liu, B.-H. ; Su, C.-Y. ; Kei, C.-C. ; Wang, H. ; Philip Wong, H. S. ; Wong, H.-S. P. ; Lee, T. Y. ; Chang, W.-H. ; Cheng, C.-C. In Nearly Ideal Subthreshold Swing in Monolayer MoS Top-Gate nFETs with Scaled EOT of 1 nm, 2022 International Electron Devices Meeting (IEDM); IEEE, 2022; pp 7.4.1–7.4.4. [ Google Scholar ] Wang Z., Ying H., Chern W., Yu S., Mourigal M., Cressler J. D., Khan A. I.. Cryogenic characterization of a ferroelectric field-effect-transistor. Appl. Phys. Lett. 2020;116:042902. doi: 10.1063/1.5129692. [ DOI ] [ Google Scholar ] Li M., Gu Y., Wang Y., Chen L.-Q., Duan W.. First-principles study of 180 domain walls in BaTiO3: Mixed Bloch-N′eel-Ising character. Phys. Rev. B. 2014;90:054106. doi: 10.1103/PhysRevB.90.054106. [ DOI ] [ Google Scholar ] Trentzsch, M. ; Flachowsky, S. ; Richter, R. ; Paul, J. ; Reimer, B. ; Utess, D. ; Jansen, S. ; Mulaosmanovic, H. ; Müller, S. ; Slesazeck, S. ; Ocker, J. ; Noack, M. ; Müller, J. ; Polakowski, P. ; Schreiter, J. ; Beyer, S. ; Mikolajick, T. ; Rice, B. In A 28 nm HKMG Super Low Power Embedded NVM Technology Based on Ferroelectric FETs, 2016 IEEE International Electron Devices Meeting (IEDM); IEEE, 2016; pp 11.5.1–11.5.4. [ Google Scholar ] Fleetwood D. M.. Interface traps, correlated mobility fluctuations, and low-frequency noise in metal–oxide–semiconductor transistors. Appl. Phys. Lett. 2023;122:173504. doi: 10.1063/5.0146549. [ DOI ] [ Google Scholar ] Yurchuk E., Müller J., Müller S., Paul J., Pesić M., Bentum Rv., Schroeder U., Mikolajick T.. Charge-Trapping Phenomena in HfO2-Based FeFET-Type Nonvolatile Memories. IEEE Trans. Electron Devices. 2016;63:3501–3507. doi: 10.1109/TED.2016.2588439. [ DOI ] [ Google Scholar ] Lu D. D., De S., Baig M. A., Qiu B.-H., Lee Y.-J.. Computationally efficient compact model for ferroelectric field-effect transistors to simulate the online training of neural networks. Semicond. Sci. Technol. 2020;35:095007. doi: 10.1088/1361-6641/ab9bed. [ DOI ] [ Google Scholar ] De, S. ; Baig, A. ; Qiu, B.-H. ; Lu, D. ; Sung, P.-J. ; Hsueh, F. ; Lee, Y.-J. ; Su, C.-J. In Tri-Gate Ferroelectric FET Characterization and Modelling for Online Training of Neural Networks at Room Temperature and 233K, 2020 Device Research Conference (DRC); IEEE, 2020. [ Google Scholar ] Aabrar, K. A. ; Kirtania, S. G. ; Deng, S. ; Choe, G. ; Khan, A. ; Yu, S. ; Datta, S. In Improved Reliability and Enhanced Performance in BEOL Compatible W-doped In2O3 Dual-Gate Transistor, 2023 International Electron Devices Meeting (IEDM); IEEE, 2023; pp 1–4. [ Google Scholar ] Batatia I., Benner P., Chiang Y., Elena A. M., Kovács D. P., Riebesell J., Advincula X. R., Asta M., Avaylon M., Baldwin W. J., Berger F., Bernstein N., Bhowmik A., Bigi F., Blau S. M.. et al. A foundation model for atomistic materials chemistry. J. Chem. Phys. 2025;163:184110. doi: 10.1063/5.0297006. [ DOI ] [ PubMed ] [ Google Scholar ] Smidstrup S., Markussen T., Vancraeyveld P., Wellendorff J., Schneider J., Gunst T., Verstichel B., Stradi D., Khomyakov P. A., Vej-Hansen U. G., Lee M.-E., Chill S. T., Rasmussen F., Penazzi G., Corsetti F., Ojanperä A., Jensen K., Palsgaard M. L. N., Martinez U., Blom A.. et al. QuantumATK: an integrated platform of electronic and atomicscale modelling tools. J. Phys.: Condens. Matter. 2020;32:015901. doi: 10.1088/1361-648X/ab4007. [ DOI ] [ PubMed ] [ Google Scholar ] Eshraghian J. K., Ward M., Neftci E., Wang X., Lenz G., Dwivedi G., Bennamoun M., Jeong D. S., Lu W. D.. Training spiking neural networks using lessons from deep learning. Proc. IEEE. 2023;111:1016–1054. doi: 10.1109/JPROC.2023.3308088. [ DOI ] [ Google Scholar ] Zhang M., Qian H., Xu J., Ma M., Shen R., Lin G., Gu J., Liu Y., Jin C., Chen J., Han G.. Enhanced Endurance and Stability of FDSOI Ferroelectric FETs at Cryogenic Temperatures for Advanced Memory Applications. IEEE Trans. Electron Devices. 2024;71:6680–6685. doi: 10.1109/TED.2024.3456763. [ DOI ] [ Google Scholar ] Hur J., Luo Y.-C., Wang Z., Lombardo S., Khan A. I., Yu S.. Characterizing Ferroelectric Properties of Hf0.5Zr0.5O2 From Deep-Cryogenic Temperature (4 K) to 400 K. IEEE J. Explor. Solid-State Computat. Devices Circuits. 2021;7:168–174. doi: 10.1109/JXCDC.2021.3130783. [ DOI ] [ Google Scholar ] Bohuslavskyi H., Grigoras K., Ribeiro M., Prunnila M., Majumdar S.. Ferroelectric Hf0.5Zr0.5O2 for Analog Memory and In-Memory Computing Applications Down to Deep Cryogenic Temperatures. Adv. Electron. Mater. 2024;10:2300879. doi: 10.1002/aelm.202300879. [ DOI ] [ Google Scholar ] Senapati, A. ; Das, A. ; Kumar, G. ; Lou, Z.-F. ; Müller, J. ; Maskeen, J. S. ; Chang, Y.-T. ; Tewari, M. ; Agarwal, A. ; Raffel, Y. ; Maikap, S. ; Kao, K.-H. ; Agarwal, T. ; Lashkare, S. ; Lu, D. ; Larrieu, G. ; Lee, M.-H. ; DE, S. . Sub-2 nm equivalent-oxide thickness ferroelectric transistors for cryogenic memory and computing. 2025. [ DOI ] [ PMC free article ] [ PubMed ] Associated Data This section collects any data citations, data availability statements, or supplementary materials included in this article. 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