3-Tier CFET 6T-SRAM with 2D-TMDs channels for Angstrom technology node.

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Learn more: PMC Disclaimer | PMC Copyright Notice Sci Rep . 2026 Apr 10;16:16857. doi: 10.1038/s41598-026-37881-5 3-Tier CFET 6T-SRAM with 2D-TMDs channels for Angstrom technology node Jonghun Lee 1 , Junyeol Lee 2 , Jimyeong Lee 3, 4 , Saetbyeol Ahn 3, 5 , Donghyun Jin 6 , Jongwook Jeon 2, ✉ Author information Article notes Copyright and License information 1 Department of Display Engineering, Sungkyunkwan University, Suwon, 16419 Republic of Korea 2 Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, 16419 Republic of Korea 3 Department of Semiconductor and Display Engineering, Sungkyunkwan University, Suwon, 16419 Republic of Korea 4 The Foundry Business Division, Samsung Electronics, Hwaseong, 18488 Republic of Korea 5 The Computational Science and Engineering Team, Semiconductor Research Center, Samsung Electronics, Hwaseong, 18448 Republic of Korea 6 Research and Development Center, Alsemy Inc, Seoul, Republic of Korea ✉ Corresponding author. Received 2025 Oct 2; Accepted 2026 Jan 27; Collection date 2026. © The Author(s) 2026 Open Access This article is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License, which permits any non-commercial use, sharing, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons licence, and indicate if you modified the licensed material. You do not have permission under this licence to share adapted material derived from this article or parts of it. The images or other third party material in this article are included in the article’s Creative Commons licence, unless indicated otherwise in a credit line to the material. If material is not included in the article’s Creative Commons licence and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this licence, visit http://creativecommons.org/licenses/by-nc-nd/4.0/ . PMC Copyright notice PMCID: PMC13230523  PMID: 41963381 Abstract As the scaling of conventional SRAM faces fundamental physical and area limitations, novel device architectures are essential for next-generation computing. This paper proposes and comprehensively evaluates a novel 3-Tier 6T-SRAM cell based on a vertically stacked Complementary FET (CFET) architecture that incorporates 2D Transition Metal Dichalcogenides (TMDs) as channel materials. The proposed 3-Tier CFET architecture demonstrates a significant cell area reduction of approximately 29.5% compared with the Conventional 2-Tier structure. This miniaturization lowers the internal-node capacitance by 13–22%, yielding markedly better write performance (e.g. >39% lower write energy). By systematically adjusting the nanosheet stack ratios (PU: PD: PG), we precisely control the trade-offs between stability and speed. The optimized design (2P4N + 3N_Access) improves read-access time by 11.9% while maintaining robust write characteristics. This synergistic optimization results in a 24.9% reduction in the Energy-Delay Product (EDP), indicating improved overall efficiency. These findings validate that the strategic integration of a 3-Tier CFET architecture with 2D TMDs channels provides a robust pathway to high-density, high-performance, energy-efficient SRAM for future high-performance computing and low-power mobile application. Supplementary Information The online version contains supplementary material available at 10.1038/s41598-026-37881-5. Keywords: 3-Tier CFET (Complementary FET), 2D TMDs, Area scaling, 6T-SRAM, Parasitic RC analysis, Static stability, Access time, RC delay, Energy-delay product (EDP) Subject terms: Engineering, Materials science, Nanoscience and technology Introduction Static Random-Access Memory (SRAM) is a critical component in modern computing systems, serving as cache memory, buffers, and registers that determine overall system performance and power efficiency. While the importance of high-density and high-performance on-chip SRAM is growing in state-of-the-art AI accelerators, the frequent data fetching between processing units and memory has become a major bottleneck that dominates the total system energy consumption 1 – 3 . Therefore, improving SRAM speed to minimize data access latency and maximizing the memory’s intrinsic power and energy efficiency are key challenges for next-generation AI semiconductor design 4 – 6 . For decades, advancements in 3D architectures, from planar structures to FinFETs and Gate-All-Around FETs (GAAFETs), have driven scaling in accordance with Moore’s Law by enhancing electrostatic control over the channel 7 . However, upon entering the sub-10 nm technology nodes, significant challenges such as physical scaling limits and routing congestion have emerged, slowing the pace of cell area reduction. Notably, the industry has observed an unprecedented slowdown in SRAM cell-area scaling since the 3 nm process node 8 , 9 . To overcome this density limit, the Complementary FET (CFET) architecture has emerged. The primary advantage of CFET technology is the vertical stacking of NMOS and PMOS transistors, which eliminates the physical spacing constraints between them. This allows for a silicon footprint reduction by up to 50% for a 6T-SRAM cell compared to FinFET or GAAFET-based SRAM cells, serving as a key driver for dramatically increasing SRAM density 10 – 12 . However, Si-based CFET structures present several limitations. First, as NMOS and PMOS transistors are vertically stacked, the small n-p separation distance induces significant parasitic capacitance. Furthermore, the increased device height leads to taller vias connecting upper-level signal lines to lower-level devices, increasing parasitic resistance. This exacerbates the overall RC delay, which can degrade circuit speed and increase power consumption 7 , 13 , 14 . Second, the scalability of Si-based transistors is fundamentally limited by the physical constraints of reducing channel thickness. Quantum confinement and surface roughness scattering effects that occur when reducing the Si channel thickness below 3 nm cause severe mobility degradation and increased leakage current 15 – 18 . Finally, fabricating high-quality Si channels requires a high thermal budget, which can degrade the performance of underlying devices during 3D vertical integration 13 . Beyond these material-level challenges, the conventional 2-Tier CFET architecture introduces its own set of structural constraints that hinder performance optimization. A standard 6T-SRAM cell consists of Pull-Up (PU), Pull-Down (PD), and Pass-Gate (PG) transistors, each requiring different drive strengths for optimal performance in terms of stability, speed, and power 19 . However, the Conventional 2-Tier CFET 6T-SRAM architecture has a structural limitation wherein the PD and PG transistors are grouped in the same tier, making it difficult to independently optimize the three transistor types according to their functional requirements. To simultaneously overcome the material and structural limitations faced by existing Si-based 2-Tier CFETs, this work proposes an integrated strategy with two key innovations: (1) replacing the channel material with 2D Transition Metal Dichalcogenides (TMDs) and (2) advancing the device architecture to a 3-Tier structure. First, introducing 2D TMDs as the channel material resolves the 3D integration limits imposed by the physical thickness of Si channels. The atomically thin nature of 2D TMDs (~ 0.7 nm) allows for vertical stacking without significantly increasing the total device height, leading to a reduction in parasitic capacitance and resistance. Furthermore, the thin body maximizes the electrostatic gate control over the channel, effectively suppressing the Short Channel Effect (SCE). The excellent interface properties, which are free of dangling bonds, and high carrier mobility further support the implementation of high-performance channels 20 . Finally, since 2D TMDs materials can be processed at relatively low temperatures 21 , multi-layer stacks of 3-Tiers or more can be stacked without causing thermal damage to the underlying devices, a decisive advantage for vertical integration. Recent advancements in 2D TMDs have opened new opportunities for promising candidates of future low-power and high-reliability SRAM memories. The TMDFETs have demonstrated superior characteristics such as improved static noise margins, reduced leakage power, and enhanced robustness against process variations compared to conventional CMOS technology 22 , 23 . Concurrently, the introduction of the 3-Tier architecture enables the independent performance optimization of the PU, PD, and PG transistors. Unlike the 2-Tier structure, this work adopts a 3-Tier CFET architecture that vertically separates the two PU/PD CFET inverters and the two PG NMOS transistors. This structural separation enables unparalleled design flexibility by allowing the number of nanosheet stacks to be freely adjusted to tune the effective channel width (W eff​ ) of each transistor. This presents a new design paradigm for precisely optimizing stability, access time, and power consumption without complex assist circuits. The proposed 3-Tier architecture provides significant advantages in integration density, leading to an approximate 29.5% reduction in bitcell area compared to the Conv. 2-Tier CFET 6T-SRAM structure. This structural miniaturization further decreases internal node (Q) capacitance by 13–22%, leading to significantly improved write performance. Consequently, all 3-Tier models exhibit more than a 42% reduction in write energy, with the write-specialized (2P3N) model achieving over 50.3% energy savings. Moreover, by precisely adjusting nanosheet stack ratios, we effectively balance the stability-speed trade-off, and our final proposed design (3-Tier 2P4N+3N_Access) delivers the fastest Read Access Time (RAT) with an 11.9% improvement while simultaneously reducing the Energy-Delay Product (EDP) by 24.9%, ensuring an optimized and well-balanced overall performance. The objective of this study is to quantitatively evaluate the advantages of the 3-Tier CFET SRAM over the Conv. 2-Tier structure in terms of performance, cell stability, and energy efficiency, and to provide a design guide for an optimized 3-Tier cell based on parasitic RC analysis. The remainder of this paper is organized as follows: The section " Simulation environment ", describes the device-to-circuit simulation framework, TCAD/SPICE modeling methodology, and the proposed 3-Tier structure. The section " The results and discussion ", provides a comprehensive comparative analysis of parasitic RC, Static Noise Margin (SNM), Dynamic Access Times (RAT/WAT), and Energy Efficiency (EDP). Finally, the section " Conclusion ", summarizes the key findings of this work and discusses the potentials and technical challenges of the proposed 3-Tier architecture as a next-generation SRAM. Simulation environment Device architecture, layout and conceptual fabrication flow To verify the feasibility and analyze the electrical characteristics of the proposed 3D device structures, we used the Synopsys Sentaurus TCAD tool as the core simulation framework. The standard 6T-SRAM cell, which serves as the foundation of this research, is depicted in the circuit diagram in Fig. 1 (b). The cell consists of two primary components. The core data storage unit is a latch formed by two cross-coupled CMOS inverters, composed of PU1/PD1 and PU2/PD2 transistors, respectively. This latch structure stably stores one bit of data on two complementary internal nodes (Q and QB). Data access is controlled by two Pass-Gate transistors (PG1 and PG2), which are gated by the Word Line (WL). When the WL signal is asserted, these transistors turn on, connecting the Q, QB to the external Bit Lines (BL, BLB) to enable read and write operations. Fig. 1. Open in a new tab Configuration of. SRAM Device Structure a 3-D schematic views of 2D TMDs Conv. CFET 6T-SRAM Layout and 2D TMDs 3-Tier CFET 6T-SRAM. b 6T-SRAM Circuitry. c Conv. CFET SRAM Layout and d 3-Tier CFET SRAM Layout each. The two SRAM structures proposed in this work maintain this fundamental 6T-SRAM operation principle but are based on a next-generation CFET architecture with vertically stacked transistors. The 3D structures, shown in Fig. 1 (a), were designed based on the 1 nm technology node specifications from the International Roadmap for Devices and Systems (IRDS) 2023 24 . A key design rule, the Contacted Poly Pitch (CPP), was set to 38 nm to ensure alignment with future technology nodes. Furthermore, to mitigate the parasitic overheads, a double-sided interconnect design was adopted. This architecture employs a Backside Power Delivery Network (BSPDN), which places the WL and BL signal lines on the Frontside while connecting the VDD and VSS power lines directly to the transistors from the Backside. This approach reduces crosstalk and optimizes the power delivery path 25 , 26 . These design criteria were applied equally to the FEOL (Front-End-Of-Line) stage of both the 2D TMDs Conv. (2-Tier) CFET 6T-SRAM and the proposed 2D TMDs 3-Tier CFET 6T-SRAM to allow for a clear comparison of performance based on structural differences. In respect to our Conv. 2-Tier (8T) and proposed 3-Tier (9T) CFET architectures, an important consideration is the presence of surplus, unconnected transistors when implementing a standard 6T-SRAM cell. Specifically, the 2-Tier configuration leaves two PMOS transistors unused, whereas the 3-Tier configuration results in one PMOS and two NMOS transistors remaining floating. The key geometric parameters and metal design rules used in the simulations are detailed in Tables 1 and 2 , respectively. Table 1. Key geometric parameters used for the device simulation. Dimension Parameter Values (nm) Channel Thickness (T ch ) 0.65 (monolayer) Channel Width (W ch ) 25 Gate Length (L ch ) 12 Contact Length (L cnt ) 18 High-k Oxide (HfO 2 ) Thickness (T hk ) 3 Protection Layer (Al 2 O 3 ) Thickness (T pr ) 3 Equivalent Oxide Thickness (EOT) 1.8 Spacer Length (L sp ) 4 Contact Poly Pitch (CPP) 38 PN Separation Vertical Distance (D pn ) 20 Cell Width (W Cell ) 76 (Convent.), 114 (3-Tier) Cell Height (H Cell ) 166 (Convent.), 78 (3-Tier) Open in a new tab Table 2. Metal design rules used for the interconnect. Parameter description Type Value (nm) Metal Line Thickness (Th M ) Common 15 M2 Pitch/Width Conv. 54/16 M1 Pitch/Width Conv. 70/16 3-Tier 23/8 M0 Width Conv. 8 Via Width (W Via ) Common 8 Via Length (L Via ) Common 12 Buried Power Rail Width/Thickness (W BPR /Th BPR ) Common 15/30 Open in a new tab The layouts of the resulting 3D devices are presented in Fig. 1 (c) and (d). In the Conv. 2-Tier structure, PU and PD transistors are arranged horizontally, resulting in a cell width of 2 x CPP = 76 nm. In the proposed 3-Tier structure, the PU, PD, and PG transistors are all stacked vertically, leading to a cell width of 3 x CPP = 114 nm. The bitcell area is calculated using the formula: Area= Cell Height(H Cell ) × Cell Width(W Cell ). The 3-Tier CFET 6T-SRAM designed in this study has an area of 8,892 nm² (78 nm x 114 nm), which is a 29.5% reduction compared to the Conv. (2-Tier) CFET 6T-SRAM area of 12,616 nm² (166 nm x 76 nm). This clearly demonstrates that the proposed 3-Tier structure is highly effective at improving integration density and overcoming the area scaling challenges inherent to SRAM. Notably, the achieved cell area is competitive against that of the state-of-the-art Si-based CFET via-optimized 6T-SRAM 27 , and a detailed comparison is provided in Supplementary Table S1 online. The proposed SRAM structures are based on a next-generation, vertically stacked CFET architecture, which is a key technology for maximizing integration density. To enhance performance, 2D TMDs were adopted as channel material. The device utilizes WSe₂ monolayers as the bottom p-type channel 28 , and MoS₂ monolayers as the top n-type channel. The source and drain are composed of metals that form low-resistance ohmic contacts with the channel material 29 . Notably, edge-contacts are applied to maximize carrier injection efficiency between the source/drain and the 2D material channels 20 . The conceptual fabrication process for the proposed 3-Tier 6T-SRAM structure, shown in Fig. 2 , is based on a Monolithic 3D (M3D) integration scheme adapted from established CFET process flows presented by TSMC 14 , 30 – 32 . A critical aspect of the stacked structure is the protection and mechanical support of the 2D TMDs channels, which are vulnerable to contamination and physical damage during fabrication. To ensure structural integrity, each channel is encapsulated by an Al₂O₃ Protection Layer, which offers excellent interface properties and a high dielectric constant. Furthermore, the channels are separated from each other by a Sacrificial (SAC) dielectric layer. This SAC layer serves the dual purpose of reserving space for subsequent gate formation and protecting the TMDs material during the channel release process. Finally, the gate electrode is designed with TiN metal within a High-k Metal Gate (HKMG) stack to minimize gate leakage current and enable stable control of the threshold voltage. Fig. 2. Open in a new tab The fabrication process flow for 2D TMDs 3-Tier CFET SRAM a First Tier, b Second Tier, c Third Tier Process Flow schematic views. The step-by-step process flow is as follows: First Tier (Fig. 2 (a)): The process begins with the formation of the bottom-most transistor (the PU device), including its channel, source/drain regions, Middle-of-Line (MOL) metal interconnects and Middle Dielectric Isolation (MDI). Second Tier (Fig. 2 (b)): The sacrificial and channel material layers are sequentially deposited on top of the first tier. Subsequently, a Replacement Metal Gate (RMG) process is performed. The sacrificial layers are selectively etched to release the protected channel stack. The resulting cavity is then filled with the gate dielectric and gate metal. The gate structure is formed along the sidewalls of the active region (the nanosheet stack), and a sidewall spacer is deposited to define the physical shape of the gate electrode, provide insulation, and suppress gate leakage and SCEs. This Channel-First and Gate-Last approach protects the critical gate dielectric from potential damage during subsequent fabrications, enhancing device reliability. At this stage, Dual Work-function metal engineering is applied to set the appropriate threshold voltages for the PMOS and NMOS devices, respectively. Third Tier and BEOL (Fig. 2 (c)): After completing the lower-level interconnects such as the Buried Power Rail (BPR) and vias at the M0 level, the third tier (containing the PD device) is fabricated using the same process as the second tier. Finally, the full device is completed by processing the Frontside and Backside Back-End-of-Line (BEOL) layers to connect the signal and power lines. Device-to-circuit simulation framework To comprehensively evaluate the performance of the proposed 2D TMDs-based 3-Tier CFET 6T-SRAM and compare it with the Conv. 2-Tier structure, a hierarchical simulation workflow was established. This workflow encompasses the entire process from device-level physical modeling to circuit-level performance analysis. As summarized in the flowchart in Fig. 3 (a), the framework consists of four key stages: (1) 3D Structure Design, (2) TCAD Device Simulation, (3) Parasitic RC Extraction, and (4) SPICE Circuit Simulation. Fig. 3. Open in a new tab The Comprehensive Process Sequence for calibration, simulation and modeling. a The process consists of four main stages: Structure Design, TCAD simulation based on 2D material channel modeling, RC Extraction and SPICE modeling. b The TCAD tool is calibrated against experimental data. c The TCAD simulation results (solid lines) show excellent agreement with the extracted SPICE model (dotted lines) Conv. CFET. The initial stage of the simulation involves designing the virtual 3D device structures. As shown in Fig. 1 (a), two primary architectures were designed for comparative analysis: the Conv. 2-Tier CFET 6T-SRAM, where the PD and PG transistors are arranged horizontally, and the proposed 3-Tier CFET 6T-SRAM, which features a vertical stack of PU, PD, and PG transistors. To obtain accurate and reliable simulation results, the physical behavior and electrical characteristics of each transistor were simulated using the Sentaurus Device tool, following a systematic process of material property definition, physics-based model setup, and experimental data calibration. First, to ensure the reliability of the physics-based models, a calibration process was performed against measured data from actual 2D GAA-FET devices fabricated by IMEC 33 . As shown in Fig. 3 (b), the simulation parameters were systematically tuned to achieve a high degree of correlation between the measured current-voltage (I-V) characteristics and the TCAD simulation results, thereby ensuring the predictive accuracy of the models. To achieve this high level of accuracy, material properties were carefully defined. Key parameters for the MoS₂ and WSe₂ channels, such as bandgap, electron affinity, effective mass, and permittivity, were defined based on Density Functional Theory (DFT) calculation results. Notably, to accurately model the anisotropic nature of 2D materials, where electrical properties differ depending on the crystal direction, distinct permittivity values were applied for the in-plane and out-of-plane directions. The key material parameters used in the simulation are detailed in Table 3 . Table 3. Material property parameters. Type Parameters Value NMOS (MoS 2 Monolayer) Dielectric constant of in-plane (ε ∥ ) 34 15.5 Dielectric constant of out-of-plane (ε ⊥ ) 34 6.2 Energy band gap (E g ) 35 1.58 [eV] Electron affinity (χ) 35 4.33 [eV] Effective mass of electron (me * /m 0 ) 36 0.506 Effective mass of hole (mh * /m 0 ) 36 0.543 PMOS (WSe 2 Monolayer) Dielectric constant of in-plane (ε ∥ ) 34 15.6 Dielectric constant of out-of-plane (ε ⊥ ) 34 7.4 Energy band gap (E g ) 35 1.21 [eV] Electron affinity (χ) 35 3.65 [eV] Effective mass of electron (me * /m 0 ) 36 0.345 Effective mass of hole (mh * /m 0 ) 36 0.341 Gate Dielectric (HfO 2 ) Dielectric constant (ε 0 ) 23 Gate Spacer (Si 3 N 4 ) Dielectric constant (ε 0 ) 2.7 S/D Metal Resistivity 9.81 × 10 − 6 Ω·cm M0 Metal (W) Resistivity 37 3.9 × 10 − 5 Ω·cm Open in a new tab The carrier transport phenomena within the 2D nanosheet channels were modeled using a combination of physics-based models. The fundamental charge carrier behavior was described using the Drift-Diffusion transport model. To account for the various scattering phenomena that occur in a realistic device environment, a comprehensive mobility model was implemented. The Thin Layer Inversion and Accumulation Mobility model was used to reflect surface roughness scattering, 2D Coulomb scattering, and phonon scattering within the thin-film channel. Additionally, the High-Field Saturation model was applied to simulate the velocity saturation effects that occur under high electric fields. With the calibrated model, performance optimization was conducted by varying the number of nanosheet stacks for each transistor in the 3-Tier SRAM structure from two to four. Modifying the number of stacks not only alters the device characteristics by changing the external and channel resistance 38 , but also adjusts the relative strengths of the PU, PD, and PG transistors, thereby changing the SRAM’s operational characteristics. A total of four SRAM cell configurations were designed and simulated for this analysis. Conv. (3P3N): The baseline model based on the Conv. 2-Tier structure 39 , with each of the PU, PD, and PG transistors having 3 nanosheet stacks (PU: PD: PG = 3:3:3). 3-Tier (3P3N): The proposed 3-Tier structure with the same 3:3:3 stack ratio as the conventional cell, designed to isolate the performance impact of the structural change. 3-Tier (2P3N): A model with a weakened PU transistor (PU: PD: PG = 2:3:3), aimed at improving the Write Margin and reducing write power. 3-Tier (2P4N+3N_Access): The final proposed optimized model, based on the 2P3N structure but with a strengthened PD transistor (PU: PD: PG = 2:4:3), designed to maximize Read Speed. The parasitic resistance and capacitance that arise from the device structure and interconnects were precisely modeled. The parasitic RC components for each 3D SRAM structure were extracted using the Synopsys Raphael tool. The extraction scope included the entire path 40 from the source/drain (S/D), gate, and via contacts at the M0 level to the WL and BL/BLB metal lines and interconnects at the M1 and M2 levels. The extracted RC values were used to create a segmented model for each node in the SRAM cell. Critically, for metal films thinner than 10 nm, the size effect, where surface and grain boundary scattering increases resistivity as the film thickness approaches the electron mean free path, becomes significant. As reported in studies by institutions 41 , this physical phenomenon was incorporated into our simulation by applying thickness-dependent resistivity values for the metal layers, as specified in Table 3 . The final stage involved integrating the device-level physical characteristics into a circuit-level simulation using HSPICE to evaluate key performance metrics such as SNM, access time, and Energy-Delay Product (EDP). First, the I-V and C-V data obtained from the TCAD simulations for each transistor were used to extract BSIM-CMG parameters and create a compact model. Figure 3 (c) shows excellent agreement between TCAD and the extracted SPICE model. Next, a complete SPICE netlist was constructed by integrating compact models with the parasitic RC components extracted in the third stage. To ensure the relevance of our simulations to future technology nodes, all electrical characteristics were evaluated at a supply voltage of 0.6 V, as specified by the IRDS 2023 roadmap for the 1 nm node. The results and discussion Parasitic RC decomposition in various CFET architectures In this chapter, we investigate the performance optimization of the proposed 3-Tier CFET 6T-SRAM structure and conduct a quantitative comparative analysis against the Conv. 2-Tier architecture. The subsequent analysis provides a detailed comparative evaluation of key performance metrics based on the simulation results for each structure. This section analyzes the variations in parasitic components stemming from the structural differences between the proposed 3-Tier CFET SRAM and the Conv. SRAM. Figure 4 (a), (b), and (c) schematically illustrate the parasitic RC components between major nodes—such as the wordline (WL), bitline (BL), and internal storage node (Q) and adjacent elements, alongside cross-sectional views of each SRAM structure. Fig. 4. Open in a new tab a Schematic cross-sectional views illustrating the key parasitic resistance and capacitance components in the Conv. (2-Tier) and the proposed 3-Tier CFET 6T-SRAM architectures (a) Y-Y’ Cut View. b , c X-X’ Cut View of Conv. and 3-Tier SRAM each. Comparative analysis of parasitic components for the designs with varying nanosheet stack configurations (PU: PD: PG ratios) d Extracted MOL+BEOL resistance for critical nodes such as the BL, WL, Q/QB-node, and power rails (VDD, VSS) e Segmentation of the total BL capacitance, showing the proportional contribution from adjacent nodes. f Of its internal storage Q node Capacitance. g Of its total WL Capacitance. As depicted in Fig. 4 (d), which presents the nodal resistances at the BEOL and MOL levels, the most notable characteristic is the substantial increase in the Q and QB node resistance for the 3-Tier structure. It measures approximately 156.4Ω, an 87% increase compared to the 83.6Ω of the Conv. structure. This is attributed to the inherent vertical stacking of the 3-Tier architecture, which results in a more intricate current path connecting the internal nodes to the BL and power lines, thereby incurring additional via resistance. For the 3-Tier (2P3N) and 3-Tier (2P4N+3N_Access) models, reducing the number of PU transistor stacks from three to two resulted in a VDD path resistance of 41.1Ω, a decrease of approximately 20% from 51.4Ω. This reduction is because the decrease in PU transistor stacks lowers the overall vertical height of the device. Consequently, the vertical length of the via connecting the upper VDD metal line to the source of the PU transistor is shortened. Since via resistance is directly proportional to its length, this shortened via is a key factor in reducing the total parasitic resistance of the VDD power supply path. The BL resistance exhibited a slight increasing trend in the 3-Tier structures, which is attributed to the increased length of the BL interconnects. The resistance values varied noticeably with the adjustment of nanosheet stacks within the 3-Tier architecture. This elevated resistance represents a potential drawback of the 3-Tier design, implying that it could adversely affect the DC margin. The analysis of BL capacitance in Fig. 4 (e) reveals that the total BL capacitance is nearly identical across the structures, measuring approximately 63.9aF for the Conv. (3P3N) structure and 63.6aF for all 3-Tier structures. In the Conv. (3P3N) design, the coupling capacitance with the WL is the dominant component at 52.0aF, accounting for about 81.3% of the total. This is due to the larger interacting area between the source/drain metal connected to the BL and the WL gate metal in the more spread-out 2-Tier layout. Furthermore, coupling with the internal storage node (Q) is also significant at 8.4aF (approx. 13.1%), as the planar layout places the diffusion regions and local interconnects of the Q node in close physical proximity to the BL vias and metal lines. Conversely, the 3-Tier structure, with its scaled footprint achieved through vertical stacking, reduces interaction with the WL and Q nodes, lowering the WL-BL coupling to 47.3aF. Moreover, the vertical separation between the Q node (connected to the lower inverter) and the BL (connected to the upper PG) ensures that Q-BL coupling drops significantly to less than 0.9aF. However, this reduction is almost entirely offset by a sharp increase in lateral coupling capacitance with the adjacent bitline bar (BLB), which rises to 12.5aF (approx. 19.6%) due to the narrowed cell pitch. In conclusion, the 3-Tier architecture exhibits a structural trade-off: it reduces vertical parasitic capacitance (vs. WL, Q) at the expense of increased horizontal capacitance (vs. BLB), resulting in a total BL capacitance comparable to that of the Conv. (3P3N) structure. As shown in the Q-node capacitance analysis in Fig. 4 (f), the total Q-node capacitance of the Conv. (3P3N) structure is approximately 377.9aF. In contrast, the 3-Tier (3P3N) structure with the same stack ratio exhibits a capacitance of 328.8aF, a reduction of about 13%. This demonstrates that the miniaturization achieved through the vertical stacking of the 3-Tier architecture is effective in reducing interactions between the internal node and surrounding conductors, thereby lowering parasitic capacitance. The 3-Tier (2P3N) model shows a further 10% reduction in total capacitance to 294.9aF compared to the 3-Tier (3P3N) model (328.8aF). The primary reasons for this decrease are the reduction in coupling with the QB node (from 170.1aF to 149.2aF) and with VDD (from 47.8aF to 36.7aF). This is a result of the smaller physical size of the weakened PU transistor (2P), which reduces the interaction between the Q node and the gate (connected to QB) and drain (connected to VDD) of that transistor. In the case of the 3-Tier (2P4N+3N_Access) model, the increased number of PD stacks to four leads to an increase in coupling with VSS to 76.2aF, causing the total capacitance to rise back to 327.7aF, a level similar to the 3-Tier (3P3N) model. In summary, the 3-Tier architecture effectively reduces Q-node capacitance compared to the Conv. structure. Finally, the WL capacitance, as shown in Fig. 4 (g), also demonstrates a significant reduction of approximately 40% in the 3-Tier structures compared to the Conv. structure. However, in modern industrial technology, the RC characteristics of the wordline are predominantly determined by array-level design variables, such as the wordline driver design, array size, and interconnect materials 42 – 45 . Therefore, this paper focuses exclusively on the optimization of the bitcell itself, which is directly related to read/write performance, and does not delve into a detailed performance analysis of the wordline, as that would require array-level optimization. Static stability evaluation The static stability of an SRAM cell is a key performance metric that represents its ability to reliably retain data without corruption from external noise. Figure 5 (a) presents a comparison of the extracted Hold Static Noise Margin (HSNM) and Read Static Noise Margin (RSNM) values for each SRAM structure. Furthermore, Fig. 5 (b) visually illustrates the changes in stability for the 3-Tier structures through their Voltage Transfer Characteristic (VTC) butterfly curves during a read operation. HSNM and RSNM were measured using the butterfly curve method, where the maximum square inscribed in the smallest lobe of the curve determines the margin 5 , 46 . Fig. 5. Open in a new tab Static Noise Margin (SNM) comparison and VTC (Voltage Transfer Characteristic) butterfly curves for the different SRAM architectures. a The bar chart compares the extracted Hold Static Noise Margin (HSNM) and Read Static Noise Margin (RSNM) for all four SRAM configurations. b The plot presents the VTC butterfly curves for the three 3-Tier models under the read condition. First, a comparison of stability was made between the Conv. (3P3N) and 3-Tier (3P3N) models, which share the same 3P3N transistor configuration. As shown in Fig. 5 (a), both models exhibit identical values for HSNM (214mV) and RSNM (201.4mV). This outcome is directly correlated with the parasitic resistance characteristics analyzed previously (Fig. 4 (d)). In the Hold state, the access transistors are turned off, isolating the cell from the external bitlines; thus, cell stability is determined solely by the internal inverter latch. The VTC of this latch is defined by the relative strengths of the PU path (VDD resistance) and the PD path (VSS resistance). Since the VDD and VSS path resistances are identical for both models, their HSNM values are also identical. Similarly, during the Read state, the VSS resistance of the PD transistor is the dominant factor for stability. As this path resistance is also the same in both models, no difference in RSNM is observed. Consequently, these results indicate that the structural transition from a 2-Tier to a 3-Tier architecture, in itself, has a negligible effect on the cell’s static stability, provided that the relative transistor strengths are maintained. Figure 5 (a) reveals a trend of gradually decreasing static stability as the transistor stacks are adjusted within the 3-Tier architecture. Compared to the baseline 3-Tier (3P3N) model, the final proposed 3-Tier (2P4N+3N_Access) model exhibits a 4.8% reduction in HSNM and a 6.5% reduction in RSNM. While this stability degradation is partly due to subtle variations in the VSS and VDD path resistances, a more fundamental cause is the VTC asymmetric imbalance resulting from the altered PU: PD transistor strength ratio. The 3P3N model, which has the highest stability, is a symmetric structure with a balanced PU and PD strength. In contrast, the 2P3N and 2P4N models are intentionally designed with an asymmetric structure, weakening the PU while strengthening the PD, to enhance write performance and read speed. This asymmetry lowers the inverter’s switching threshold voltage (V th ), inducing a leftward shift in the inverter’s VTC. This shift, as seen in the butterfly curves of Fig. 5 (b), reduces the area of the inner square, thereby degrading the RSNM. The write stability of an SRAM cell is evaluated by the Write Static Noise Margin (WSNM). WSNM was estimated from a combination of read and write VTCs, which reflects the ease of flipping the storage node during write operations 47 , 48 . As observed in Fig. 6 (a) at a 0.6 V supply voltage, the Conv. (3P3N) model (87.6mV) exhibits a marginally higher WSNM than the 3-Tier (3P3N) model (86.3mV) by approximately 1.3mV. The resistance data from Fig. 4 (d) indicates that the VDD path resistance for both models is nearly identical at 51.4 Ω, suggesting that their PU transistors have equal strength. The origin of the WSNM difference lies in the parasitic resistance of the PG transistor path. The resistances associated with the bitline (BL/BLB) and internal node (Q/QB) in the 3-Tier model are significantly higher than in the Conv. model; for instance, the Q-node resistance increases from 83.6 Ω to 156.4 Ω. This elevated resistance implies that the PG transistor in the 3-Tier model effectively possesses a weaker current driving capability than its Conv. counterpart. Fig. 6. Open in a new tab Write Static Noise Margin (WSNM) as a function of supply voltage (VDD) and associated VTC curves for the SRAM configurations. a The line graph illustrates the WSNM for all four SRAM models across a VDD range from 0.2 V to 0.6 V. b VTC curves during the write operation for the three 3-Tier models. In contrast, the 3-Tier (2P3N) and 3-Tier (2P4N+3N_Access) models, which lower the relative PU: PG strength ratio by reducing the number of PU transistor stacks from three to two, show a substantial improvement in WSNM. Notably, the 3-Tier (2P3N) model achieves the highest WSNM of 121.2mV, representing an approximately 40% enhancement over the 3-Tier (3P3N) model. This result validates that the design strategy of weakening the PU transistor is highly effective for improving WSNM. A key observation is that the 2P3N model exhibits a higher WSNM than the 2P4N+3N_Access model (115.7mV). Since the VDD path resistance for the PU is identical for both models at 41.1 Ω (Fig. 4 (d)), this discrepancy can be attributed to the effect of varying PD transistor strength. The inverter’s switching threshold voltage, or trip point, is determined by the PD: PU strength ratio. The 2P4N model, with its stronger PD, consequently, has a lower trip point than the 2P3N model, which is confirmed by the leftward shift of its VTC curve in Fig. 6 (b). A successful write operation requires the PG transistor to pull the internal node voltage below this trip point. Therefore, the lower trip point of the 2P4N model presents a more challenging write target, which explains why its WSNM is lower than that of the 2P3N model. Furthermore, the graph in Fig. 6 (a) holds additional significance as it illustrates the WSNM behavior under VDD scaling, which is critical for low-power operation. While all models follow the general trend of decreasing WSNM at lower voltages, their relative performance ranking remains consistent down to the ultra-low voltage region of 0.2 V. The 3-Tier (2P3N) model, in particular, demonstrates superior WSNM characteristics not only at 0.6 V but across the entire voltage sweep. For instance, at 0.4 V, the WSNM of the 2P3N model is 92.1mV, maintaining an approximately 30% larger margin compared to the 70.8mV of the 3P3N model. This serves as compelling evidence that optimizing the PU stack count is a highly effective strategy, not only for enhancing performance at a nominal voltage but also for securing robustness across a wide range of operating voltages. Access time and dynamic performance This section provides a comparative analysis of the dynamic performance of the proposed 3-Tier and Conv. structures by evaluating the Read Access Time (RAT) and Write Access Time (WAT) for each model. The results are then comprehensively discussed, linking them to the previously analyzed parasitic RC components and transistor characteristics. Performance metrics extracted at the single-bitcell level are insufficient to accurately predict behavior in real-world memory array environments. This is because, in an array context, the substantial RC loads of the wordlines and bitlines profoundly impact the cell’s operational speed. Therefore, to extrapolate array-level performance from single-cell characteristics, this study establishes a simulation framework that emulates the access times of a 32 × 32 SRAM array. This was accomplished by implementing a Distributed RC model, which projects the total wordline and bitline loads based on the parasitic RC parameters extracted from a single bitcell. RAT, a key indicator of SRAM read speed, is defined as the time required for the BL differential voltage (ΔBL) to reach a target magnitude following the activation of the WL, representing a typical sensing margin. RAT is defined as the time gap between the WL activation to the moment when the BL is discharged by 50 mV from its initial high precharged value during read operation 22 . Transitioning from the Conv. to the 3-Tier (3P3N) structure resulted in a minor RAT increase of approximately 3.7%, from 197.1ps to 204.4ps. This can be explained by the principle of RC delay (τ = R⋅C). In this context, C corresponds to the total bitline capacitance (C BL​ ), and R represents the effective resistance (R path ​) of the discharge path through the series-connected PD and PG transistors. While the C BL ​ was nearly identical for both models (see Fig. 4 (e)), the access path resistance (BL, BLB resistance) of the 3-Tier model was higher due to its structural complexity (see Fig. 4 (d)). This increased R value served as the primary contributor to the longer RAT. Within the 3-Tier architecture, the 2P3N model, featuring a weakened PU stack, exhibited a 1.6% longer RAT of 207.6ps compared to the 3-Tier (3P3N) model. This is attributed to the weakened PU in the 2P3N model, which slightly destabilizes the opposing node (QB) during the transient state of a read operation 49 , 50 . This leads to a minute reduction in the gate voltage of the PD transistor, ultimately causing a slight decrease in the read current (I read ​). This correlation is evident in the first-order approximation model shown in Eq. ( 1 ), which also views the RC delay from a current-based perspective. RAT (T read ​) is proportional to C BL ​ and inversely proportional to the I read ​. Since the C BL ​ of the 2P3N model showed no significant difference from the 3-Tier (3P3N) model (see Fig. 4 (e)), the slight reduction in I read ​ observed in Fig. 9 (b) was the direct cause of the increased RAT in Fig. 7 (red bars). 1 2 Fig. 9. Open in a new tab Dynamic performance analysis comparing normalized energy consumption, power dissipation, and read transient behavior for the four SRAM configurations. a Normalized read and write energy consumption per operation, with the Conv. (3P3N) model as the baseline (1X). b Simulated transient waveforms for the read operation. The upper plot shows the bitline (BL) voltage discharge, while the lower plot shows the corresponding read current (I read ). c Normalized read and write power dissipation. Fig. 7. Open in a new tab Comparison of Read Access Time (RAT) and Write Access Time (WAT) for the four SRAM configurations. In the final proposed 2P4N structure, the fastest RAT of 173.6ps was achieved, representing a remarkable 11.9% speed enhancement compared to the Conv. model. This performance gain is attributed to the intentional strengthening of the PD transistor (4-nanosheet) to maximize the I read , unlike the other models. The current graph in Fig. 9 (b) clearly confirms that the 2P4N model (red line) possesses the highest read drive current. Furthermore, the steep slope of its BL voltage curve indicates the fastest discharge rate. This robust current driving capability results in a RAT improvement substantial enough to more than offset the drawbacks from parasitic resistance and capacitance present in the other models. WAT is the time required to flip the state of the cell’s internal storage node (Q). WAT is defined as the time elapsed from the moment the WL reaches 50% of VDD until the internal storage nodes (Q and QB) intersect each other during write operation 51 . The WAT results in Fig. 7 (blue bars) show that all 3-Tier structures exhibit a distinct performance improvement over the Conv. structure. The WAT for the Conv. model was 107.1ps, whereas the 3-Tier models showed a progressive reduction in time: the 3-Tier (3P3N) model recorded 101.3ps (−5.4%), the 3-Tier (2P3N) model 100.7ps (−6.0%), and the 3-Tier (2P4N) model achieved the fastest time of 100.3ps (−6.3%). The primary underlying reason for this enhancement is the lower internal node capacitance (C node ​) inherent to the 3-Tier architecture. As indicated by Eq. ( 2 ), WAT(T write ) is determined by the C node​ and the write current (I write ​). As established in Fig. 4 (f) and the associated data, the 3-Tier structures possess 13–22% lower C node​ values than the Conv. structure. The smaller total load that needs to be charged/discharged directly reduces the time required to flip the node’s state. Within the 3-Tier models, a clear trend emerges where a weaker PU transistor (2P) leads to a faster WAT. This is because during the contention between the PU and the PG transistor in a write operation, a weaker PU is more easily overpowered, thus facilitating the process. The faster WAT of the 2P3N and 2P4N models compared to the 3P3N model demonstrates the successful implementation of this design intention. Notably, the 2P4N model achieved the best WAT despite having a strong PD, which lowers the inverter’s trip point and presents an initial disadvantage for writing 52 . This drawback was overcome by the regenerative feedback effect of the SRAM circuit 45 . Once the node voltage crosses the lowered trip point, the strong PD transistor works in concert with the PG to rapidly discharge the Q node to VSS, compensating for the initial loss and ultimately securing the fastest WAT. In conclusion, the final proposed model, 3-Tier (2P4N+3N_Access), achieved the most superior WAT owing to a synergistic combination of three factors: (1) the inherently low C node ​ of the 3-Tier structure, (2) the adoption of a write-friendly weak PU (2P), and (3) the use of a strong PG (3 N). Process variation analysis: statistical distributions of noise margin and access time To test the robustness of our proposed 3-Tier (2P4N+3N_Access) CFET SRAM cell against process-induced variations, we performed a 1000-iteration Monte Carlo simulation. This analysis focused on variations in the gate metal work-function (WFV), which is a dominant variability component in advanced nodes. The work-function was randomly varied (using a Gaussian distribution) within a ± 0.1 eV range of the nominal value 10 , assuming this range represents the 6σ (six-sigma) process window. This WFV directly induces statistical variations in the threshold voltage of the individual NMOS and PMOS transistors 53 , which in turn impacts the overall VTCs, SNMs, and access times. The statistical simulation results are summarized in Fig. 8 . Figure 8 (a), (b) show the 1000 superimposed VTCs for the read and write operations, respectively. The read butterfly curves (Fig. 8 (a)) exhibit a stable behavior, while the write VTCs (Fig. 8 (b)) demonstrate consistent switching across all iterations, confirming robust operation under these variations. The statistical distributions of the noise margins are presented in Fig. 8 (c) and (d). For the RSNM shown in Fig. 8 (c), the simulation yields a mean (µ) of 188.12mV and a standard deviation (σ) of 5.20mV. For the WSNM in Fig. 8 (d), a mean of 115.98mV and a standard deviation of 7.25mV are observed. The stability of the read and write margins is evaluated using the cell sigma (µ/σ). The calculated cell sigma values are 36.13 for RSNM and 16.00 for WSNM. These values are well above the 6σ target required for ensuring the robust access disturb margin 54 , which confirms the final-proposed 3-Tier CFET SRAM cell’s high immunity to process variations. Furthermore, the distributions for RAT in Fig. 8 (e) and WAT in Fig. 8 (f) demonstrate the cell’s performance consistency. RAT exhibits a mean of 173.83ps with a standard deviation of 4.48ps. Similarly, WAT shows a mean of 100.26ps with a very tight standard deviation of 0.3761ps. This performance consistency is also quantified using cell sigma. RAT achieves a cell sigma value of 38.84, while WAT shows an exceptionally high value of 266.59. These high ratios, where the standard deviation is a small fraction of the mean, indicate that the cell’s speed performance is highly consistent and robustly stable against the WFV. Fig. 8. Open in a new tab Statistical variability analysis of the 3-Tier (2P4N+3N_Access) SRAM cell under gate work-function variations (WFV) using 1000 iterations of Monte Carlo simulations at V DD = 0.6 V. a , b Superimposed Voltage transfer characteristics (VTCs) representing the read and write operation butterfly curves, respectively. c , d Statistical distribution of RSNM and WSNM, respectively. e , f Statistical distribution of RAT and WAT, respectively. Dynamic performance: power and energy efficiency The dynamic performance of an SRAM is determined not only by its speed but also by the energy and power consumed during each operation. As energy efficiency is a critical design objective, particularly for low-power applications, this section provides an in-depth comparative analysis of the dynamic energy and power consumption characteristics of each SRAM structure. The dynamic energy (E Dyn ​) of an SRAM cell is calculated by integrating the total current (I total ​) drawn from the supply voltage (V DD ​) over the duration of a specific operation (read or write), as shown in Eq. (3). Here, T WL ​ is the time when the WL activation begins, and T Access ​ represents the access time of the operation (RAT or WAT). The average dynamic power (P Dyn​ ) is the dynamic energy divided by the T Access , serving as a measure of the circuit’s instantaneous load, and is defined in Eq. (4). Figure 9(a) and (c) show the read/write energy and power consumption for each model, calculated using these formulas and normalized to the Conv. (3P3N) model (1X). 3 4 For the read operation, the energy and power metrics exhibit divergent trends, clearly illustrating a performance trade-off depending on the design goals. As seen in Fig. 9 (a), only a marginal energy reduction of approximately 3.0% to 3.5% was observed across all 3-Tier models. Although the RAT and I read​ varied among the models, the total energy required to complete a single read operation was similarly, albeit slightly, improved. However, a notable performance trade-off emerges in the read power analysis in Fig. 9 (c). While the 3-Tier (3P3N) and (2P3N) models showed power reductions of 6.5% and 7.9%, respectively, the final proposed model with the fastest read speed, 3-Tier (2P4N+3N_Access), conversely exhibited a 9.5% increase in read power. This is clearly explained by the read current graph in Fig. 9 (b). The 2P4N model possesses the largest I read​ due to its strengthened PD transistor. Since instantaneous power is the product of voltage and current (P = V⋅I), the 2P4N model, which draws the most current, naturally has the highest instantaneous power consumption. Although its RAT was the shortest, the higher current drawn during that period resulted in an overall increase in average power. In terms of write operation energy efficiency, all 3-Tier models demonstrated a commanding improvement over the Conv. model. As shown in Fig. 9 (a), the 3-Tier (3P3N) model achieved a 42.8% reduction in write energy, while the 3-Tier (2P3N) model, which has a weakened PU transistor, attained the largest energy savings of 50.3%. The final proposed model, 3-Tier (2P4N+3N_Access), also showed a high energy efficiency improvement of 46.4%. This dramatic energy reduction is primarily attributed to the low C node​ of the 3-Tier structure. Since the write operation is the process of charging or discharging this C node ​, the smaller capacitive load itself significantly reduces the energy consumed. Write power in Fig. 9 (c) follows a similar trend to energy, showing a substantial reduction of over 39.5% for all 3-Tier models. This is because less energy was consumed over a shorter WAT, thanks to the reduced C node ​ and optimized stack ratio design. In conclusion, the proposed 3-Tier structure achieves noticeable improvements in write speed, energy, and power efficiency for the write operation compared to the Conv. structure. For the read operation, a design choice is available: one can either sacrifice some power for speed (as in the 2P4N model) or prioritize power efficiency (as in the 3P3N and 2P3N models). Energy-delay product and scalability analysis Figure 10 (a) presents the normalized Total Dynamic Energy, calculated by summing the dynamic energies consumed during read and write operations, and the Energy-Delay Product (EDP), a key figure-of-merit for evaluating both speed and energy efficiency concurrently. The EDP is calculated as shown in Eq. ( 5 ); a lower value signifies the ability to perform faster operations with less energy, thus representing superior overall performance efficiency. 5 Fig. 10. Open in a new tab EDP performance summary and scalability analysis of the different SRAM architectures. a Normalized total dynamic energy (sum of read and write operations) and normalized Energy-Delay Product (EDP) for the four models, benchmarked against the Conv. case(1X). b – d Scalability pentagon charts comparing the performance of the three 3-Tier models against the Conv. (3P3N) baseline. A larger enclosed area indicates superior overall performance relative to the Conv. design. In terms of Total Dynamic Energy, all 3-Tier models demonstrated an improvement of over 12.6% compared to the Conv. model. The 3-Tier (2P3N) model, in particular, recorded the largest energy reduction of 23.0%, primarily due to its commanding energy savings in the write operation (−50.3%). The EDP analysis, however, reveals that the final proposed model, 3-Tier (2P4N+3N_Access), achieved the highest efficiency with a 24.9% reduction compared to the Conv. model. Although this model’s total energy consumption (−21.7%) was marginally higher than that of the 2P3N model (−23.0%), it achieved a substantially shorter RAT. According to Eq. ( 5 ), the superior speed enhancement (Delay reduction) of the 2P4N model more than compensated for the minor energy trade-off, allowing it to achieve the best energy-delay efficiency. Figure 10 (b), (c), and (d) compare the performance of each 3-Tier model against the Conv. model using a Scalability Pentagon chart, with the five vertices representing key performance metrics: RSNM, WSNM, 1/RAT (Read Speed), 1/WAT (Write Speed), and 1/EDP (EDP Efficiency). A larger area signifies better overall performance. Figure 10 (b) 3-Tier (3P3N): This model shows a distinct improvement in write speed and EDP efficiency over the Conv. structure, which is an effect of the lower parasitic capacitance inherent to the 3-Tier design. However, its read speed is slightly degraded, while its stability metrics (RSNM, WSNM) remain at nearly the same level. Figure 10 (c) 3-Tier (2P3N): This model exhibits a profile highly specialized for write performance. Owing to its weakened PU design, it records the greatest improvements in WSNM and write speed among all models. However, this comes at the cost of reduced RSNM and the slowest read speed, indicating its suitability for write-intensive applications. Figure 10 (d) 3-Tier (2P4N+3N_Access): The final proposed structure demonstrates the most balanced and superior overall performance. It simultaneously achieves the best-in-class read speed and excellent write speed, while also recording the highest EDP efficiency. The sole trade-off is a slight reduction in RSNM, but its dominating advantage across all other dynamic performance metrics sufficiently compensates for this. Conclusion To overcome the challenges of conventional SRAM scaling, this study proposed and comprehensively analyzed a novel 6T-SRAM structure that integrates a 3D vertically stacked CFET architecture with 2D TMDs as a next-generation channel material. Through a hierarchical analysis methodology encompassing TCAD simulation for 3D structure design, parasitic RC extraction, and SPICE circuit simulations, we have demonstrated the superiority of the proposed 3-Tier structure over the Conv. 2-Tier architecture. The key conclusions derived from this study are as follows: First, the structural innovation led to significant improvements in integration density and dynamic performance. The proposed 3-Tier CFET 6T-SRAM, by vertically stacking the PU, PD, and PG transistors, reduces the cell area by approximately 29.5% compared to the Conv. 2-Tier structure. This miniaturization had the direct benefit of reducing the internal node’s parasitic capacitance (C node ​) by 13–22%. Consequently, all 3-Tier models exhibited a reduction in WAT of over 4.9% and a substantial decrease in write energy consumption of more than 42%. Second, we successfully managed the critical performance trade-offs inherent in SRAM design. The stability and speed of an SRAM cell are intrinsically linked in a trade-off relationship. While designing a weaker PU transistor to enhance the WSNM, as seen in the 2P3N model, the asymmetry of the VTC curve leads to a slight decrease in read/hold stability (RSNM/HSNM). This study demonstrated that this trade-off can be precisely controlled by adjusting the nanosheet stack ratio of the PU: PD: PG transistors. This provides designers with the flexibility to create designs specialized for write performance (e.g., 2P3N) or those focused on stability (e.g., 3P3N), tailored to specific target applications. Third, we presented an optimized design that balances both read and write dynamic performance. The final proposed model, the 3-Tier (2P4N+3N_Access), maintains a weak PU (2P) to ensure superior write performance while simultaneously strengthening the PD (4 N) to maximize read current, thereby achieving the fastest read speed (RAT, an 11.9% improvement). This is the result of an optimized design that considers the dynamics of both read and write operations. Although there was a marginal increase in instantaneous read power to achieve this speed, the design proved its superior overall efficiency by achieving the largest improvement of 24.9% in the EDP metric, which holistically evaluates speed and energy. This suggests that the proposed structure is a robust and highly viable SRAM solution for next-generation high-performance computing and low-power mobile systems. Fourth, despite the advantages demonstrated by the proposed architecture, it is important to acknowledge potential challenges. A potential disadvantage of remaining surplus transistors floating may lead to additional parasitic resistance and capacitance to the structure. This parasitic load, if left unaddressed, could contribute to performance degradation, such as increased delays, compared to a baseline 6T-only design. However, we propose that this apparent limitation is, in fact, a significant forward-looking advantage of our architecture. These surplus transistors are not a structural defect but an opportunity for functional extensibility. By incorporating additional metal interconnects in the BEOL process, our CFET platform can be seamlessly scaled to realize more advanced SRAM bit-cells, such as 8 T (e.g., for decoupled read ports 51 or 9 T (e.g., feedback-cutting 23 structures, all within the same footprint. This inherent scalability to support future 8T/9T designs highlights the versatility and long-term viability of our proposed multi-tier CFET approach. Lastly, an additional challenge emerges in its dynamic performance. Our analysis indicates that the 3-Tier structure did not achieve significant improvements in RAT compared to that of 2-Tier structure. This is attributed to the increased vertical complexity, which leads to higher overall parasitic resistance components, while the BL capacitance was not substantially reduced. We identify the main cause of this performance bottleneck in our BEOL design selection, where both WL and BL are co-integrated within the same M1 metal level. This M1-centric design inherently increases parasitic RC loading and routing congestion, which counteracts the expected performance benefits. Therefore, to resolve the full performance potential of multi-tier CFETs, future research must extend beyond the single-cell level. A comprehensive, array-level Design-Technology Co-Optimization (DTCO) is required, focusing on optimizing the BEOL interconnect scheme. This future work should explore alternative routing strategies, such as utilizing different metal levels for BL and WL or changing their routing directions. Such optimization of the interconnects based on their metal level and orientation is crucial for minimizing the parasitic RC components and fully realizing the high-speed, high-density advantages of the 3-Tier CFET platform. Supplementary Information Below is the link to the electronic supplementary material. Supplementary Material 1 (23.5KB, docx) Acknowledgements The EDA Tool was supported by the IC Design Education Center. Author contributions Jonghun Lee contributed to the conceptualization, methodology, software, formal analysis, writing – manuscript. Jimyeong Lee provided the methodology and formal analysis. Junyeol Lee took care of data curation and software. Saetbyeol Ahn and Donghyun Jin took care of software. Jongwook Jeon took care of conceptualization, supervision, and writing reviews and editing. All authors reviewed and approved the final version of the manuscript. Funding This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No. RS-2025-23323202), and partly by the National Research Foundation of Korea(NRF) grant funded by the Korea government(MSIT) (RS-2025-12872969). Data availability All the data and methods needed to evaluate the conclusions of this work are present in the main text and figures. Additional data can be requested from the corresponding author. Supplementary Information associated with this article can be found in the online version. Declarations Competing interests The authors declare no competing interests. Footnotes Publisher’s note Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. References 1. Sadaf, M. U. K. et al. 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Supplementary Materials Supplementary Material 1 (23.5KB, docx) Data Availability Statement All the data and methods needed to evaluate the conclusions of this work are present in the main text and figures. Additional data can be requested from the corresponding author. Supplementary Information associated with this article can be found in the online version. Articles from Scientific Reports are provided here courtesy of Nature Publishing Group ACTIONS View on publisher site PDF (3.3 MB) Cite Collections Permalink RESOURCES Similar articles Cited by other articles Links to NCBI Databases Follow NCBI NCBI on X (formerly known as Twitter) NCBI on Facebook NCBI on LinkedIn NCBI on GitHub NCBI RSS feed Connect with NLM NLM on X (formerly known as Twitter) NLM on Facebook NLM on YouTube National Library of Medicine 8600 Rockville Pike Bethesda, MD 20894 Web Policies FOIA HHS Vulnerability Disclosure Help Accessibility Careers NLM NIH HHS USA.gov Back to Top

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