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Amortized Neural Optimization for Pre-Layout Signal Integrity Design Space Exploration using Differentiable Surrogates

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Amortized Neural Optimization for Pre-Layout Signal Integrity Design Space Exploration using Differentiable Surrogates

arXiv:2606.07463v1 [eess.SP] 5 Jun 2026

Julian Withöft, Werner John, Emre Ecik, Ralf Brüning, Jürgen Götze

Abstract—Pre-layout design space exploration (DSE) for highspeed signal integrity (SI) analysis is often limited by the computational cost of simulations and iterative optimization algorithms within modern electronic design automation (EDA) workflows. While machine learning surrogate models accelerate the simulation step, optimizing designs still requires utilizing iterative black-box search methods. This iterative nature scales poorly, making multi-corner sweeps computationally expensive. As a solution, this paper proposes amortized neural optimization (ANO) for pre-layout SI design. ANO entirely eliminates iterative black-box inference by utilizing fully differentiable neural network surrogate models. ANO extracts analytical gradients from the surrogate to train a global optimization policy. Instead of solving the optimization problem repeatedly at inference, the optimization process is learned offline and therefore amortized. Once the ANO policy is trained, it maps different channel contexts directly to near-optimal design parameters in a single deterministic forward pass. The efficiency and accuracy of the ANO framework are demonstrated based on three complex SI design scenarios, including DDR5 decision feedback equalization (DFE), 9-dimensional SerDes Tx/Rx co-equalization, and DDR3 DQS differential pair routing to optimize eye diagram metrics under intra-pair skew constraints. By trading roughly 10% in optimality compared to instance-specific black-box algorithms, it realizes speedups of three to four orders of magnitude. For a large-scale 320,000-instance multi-corner SerDes sweep optimization, ANO collapses what would have taken days of computation using iterative search algorithms into a single batched forward pass that completes in milliseconds. This transforms computationally expensive SI optimization into real-time and interactive pre-layout DSE. Index Terms—Amortized neural optimization, design space exploration, differentiable surrogate model, equalization, highspeed interconnects, neural networks, pre-layout, signal integrity.

I. I NTRODUCTION

P

RE-LAYOUT design space exploration (DSE) for signal integrity (SI) analysis on high-speed interconnects plays an essential role within modern electronic design automation (EDA) workflows to achieve efficient and reliable printed This article is an extended version of a paper accepted for presentation at the 2026 IEEE International Symposium on Electromagnetic Compatibility and Signal/Power Integrity (EMC+SIPI) [1]. This work is funded as part of the research project KI4BoardNet in the funding programme MANNHEIM (BMBF) (Grant numbers 16ME0779/TUDO - 16ME0777/IDMT). The responsibility for this publication is held by the authors only. Julian Withöft, Emre Ecik and Jürgen Götze are with the Information Processing Lab, Faculty for Electrical Engineering and Information Technology, TU Dortmund, Germany (e-mail: {julian.withoeft, emre.ecik, juergen.goetze}@tu-dortmund.de) Werner John is with Pyramide2525, Paderborn, Germany and the Information Processing Lab, Faculty for Electrical Engineering and Information Technology, TU Dortmund, Germany (e-mail: [email protected]) Ralf Brüning is with EMC Technology Center Paderborn, Zuken GmbH, Paderborn, Germany (e-mail: [email protected])

circuit board (PCB) layouts. During this phase, key decisions regarding critical high-speed nets are made, which makes it essential to obtain fast and reliable feedback on which configurations will satisfy target SI specifications. The pre-layout design phase offers the greatest flexibility in the overall design process, as fundamental architectural decisions can still be adjusted with comparatively low cost and effort. Therefore, it represents the stage with the highest degree of design freedom and the greatest impact on overall system performance. However, evaluating the large number of possible designs through conventional simulation-based approaches is time-consuming and costly. Moreover, it requires significant domain expertise, making the process challenging, especially for less experienced designers. In this context, machine learning (ML) methods have great potential in the form of artificial intelligence (AI)-assisted decision support and design assistance EDA tools. By training ML models on large amounts of simulation data, they provide fast SI performance predictions during the pre-layout design exploration phase. This allows designers to analyze the design space much more efficiently and to identify promising configurations early, while also reducing the number of costly design iterations to support SI-compliant PCB development. For ML-driven SI design, significant effort has been dedicated to predicting eye diagram metrics such as eye-height (EH) and eye-width (EW) from PCB design parameters. Different forward modeling approaches have been applied, e.g., neural networks (NNs) [2]–[5], support vector regression (SVR) [2], [6], and Gaussian process regression (GPR) [7]. Other approaches utilized NNs and kernel ridge regression to predict entire inner eye contours for direct mask-compliance checking [8], [9]. However, while these forward surrogates accelerate the SI evaluation step, they do not solve the design optimization problem. Identifying optimal PCB geometries or equalizer settings still requires combining the surrogate with an iterative search algorithm. Historically, SI design optimization has relied on iterative black-box search methods applied either directly based on simulators or layered on top of ML surrogate models. For direct simulation-based tuning, Bayesian optimization (BO) is frequently utilized, for example, for continuous-time linear equalization (CTLE) [10], transmitter-side (Tx) feedforward equalization (FFE) [11], and combined receiver-side (Rx) FFE and decision feedback equalization (DFE) tuning [12], [13]. While BO is very sample-efficient for expensive black-box simulations, a contradiction arises when BO is paired with a fast ML surrogate model, as the probabilistic acquisition function and the underlying Gaussian process introduce mathematical overhead that completely negates the speed of the

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underlying ML surrogate. In contrast, evolutionary algorithms such as genetic algorithms (GAs) [3]–[5] and differential evolution (DE) [14] have been utilized directly in combination with ML surrogates to optimize EH/EW metrics or Tx-side FFE settings. To further reduce search times, hybrid approaches, such as combining SVR surrogates with active-subspace reduction, have been proposed to constrain the search space for FFE, CTLE, and DFE tuning [6]. Even though the population-based methods like GAs are faster compared to BO because they can evaluate batches of candidates simultaneously on the surrogate, they remain fundamentally iterative. As a consequence, for largescale DSE requiring the evaluation of thousands of varying channel configurations, the cumulative runtime of the iterative loop remains prohibitive. More critically, all of these methods treat the surrogate model just as a fast black-box oracle and fail completely to exploit the continuous differentiability and analytical gradients of NN architectures. In order to bypass iterative search completely, inverse modeling approaches attempt to map desired SI targets directly back to the required PCB and equalizer parameters. Direct NN- and SVR-based surrogate models targeted specific transient response metrics such as overshoot and rise time [15], [16], or eye diagram metrics [17], [18]. However, standard direct modeling experiences problems with the ambiguity of SI design, where multiple different combinations of design parameters can result in identical SI metrics. Specialized invertible neural networks (INNs) have proven particularly effective to resolve the one-to-many mapping challenges. The basic implementation was established in [19], which demonstrated INNs based on two CTLE parameters and was later extended in [20] to include a total of five parameters with additional PCB variables like trace length and impedance. Benchmarking in [21] has also demonstrated that INNs are superior in comparison to direct feedforward inverse NNs and conditional generative adversarial networks (cGANs). However, all inverse models suffer from a critical practical limitation as they rely on pre-specified targets. This effectively forces the designer into a guessing game of either risking to request physically infeasible metrics or under-utilizing the channel’s true maximum capacity. Additionally, their probabilistic properties lead to a distribution of potential designs rather than a single deterministic optimal solution, which requires subsequent selection and simulation verification. To realize near-instantaneous inference without requiring pre-defined targets, recent research has moved towards reinforcement learning (RL) and imitation learning. Pure rewardbased RL has been applied to learn global SI optimization policies for tasks such as double data rate (DDR) eye aperture maximization [22], hybrid equalizer optimization for highbandwidth memory (HBM) modules [23], and optimization of transient response parameters in DDR memory systems [24]. In contrast, imitation learning has been utilized to train neural networks that mimic the behavior of expert blackbox optimizers such as GA or BO for reusable FFE/CTLE optimization [25], [26] and dimensioning of vias [27]. However, while the inference is near-instantaneous, training these policy networks requires large datasets from computa-

tionally intensive simulations. Imitation learning is especially constrained by this requirement, as the expert datasets must be generated by the same iterative search algorithms, such as GA or BO, that were previously established as computationally inefficient, which causes the method to inherit their computational overhead. Concurrently, RL suffers from sample inefficiency and the required empirical and fragile reward shaping process. Additionally, there is an architectural mismatch, as RL is designed for complex sequential state transitions and Markov processes rather than the bandit-like singlestep mapping of a channel context to its optimal design parameters. Finally, because both methods train neural networks to obtain global optimization policies based on trial-and-error black-box interactions without access to analytical gradients to efficiently guide the optimization, achieving convergence remains a resource-intensive and sample-inefficient process. Recent methodologies in S-parameter modeling have demonstrated that leveraging the continuous differentiability of neural surrogates allows for direct gradient-based optimization with respect to the design parameters [28]. Gradient descent is more sample-efficient than black-box search or RL, but it still remains a local iterative procedure at core. For optimization, it requires repeated forward and backward passes through the neural network for every new instance and remains susceptible to getting stuck in local minima. To overcome these limitations of iterative search algorithms, inverse modeling, and black-box policy learning, this paper proposes an amortized neural optimization (ANO) framework that utilizes differentiable surrogates for comprehensive prelayout SI-DSE. Building upon the proof-of-concept introduced in [1], this extended work benchmarks the ANO framework against a comprehensive suite of state-of-the-art optimization methods, while demonstrating that the architecture generalizes to different complex SI design tasks, including co-equalization and constrained PCB parameter optimization. This method uses a dual-network setup with a differentiable NN surrogate model and a global ANO policy network to completely change the optimization strategy. Instead of treating SI analysis as a black-box problem, the ANO framework utilizes gradient descent directly through the frozen surrogate [29] to update the weights of the ANO policy network. By utilizing the gradient information, the ANO policy can be trained in a way so it directly minimizes a specific loss function, which is based on a custom objective function for the given optimization scenario. This elegantly avoids guessing fixed a priori performance targets like in inverse modeling, while also providing a much more clear and direct optimization path compared to the fragile reward shaping process required when using RL. While iterative black-box algorithms such as GA or BO applied directly based on simulators may be efficient for tuning a single isolated channel instance, they become computationally prohibitive for large-scale DSE. Even when accelerated with fast ML surrogates, their sequential nature re-introduces a computational bottleneck that must be repeated from scratch for every new design instance, while the ANO framework overcomes this limitation. In alignment with the general principles of amortized optimization [30], the computational

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complexity of the optimization process is amortized offline during the training phase and during inference the learned policy maps physical channel contexts to optimized deterministic design configurations in a single forward pass. This transforms design space sweeps that would have taken multiple days using evolutionary search algorithms into a near-instantaneous process that finishes within milliseconds. To showcase this efficiency and demonstrate the framework’s applicability, the ANO methodology is evaluated across diverse high-speed SI scenarios. To realize these SI optimization tasks, advanced techniques are introduced, such as multi-task learning for shared multi-receiver equalization, and curriculum penalties for constrained physical layout optimization.

there were 45 PCB-related context parameters C, including the transmitter, vias, packages, interconnects, and receivers. The remaining 8 tunable parameters T corresponded to the DFE tap equalization parameters, with four taps assigned to each receiver. Both sets of parameters, C and T , were varied according to the parameter ranges in Table I using Latin hypercube sampling (LHS) to produce a dataset consisting of 40,000 training, 10,000 validation, and 10,000 testing samples.

TABLE I PARAMETER RANGES FOR THE DDR5 DAISY CHAIN [1]

II. S IGNAL I NTEGRITY A PPLICATION E XAMPLES To demonstrate the ANO approach and its feasibility for fast and efficient pre-layout SI design space exploration, three different SI application scenarios were considered. A. DDR5 Daisy Chain DFE Equalization Optimization Firstly, a simplified DDR5 daisy chain interconnect with two receivers (Rx1/Rx2) [31], shown in Fig. 1, was considered [1]. The simulation setup employed a generalized linear transmitter (Tx) model parameterized in accordance with [31], including clock frequency, supply voltage, rise/fall times, internal resistance and capacitance, as well as jitter. In addition, package and via parasitics were incorporated, and the interconnect traces and stubs were represented as frequencydependent lossy transmission lines using multi-segment RLGC ladder networks. At each receiver, on-die termination (ODT), input capacitance, and a 4-tap decision feedback equalizer (DFE) were included to account for receiver-side equalization effects. ODT was treated as a static tunable parameter at both receivers to provide a generalized multi-drop termination abstraction for optimization. However, the proposed ANO framework remains directly applicable to typical far-end ODT and multiDRAM fly-by configurations. The simulations were performed using LTspice [32] with a PRBS-10 excitation. The DFE was subsequently applied in a dedicated post-processing step to the simulated waveform in order to compute the final post-DFE worst-case inner eye contour, which was evaluated at SL = 50 sampling points within the unit interval (UI). This resulted in a 100-dimensional output vector, comprising 50 samples for the upper contour and 50 samples for the lower contour. A total of 53 design parameters were varied to generate the dataset for training the ML surrogate model. Among these, RX1 Via

RX1 Pkg

Stub 1 TX Via TX TX Pkg

TL1

RX1

TL2

Stub 2

RX2 Via

RX2 Pkg

Fig. 1. DDR5 daisy chain PCB structure with two receivers [1].

RX2

Parameter [Unit]

Min.

Max.

Clock Frequency fclock [GHz] Supply Voltage VDDQ [V] Jitter [% of Tclock ] Rise Time [% of Tclock ] Fall Time [% of Tclock ] Tx Resistor RTx [Ω] Tx Capacitance CTx [pF] Tx Package Resistor Rpkg,Tx [Ω] Tx Package Inductor Lpkg,Tx [nH] Tx Package Capacitance Cpkg,Tx [pF] Tx Via Resistor Rvia,Tx [Ω] Tx Via Inductor Lvia,Tx [nH] Tx Via Capacitance Cvia,Tx [pF]

2.4 1.0 0 10 10 30 0.1 0.01 0.1 0.1 0.001 0.1 0.1

3.6 1.4 3 25 25 50 2.0 0.50 1.5 0.8 0.10 0.8 0.4

Transmission Line 1 Length LTL1 [mm] Transmission Line 1 Impedance Z0,TL1 [Ω] Transmission Line 1 Dielectric εr,TL1 Transmission Line 1 Loss Tangent tan δTL1 Stub 1 Length LStub1 [mm] Stub 1 Impedance Z0,Stub1 [Ω] Stub 1 Dielectric εr,Stub1 Stub 1 Loss Tangent tan δStub1

10 30 3 0.003 0.1 30 3 0.003

120 70 5 0.045 10 70 5 0.045

Rx1 Via Resistor Rvia,Rx1 [Ω] Rx1 Via Inductor Lvia,Rx1 [nH] Rx1 Via Capacitance Cvia,Rx1 [pF] Rx1 Package Resistor Rpkg,Rx1 [Ω] Rx1 Package Inductor Lpkg,Rx1 [nH] Rx1 Package Capacitance Cpkg,Rx1 [pF] Rx1 Input Capacitance CRx1 [pF] Rx1 ODT Termination Rodt,Rx1 [Ω] Rx1 DFE Tap 1 Rx1 DFE Tap 2 Rx1 DFE Tap 3 Rx1 DFE Tap 4

0.001 0.1 0.1 0.01 0.1 0.1 0.1 30 -0.40 -0.15 -0.10 -0.08

0.10 0.8 0.4 0.50 1.5 0.8 2.0 120 0.10 0.15 0.10 0.08

Transmission Line 2 Length LTL2 [mm] Transmission Line 2 Impedance Z0,TL2 [Ω] Transmission Line 2 Dielectric εr,TL2 Transmission Line 2 Loss Tangent tan δTL2 Stub 2 Length LStub2 [mm] Stub 2 Impedance Z0,Stub2 [Ω] Stub 2 Dielectric εr,Stub2 Stub 2 Loss Tangent tan δStub2

10 30 3 0.003 0.1 30 3 0.003

80 70 5 0.045 10 70 5 0.045

Rx2 Via Resistor Rvia,Rx2 [Ω] Rx2 Via Inductor Lvia,Rx2 [nH] Rx2 Via Capacitance Cvia,Rx2 [pF] Rx2 Package Resistor Rpkg,Rx2 [Ω] Rx2 Package Inductor Lpkg,Rx2 [nH] Rx2 Package Capacitance Cpkg,Rx2 [pF] Rx2 Input Capacitance CRx2 [pF] Rx2 ODT Termination Rodt,Rx2 [Ω] Rx2 DFE Tap 1 Rx2 DFE Tap 2 Rx2 DFE Tap 3 Rx2 DFE Tap 4

0.001 0.1 0.1 0.01 0.1 0.1 0.1 30 -0.40 -0.15 -0.10 -0.08

0.10 0.8 0.4 0.50 1.5 0.8 2.0 120 0.10 0.15 0.10 0.08

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B. SerDes Co-Equalization Optimization Secondly, a SerDes interconnect architecture incorporating a Tx-side FFE, an Rx-side CTLE, and an Rx-side DFE was analyzed, as shown in Fig. 2. To generate training data, transient simulations with a PRBS-16 stimulus truncated to 50,000 bits were performed in Matlab [33]. A 3-tap FFE was applied at the Tx to pre-compensate the digital bit sequence for expected intersymbol interference (ISI). This signal was then converted into a differential analog Tx waveform by the transmitter, incorporating configurable rise and fall times, differential swing, and jitter. The Tx signal propagated through the transmitter package, vias, and a coupled stripline channel, before reaching the receiver package and vias. At the receiver, the CTLE amplified frequency components attenuated by the channel, compensating for high-frequency loss. This was followed by a 4-tap DFE designed to iteratively cancel residual post-cursor ISI. A total of 34 design parameters, spanning stimulus charac-

TABLE II PARAMETER RANGES FOR THE S ER D ES CHANNEL DESIGN

0.0 0.0 15 1.50 5.00 0.30 0.15 0.10 0.08

Tx Resistor RTx [Ω] Tx Capacitance CTx [pF] Rx Resistor RRx [Ω] Rx Capacitance CRx [pF] Tx Package Inductor Lpkg,Tx [nH] Tx Package Capacitance Cpkg,Tx [pF] Rx Package Inductor Lpkg,Rx [nH] Rx Package Capacitance Cpkg,Rx [pF] Rx RMS Noise [mV]

40 0.1 40 0.1 0.1 0.1 0.1 0.1 0.5

60 0.3 60 0.3 0.8 0.4 0.8 0.4 3.0

Tx Via Inductor Lvia,Tx [nH] Tx Via Pad Capacitance Cpad,Tx [pF] Tx Via Anti-pad Capacitance Canti,Tx [pF] Rx Via Inductor Lvia,Rx [nH] Rx Via Pad Capacitance Cpad,Rx [pF] Rx Via Anti-pad Capacitance Canti,Rx [pF]

0.1 0.10 0.05 0.1 0.10 0.05

0.6 0.25 0.15 0.6 0.25 0.15

Channel Length L [mm] Trace Width W [µm] Trace Spacing S [µm] Substrate Height H [µm] Dielectric Constant εr (Dk ) Loss Tangent tan δ (Df )

10 70 70 70 3.0 0.002

300 300 300 250 5.0 0.030

Fig. 2. SerDes interconnect architecture.

C. DDR3 DQS Eye Optimization under Skew Constraints Finally, to demonstrate that the framework extends beyond equalization tuning to constrained SI optimization tasks, a DDR3 differential data strobe (DQS) interconnect, shown in Fig. 3, was analyzed [4]. In this scenario, the objective was to optimize the microstrip trace geometries and termination to maximize EH and EW while satisfying intra-pair skew constraints. In this setup, the trace width W , differential pair spacing S, and the termination resistor RT served as the tunable design parameters T to control the differential impedance, coupling, and reflection characteristics. The transmission line routing lengths (DL1 , DL2 , DL3 , T L3 ) and the dielectric constant εr defined the fixed physical layout context C. Additionally, to amortize the optimization over varying design specifications, the maximum allowable intra-pair skew threshold was also treated as an explicit dynamically sampled input context C to the framework. The interconnect consisted of a differential stub series terminated logic (DSSTL) point-to-point structure connecting TABLE III PARAMETER RANGES FOR THE DSSTL DDR3 DQS INTERCONNECT [4] Parameter

Min.

Max.

RT = R1 = R2 [Ω] Length DL2 [mm] Length DL1 [mm] Length DL3 [mm] Length T L3 [mm] Trace width W [µm] Diff. pair spacing S [µm] Dielectric constant εr

0 1 1 1 0.1 70 70 4

180 200 200 200 50 300 3500 4.8

Post-EQ RX Signal Out

Via

Via

Channel

DFE

-0.15 -0.35 0 0.30 0.10 -0.30 -0.15 -0.10 -0.08

CTLE

FFE (Tx) Pre-Cursor Tap FFE (Tx) Post-Cursor Tap CTLE (Rx) Boost Magnitude [dB] CTLE (Rx) Pole 1 Ratio [fp1 /fNyq ] CTLE (Rx) Pole 2 Gap Ratio [∆fp2 /fNyq ] DFE (Rx) Tap 1 DFE (Rx) Tap 2 DFE (Rx) Tap 3 DFE (Rx) Tap 4

RX + Pkg

32 1.2 3.0 40

TX + Pkg

Max.

10 0.4 0.1 10

FFE

Min.

Data Rate [Gbps] Differential Swing Vswing [V] Tx Jitter [% of UI] Tx Rise/Fall Times [% of UI]

PRBS Stimulus

Parameter [Unit]

teristics, Tx/Rx equalization parameters, analog front-ends, via and package parasitics, and coupled stripline channel geometry, were varied within the ranges summarized in Table II, while the trace thickness was kept constant at 17 µm (0.5 oz copper). LHS was used to generate datasets comprising 50,000 samples for training, 10,000 for validation, and 10,000 for testing. Each sample produced an eye diagram and the corresponding 1% probability inner eye contour, which was evaluated at SL = 64 samples per UI. This resulted in a 128-dimensional output vector, comprising 64 samples for the upper contour and 64 samples for the lower contour. In this scenario, there were 25 context parameters C describing the physical SerDes channel design as well as Tx/Rx parameters and 9 tunable equalization parameters T determining the active effect of the FFE, CTLE, and DFE.

Fig. 3. DDR3 DQS interconnect [4].

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Tx and Rx via differential transmission lines and a termination branch to half of VDDQ, as typical for DDR3 DQS signals. As shown in Fig. 3, the single-ended transmission line T L3 was added to one leg of the differential pair to artificially create a length imbalance, resulting in increased intra-pair skew and decreased common-mode rejection. Data was generated using simulations in the Zuken eCADSTAR Signal Integrity software [34]. The buffer characteristics were described using IBIS models featuring an Intel Arria V for the Tx and a Micron MT41J256M4DA for the Rx, which operate at an I/O clock frequency of 800 MHz (Speedgrade 1600) at 1.5 V. For the eye diagram simulations, a PRBS10 stimulus was utilized with a 5% uniformly distributed jitter relative to the UI. A total of 20,000 simulations were generated based on LHS within the parameter ranges specified in Table III, which were later divided into an 80-10-10% trainvalidation-test split. The trace thickness, dielectric thickness, and loss tangent were kept constant throughout the simulations at 35 µm, 200 µm, and 0.007, respectively. III. A MORTIZED N EURAL O PTIMIZATION M ETHODOLOGY A. Problem Formulation For pre-layout SI-DSE, the objective is to rapidly obtain design parameters that comply with specific requirements and optimize the SI metric for a given channel. Let the fixed interconnect and PCB context parameters be denoted by the vector C ∈ RNC , and the tunable design parameters by the vector T ∈ RNT . The non-linear physical system is usually evaluated via computational electromagnetic or transient circuit simulations and can be represented as a function f :

Y = f (C, T ),

where Y ∈ RNY represents the extracted SI metrics such as EH, EW, inner eye contour, or intra-pair skew. Traditional search-based optimization aims to find the optimal settings T ∗ that minimize a specific performance objective J(Y ) within the valid parameter space, denoted by T : T ∗ = arg min J(f (C, T )).

(2)

T ∈T

Because f (C, T ) is extracted from computationally expensive simulations, wrapping this system in an iterative search algorithm creates a computational bottleneck, which makes real-time large-scale DSE computationally intractable. B. Differentiable Surrogate Models To overcome the computational inefficiencies of simulation, the physical system f (C, T ) is approximated by an ML surrogate model S(C, T ; θS ) parameterized by its learnable parameters θS . Fully differentiable neural networks are the natural choice over other partially differentiable regression techniques, especially because the subsequent optimization policy requires continuous gradient flow. Depending on the nature of the target SI metric Y , different neural network architectures can be applied. For predicting sequential data, such as the timesteps of an inner eye contour, an encoder-decoder architecture is utilized. As illustrated in Fig. 4 (a), this architecture uses fully-connected layers to transform design parameters into a latent representation, followed by sequence expansion and recurrent processing using

Encoder-Decoder DenseBiLSTM Surrogate Model Architecture for Eye Contour Prediction Input: Context (C) + Tunable Parameters (T)

Fully-Connected MLP Surrogate Model Architecture Input: Context (C) + Tunable Parameters (T)

Feature Extraction

Dense (ReLU, 256)

Dense (ReLU, 256)

Dense (Linear, Y)

Fully-Connected MLP

(1)

Amortized Neural Optimization Training Workflow C Generate Uniform Random Batch in Normalized Space [0,1]

ANO Network Forward Pass

Dense (ReLU, 256)

Dense (ReLU, 256)

Sequence Expansion

RepeatVector (SL)

Recurrent Processing

BiLSTM(256) BiLSTM(256) TimeDistributed (2R)

^ Output: SI Metrics Y (b) Amortized Neural Optimization Architecture Context Parameters (C)

^} ^ {C,T Concat T

Surrogate Model (Frozen Weights)

Tunable Parameters

^ Y Surrogate Output (SI Metrics)

^ Y

Compute ANO Loss

L

ANO Model Dense (ReLU, 256)

...

Dense (ReLU, 256) Dense (Sigm, T)

Output Shape: (SL,2R): Eye Contour of R Rx (a)

^ T

Optimizer updates ANO Weights via Backpropagation

L

^ Tunable Parameters T (c)

(d)

Fig. 4. The proposed generalized amortized neural optimization (ANO) framework. The differentiable surrogate models utilizing either (a) an encoder-decoder Dense-BiLSTM architecture specifically for sequential SI metrics such as inner eye contours or (b) a fully-connected MLP architecture. The ANO policy network (c) predicts the optimal tunable parameters T̂ directly from the given channel context C. In the gradient-based training workflow (d), the ANO loss is calculated from the surrogate’s predictions and the resulting gradients are backpropagated through the frozen surrogate to update the ANO policy network.

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bidirectional long short-term memory (BiLSTM) layers to capture the temporal structure of the inner eye contour at the output. For scalar metrics, such as a single EH or intrapair skew value, a standard multi-layer perceptron (MLP) consisting of only fully-connected layers is utilized, as shown in Fig. 4 (b). Prior to training these surrogate models, all inputs, including C and T , were normalized to [0, 1]. This ensures training stability across the design parameters, which comprise multiple orders of magnitude. Moreover, it also establishes a uniform space for the optimization phase.

optimizer updates only the ANO weights θΠ to adjust the global policy to output parameter settings that satisfy all physical constraints and at the same time maximize the target SI metrics. Through this process, the computational cost is amortized into the neural network weights. While this requires an upfront offline investment to generate training data to train the surrogate models and then based on that the ANO policy network, it results in a globally reusable asset for the entire design space, which shifts the iterative optimization complexity completely to the offline training phase. E. Benchmarking Methodology

C. Amortized Neural Optimization Architecture Black-box optimization algorithms search for the optimal parameters T ∗ iteratively during the inference phase. In contrast, the ANO framework takes a completely different route by training a second neural network. This ANO policy network is denoted as Π(C; θΠ ). As shown in Fig. 4 (c), the ANO policy network only receives the context parameters C as input. Through its hidden fully-connected dense layers, it directly outputs the predicted optimal tunable settings T̂ . The forward pass of this network maps the channel context to the optimal configuration: T̂ = Π(C; θΠ ).

(3)

As the underlying surrogate model operates in the normalized [0, 1] space, the final layer of the ANO policy network employs a sigmoid activation function. This bounds the ANO policy network’s predictions to the exact parameter ranges that were defined during the data generation phase to make sure that all outputs satisfy the valid design space T . This dual-network architecture eliminates the need for an iterative solver during DSE. Once trained, the policy network provides a near-instantaneous and deterministic prediction of the optimal tunable parameters for any given channel configuration. D. Amortized Policy Training via Surrogate Gradients The core of the ANO methodology lies in how the policy network Π is trained without requiring an expert dataset of optimal parameter configurations. This is achieved by utilizing the gradient of the fully differentiable surrogate model. The training workflow is shown in Fig. 4 (d). First, uniform random context parameters C are generated per batch. The ANO network performs a forward pass to predict the tunable parameters T̂ . These predictions and the context parameters C are concatenated and evaluated using the surrogate model. During this phase, the weights of the surrogate model θS are frozen, and it then predicts the SI performance metrics, denoted as Ŷ . A custom loss function L is then computed directly from these predictions, for example, to maximize the target SI performance metrics while penalizing physical constraint violations or performance degradation relative to a baseline configuration. Because the surrogate is fully differentiable, the gradients of this loss are backpropagated through the frozen surrogate model and directly into the ANO policy network. The

To evaluate the proposed ANO framework, its performance is benchmarked against a comprehensive suite of optimization algorithms. To ensure a fair comparison, all baseline algorithms were combined with the same ML surrogate models and using the same objective. The evaluated baselines represent different optimization methodologies: • Gradient-Based: Gradient descent (GD) also directly exploits the continuous differentiability of the neural surrogate based on the objective. GD was realized using the Adam optimizer with a learning rate of 0.05 for a maximum of 200 iterations to ensure convergence while also keeping runtime feasible as each iteration utilizes a computationally more intensive backpropagation pass in addition to the forward pass. • Evolutionary/Swarm: These gradient-free, populationbased methods start with a set of candidate solutions and improve these in an iterative manner inspired by biological processes. The evaluated algorithms include the genetic algorithm (GA) [35], differential evolution (DE) [36], and particle swarm optimization (PSO) [37], all configured with a population size of 100 and executed for 50 generations. Furthermore, the covariance matrix adaptation evolution strategy (CMA-ES) [38] was evaluated using an initial step size σ of 0.3 with a computational budget of 5,000 surrogate evaluations. • Probabilistic: Bayesian optimization (BO) [39] constructs a probabilistic Gaussian process surrogate of the objective function and utilizes an acquisition function to guide the search. BO was executed for a total of 200 optimization steps using expected improvement as the acquisition function. The BO budget had to be limited to 200 steps due to the O(N 3 ) cubic scaling complexity of the underlying Gaussian process, making larger evaluation limits computationally prohibitive. • Heuristic/Search: The Nelder-Mead (NM) simplex method [40] is based on the geometric transformation of a simplex to navigate the search space, while random search (RS) acts as a baseline stochastic sampler. Both methods were limited to a maximum of 5,000 surrogate evaluations. F. Implementation Details For the differentiable surrogate models, training was realized using the Adam optimizer with an initial learning rate of 10−3 and a batch size of 32. The models were trained

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to minimize the mean squared error (MSE) loss with a maximum of 1,000 epochs. To ensure convergence and prevent overfitting, a learning rate schedule was employed alongside an early stopping mechanism with a patience of 50 epochs. The ANO policy networks were subsequently trained using the frozen surrogates. Because the policy networks had to evaluate randomized channel contexts simultaneously, they utilized a significantly larger batch size of 2,048 and a smaller Adam learning rate of 10−4 . Specific epoch counts and customized loss formulations were adapted per experiment based on the nature and complexity of the design scenario. While the trained ANO framework achieves nearinstantaneous inference for DSE, it relies on an upfront offline computational investment to simulate the datasets and train the dual-network models. For transparency and to quantify this one-time investment, the specific runtimes are reported based on the following workstation hardware equipped with an AMD Ryzen 9 7900 CPU (for data generation), an NVIDIA RTX 4080 Super GPU (for model training), and 64 GB of DDR5 RAM. The DDR5 topology required approximately 136.8 hours for data generation, 51.6 minutes for surrogate training, and 121.5 minutes for ANO policy training. The SerDes link required 48.3 hours, 50.2 minutes, and 28 minutes for the same respective stages. Finally, the DDR3 DQS interconnect required 22.8 hours, 3.3 minutes, and 6.4 minutes. Because these represent a one-time investment to map a specific technology domain or interconnect, they are rapidly amortized during large-scale pre-layout DSE. IV. DDR5 DFE E QUALIZATION The first evaluation of ANO focuses on optimizing the DFE settings T of the two receivers in the DDR5 daisy chain interconnect, shown in Fig. 1, based on the given PCB context parameters C [1]. The first requirement for the ANO framework is an accurate and differentiable approximation of the DDR5 interconnect. Table IV confirms that the DenseBiLSTM encoder-decoder surrogate, see Fig. 4 (a), achieves accurate regression metrics on the unseen test dataset, maintaining R2 -scores above 96% and a sample-wise normalized root mean squared error (NRMSE) below 7% across both receivers. This sample-wise metric scales the absolute error not by the global minimum and maximum, but rather by the maximum vertical swing of the inner eye contour to ensure meaningful errors relative to the actual eye opening. Fig. 5 validates this visually by demonstrating that the surrogate predicts inner eye contours, which match the ground-truth simulations well. This accurate and differentiable backbone is what enables the ANO framework to perform gradient-based policy learning. For this dual-receiver DFE optimization task, the ANO policy network was designed with a shared feature-extraction trunk and two independent heads, which output the 4-tap settings for Rx1 and Rx2. The ANO network was trained for 50 epochs. To compute EH during training, it was extracted from the predicted 100-dimensional inner eye contour defined as the minimum vertical distance between the upper and lower contour bounds within a localized sampling window at the

TABLE IV E NCODER - DECODER SURROGATE MODEL REGRESSION ACCURACY METRICS FOR DDR5 EYE CONTOUR PREDICTION ON THE TEST DATASET, AS ESTABLISHED IN [1] Receiver Rx1 Rx2

RMSE [mV]

NRMSE [%]

R2 [%]

27.2 23.6

6.46 6.98

96.11 96.55

Fig. 5. DDR5 encoder-decoder surrogate model prediction example on the test dataset.

center of the UI. The objective was to maximize the post-DFE eye-height improvement, defined as g = EHDFE − EHDFE off at each receiver. To achieve this, the network was trained using a custom loss function L(g): 2

L(g) = λ1 [max(0, −g)] − λ2 ln (1 + max(0, g) · α), | {z } | {z } Quadratic Penalty

(4)

Logarithmic Reward

where the hyperparameters were set to λ1 = 1000, λ2 = 1, and α = 100. This formulation enforces an asymmetric optimization policy. The first term imposes a quadratic penalty to steer the network away from any configuration where the DFE degrades the EH compared to the DFE-off setting. The second term provides a logarithmic reward for EH improvements where the diminishing gradient magnitude of the logarithm prevents the optimizer from overfitting to simple channel instances to promote convergence across the entire design space. Furthermore, to prevent the receiver with heavier signal degradation from producing large gradients and dominating the shared network weights, a multi-task gradient balancing technique was utilized. During backpropagation, the gradient vectors for L(gRx1 ) and L(gRx2 ) were computed independently and divided by their respective magnitudes. This normalized both gradient updates to a unit length before they were summed to ensure that both receiver heads contributed equally to the optimization of the shared trunk. The training process of the ANO policy network is shown in Fig. 6. The loss function converged quickly and then stabilized within the first 2,500 training batches. The network achieved a final improvement success rate of over 95% at both receivers. Because Rx2 is located farther from the Tx in the daisy chain and is therefore more heavily impaired by ISI and signal attenuation, the ANO network learned to apply more aggressive equalization, which resulted in massive post-DFE EH improvements of roughly 80 mV. Rx1 experienced less channel degradation, which resulted in smaller but consistent gains of approximately 40 mV.

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Fig. 6. DDR5 ANO training curves showing loss, post-DFE eye-height, success rates, and ANO-based eye-height improvement for both Rx1 and Rx2.

In order to assess the accuracy and efficiency of the ANO framework, it was evaluated against the suite of optimization methods. The results are summarized in Table V and highlight a massive shift in computational efficiency. Population-based evolutionary and swarm algorithms, such as GA, DE, and PSO achieve near-perfect success rates and slightly higher absolute EH improvements. However, this marginal performance edge comes at a computational cost of over 17 seconds on the CPU and 2.7 seconds on the GPU per channel due to the thousands of sequential surrogate evaluations required per optimization run. CMA-ES only performs slightly worse at Rx2 and slightly better at Rx1 compared to the other evolutionary algorithms, and is even more computationally intensive at 53 seconds on the CPU. Bayesian Optimization (BO) similarly achieves a high success rate of 96% and solid EH improvements, but it is even more bottlenecked computationally due to the cubic scaling complexity of the underlying Gaussian process, which results in an impractical execution time of over 136 seconds on the CPU per channel. In contrast, the ANO framework predicts the near-optimal DFE taps using one single forward pass, which reduces the inference time to just 1 millisecond on the CPU and 4 milliseconds on the GPU, where overhead is dominated by

data transfer for a single evaluation. This represents a speedup of three to four orders of magnitude compared to evolutionary and swarm methods. GD also makes use of the surrogate’s differentiability, but it remains iterative and computationally expensive due to repeated forward and backpropagation steps for each new channel. GD takes 7.5 seconds to converge at slightly worse performance compared to ANO on average. Finally, simpler methods such as NM and RS struggle to find adequate solutions in these complex SI design optimization scenarios. NM collapses with a 32% success rate and small gains, while RS leads to sub-optimal EH improvements, which validates the necessity for global optimization policies. The true practical value of this near-instantaneous inference is demonstrated based on the large-scale SI-DSE shown in Fig. 7 [1]. The green regions indicate feasible design configurations where the ANO-predicted DFE settings successfully satisfy the rectangular-shaped eye mask (70 mV height, 0.4 UI width) across the corner cases 50 Ω ± 10 Ω. Orange regions show design areas where compliance is only achievable under typical 50 Ω conditions, while red regions indicate failure zones where no equalization strategy can rescue the signal. By mapping these SI boundaries, the ANO framework provides a real-time feasibility map for floorplanning and routing. The compliance predictions generated by the ANO framework using the ANO policy DFE settings and the surrogate model for contour prediction were additionally validated using simulations denoted by stars in Fig. 7, which confirmed that the framework reliably maps the feasible design space. This large-scale sweep of a 50 × 50 transmission line length grid across three global Z0 corner cases leads to a total of 7,500 unique channel configurations and exposes the scaling limitations of the other optimization algorithms. Based on the single-run CPU timings established in Table V, it would take approximately 15 hours using gradient descent (GD), 35 hours using standard evolutionary and swarm methods (GA, DE, PSO), over 4 days with CMA-ES, and nearly 12 days using Bayesian Optimization (BO) to sequentially optimize this grid. Even on a GPU, multiple hours of runtime are to be expected. Even though multi-threaded execution can proportionally reduce the runtime for these iterative algorithms, their aggregate computational burden remains immense. In contrast,

TABLE V DDR5 BENCHMARK COMPARISON ( MEANS ) OF OPTIMIZATION METHODS AVERAGED OVER 100 RANDOMIZED CHANNEL CONTEXTS USING CPU AND GPU- ACCELERATED SURROGATE /ANO EVALUATIONS Method

Success

gRx1

gRx2

tCP U

tGP U

ANO GD GA DE PSO CMA-ES BO NM RS

96% 89% 100% 100% 100% 92% 96% 32% 83%

41.4 mV 47.2 mV 51.4 mV 51.5 mV 50.9 mV 52.9 mV 49.6 mV 4.0 mV 27.9 mV

82.3 mV 73.2 mV 84.5 mV 84.4 mV 84.3 mV 74.7 mV 73.3 mV 15.1 mV 56.4 mV

0.001 s 7.5 s 17.2 s 17.1 s 17.6 s 53.7 s 136.4 s 63.8 s 16.1 s

0.004 s 7.8 s 2.7 s 2.8 s 2.8 s 10.3 s 163.4 s 21.7 s 0.160 s

Hardware: AMD Ryzen 9 7900, NVIDIA RTX 4080 Super, 64 GB DDR5 RAM

Fig. 7. SI design space exploration for the DDR5 interconnect using the optimized DFE taps. Adapted from [1] with explicit simulation verification denoted by stars to validate the ANO and surrogate boundary predictions.

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by processing the entire 7,500-point sweep as a single batched input matrix, the ANO framework maps the complete design space in just 30 milliseconds on a standard CPU, and under 2 milliseconds when GPU-accelerated. This transforms an otherwise infeasible or highly resource-intensive optimization task into an instantaneous pre-layout SI-DSE tool. V. S ER D ES C O -E QUALIZATION Following the demonstration of Rx-side DFE optimization in the DDR5 topology, the ANO framework was evaluated for complex co-equalization of the SerDes interconnect, which requires the simultaneous optimization of 9 active equalization parameters T distributed across both the transmitter (FFE) and receiver (CTLE/DFE) to counteract frequency-dependent loss and ISI across a 25-dimensional design space context C. To train the gradient-based ANO policy, an accurate and fully differentiable surrogate model has to be trained first to approximate the inner eye contour of the SerDes link at the receiver. Two neural network architectures were trained and compared, namely a standard fully-connected MLP, see Fig. 4 (b), and a Dense-BiLSTM encoder-decoder, see Fig. 4 (a). The prediction performance of both models on the unseen test dataset is summarized in Table VI. The MLP creates a baseline approximation, but the encoder-decoder architecture demonstrates superior accuracy across all metrics, significantly reducing the error and improving the R2 -score by more than 5%. The underlying reason for this difference in performance becomes clear when inspecting the predicted inner eye contours in comparison to the simulated ground truth, as shown in Fig. 8 for two randomly selected test samples. The MLP predictions (dashed purple) struggle to capture the highly non-linear temporal dynamics of the eye contour, as they tend to overly smooth the contour and miss the maximum

TABLE VI R EGRESSION ACCURACY METRICS FOR MLP VS . D ENSE -B I LSTM SURROGATE MODELS FOR S ER D ES EYE CONTOUR PREDICTION ON THE TEST DATASET

Model

RMSE [mV]

NRMSE [%]

R2 [%]

MLP Enc-Dec

23.21 16.62

7.05 4.39

88.86 94.35

Fig. 8. Two SerDes prediction examples of the MLP and encoder-decoder surrogate models on the test dataset.

Fig. 9. SerDes ANO training curves showing loss, post-EQ eye-height, success rate, and ANO-based EQ eye-height improvement vs. unequalized baseline.

vertical opening. In contrast, the Dense-BiLSTM encoderdecoder (dashed cyan) utilizes its recurrent layers to model the sequential dependencies of the eye contour, which allows it to track the ground-truth contour (solid orange) and capture the exact temporal details required for accurate SI analysis. Due to this superiority in accuracy, the encoder-decoder model was exclusively deployed as the differentiable surrogate backbone for the following SerDes ANO policy training. The ANO policy network was trained to co-optimize the 9 active equalization parameters, including 2 Tx FFE taps, 3 Rx CTLE parameters, and 4 Rx DFE taps, based on the 25-dimensional channel context parameters. The target of maximizing the EH improvement g = EHEQ − EHEQ off remains the same as for the DDR5 scenario, and therefore the policy network was trained using the same asymmetric loss formulation defined in Eq. (4). The EH was similarly extracted from the surrogate’s 128-dimensional predicted eye contour at the UI center. However, in contrast to the DDR5 scenario, this network utilized a single output head to predict all of the tunable equalization parameters together. The training process of the SerDes ANO policy is shown in

Fig. 10. Violin plots statistically visualizing the EH improvement distributions of the benchmark comparison in Table VII.

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TABLE VII S ER D ES BENCHMARK COMPARISON ( MEANS ) OF CO - EQUALIZATION OPTIMIZATION METHODS OVER 100 RANDOMIZED CHANNEL CONTEXTS USING CPU AND GPU- ACCELERATED SURROGATE /ANO EVALUATIONS Method

EH

EH Gain

tCP U

tGP U

ANO GD GA DE PSO CMA-ES BO NM RS

424.2 mV 340.6 mV 437.8 mV 439.7 mV 439.0 mV 421.7 mV 413.1 mV 312.6 mV 375.5 mV

132.5 mV 48.9 mV 146.2 mV 148.0 mV 147.3 mV 130.0 mV 121.4 mV 20.9 mV 83.8 mV

0.0006 s 8.9 s 26.5 s 26.3 s 26.9 s 28.3 s 114.2 s 23.9 s 20.5 s

0.003 s 5.0 s 2.1 s 2.2 s 2.3 s 5.3 s 173.4 s 8.8 s 0.149 s

Hardware: AMD Ryzen 9 7900, NVIDIA RTX 4080 Super, 64 GB DDR5 RAM

Fig. 9 and despite the larger and more complex output space, the loss stabilized quickly. Within 50 epochs, the network achieved a post-EQ improvement success rate of almost 100% on the validation set. By learning the synergies between FFE, CTLE, and DFE, the amortized policy elevated the total EH to an average of approximately 424 mV and achieved a substantial mean EH improvement of over 130 mV compared to the unequalized baseline. To evaluate the accuracy and computational efficiency of the ANO policy, its performance was benchmarked against the suite of optimization algorithms based on 100 randomized SerDes channel contexts. The results are summarized in Table VII, and the EH improvement distributions are visualized using violin plots in Fig. 10. The findings further confirm the computational efficiency shift observed in the DDR5 scenario. Population-based evolutionary and swarm algorithms (GA, DE, and PSO) achieve the highest average EH gains at approximately 147 mV. However, the violin plots show that ANO maintains a comparable performance distribution compared to these population-based optimization methods. In contrast, GD and RS exhibit significantly larger variances and more frequent convergence to sub-optimal local minima within the 9-dimensional equalization space. NM degrades substantially in this high-dimensional and complex setting, while BO and CMA-ES are performance-wise close to ANO in this comparison.

Although the evolutionary and swarm approaches achieve roughly 15 mV of additional eye opening on average, this difference reflects the amortization gap between a learned global policy and instance-specific iterative optimization. In many practical design space exploration scenarios, sacrificing approximately 10% of the maximum achievable gain represents a beneficial trade-off given the significant reduction in runtime. The population-based iterative methods require more than 26 seconds per run on the CPU due to the 5,000 sequential surrogate evaluations performed during each optimization run. In direct comparison, ANO predicts the equalizer parameters in a single deterministic forward pass that only takes 0.6 milliseconds on a standard CPU and therefore provides a speedup that exceeds four orders of magnitude. This demonstrates that ANO realizes a computationally efficient alternative to iterative black-box search while keeping performance close to these best-performing strategies. This characteristic positions the ANO framework as a strong candidate for real-time Tx/Rx co-equalization optimization scenarios in high-speed SerDes links. Before deploying the ANO framework for the highdimensional SerDes design space exploration, its physical consistency had to be verified using a fixed context C at a data rate of 32 Gbps using only a 1-dimensional channel length sweep, as shown in Fig. 11. As channel length L increases and high-frequency attenuation becomes more pronounced, the ANO policy performs a smooth and controlled strategy that is physically consistent and interpretable. To compensate for the rising insertion loss, the CTLE boost is progressively ramped up toward its 15 dB limit, while the first and second pole frequencies are increased simultaneously all of which aim to mitigate the rising high-frequency attenuation. Concurrently, the Tx FFE pre-cursor tap is activated to mitigate pre-cursor ISI, while relying on the Rx DFE taps to cancel the remaining post-cursor ISI. The policy keeps the Tx FFE post-cursor at zero across the entire range, which demonstrates that the model has discovered a power-optimal equalization strategy for this environment. By delegating all post-cursor cancellation to the Rx-side CTLE and the nonlinear idealized 4-tap DFE, the policy avoids the voltage penalty of the Tx FFE post-tap, thereby preserving Tx output amplitude.

Fig. 11. 1-dimensional channel length sweep to validate the physical consistency of the 9-dimensional ANO-optimized equalization parameters.

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Fig. 12. Large-scale design space exploration example using the ANO-based EQ and surrogate predictions of worst case EH performance over a 100 × 100 grid of data rates and channel lengths at 32 manufacturing corner cases and a nominal loss tangent (Df = 0.02) for the unequalized baseline (left), ANO-based EQ (center), and ANO-based EQ improvement (right).

To demonstrate the potential of the ANO framework for real-world EDA applications, DSE was performed across a dense 100 × 100 grid of channel lengths (10 to 300 mm) and data rates (10 to 32 Gbps). To include manufacturing tolerances, each of the 10,000 grid points was evaluated across 25 = 32 corner cases spanning ±5% process tolerances to the nominal values of trace width (W = 100 µm), trace spacing (S = 200 µm), substrate height (H = 250 µm), dielectric constant εr (Dk = 4.5), and loss tangent tan δ (Df = 0.02), which led to a nominal differential impedance Zdiff of approximately 100 Ω. This corresponds to 32 manufacturing corner evaluations per grid point, resulting in a total of 320,000 channel configurations and ANO optimization runs. The aggregated worst-case EH performance for these 320,000 evaluations is visualized in Fig. 12. The unequalized baseline (left) shows eye closure for larger lengths and data rates, while the ANO-based equalization (center) successfully rescues the eye across the majority of the design space. The ANO-based EH improvement (right) shows that the ANO framework provides an additional worst-case eye opening of up to 300 mV in high-loss regions to effectively improve the feasible interconnect length even under manufacturing tolerances.

safe designs even without equalization (dark green) from those successfully salvaged by ANO-based equalization (light green) and unrecoverable failure zones (red). Finally, this 320,000-point multi-corner sweep provides even stronger evidence for the scaling advantage of the ANO framework. Based on the runtimes established in Table VII, performing this multi-corner optimization using a conventional iterative algorithm (averaging 26.5 s on a CPU and 2.2 s on a GPU) would require approximately 98 days of continuous computation on a CPU (320, 000×26.5 s) and 8 days on a GPU (320, 000 × 2.2 s). In contrast, the ANO policy processes the entire 320,000-point batch vectorized as a single matrix operation. On a CPU, this large sweep optimization run is executed in just 280 milliseconds. When utilizing GPU acceleration, the inference time for all 320,000 configurations collapses to only 9.3 milliseconds. By reducing the computational cost from days to milliseconds, the ANO framework transforms computationally prohibitive multi-corner pre-layout analysis into an instantaneous real-time feedback mechanism for highspeed DSE and worst-case analysis.

Additionally, two further 100 × 100 grid sweeps incorporating the same ±5% manufacturing tolerances with loss tangent vs. channel length and loss tangent vs. data rate have been considered. The results of these experiments and the specific equalization settings for these scenarios and the one in Fig. 12 are shown in the Appendix A. To translate these EH improvements into practical prelayout DSE decisions, Fig. 13 presents the worst-case eye mask compliance map. As opposed to a simple EH threshold, a design coordinate is classified as a “Pass” only if the ANO-predicted equalizer settings produce eye contours that satisfy a hexagonal eye mask for all 32 independent manufacturing corners simultaneously. The specific eye mask enforces a minimum vertical eye opening of 200 mV peakto-peak (±100 mV) for the central region with a flat top that spans 0.25 UI and symmetrical slopes terminating at 0 V at ±0.25 UI from the UI center. This analysis then delineates

Fig. 13. Worst-case eye mask compliance feasibility boundary across all 32 manufacturing corner cases.

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VI. DDR3 DQS E YE O PTIMIZATION UNDER I NTRA -PAIR S KEW C ONSTRAINTS Finally, ANO is evaluated for direct constrained SI optimization instead of equalization. For this, the scalar metrics eye-height, eye-width, and intra-pair skew were approximated using fully-connected MLP surrogate models, see Fig. 4 (b), as established in [4]. By backpropagating through these MLPs, the ANO policy learned to map the design space of transmission line lengths and the dielectric constant εr to near-optimal trace width W and spacing S to control the differential impedance Zdiff and coupling, while adjusting RT to minimize reflections. Concurrently, it had to satisfy the intra-pair skew constraints that were also given as context C. Because enforcing these constraints on an untrained network often leads to collapsing gradients or trivial solutions, e.g., closing the eye entirely to satisfy timing, the ANO policy was trained using a two-stage curriculum, as shown in Fig. 14. In Stage 1, across the initial 100 epochs comprising 20,000 batches, the network went through an unconstrained warm-up phase that was dedicated only to maximizing the normalized eye opening, defined as Meye = EW/U I ·EH/VDDQ . During this phase, the network learned to maximize EH and EW, but skew compliance stagnated below 90%, as expected. In Stage 2, over the remaining 100 epochs, the dynamic skew constraint was actively enforced. For every training batch, a target skew threshold tskew was uniformly sampled between 10 and 200 ps. This forced the global ANO policy to generalize across varying skew compliance limits. To ensure that there was a continuous gradient flow at the constraint boundary, the total loss L incorporated a differentiable Softplus penalty for skew violations:  λ  (5) L = −Meye + ln 1 + eγ(s−tskew ) , γ where s denoted the predicted intra-pair skew, and γ = 20 controlled the sharpness of the penalty. The weighting factor λ was set to zero during Stage 1 and was gradually annealed from 0.005 to 0.05 throughout Stage 2. The training curves in Fig. 14 demonstrate how the network actively adapted to this skew penalty and the physical trade-off. As the penalty increased, skew compliance was driven above 95%, which inevitably forced a slight degradation in the absolute eye opening to satisfy the skew constraints. To evaluate these learned constrained optimization capabilities of the trained ANO policy, it was benchmarked against the

Fig. 14. DDR3 DQS training process showing EW/U I · EH/VDDQ (left) and skew compliance rate [%] (right).

TABLE VIII C OMPARISON OF ANO VS . GA FOR DDR3 DQS AVERAGED OVER 25 SAMPLES PER SKEW LIMIT THRESHOLD

Limit

Eye-Width [ps]

Eye-Height [mV]

Skew Compliance

[ps]

ANO

GA

ANO

GA

ANO

GA

50 100 150 200

125 114 133 141

130 121 134 137

594 531 627 684

711 576 698 749

100% 100% 100% 100%

100% 100% 100% 100%

Avg.

128

131

609

684

100%

100%

GA, which has also been utilized for feasible region optimization in [4]. Both algorithms were tested across four dynamic skew thresholds on 25 randomized channel contexts each. The results, which are summarized in Table VIII, demonstrate the algorithmic trade-off. Because the GA runs an iterative search for each specific channel instance, it achieves a marginally better EW and EH compared to ANO, outperforming it by roughly 9.3% on average, which corresponds to the discussed amortization gap. However, both methods achieve a 100% intra-pair skew constraint compliance rate across all test cases. As the underlying surrogate for this task is a computationally lightweight MLP rather than the previously used complex recurrent encoder-decoder architecture, the iterative GA is able to converge on a single channel in an absolute runtime of just 271 milliseconds on a CPU and 268 milliseconds on a GPU. The ANO framework achieves this in just 1.8 milliseconds on a standard CPU/GPU. While this GA runtime is perfectly acceptable for a single optimization run, its underlying sequential methodology collapses as before when scaled to large-scale SI-DSE. This scaling limitation is handled much more efficiently by the ANO framework through batched inference, which transforms how SI constraints can be analyzed during prelayout. Fig. 15 illustrates a large-scale DSE where the routing lengths DL1 and DL2 are swept across a 100 × 100 grid, resulting in 10,000 design points. For every point on the grid, the ANO framework predicts the near-optimal W , S, and RT to maximize the eye under the specified skew constraint. The heatmaps show the intra-pair skew impact as under a 10 ps threshold, the feasible design space is restricted, because the optimizer faces problems when compensating for the T L3 imbalance. Relaxing the constraint to 100 ps expands the

Fig. 15. DDR3 DQS DSE for DL1 vs. DL2 with skew constrained to 10 ps (left) and 100 ps (right).

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valid transmission line lengths as expected. At this scale, the inefficiency of black-box search methods such as the GA becomes clear. Iterative methods scale linearly with the number of design space points, which leads to an estimated 45 minutes of sequential GA evaluations for this application. In contrast, the ANO framework solves the entire 10,000point constrained optimization task in a single forward pass. This batched inference takes just 19 milliseconds on a CPU and 1.8 milliseconds when GPU-accelerated, which enables interactive and real-time feasibility analysis. VII. C ONCLUSION AND F UTURE W ORK This paper introduced an amortized neural optimization framework for pre-layout signal integrity design space exploration. Traditional SI optimization relies heavily on simulations and iterative black-box optimization algorithms. Even when accelerated by fast machine learning (ML) surrogates, these sequential approaches introduce cumulative runtimes that are prohibitive for large-scale multi-corner design space exploration and analysis. The proposed ANO methodology overcomes this limitation by exploiting the continuous differentiability of neural surrogates. By extracting analytical gradients, the framework trains a global optimization policy network offline. The computational cost is amortized during training, which enables the learned policy to map previously unseen physical channel contexts to near-optimal design configurations in a single deterministic forward pass. The framework was evaluated across three high-speed interconnect design scenarios regarding its versatility and efficiency. In the DDR5 daisy chain topology, a multi-task ANO policy optimizes dual-receiver DFE taps across the channel context parameters. It eliminates the need for iterative optimization and provides an instantaneous feasibility check that evaluates eye mask compliance, delineating which routing configurations can be rescued by optimal DFE settings and which remain physically unrecoverable. In the highly complex SerDes environment, the policy learns the synergies of 9-dimensional Tx/Rx co-equalization to map a large-scale 320,000-point multi-corner analysis to near-optimal EQ parameters in milliseconds. Verifying the predicted eye contours against a hexagonal eye mask across all manufacturing corners transforms costly verification and evaluation into fast compliance checking to explicitly identify which channels can still be salvaged by optimal EQ settings. Finally, the DDR3 DQS scenario demonstrates that the ANO framework’s capabilities also translate directly to constrained SI optimization using a curriculum learning strategy to optimize trace geometries and termination for the maximization of eye-height and eye-width while maintaining timing compliance under dynamic intra-pair skew constraints. Comprehensive benchmarking against gradient-based, probabilistic, heuristic, as well as evolutionary and swarm optimization algorithms confirmed the expected trade-off. Because the global ANO policy must generalize across the entire design space, there is an amortization gap of roughly 10% compared to the best-performing instance-specific evolutionary and swarm algorithms. However, this marginal loss in absolute

optimality is outweighed by the reduction in computational cost. By reducing large-scale optimization runtimes from several hours or days down to only milliseconds, the ANO framework successfully shifts comprehensive multi-corner SI analysis from a slow verification step into an interactive realtime pre-layout design space exploration tool. Future work will focus on integrating graph neural networks (GNNs) as the differentiable surrogate backbone to allow the framework to encode arbitrary connectivity patterns of topologies and interconnects. Additionally, to bridge the amortization gap, future research will explore hybrid inference strategies. By combining the fast ANO prediction with an active fine-tuning step using gradient descent on the surrogate, the framework could recover absolute optimality for edge cases without reverting to full iterative black-box search. R EFERENCES [1] J. Withöft, W. John, E. Ecik, R. Brüning, and J. Götze, “SurrogateAssisted Amortized Neural Optimization of DDR5 Decision Feedback Equalization,” in 2026 IEEE International Symposium on Electromagnetic Compatibility, Signal & Power Integrity (EMC+SIPI), 2026, (accepted for presentation). [2] T. Lu, J. Sun, K. Wu, and Z. Yang, “High-Speed Channel Modeling With Machine Learning Methods for Signal Integrity Analysis,” IEEE Transactions on Electromagnetic Compatibility, vol. 60, no. 6, pp. 1957– 1964, 2018. [3] H. H. Zhang, Z. S. Xue, X. Y. Liu, P. Li, L. Jiang, and G. M. Shi, “Optimization of High-Speed Channel for Signal Integrity With Deep Genetic Algorithm,” IEEE Transactions on Electromagnetic Compatibility, vol. 64, no. 4, pp. 1270–1274, 2022. [4] J. Withöft, W. John, E. Ecik, R. Brüning, and J. Götze, “Machine Learning Methods for Elaborating the Feasible Region for Signal Integrity Analysis in Differential Pair PCB Structures,” in 2024 International Symposium on Electromagnetic Compatibility – EMC Europe, 2024, pp. 151–156. [5] J. Withöft, W. John, E. Ecik, J. Wastian, R. Brüning, and J. Götze, “A Machine Learning Modeling and Optimization Framework for Signal Integrity Design Support,” in 2025 Asia-Pacific International Symposium and Exhibition on Electromagnetic Compatibility (APEMC), 2025, pp. 410–413. [6] H. Ma, D. Li, E.-P. Li, A. C. Cangellaris, and X. Chen, “A Fast Optimization Method for High-Speed Link Inverse Design With SVRAS Algorithm,” IEEE Transactions on Signal and Power Integrity, vol. 1, pp. 22–31, 2022. [7] T. Nguyen, B. Shi, H. Ma, E.-P. Li, A. Cangellaris, and J. Schutt-Aine, “Constrained Gaussian Process for Signal Integrity applications using Variational Inference,” in 2023 IEEE/MTT-S International Microwave Symposium - IMS 2023, 2023, pp. 155–158. [8] C. H. Goay, A. Abd Aziz, N. S. Ahmad, and P. Goh, “Eye Diagram Contour Modeling Using Multilayer Perceptron Neural Networks With Adaptive Sampling and Feature Selection,” IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 9, no. 12, pp. 2427–2441, 2019. [9] M. Telescu, R. Trinchero, N. Soleimani, N. Tanguy, and I. S. Stievano, “Stochastic Time-Domain Mapping for Comprehensive Uncertainty Assessment in Eye Diagrams,” IEEE Transactions on Electromagnetic Compatibility, vol. 65, no. 6, pp. 1930–1938, 2023. [10] L. P. P. B. Bohl, K. Scharff, X. Duan, D. Kaller, and C. Schuster, “Bayesian Optimization of First-Order Continuous-Time Linear Equalization in High-Speed Links Including Crosstalk,” in 2023 IEEE 27th Workshop on Signal and Power Integrity (SPI), 2023, pp. 1–4. [11] M. Ahadi Dolatsara, “A Simplified Constrained Bayesian Optimization Approach to Optimize the Tx Equalization in SerDes Channels,” IEEE Letters on Electromagnetic Compatibility Practice and Applications, vol. 5, no. 2, pp. 41–47, 2023. [12] Z. Kiguradze et al., “High-Speed Channel Equalization Applying Parallel Bayesian Machine Learning,” in 2020 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI), 2020, pp. 251–256.

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A PPENDIX A A DDITIONAL S ER D ES D ESIGN S PACE E XPLORATION R ESULTS

Fig. 16. Large-scale design space exploration example using the ANO-based EQ and surrogate predictions of worst case EH performance over a 100 × 100 grid of loss tangents and channel lengths at 32 manufacturing corner cases and a nominal data rate of 32 Gbps for the unequalized baseline (left), ANO-based EQ (center), and ANO-based EQ improvement (right).

Fig. 17. Large-scale design space exploration example using the ANO-based EQ and surrogate predictions of worst case EH performance over a 100 × 100 grid of loss tangents and data rates at 32 manufacturing corner cases and a nominal channel length (L = 200 mm) for the unequalized baseline (left), ANO-based EQ (center), and ANO-based EQ improvement (right).

Fig. 18. Equalization parameters for the nominal W , S, H, Dk , and Df geometry parameters across the 100 × 100 grid of data rates and channel lengths.

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Fig. 19. Equalization parameters for the nominal W , S, H, Dk , and Df geometry parameters across the 100 × 100 grid of loss tangents and channel lengths.

Fig. 20. Equalization parameters for the nominal W , S, H, Dk , and Df geometry parameters across the 100 × 100 grid of loss tangents and data rates.