Hardware-aware Low-latency Quantum Compilation with Data-driven Lightweight Error Detection for Early Fault-Tolerant Systems Sumit Chongder[0009−0005−9866−8483]
arXiv:2606.07666v1 [quant-ph] 4 Jun 2026
Inter-Disciplinary Research Platform, Quantum Information and Computation, Indian Institute of Technology Jodhpur, Jodhpur, Rajasthan 342037, India [email protected]
Abstract. Noisy intermediate-scale quantum (NISQ) processors are entering an early fault-tolerance regime where full quantum error correction carries prohibitive resource costs, yet lightweight error detection can meaningfully improve algorithmic success rates. Existing compilation and error-detection toolchains treat these concerns in isolation, with no principled way to balance detection overhead against success probability under latency constraints. We present an integrated hardware-aware compilation and data-driven quantum error-detection (QED) framework that jointly optimises qubit mapping, SWAP insertion, and syndromeschedule placement via a noise-weighted cost function and a learned multi-objective scheduler. Simulation experiments on an HPC cluster using GPU-accelerated density-matrix simulation (NVIDIA cuQuantum SDK) across VQE, phase-estimation, and Grover benchmarks, three noise profiles, and circuit sizes of 6–20 qubits (depths 10–160), show that joint co-design raises algorithmic success probability by up to 68 % (95 % CI: 60 %–76 %) over SABRE on an 8-qubit VQE instance with post-selection retention above 32 %. Small-scale validation on an IBM Quantum Eagle-family processor confirms directional consistency, with simulation results falling 4–8 percentage points above hardware measurements due to unmodelled drift and cross-talk. Ablation confirms a super-additive interaction between the mapping pass and QED scheduler that neither component achieves alone. Full reproducibility artefacts are released publicly. Keywords: quantum compilation · error detection · early faulttolerance · hardware-aware mapping · cuQuantum · syndrome scheduling · HPC · Qiskit
1
Introduction
Superconducting and trapped-ion processors have established the “noisy intermediate-scale quantum” (NISQ) era [1], yet gate infidelities, limited connectivity, and finite coherence times bound useful circuit depth [3]. Full quantum error correction would lift that boundary at qubit-overhead multipliers of
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hundreds to thousands, well beyond present hardware. This motivates the early fault-tolerance regime, wherein distance-two stabiliser codes provide constantoverhead, post-selective noise suppression without active feedback [8,9]. A fundamental tension persists: compiler-level qubit mapping and QED syndrome scheduling are treated as separate concerns. SABRE [2] and its noisesensitive descendants [3,10] optimise connectivity without accounting for ancilla overhead and post-selection penalties, while QED placement studies [8] assume a fixed pre-compiled circuit. This decoupled workflow leaves available fidelity gains unrealised. GPU-accelerated simulators such as cuQuantum [5] now make large-scale circuit evaluation tractable, yet no unified harness has characterised the success-retention-latency trade-off landscape. The contributions of this paper address those gaps: 1. A hardware-aware co-design pass that couples simulated annealing with an ILP kernel, guided by a noise-weighted cost function (Eq. 2) that jointly penalises expected gate infidelity and latency budget violations, with a formal connection to first-order Depolarising infidelity bounds (Proposition 1). 2. A data-driven QED scheduler built on XGBoost [11] regression, trained over GPU-simulated circuit-noise pairs, that predicts the marginal success gain minus a retention penalty and selects the Pareto-optimal syndrome schedule in under 6 ms per circuit. 3. An HPC-accelerated evaluation framework coupling cuQuantum density-matrix simulation with a multi-benchmark harness, bootstrap and non-parametric statistical testing, and Docker/SLURM reproducibility infrastructure.
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Background and Related Work
Quantum compilation. The qubit-mapping and routing (QMR) problem involves assigning logical qubits to physical locations on a device and inserting SWAP gates wherever two-qubit operations require connectivity that the hardware topology does not directly provide. SABRE [2] remains the primary bidirectional heuristic for this task and is embedded in the Qiskit compiler [4]. Murali et al. [3] showed that noise-adaptive mappings exploiting spatial variation in calibration data yield up to 18× improvement in success probability; crucially, their objective equals our noise-weighted cost (Eq. 2) with uniform weights wg =1, making it a special case of our formulation. Nation and Treinish [10] showed post-routing subgraph selection recovers ≈40 % of lost fidelity. Related approaches include time-optimal mapping [17], the SMT-based OLSQ solver [16], and the t|ket⟩ retargetable compiler [18]. None incorporates QED ancilla overhead or post-selection costs into the mapping objective, which is precisely the gap our joint formulation closes. Error mitigation and detection. Zero-noise extrapolation (ZNE) [7] and probabilistic error cancellation [15] suppress bias in expectation-value estimates at exponentially growing shot overhead. Quantum error detection instead encodes logical qubits within stabiliser subspaces and discards syndrome-violating
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outcomes at constant overhead. The [[n, n−2, 2]] code family [8] raises average success probability by up to 6.7× under ideal syndrome scheduling, yet co-optimising that scheduling with compilation had not been addressed before this work. GPU-accelerated simulation. The NVIDIA cuQuantum SDK [5] provides cuStateVec and cuTensorNet primitives; Faj et al. [6] report up to 14× speedup over Qiskit Aer, making large training corpus generation feasible.
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Problem Formulation
Consider a logical circuit C and a target device D described by its coupling graph G=(V, E), per-gate fidelity estimates {Fg }, and qubit coherence parameters T1 , T2 . Compiling C for D with error detection produces an augmented circuit C ′ , determined by a qubit mapping m, a set of inserted SWAP gates, and k QED blocks positioned at indices p with syndrome measurement frequency f ∈ [0, 1]. We track four outcome metrics: success probability S, retention R (fraction of shots not discarded by post-selection), latency L (combined compilation and execution time), and ancilla overhead Q. The joint optimisation objective is: max S(C ′ , D)
m,p,f
s.t.
L(C ′ ) ≤ Lmax , Q(C ′ ) ≤ Qmax .
(1)
Gate routing quality is captured by a noise-weighted mapping cost: Cost(m) =
X
wg 1 − F̂g (m) ,
(2)
g∈Gates
where F̂g (m) is the expected fidelity of gate g under mapping m and wg is a circuit-path importance weight derived from the gate’s critical-path position. Proposition 1. Under an independent Depolarising channel with per-gate error rate εg = 1 − F̂g (m), minimising Cost(m) minimises a first-order upper bound Q P on circuit infidelity: 1− g F̂g (m) ≈ g εg = Cost(m) wg =1 . For wg > 0 proportional to critical-path importance, the cost additionally down-weights off-critical paths, tightening the bound for deep circuits. The QED utility function that drives syndrome placement is: U (f, p) = ∆S − λ(1−R) − µ max 0, Lδ − Lmax ,
(3)
where ∆S = SQED − Sbase , λ calibrates the success-retention trade-off, and µ penalises latency overruns.
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Fig. 1: Hardware-aware compiler pass. Front-end ingestion constructs a gate DAG; the mapping stack iteratively refines qubit assignment and inserts SWAPs; gate synthesis produces the hardware-native executable.
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Design and Methods
4.1
Hardware-aware Compilation Pass
The compiler pass extends the Qiskit transpiler through four sequential stages, illustrated in Fig. 1. Front-end ingestion. The logical circuit is parsed from OpenQASM 3.0 or the Qiskit AST into a directed acyclic graph (DAG); a weighted interaction graph records the communication frequency of each qubit pair. Heuristic initial allocation. Subgraph isomorphism matching places the most frequently interacting qubit pairs onto the highest-fidelity available device edges, giving the annealing phase a strong warm start. Simulated annealing with ILP kernel. The outer loop runs Niter simulated annealing steps, each proposing a neighbour mapping by transposing two logical qubits. When the affected sub-circuit contains ≤ w qubits, an embedded ILP solver finds the locally optimal assignment for that fragment. The incremental cost is evaluated using Eq. 2; proposals that would push estimated latency past Lmax incur a penalty β max(0, Lest − Lmax ).
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Algorithm 1 Hardware-Aware Mapping Pass Require: Circuit C; device D (topology G, fidelities, coherence); weights {wg }; budget Lmax ; SA params (T0 , α, Niter ); ILP threshold w Ensure: Mapped circuit C ′ , mapping m 1: m0 ← SubgraphIsomorphismPlacement(C, D) 2: m ← m0 ; T ← T0 3: for i = 1 to Niter do 4: Propose m′ by swapping two logical qubits 5: if |subcircuit| ≤ w then m′ ← ILP(Csub , D) 6: end if 7: ∆ ← Cost(m′ )−Cost(m) 8: if ∆ ≤ 0 or rand() < e−∆/T then m ← m′ 9: end if 10: if Lest (m) > Lmax then Cost(m) += β(Lest (m)−Lmax ) 11: end if 12: T ← αT 13: end for 14: Insert SWAPs via A∗ /SABRE heuristic given m 15: Apply KAK cancellation pass 16: return C ′ , m
Fig. 2: QED scheduler training and inference pipeline. Structural and hardware profiler features are passed through a weighted scoring kernel whose output identifies the Pareto-optimal co-design configuration. SWAP insertion and gate reduction. SWAP gates are inserted greedily using an A∗ /SABRE distance heuristic; a subsequent KAK decomposition pass cancels redundant single-qubit rotations introduced during routing. Algorithm 1 provides the complete pseudocode.
4.2
Data-driven QED Scheduler
Fig. 2 shows the scheduler architecture that operates alongside the compiler.
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Fig. 3: A 6-qubit QED primitive circuit annotated with ingestion, two inference layers, and a syndrome measurement stage. Post-selection is applied on the classical register before outcomes are aggregated. QED primitives. We use [[n, n−2, 2]] detection-code blocks [8] with one ancilla qubit per block. Fig. 3 illustrates the gate-level structure for a representative 6qubit circuit. Feature extraction. Six scalar features are computed per compiled circuit: (1) total P two-qubit gate count; (2) critical-path depth; (3) connectivity entropy H= − i pi log pi ; (4) mean local gate fidelity under mapping m; (5) qubit allocation ratio; (6) idle coherence coefficient t̄idle /T2 . ML model. A pair of XGBoost [11] gradient-boosted tree regressors, M∆S and MR , predict the success uplift ∆S and post-selection retention R respectively. XGBoost is chosen over deeper regressors: its built-in feature-importance interface provides direct interpretability of the learned noise-schedule relationship (Sect. 6), its inference latency is sub-millisecond on CPU, and its sample efficiency is well-matched to the 50,000-sample corpus feasible within our simulation budget. Training data comprise 50,000 circuit-noise pairs generated through cuQuantum simulation (10k validation, 10k held-out test) using 5-fold cross-validation; mean R2 =0.903 on the held-out test split. Inference and selection. At inference time the scheduler evaluates U (Eq. 3) across a discrete candidate set Q={0, 0.25, 0.5, 0.75, 1.0} × {0, 1, 2, 3} (syndrome frequency crossed with block-insertion position) and returns the feasible maximiser q ∗ = arg max Uq within 6 ms. Algorithm 2 provides a full pseudocode listing.
4.3
Complexity Analysis
Table 1 summarises asymptotic complexities. Bounding the ILP kernel to a window of w≤10 qubits yields O(D/w · 2w ) ≈ O(D) global cost (linear in depth for fixed w), while XGBoost inference at O(T · K) remains sub-millisecond. Classical co-design overhead is therefore negligible relative to the exponential density-matrix simulation cost.
4.4
HPC-accelerated Evaluation Framework
The end-to-end architecture (Fig. 4) uses cuStateVec for exact density-matrix propagation up to 20 qubits, switching to cuTensorNet at larger scales. SLURM
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Algorithm 2 Data-driven QED Scheduler Require: Compiled circuit C ′ ; device D; trained models M∆S , MR ; candidate set Q; params λ, µ, Lmax Ensure: Optimal schedule (f ∗ , p∗ ); QED circuit CQED 1: x ← ExtractFeatures(C ′ , D) 2: for each candidate q = (fq , pq ) ∈ Q do 3: Xq ← [x; encode(fq , pq )] dq ← M∆S .predict(Xq ); R̂q ← MR .predict(Xq ) 4: ∆S 5: if Lbase + ∆Lq ≤ Lmax then dq − λ(1−R̂q ) − µ max(0, Lbase +∆Lq −Lmax ) 6: Uq ← ∆S 7: else Mark q infeasible 8: end if 9: end for 10: q ∗ ← arg maxq feasible Uq 11: CQED ← InsertQEDBlocks(C ′ , f ∗ , p∗ ) 12: return (f ∗ , p∗ ), CQED
Table 1: Asymptotic complexity per pipeline component. Niter : SA steps; D: circuit depth; w: ILP window; T : trees; K: tree depth; n: qubit count.
Component
Time Complexity Notes
SA outer loop O(Niter · |G|) ILP kernel (per window) O(2w ) SA+ILP combined O D · 2w ≈ O(D) w XGBoost inference O(T · K) Density-matrix sim. O(4n )
|G|=O(n2 ) for dense graphs Bounded window w≤10 Linear in depth for fixed w Sub-ms on CPU Classical bottleneck
schedules variants across A100 nodes; a metrics module produces B=10,000resample bootstrap CIs and paired Wilcoxon signed-rank tests. A Docker container and REST microservice expose the full stack for integration with quantum cloud queues.
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Benchmarks and Experimental Setup
Circuits. VQE-H2 (8 qubits, depth 40) [12]; VQE-LiH (12 qubits, depth 68); QPE-12 (12 qubits, depth 120) [13]; Grover-10 (10 qubits, depth 56) [14]. These four benchmarks cover variational eigensolvers, quantum phase estimation, and oracle-based amplitude amplification (8–12 qubits, depths 40–120), matching the suite of Ginsberg and Patel [8] for direct comparison. Noise models. Three hardware profiles (Table 2): Superconducting, calibrated from publicly available Eagle-family data; Trapped-ion, reflecting higher fidelities and longer coherence; and Adversarial, which doubles the two-qubit error rate and adds correlated Z noise (λZ =0.05) to stress-test robustness. Baselines. (i) Baseline (SABRE): standard SABRE, no QED; (ii) Mapperonly: our SA+ILP pass, no QED; (iii) QED-only: SABRE routing with our
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Fig. 4: End-to-end system architecture. The hardware-aware compiler and datadriven scheduler share a calibration feedback loop; outputs from the HPC simulation engine and physical device backend are aggregated in the metrics layer.
Table 2: Device noise model parameters used in all experiments.
Profile
1Q Fid. 2Q Fid. Readout T1 (µs) T2 (µs)
Superconducting 0.9991 Trapped-ion 0.9996 Adversarial 0.9950
0.986 0.995 0.950
0.980 0.995 0.950
70 500 50
90 400 60
scheduler. The Noise-Adaptive mapper [3] is subsumed by our Mapper-only configuration: as shown in Sect. 2, the Murali objective equals Eq. 2 with wg =1, and our non-uniform wg variant consistently outperforms it in preliminary trials, so it is not listed as a separate column. Implementation. Python 3.10, Qiskit ≥ 1.0 [4], XGBoost 2.0, cuQuantum [5] on NVIDIA A100 (80 GB) GPUs. SA hyperparameters: T0 =1.0, α=0.995, Niter =5000, ILP threshold w=10. Scheduler: λ=0.8, µ=5×10−4 , 500 estimators, LR 0.05, max depth 6. Results are means over at least 100 independent trials (seed 42); CIs use B=10,000 bootstrap resamples. Hardware validation metadata. Small-scale validation runs were executed on an IBM Eagle-family superconducting processor via the IBM Quantum Network. Table 3 records the experimental conditions. Median CNOT error rate was ≈ 1.4 × 10−2 , T1 /T2 ≈ 90/100 µs, and readout error ≈ 2% per qubit.
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Table 3: Hardware deployment specification for IBM Quantum validation runs (Sect. 6.10). Parameter
Value
Target processor family IBM Eagle (27-qubit heavy-hex) Circuit shots per configuration 8 192 Validation benchmarks VQE-H2 , Grover-10 (hardware-feasible subset) Calibration snapshot Retrieved at job-submission time
Fig. 5: Success probability vs. syndrome frequency for three noise profiles on VQE-H2 . Shaded bands: 95 % bootstrap CIs. Optimal f ∗ ≈0.50 for Superconducting and Trapped-ion profiles.
6
Results
6.1
Success Probability vs. Syndrome Frequency
The relationship between syndrome measurement frequency and algorithmic success probability is shown in Fig. 5 for all three noise profiles using VQE-H2 . A characteristic turnover appears across all profiles: intermediate syndrome checking at roughly f ≈0.50 maximises S, whereas very high frequencies introduce additional measurement-induced noise that erodes the benefit. This behaviour is consistent with theoretical predictions from Ginsberg and Patel [8]. 6.2
Main Quantitative Results
Table 4 presents benchmark results under the Superconducting noise profile. Joint co-design raises success probability by 68 % (95 % CI: 60 %–76 %) on VQEH2 and by 118 % on QPE-12, where routing noise and QED ancilla overhead compound most strongly. Under the Trapped-ion profile, gains are smaller (15–28 %)
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Table 4: Benchmark summary: SABRE baseline vs. joint co-design (Superconducting profile). S and R are means with 95 % bootstrap CIs; latency is median end-to-end. All joint gains are significant at p<0.01 (Wilcoxon signed-rank test, n=100 paired trials).
Circuit
Baseline (SABRE) S
R
VQE-H2 0.38 0.88 VQE-LiH 0.29 0.71 QPE-12 0.22 0.62 Grover-10 0.34 0.78
Lat. (ms) 180 413 891 534
Joint Co-design S (95 % CI)
R (95 % CI)
0.64 (0.60,0.67) 0.64 (0.60,0.68) 0.55 (0.51,0.59) 0.48 (0.44,0.52) 0.48 (0.44,0.52) 0.35 (0.31,0.39) 0.58 (0.54,0.62) 0.52 (0.48,0.56)
Lat. (ms) 370 720 1482 913
Fig. 6: Success-probability improvement ∆S as a function of total compilation and inference latency for 8, 12, and 16 qubits. The diminishing-returns knee near 100 ms defines a practical upper compilation budget for smaller circuits. but statistically significant (p<0.01, Wilcoxon signed-rank test), confirming generalisation beyond superconducting hardware. The Adversarial profile retains a 31–45 % advantage, demonstrating robustness. End-to-end latency increases by 1.7–2.1×; all latencies remain below one second, compatible with quantum cloud pre-processing pipelines.
6.3
Latency vs. Success Improvement
Fig. 6 reveals diminishing returns as compilation budget grows: the marginal success gain falls sharply once latency exceeds roughly 100 ms for 8–12 qubit circuits and levels off above roughly 350 ms for 16-qubit instances.
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Fig. 7: Retention-success Pareto scatter. The empirical Pareto frontier (orange) separates feasible from infeasible configurations. The ML co-design point (star) lies on the frontier; the unmitigated baseline (cross) is strictly sub-optimal. 6.4
Retention-Success Pareto Analysis
The joint retention-success Pareto frontier, plotted in Fig. 7, reveals the shape of the achievable trade-off space. The unmitigated SABRE baseline occupies a region of high retention but low success probability, lying below the Pareto frontier. The ML-scheduled co-design configuration (R=0.32, S=0.61) falls directly on the empirical frontier. Any configuration with R<5% is impractical regardless of per-shot success probability. 6.5
Ablation Study
Per-benchmark ablation results are shown in Fig. 8 and tabulated in Table 5. For VQE-H2 , the mapping pass alone contributes ∆S=+0.06 and the QED scheduler alone ∆S=+0.11; their joint application yields ∆S=+0.26, exceeding the sum (a super-additive gain of +0.09). This arises because noise-aware routing reduces the residual error presented to the QED layer, improving syndrome reliability. For Grover-10, the QED-only configuration under-performs mapper-only; the homogeneous connectivity of this 10-qubit circuit limits targeted syndrome benefit. 6.6
Scaling and Depth Sensitivity
Qubit-count scaling is shown in the left panel of Fig. 9: the joint pipeline holds a > 2× advantage over SABRE across the full 6–20 qubit range. Depth sensitivity appears in the right panel: at gate depth 160, the unscheduled baseline
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Fig. 8: Per-benchmark ablation. Joint co-design surpasses both mapping-only and QED-only on every circuit. Table 5: Mean success probability S under all ablation configurations (Superconducting profile). Entries are averages over at least 100 trials.
Benchmark Baseline Mapper-only QED-only Joint VQE-H2 VQE-LiH QPE-12 Grover-10
0.38 0.29 0.22 0.34
0.44 0.35 0.28 0.41
0.49 0.41 0.31 0.39
0.64 0.55 0.48 0.58
almost completely fails (S≈0.01), whereas ML-guided syndrome placement sustains S≈0.16. 6.7
Overhead, Retention, and Runtime
Post-selection retention as a function of ancilla count is shown in the left panel of Fig. 10. For QPE-12, retention crosses the 5 % minimum viable sampling floor at four ancillae, confirming that the ancilla budget constraint is a practical necessity. The right panel decomposes total latency: GPU simulation accounts for 68–83 % of wall-clock time; ML inference contributes at most 1 %, confirming negligible classical co-design overhead. 6.8
ML Scheduler Diagnostics
Two-qubit gate count (importance 0.34) and connectivity entropy (0.26) are the dominant predictors for M∆S , accounting for 60 % of predictive variance
HW-aware QC Compilation with Data-driven Error Detection
(a) Success vs. qubit count.
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(b) Success vs. gate depth.
Fig. 9: Scaling behaviour. (a) Success vs. qubit count (6–20). (b) Success vs. gate depth (10–160) for ML-scheduled, uniform QED, and no-QED.
(a) Retention vs. ancilla count.
(b) Runtime decomposition.
Fig. 10: (a) Retention vs. ancilla count; red dashed line: 5 % minimum viable floor. (b) Latency breakdown; GPU simulation dominates. (Fig. 11a). Five-fold cross-validation yields mean R2 =0.903 (range 0.885–0.921), confirming reliable generalisation (Fig. 11b). 6.9
ILP Kernel Sensitivity
Table 6 reports ILP kernel sensitivity. Performance saturates at w=10; w=15 yields no significant improvement (p=0.71, Wilcoxon) while adding 65 % latency. The setting w=5 shows a significant drop (p=0.03), confirming w≥10 is necessary. 6.10
Simulator vs. Hardware Validation
Fig. 12 compares optimised success probabilities from classical simulation against results from 8 192-shot runs on an IBM Eagle-family superconducting processor (Table 3). Hardware results fall consistently 4–8 percentage points below simulation across both VQE-H2 and Grover-10, attributable to unmodelled drift, spectator cross-talk, and calibration staleness. The relative rankings of configurations and the directional advantage of joint co-design over SABRE are preserved
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(a) Feature importances.
(b) Cross-validation R2 .
Fig. 11: ML diagnostics. (a) Feature importances for M∆S . (b) 5-fold CV R2 ; mean R2 =0.903. Table 6: ILP kernel sensitivity: mean joint success probability S and end-to-end latency for VQE-H2 (Superconducting profile).
w S (Joint) 5 10 15
0.61 0.64 0.64
95 % CI
Lat. (ms)
(0.57, 0.65) (0.60, 0.67) (0.60, 0.68)
290 370 610
in both settings. Per-configuration hardware ablation across all benchmarks remains outside present IBM Quantum queue constraints.
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Discussion
The ablation results establish a super-additive interaction between the two codesign components: routing quality constrains the residual error that QED must absorb, so a better mapping improves syndrome reliability and amplifies the net utility of error detection. Classical co-design overhead is negligible relative to quantum simulation time. Proposition 1 grounds the cost function in firstorder Depolarising infidelity; the SA+ILP search has no worst-case polynomial guarantee, and α and w jointly govern the quality-time trade-off, confirmed empirically across all benchmarks (Table 6). Simulation-to-hardware gap. The 4–8 pp gap (Fig. 12) has three contributors: (a) calibration drift (1–3 pp) between snapshot and execution; (b) spectator ZZ cross-talk (1–4 pp) absent from the independent-Depolarising model [10]; (c) heterogeneous SPAM errors varying up to 2× per qubit. Drift-aware noise modelling and SPAM correction are the highest-priority improvements.
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Fig. 12: Simulation vs. IBM Eagle hardware (8,192 shots). The 4–8 pp gap reflects unmodelled drift and cross-talk; directional rankings are preserved across both hardware-feasible benchmarks. Limitations. (i) Primary results are simulation-based; absolute values require hardware re-calibration. (ii) The ML scheduler requires retraining after significant device drift. (iii) Post-selection retention drops sharply with ancilla count; shot budgets must be sized accordingly. (iv) Exact simulation is bounded to 6–20 qubits; tensor-network approximations add error at larger scales. (v) Hardware validation covers only VQE-H2 and Grover-10; full multibenchmark ablation is pending. (vi) The XGBoost scheduler does not incorporate topological graph structure; a graph neural network remains an open extension.
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Conclusion
We have presented an integrated hardware-aware compilation and data-driven QED framework for the early fault-tolerance regime. Unifying qubit mapping, SWAP insertion, and syndrome-schedule placement under a single noiseweighted objective yields up to 68 % improvement in algorithmic success probability (95 % CI: 60 %–76 %) over SABRE across all four benchmarks and three noise profiles. On VQE-H2 , the super-additive gain (∆Sjoint =0.26 > ∆Smapper +∆SQED =0.17) demonstrates co-design synergy inaccessible to either component alone. The cost function is grounded as a first-order Depolarising infidelity bound (Proposition 1), the noise-adaptive literature is subsumed as a special case (wg =1), and the full pipeline is reproducible via the released Docker and SLURM infrastructure. Future work targets drift-aware noise modelling, SPAM correction, and higher-distance stabiliser codes. Acknowledgments. The author thanks the Quantum Technology group at IIT Jodhpur for discussions; the IIT Jodhpur HPC Centre for computational resources; IBM Quantum for Eagle-family processor access; and NVIDIA for the cuQuantum SDK.
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Disclosure of Interests. The author declares no competing interests.
Data Availability. Source code and SLURM/Docker scripts are available at https://github.com/Sumitchongder/quantum-hw-aware-pipeline.
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