A Modern Large-Scale Memory Characterization Laboratory

A Modern Large-Scale Memory Characterization Laboratory Ataberk Olgun§

Haocong Luo§ İsmail Emir Yüksel§ A. Giray Yağlıkcı§ Onur Mutlu§

arXiv:2606.13725v1 [cs.AR] 11 Jun 2026

§

F. Nisa Bostancı§

SAFARI Research Group ETH Zürich

Real memory chip characterization yields insights into fundamental operational characteristics of modern memory, enabling new mechanisms that improve memory performance, robustness, security, and energy efficiency. We describe our large-scale DRAM characterization laboratory for understanding DRAM. A key building block of this laboratory is DRAM Bender [1, 2], a versatile and easy-to-use modern DRAM characterization infrastructure. We have updated DRAM Bender to i) introduce support for new types of characterization experiments, ii) expand on its DRAM interface standard support, and iii) make it easier to use at large scale. This paper introduces these updates for the first time. We hope our infrastructure enables the community to discover new problems and solve critical memory scaling issues, enabling the overcoming of the huge memory bottleneck that plagues modern computing systems.

and other major parameters. This infrastructure, which took us more than a year to build and which we later open sourced as SoftMC [13,14] and DRAM Bender [1,2], enabled us (and many others) to empirically study and understand many interesting and important characteristics of modern DRAM chips. Many researchers and practitioners from industry and academia have been using DRAM Bender (and SoftMC) to deeply understand DRAM and solve major memory challenges [11, 15–68]. For example, DRAM Bender has enabled the discovery and study of major DRAM phenomena including RowHammer [28], RowPress [21], Variable Read Disturbance [18], ColumnDisturb [15], the DejaVu effect [57], Variable Retention Time [11, 67, 69, 70], data pattern dependence [11, 27, 71], data retention failures [11, 71], and computational capabilities of real commercial off-the-shelf (COTS) DRAM chips [34–48, 58, 59, 61–63]. The earlier discoveries [11, 25, 28, 69, 71] are already recognized with major awards [12, 72–76] and have had major impact on industry’s thinking and handling of DRAM robustness issues. Many read disturbance characterization works use DRAM Bender to identify new aspects of the vulnerability [15–25,29–31,33,49,57,60]. DRAM Bender (building on its predecessor SoftMC) has seen widespread use due to its three key properties: i) flexibility in the types of DRAM characterization experiments it supports, ii) ease of use in a manner accessible to both software and hardware developers, and iii) wide availability across many DRAM standards, DRAM module form factors, and FPGA boards. Our journal article on DRAM Bender [1] describes how DRAM Bender was built from the ground up around the three key properties. Figure 1 shows a picture of a DRAM Bender setup used to test modern 3D-stacked high bandwidth memory (HBM) stacks. Figure 2 shows a picture of another DRAM Bender setup, equipped with a temperature controller, used to test modern DDR4 DRAM modules.

1. Background DRAM [3] is the prevalent memory technology overwhelmingly used for main memory in modern systems. Unfortunately, as DRAM scales down to smaller technology nodes, it faces key challenges [4–10] in both data integrity and latency, which strongly affect overall system performance, robustness, security, and energy efficiency. To develop high-performance, robust, secure, and energy-efficient DRAM-based main memory in future systems, researchers rely on publicly-available DRAM testing infrastructure to experimentally characterize, understand, and analyze various aspects (e.g., reliability, latency) of real DRAM chips. DRAM Bender [1, 2] is a prominent, publicly-available DRAM testing infrastructure. This infrastructure is a product of our almost two-decade-long research into empirically studying and understanding many interesting characteristics of modern DRAM chips. In 2011, we set out to rigorously understand the difficulty of DRAM data retention time identification using an empirical approach [11,12]. No prior work at the time provided real data on the retention characteristics of state-ofthe-art DRAM chips, let alone a detailed empirical analysis of major problems that make retention time profiling challenging and how DRAM technology scaling affects those challenges. In fact, no infrastructure to study these characteristics existed (or was available to us). We decided to build our own FPGA-based infrastructure to characterize real DRAM chips in a flexible manner so that we could change the refresh rate, data patterns,

2. DRAM Characterization Laboratory Large scale DRAM characterization accelerates the discovery of various unknown DRAM characteristics, yielding new scientific insight to ultimately improve DRAM-based memory system performance, robustness, security, and energy efficiency. Access to a larger DRAM Bender characterization infrastructure enables researchers to concurrently test more new ideas, properties, and hypotheses, and also enables more in-depth 1

cover new problems and solve outstanding DRAM technology scaling issues.

FPGA board with HBM2 DRAM Bender

Understanding DRAM Robustness Problems [11, 15–33, 49, 50, 57–60, 64–69, 78]. DRAM Bender gives its users access to the underlying low-level DRAM interface, enabling direct observation of DRAM-device-level error patterns. Leveraging this key feature of DRAM Bender, researchers have made significant discoveries of key DRAM robustness issues such as read disturbance and data retention failures. The original RowHammer paper [28] showed that repeatedly activating an aggressor DRAM row many times induces bitflips in physically-neighboring victim rows. The paper also showed that RowHammer was a widespread phenomenon across commodity DRAM modules manufactured in 2012-2013. Kim et al. [25] revisited RowHammer in 2020 by quantitatively analyzing the RowHammer vulnerability in thousands of commodity DRAM chips and showed that DRAM became more vulnerable to RowHammer as DRAM technology advanced. Orosa and Yaglikci et al. [22, 24, 78] provided an in-depth analysis of RowHammer’s sensitivities to temperature, access patterns, and physical location of victim rows. Luo et al. [21] discovered a new read disturbance phenomenon called RowPress, where keeping a DRAM row open for a very long time induces read disturbance bitflips with as few as only one DRAM row activation. More recently, the ColumnDisturb discovery [15] showed that the read disturbance effect of activating a DRAM row is not limited to the few victim rows physically neighboring an aggressor row, but that the disturbance effect can span entire subarrays (thousands of DRAM rows) along a DRAM column due to perturbations caused on thousands of bitlines. All these works showed that these new read disturbance phenomena can manifest as bitflips in standard DRAM operating conditions and jeopardize the robustness (i.e., security, safety, and reliability) of modern systems. These works kickstarted an ongoing line of research and industrial development that has led to many different types of DRAM read disturbance mitigation techniques [10, 22, 28, 37, 51, 52, 79–157], including major changes to DRAM standards in industry [148, 149, 158].

Compact host machine with DRAM Bender software stack

Figure 1: DRAM Bender high bandwidth memory (HBM) characterization setup. More detail in [18, 20, 77]. 2

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Xilinx Alveo U200 FPGA Board (with DRAM Bender)

PCI-e Connection to the Host Machine

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Temperature Controller

DRAM Module w/ Heater Pads

Figure 2: DRAM Bender DDR4 characterization setup

quantitative consideration of previously-known ideas, properties, and hypotheses that could otherwise be potentially discarded due to lack of resources given a smaller infrastructure. To accelerate scientific discovery that leads to better memory systems, we have built a large-scale characterization laboratory comprising 100+ DRAM Bender setups. Figure 3 shows a picture of this laboratory.

Uncovering New DRAM Functionality [34–48, 58, 59, 61– 63,159]. DRAM Bender enables users to issue arbitrary DRAM commands with an arbitrary delay between subsequently issued commands to the tested DRAM chip. Using this key feature, various works demonstrated previously-unknown functionality in real commercial off-the-shelf (COTS) DRAM chips. The DRAM Latency PUF [63] showed that the DRAM read access latency can be reduced below the reliable datasheet specifications and the resulting error patterns used as physical unclonable functions (PUFs). D-RaNGe [40] proposed a new DRAM-based true random number generator based on the key idea of intentionally violating DRAM access timing parame-

Figure 3: Our laboratory for understanding DRAM with 100+ DRAM Bender setups

2.1. A Versatile DRAM Infrastructure DRAM Bender enables a wide variety of DRAM characterization experiments. We highlight two classes of prior works that use DRAM Bender (and its predecessor, SoftMC) to dis2

ters and using the resulting errors as a source of randomness. ComputeDRAM [46] showed that real DDR3 DRAM chips are capable of RowClone [160] and bitwise majority [161–163] operations by constructing carefully engineered DRAM command sequences with greatly violated DRAM timing parameters and issuing these commands to DRAM chips in quick succession. QUAC-TRNG [39] showed that four DRAM rows can be concurrently activated if timing parameters between activate and precharge commands are greatly violated. Using this four-row activation primitive, QUAC-TRNG generates true random numbers at higher throughput than the state-of-theart at the time. Building on QUAC-TRNG, SiMRA-TRNG [34] showed that even more rows can be concurrently activated to provide even higher throughput true random number generation. FCDRAM [36] and SiMRA-DRAM [35] demonstrated that real modern COTS DRAM chips can perform a wide range of Processing Using DRAM operations, including functionally complete Boolean logic, many-input Boolean operations, simultaneous many-row activation, majority operations, and multi-row copy. PiDRAM [159] demonstrated COTS DRAMbased bulk data movement and true random number generation in an FPGA-based prototype and showed practical benefits for bulk data copy and initialization, while also providing foundational solutions to key COTS DRAM-based Processing Using DRAM (PUD) integration challenges such as memory allocation, alignment, coherence, and host-PUD coordination. Other Works [44, 49–56, 64–66, 159]. DRAM Bender’s ease of use also enabled researchers to gain insight into DRAM internals [49–52,64–66], uncover other DRAM functionality [44], understand DRAM voltage and latency sensitivity [53,54], characterize DRAM power consumption [55]. Part of DRAM Bender’s hardware design was reused in other system evaluation infrastructure [56, 159].

our new validated power models and the sources for our power measurement setups after we rigorously test and calibrate them (as we have done in the past for DDR3 DRAM [55, 164]). DDR4 Power Measurement. To enable fine-grained power measurement of DDR4 modules in DRAM Bender, we designed a dedicated riser board that sits between the DIMM slot and the DDR4 module. Figure 4 shows a picture of the riser board. The board intercepts the power rails delivered to the module and routes these rails through on-board components to provide accurate, real-time power readings. The board connects to a host machine via a universal serial bus (USB) link. We use the USB link to record power data during DRAM Bender experiments.

Figure 4: Custom DDR4 DRAM riser board used for power measurement

HBM2 Power Measurement. We provide fine-grained power measurement support for HBM2 stacks in DRAM Bender by integrating the AMD Card Management Subsystem (CMS) [165] into an Alveo U55C [166] (HBM2-based FPGA board) DRAM Bender setup.1 CMS periodically queries an on board satellite controller for current measured on the primary HBM2 voltage rail. We augment the DRAM Bender software stack with a routine that fetches measured instantenous, maximum, and average current values via the PCIe interface from the DRAM Bender setup.

3. New DRAM Bender Features 3.2. High Bandwidth Memory (HBM2) Support

We have updated DRAM Bender’s hardware and software components with new features to 1) enable DRAM Bender to support new types of experiments (§3.1), 2) expand on its DRAM interface standard support (§3.2), and 3) make it easier to use at large scale (§3.3). We strongly believe these features will accelerate discovery and experimental studies that would lead to better memory and DRAM-based computing systems.

To meet the high-bandwidth requirements of modern dataintensive applications [167–176], DRAM designers develop HBM stacks, which contain multiple layers of 3D-stacked DRAM dies. We have updated our infrastructure with a new DRAM Bender design that supports HBM2 in the Bittware XUPVVH [177] and Alveo U50 [178] FPGA boards.2 These designs are already publicly available in our GitHub repository [2]. Figure 5 shows a picture of one of our HBM2-based DRAM Bender setups.

3.1. DRAM Power Measurement Power consumption of main memory is a critical system design constraint. Unfortunately, detailed empirical power consumption data for newer DRAM standards is scarce. Our updated infrastructure provides DRAM power measurement support for DDR4 modules and for HBM2 stacks, enabling users to empirically measure DRAM power using commodity DRAM and develop better power models. We aim to publicly release

1 Any FPGA board that supports CMS [165] and provides current measurement capability on DRAM power rails (e.g., Alveo U55C [166]) can be used with DRAM Bender to conduct power measurement studies. 2 We have ported DRAM Bender to AMD and Bittware boards so far, but there is no fundamental limitation that prevents DRAM Bender from being ported to other FPGA boards from other manufacturers or custom FPGA boards.

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(3) Cooling Fan

(e.g., temperature controller, power measurement board) as Slurm features. Researchers submit experiments as Slurm jobs tagged with the required features, and Slurm dispatches each job to a compatible idle setup as resources become available. We aim to publicly release our Slurm integration alongside DRAM Bender to enable other research groups to easily operate similar large-scale characterization laboratories.

(4) Temperature Controller (2) Heating Pad

(1) FPGA Board with HBM2

4. DRAM Bender Adoption & Community DRAM Bender has been adopted by research groups across both industry and academia [11, 15–68], yielding a growing body of work to discover new problems and new capabilities, and solve outstanding DRAM technology scaling issues. To further accelerate adoption and lower the barrier to entry for new researchers, we organize a recurring joint Ramulator [180–184] and DRAM Bender tutorial series co-located with major computer architecture conferences. Each tutorial provides an extensive overview of both i) Ramulator, our cycleaccurate and extensible main memory simulator, and ii) DRAM Bender, covering its programming interface, supported DRAM standards, and example characterization workflows. The tutorial series also serves as a venue for the community to present and discuss new research conducted using DRAM Bender. We have so far successfully held the first edition of the tutorial at ASPLOS 2026 [185], which featured invited presentations on DRAM characterization and memory system simulation. We are organizing the second edition at ISCA 2026 [186], where we plan to additionally provide a hands-on session that walks attendees through writing, running, and analyzing the results of real DRAM characterization experiments using DRAM Bender. We are also organizing a third edition at ICS 2026 [187], whose workshop proceedings include this paper. We offer the DRAM Bender projects & seminars course [188, 189] where ETH Zürich undergraduate students learn how DRAM is organized and operates in a low-level and gain practical experience in using DRAM Bender. The sources for this course are available online (see [188] for the latest edition) and the recordings of the lectures are uploaded to YouTube for Spring 2022 [190], Fall 2022 [191], Spring 2023 [192], Fall 2023 [189], and Spring 2024 [189] editions. These playlists feature DRAM Bender tutorials and research talks on scientific papers that use DRAM Bender. We hope our tutorial series, course offerings, and the continued open-source development of DRAM Bender will enable a broader segment of the community to conduct rigorous experimental DRAM research and discover more new characteristics and ideas in memory systems.

(5) PCIe Host Interface

Figure 5: HBM2 DRAM Bender setup as depicted in [20]

DRAM Bender allows precise control of the HBM2 command timings at the granularity of 1.67 ns (i.e., the HBM2 interface clock speed is 600 MHz). Each Bittware XUPVVH and Alveo U50 board has a 4 GiB HBM2 stack with 8 channels, 2 pseudo channels, 16 banks, 16K rows, and 1 KiB row size. We used the HBM2-based DRAM Bender design to show for the first time that read disturbance (RowHammer and RowPress) was prevalent across real HBM2 stacks [18, 20, 77].

3.3. Job Scheduling System for Large-Scale Experiments Experimental rigor in hypothesis testing requires gathering characterization data from a wide variety of DRAM chips spanning different chip organizations, manufacturers, die revisions, and die densities. Without access to a large-scale laboratory, researchers must physically replace DRAM modules in a small number of DRAM Bender setups as they conduct experiments across a diverse pool of DRAM chips. This manual process i) is labor-intensive, ii) gradually damages DRAM module slots on FPGA boards to a point of failure, and iii) accelerates the aging of DRAM Bender setup components because of repeated manual handling. Our large-scale laboratory eliminates this overhead by statically allocating a wide variety of DRAM chips across our 100+ DRAM Bender setups: each DRAM module is installed once and rarely replaced with another module setup, such that no manual DRAM module replacement is required during typical use. Static allocation introduces new resource allocation problems. First, each submitted experiment must be dispatched to a setup that hosts a DRAM chip matching the experiment’s requirements (e.g., a target manufacturer, die revision, or DRAM standard). Second, contention between concurrent experiments must be resolved fairly. We address this problem by integrating DRAM Bender with Slurm [179], a widely-used open-source workload manager. We model each DRAM Bender setup as a Slurm node and expose the attributes of the setup’s installed DRAM chip and supplementary hardware

Acknowledgments We thank the SAFARI Research Group members for their constructive feedback for decades and for providing a stimulating 4

intellectual, scientific, scholarly environment. We acknowledge the generous gift funding provided by our industrial partners (especially Google, Huawei, Intel, Microsoft), which has been instrumental in enabling the research we have been conducting on read disturbance in DRAM in particular and memory systems in general [4–10, 12, 73, 175, 193–208]. This work was in part supported by a Google Security and Privacy Research Award and the Microsoft Swiss Joint Research Center.

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