S UPRA SNN: E XPLOITING S YNAPSE -L EVEL PARALLELISM IN S PIKING N EURAL N ETWORK ACCELERATORS THROUGH C O -O PTIMIZED M APPING AND S CHEDULING
arXiv:2606.13354v1 [cs.AR] 11 Jun 2026
A P REPRINT Seyed Sadra Ghavami High-Performance Embedded Architecture Laboratory (HiPEAL) School of Electrical and Computer Engineering College of Engineering, University of Tehran Tehran, Iran [email protected] Mohammad Hossein Nikkhah High-Performance Embedded Architecture Laboratory (HiPEAL) School of Electrical and Computer Engineering College of Engineering, University of Tehran Tehran, Iran [email protected] Mohammad Rasoul Roshanshah High-Performance Embedded Architecture Laboratory (HiPEAL) School of Electrical and Computer Engineering College of Engineering, University of Tehran Tehran, Iran [email protected] Saeed Safari High-Performance Embedded Architecture Laboratory (HiPEAL) School of Electrical and Computer Engineering College of Engineering, University of Tehran Tehran, Iran [email protected]
A BSTRACT Spiking Neural Networks (SNNs) offer a brain-inspired path toward highly efficient computation, but their practical deployment is constrained by the challenge of managing and executing their massive parallelism on physical hardware. This problem mirrors the historical challenge in processor design of moving beyond serial execution, a barrier broken by superscalar architectures that dispatch multiple instructions to parallel functional units. Drawing inspiration from this paradigm, we introduce a hardware-software co-design framework that treats synaptic events as parallelizable micro-operations. We present SupraSNN, a superscalar-inspired architecture that achieves high synapse-level parallelism by physically decoupling synaptic and neuronal computations. Within this architecture, a Multi-Cast Tree routes spike data to multiple parallel Synapse Processing Units serve as the computational pipelines, while a Merge Tree consolidates distributed results for processing by a unified Neuron Unit–deliberately centralizing complex neuron state dynamics to mitigate hardware overhead and resource duplication. The efficacy of this architecture is enabled by a sophisticated partitioning and
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scheduling framework that first maps the SNN onto hardware respecting memory constraints, then heuristic scheduling determines the synaptic execution order, maximizing throughput and resource utilization. Implementing a feedforward SNN trained on MNIST (93.44% accuracy), SupraSNN achieves 149 µs inference latency and 0.025 mJ per image (0.276 nJ per synapse) on the Xilinx Zynq XC7Z020 FPGA–delivering 47.6% lower latency and 5.6× better energy efficiency than prior FPGA-based SNN accelerators. Beyond vision tasks, a recurrent SNN on the Spiking Heidelberg Dataset (71.82% accuracy) achieves 1.41 ms latency and 0.77 mJ per sample on XC7Z030. Keywords Spiking Neural Networks · Neuromorphic Hardware · Hardware-Software Co-Design · Mapping and Scheduling · Superscalar Architecture · Probabilistic Mapping
1
Introduction
Artificial neural networks have revolutionized computing paradigms for machine learning workloads, yet conventional deep learning architectures face fundamental challenges in efficiently processing temporal, event-based data streams [1]. Spiking Neural Networks (SNNs) have emerged as a promising model for temporal processing and event-based sensing because they natively capture rich spatiotemporal dynamics [2]. Additionally, by intrinsically exploiting the temporal domain and operating in a highly sparse, event-driven manner, SNNs offer a biologically plausible pathway to extremely energy-efficient computation [3]. The actualization of these theoretical benefits depends heavily on the underlying hardware implementation [4]. While SNNs can be simulated on general-purpose processors, specialized hardware is required to truly capture the massive parallelism, microsecond-level latency, and drastic power reductions promised by these networks [5]. Consequently, the pursuit of specialized neuromorphic accelerators has led to a broad design space encompassing analog [6], [7], mixed-signal [8], [9], and fully digital architectures [10], [11]. Digital hardware implementations, in particular, provide a robust solution by offering strict mathematical determinism [12], high scalability across modern technology nodes [13], [11], and resilience against the noise and process variations typically found in analog neuromorphic systems [14]. Moreover, digital systems allow for the precise control and reconfigurability necessary to implement the complex, time-dependent dynamics of various rapidly evolving spiking neuron models [10]. However, existing digital hardware implementations require further improvement to maximize their computational throughput, as handling modern, highly sparse, and irregularly connected SNNs demands deep, fine-grained parallelism [15]. Traditional SNN accelerators tightly couple synaptic accumulations with neuronal membrane potential updates [35], [8]. This structural rigidity fundamentally limits parallel execution because modern SNN topologies exhibit a severe computational asymmetry: synapses demand a massive number of simple accumulations, whereas neurons require a significantly lower frequency of structurally complex, state-dependent updates [34]. To decouple these processes and unlock higher throughput, we draw inspiration from the evolution of high-performance single-core CPUs—specifically, the superscalar microarchitecture [16], [17]. These architectures achieve high throughput by issuing multiple independent instructions to parallel execution units (ALUs) and subsequently merging the results back into a centralized, deterministic architectural state (the Register File). Guided by this paradigm, we propose a novel architectural approach for digital neuromorphic engines, which we conceptualize as synapse-level parallelism. By treating individual synaptic operations as independent tasks that can be dynamically dispatched to parallel units, this approach fundamentally redefines how SNN workloads are executed. This superscalar-inspired shift toward synapse-level parallelism enables three key advantages for modern SNN workloads: 1. Controlled Parallelism: By decoupling synaptic operations from the update cycle of the entire neuron, the engine can achieve a much higher, strictly controlled level of parallelism. Multiple synaptic events can be processed simultaneously across different units, completely independent of the slower membrane potential updates [22]. 2. Irregular Dataflow Flexibility: It provides the vital flexibility required to handle the irregular connectivity of advanced SNN architectures. This is critical for mapping complex topologies, including fully recurrent and randomly connected layers, which do not follow the rigid dataflow patterns of traditional convolutional networks [18]. 3. Unstructured Sparsity Support: It allows the hardware to natively support unstructured weight sparsity with fully general connectivity. Instead of being bound by dense matrix structures, the engine skips zero-valued synapses at a fine-grained level, translating algorithmic sparsity into direct latency and energy savings [19], [15]. 2
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However, implementing such fine-grained parallelism within an SNN accelerator introduces several non-trivial hardware challenges: • Selective spike distribution (multicasting): Global broadcasting of spikes to every processing unit simplifies routing logic but results in massive interconnect energy waste. An efficient mechanism is needed to distribute spikes only to the specific parallel units that require them. • Parallelism–memory trade-off: Partitioning synapses widely across parallel compute units exposes abundant parallelism but creates fragmented partial results that must be buffered and merged. Conversely, clustering neuron states to minimize storage leads to severe compute load imbalances under irregular connectivity. • Deterministic commit (accumulation): When multiple synaptic updates targeting the same post-synaptic neuron are produced in parallel, the system must ensure a deterministic commit to the neuron’s state. Relying on queues or atomic memory updates can bottleneck high fan-in neurons and introduce non-deterministic mathematical behavior that depends entirely on low-level hardware arbitration. To overcome these challenges, we present SupraSNN, an SNN processing engine designed to realize synapse-level parallelism through a superscalar-inspired architecture. SupraSNN effectively treats incoming spikes as "instructions" that are dispatched to a parallel array of Synapse Processing Units (SPUs). These SPUs operate in parallel to calculate synaptic contributions, which are then synchronously and deterministically committed to a centralized Neuron Unit utilizing a custom buffer-less merge fabric. This decoupled approach allows our single-core engine to exploit massive parallelism while maintaining the strict mathematical determinism and flexibility required for highly irregular SNN topologies. The primary contributions of this work are summarized as follows: • Superscalar-Inspired Single-Core Engine that physically decouples synapse and neuron operations, introducing fine-grained, synapse-level parallelism within a single processing core. • Lightweight Multi-Cast (MC) Tree that employs an O(N ) scaling bitstream for spike multicasting, strictly avoiding the overhead of global broadcasting and large routing tables. • Bufferless Merge (ME) Tree that deterministically and synchronously commits all parallel synaptic partial sums to the centralized neuron state, eliminating queue and atomic lock bottlenecks. • Hardware-Software Co-Design Framework that resolves the parallelism–memory trade-off by intelligently partitioning irregular SNN workloads across SPUs. • Evaluation on Sparse and Temporal Datasets via FPGA prototyping, demonstrating that the architecture dynamically scales latency and power consumption in direct proportion to unstructured network sparsity, with competitive performance on both the MNIST [20] and Spiking Heidelberg Dataset (SHD) [21] benchmarks.
2
Background
SNNs–often regarded as the third generation of neural networks–extend traditional artificial models by incorporating stateful neurons and adaptive synaptic connections, thereby more closely resembling biological computation [3]. In the brain, a neuron consists of several main components: the soma (cell body), which maintains the neuron’s membrane potential; the dendrites, which receive spikes (electrical impulses) from other neurons; and the axon, which transmits spikes to neighboring neurons via axon terminals [2]. When an excitatory synapse receives a spike, it causes a rapid increase in the postsynaptic membrane potential [22]. Once the membrane potential exceeds a defined threshold, the neuron emits a spike and the potential is reset to a reset value [24]. The generated spike then propagates along the axon and reaches the synaptic terminals, where it is transmitted to the dendrites of neighboring neurons [23]. The magnitude and sign of the resulting postsynaptic response depend on the ionic concentration and synaptic strength at the corresponding connection [22]. To mathematically model this behavior, the Hodgkin–Huxley (HH) [28] model was introduced as a detailed biophysical representation of neural dynamics, although its computational complexity limits its practical use in large-scale simulations and hardware implementations. The Izhikevich model [29] later provided a simplified biologically plausible alternative, yet the Leaky Integrate-and-Fire (LIF) model ultimately emerged as the most practical compromise between biological realism and computational simplicity [25]. Its simple dynamics, based on a linear differential equation with a threshold-and-reset mechanism, enable low-latency, energy-efficient operation while maintaining sufficient fidelity for large-scale network modeling. In the LIF neuron, the membrane—representing the internal state of the neuron—is modeled as a capacitor, while the leak mechanism is represented by a resistive path [22]. An external input current is injected through another resistive 3
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branch [22]. As a result, the membrane voltage follows the dynamics of a standard resistor–capacitor (RC) circuit, expressed in continuous time by [2] dVm (t) τm = −Vm (t) + Rm I(t), (1) dt where Vm (t) is the membrane potential, τm is the membrane time constant, Rm is the membrane resistance, and I(t) is the synaptic input current. Digital implementations require a discretized version of the LIF dynamics, evaluated at distinct timesteps. Using a forward Euler method with timestep ∆t, the discrete-time membrane update can be written approximately as [2] Vmupdated [t] = (1 − α) Vm [t] + I[t], where α = 1 − e
−∆t τm
(2)
is the leak factor.
The synaptic input current at each timestep is computed as a weighted sum of presynaptic spikes, [2] I[t] =
k X
Wi Si [t],
(3)
i=0
where Wi is the synaptic weight and Si [t] ∈ {0, 1} is the spike from the i-th presynaptic neuron at time t. The neuron emits an output spike whenever its updated membrane potential exceeds the firing threshold Vth : [2] ( 1, if Vmupdated [t] ≥ Vth , Sout [t] = (4) 0, otherwise. Finally, the membrane potential for the next timestep is either reset to the reset potential (if a spike is generated) or set to the updated value (if no spike occurs): [2] ( Vreset , if Vmupdated [t] ≥ Vth , Vm [t + 1] = (5) Vmupdated [t], otherwise. In summary, each timestep of the LIF neuron involves: (i) synaptic computation, where the input current I[t] is obtained by accumulating weighted presynaptic spikes according to (3); and (ii) neuronal computation, where the membrane potential is updated via leaky integration, compared against the threshold, and either reset or carried forward according to (2)–(5). Figure 1 illustrates this complete process. The most common structure is the Spiking Feedforward Neural Network (SFNN), in which neurons in each layer receive spikes only from the preceding layer [25], with connections being either fully connected or sparse, as illustrated in Figure 2a. Such architectures are typically used in pattern-recognition tasks, including classification of static sensory inputs [27]. Beyond feedforward architectures, the Spiking Recurrent Neural Network (SRNN) is another important structure, in which neurons form a sparse, irregular recurrent graph with randomized connectivity [2], as shown in Figure 2b. Such networks are particularly well suited for temporal processing, including speech recognition, gesture sequence classification, and general time-series analysis [26].
3
Related Work
A wide range of neuromorphic processors and accelerators have been proposed to enable low-power inference and learning in SNNs. One representative design is ODIN [30], a fully digital neuromorphic processor capable of simulating 256 neurons with 64k synapses and supporting on-chip online learning through the Spike-Driven Synaptic Plasticity (SDSP) rule. ODIN employs a time-multiplexed crossbar organization, in which synapse and neuron update logic are shared over time to emulate a large synaptic array while significantly reducing area and power overhead. Its architectural organization is structured into three conceptual stages—analogous to dendrites, soma, and axon—corresponding respectively to excitatory/inhibitory weight accumulation, subthreshold neuron dynamics, and event generation. ODIN also extends the Address-Event Representation (AER) [31] protocol to support multiple event types, including neuron spikes and time-reference events, enabling fully event-driven computation. A key component is its internal event scheduler, which manages single-spike and burst events using a combination of a 32-stage FIFO and multiple rotating 4-stage FIFOs. This event-centric architecture supports both inference and online learning with high energy efficiency. However, the time-multiplexed crossbar requires updating the full set of postsynaptic entries for each presynaptic spike, 4
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Synaptic Computations t=3
t=2
t=1
t=0
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t=2
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t=0
Synapse 1 Vrest W2
Input Current
Synapse 2
Output Spikes W4
Synapse 3
Input Spikes Figure 1: Synaptic and neuronal computations in a discrete-time LIF neuron. Presynaptic input spikes are weighted and accumulated to form the input current, which is then integrated by the LIF membrane dynamics to produce output spikes.
Recurrent SNN
Feedforward SNN
Sparse
(b)
Fully-Connected
(a)
Figure 2: Common connectivity schemes in SNNs. (a) Feedforward SNNs with either sparse or fully-connected layers. (b) Recurrent SNN, representative of reservoir or liquid-state topologies.
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which may introduce scalability challenges when network connectivity is sparse, due to many SRAM accesses that do not contribute to computation. A contrasting approach is demonstrated by Spiker+ [32], a configurable hardware–software framework that automatically generates FPGA-based SNN accelerators from high-level network descriptions. In Spiker+, each neuron in a layer is mapped to a lightweight physical neuron core implementing variants of the LIF model, enabling high degrees of parallelism for fully connected feedforward and recurrent networks. The control flow is intentionally simple and hierarchical: neuron-level, layer-level, and network-level control units coordinate computation through a two-signal start/ready handshake. Spikes are propagated through parallel inter-layer connections, allowing clock-driven real-time inference on small workloads. The architecture is designed to minimize logic complexity and power consumption; however, its fully parallel neuron-per-neuron mapping requires accessing all synaptic weights in parallel at each timestep, making on-chip memory capacity the primary scalability constraint. This resource requirement limits the practical size of networks that can be deployed on FPGA devices. ODIN and Spiker+ represent two opposing extremes of a fundamental design trade-off: minimizing hardware resources at the cost of throughput, or maximizing parallelism at the cost of scalability. Neither addresses the intervening design space of balancing fine-grained parallel execution with efficient resource utilization under irregular connectivity– precisely the gap that motivates the architecture proposed in this work. To exploit parallelism in neuromorphic systems, partitioning, mapping, and scheduling are essential steps. SpiNeMap [33] is a prominent work addressing this problem for multi-crossbar neuromorphic hardware. It provides two stages—SpiNeCluster and SpiNePlacer—to partition and map large SNNs onto crossbar arrays connected via a shared interconnect. SpiNeCluster partitions the network into clusters that fit within individual crossbars while minimizing the number of spikes communicated on global synapses—synapses that connect two different clusters—since they generate inter-crossbar traffic, increase spike latency, and consume energy. To achieve this, SpiNeCluster uses a heuristic inspired by the Kernighan–Lin graph-partitioning method. SpiNePlacer then determines where clusters should be placed on the physical crossbars. Placement affects energy and latency because spikes may need to traverse multiple hops in a NoC to reach their target crossbar. SpiNePlacer uses particle-swarm optimization (PSO) combined with Noxim++, an extended cycle-accurate NoC simulator, to evaluate hop counts, routing behavior, congestion, and energy. This two-phase strategy allows SpiNeMap to jointly reduce interconnect energy and spike latency. However, SpiNeMap does not model cluster-level workload balance: some clusters may contain significantly higher firing rates than others, which can create per-crossbar bottlenecks and reduce achievable parallel throughput. A different perspective is taken in the synapse-centric mapper for SpiNNaker systems [34]. SpiNNaker [35] consists of many interconnected chips, each containing 18 ARM cores with limited Tightly Coupled Memory (TCM)—32 KB for instructions and 64 KB for data—and shared SDRAM accessed via DMA. Traditional SpiNNaker mapping assigns post-synaptic neurons to cores, with each core performing both synaptic and neuronal computation for its assigned neurons [36]. In sparse networks, however, this neuron-centric partitioning becomes inefficient because DMA fetches fan-out–organized rows from SDRAM, and short sparse rows force repeated DRAM accesses, increasing latency and reducing throughput. The synapse-centric mapper restructures the computation by splitting synaptic and neuronal processing across separate cores. Some cores become synapse cores, each responsible for a subset of synaptic rows, while others act as neuron cores that perform membrane updates. Synaptic rows are distributed among synapse cores in a workload-aware way that accounts for firing activity, ensuring more balanced load and better utilization. This design increases the efficiency of DRAM row fetches because every fetched row is fully consumed by the assigned synapse core. However, separating synapse computation introduces a partial-sum merging overhead: neuron cores must retrieve partial contributions from SDRAM and accumulate them, which can become a communication bottleneck and limit achievable parallelism. Together, these two frameworks indicate a gap. SpiNeMap [33] focuses on reducing interconnect cost (global-synapse traffic and placement-induced latency), whereas the synapse-centric mapper [34] focuses on core-level workload balance and efficient memory access. Neither framework simultaneously addresses balanced distribution of synaptic workload across parallel compute units and efficient merging of partial neuronal results without introducing bottlenecks, which could improve the resource utilization significantly. This highlights the need for a mapping strategy capable of distributing synchronous synaptic load evenly while also supporting a scalable mechanism for combining partial results in parallel.
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Index
ctrl
Neuron index Routing Bitstring SRAM
0 1
1 0 1 0 1 1 0 0
N
Index Routing Bitstring ctrl
Multi-Cast Tree
Packet Injector
MC switch
MC switch
MC switch
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Internal Buffer
MC switch
MC switch
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Synapse Processing Unit
ME switch
ME switch
Spike Handler
MC switch
Synapse Processing Unit
ME switch
ME switch
Merge Tree
ME switch
Input Interface
Index
Current
Neuron Unit
Output Buffer Interface
Figure 3: Overview block diagram of SupraSNN Hardware Architecture.
4
SupraSNN Hardware Architecture
4.1
Design Overview
Figure 3 illustrates the overall architecture of SupraSNN, composed of five principal components. The parallel Synapse Processing Units (SPUs) receive spike events and concurrently execute their assigned synaptic operations. The Routing Unit stores a per-neuron bitstring that encodes which SPUs demand that neuron’s spike information. The MC Tree forms a binary dispatch fabric that propagates incoming spikes exclusively to the relevant SPUs, guided by the routing bitstring. The ME Tree serves as a bufferless accumulation fabric that sums the partial results produced by all SPUs in a synchronized manner. Finally, the centralized Neuron Unit receives the fully accumulated synaptic results, updates each neuron’s membrane state according to the LIF dynamics, and generates output spikes for the next timestep. Drawing inspiration from superscalar processors, these components collectively provide high levels of synapse-level parallelism while maintaining deterministic neuron-state updates. In this architecture, synaptic computations are distributed across multiple parallel units, whereas neuronal state is maintained in a single shared unit, analogous to centralized architectural state in superscalar microarchitectures. 7
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LIF
Current
Potential 2
load update
LIF
Current
END Invalid
1
Invalid
3
t=2
Invalid
t=3 t=4
END
Execution Flow
t = 4 END
Start
Spike
Invalid
0
0 1
0
0 0 0 0 1 0 0 -
Spike
Operation Table Pre Post
Spike
1 6 NOP NOP 4 3 NOP NOP 4 1 4 0
0
Index Partial Current
END
0
6
W45
5
W23 + W43
3
W22
0
2
SPU 1
Partial
0
0 Current 6
1
W16
load
LIF
Current
Invalid Invalid
1
W40
0
0
END
Invalid
1
0
Index Partial Current
Partial
0 1
W43
3
W43
Index Partial Current
Partial Spike - Current 0 0
0
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1
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Index Partial Current
Invalid
t=2
Invalid
2
t=3
2
t=4
END
Start
Execution Flow Spike
0 0 1 0 0 0 0 -
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Operation Table Pre Post
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Spike
5 6
6 5
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NOP NOP
Partial 1 Current 1 W41
0 1
1 W41 Index Partial Current
Partial
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1 Current 0
1
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0
2
2
NOP NOP NOP NOP
W40
Index Partial Current
End of Execution
t=6 6 0 t=7 W45 5 3 W23 + W43 t = 8 t=9 0 1 W41 t = 10 t = 11 0 W40 END t = 12 0 Invalid
Current W21 + W41
Invalid
Invalid
Spike Mem 0
1 Current 3
Spike
t=1
Index Partial Current
Partial - Current 0 0
Spike
ME Packets 6 0
Invalid
Neuron Unit
END
0
SPU 2
Partial
0 Current 6 W56 Partial
0 Current 5 W65 Partial
- Current 0 0
Partial 1 Current 2 W22 Partial - Current 0 0 Partial
- Current 0 0
End of Execution
0 1
t=4
ME Packets 6 0
6 4 5
Execution Flow
Start
Index Partial Current
t=5
4
t=3
3 t=0
Spike
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t=2
t=2
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t=7
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2
END t = 3
Spike
t=8
t=1
t=1
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t=9
Invalid
Invalid
0
Spike
t = 10
0
Index Partial Current
LIF
t = 14 t = 13 t = 12 t = 11 t = 10 t = 9
Invalid
1
load reset
Potential 0 update
MC Packets
0
End of Execution
load reset
W23
Index Partial Current
W10
Potential 3
Potential 1
0
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Current
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LIF
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load
4 END
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5
Index Partial Current
Partial
Neuron Mem Neuron Dynamic load LIF Current Potential 6 update
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1
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2
W22
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0
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0 0 1 0 0 0 0 -
Operation Table Pre Post
NOP NOP NOP NOP NOP NOP 3 2 2 1 NOP NOP
0
Index Partial Current
END
0
SPU 3
t = 11
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t=8
2 3 4 5 0 3 NOP NOP NOP NOP 1 0
t=0
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t=9
Operation Table Pre Post
Invalid
Invalid
Invalid
Index Partial Current
0
W45
t = 10
4 END 3 1 END
W23
Partial
1 Current 5
t = 11
Internal Buffer
0 0 1 0 1 0 0 -
0 1
t=4
1 Invalid
t=6
t=6
Spike
Spike Mem
Partial
1 Current 3
Invalid
t=7
t=5
Spike
t=7
Start
ME Packets 0
END
t=3
t=8
Execution Flow
t=2
Mapped SNN
t=9
2
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t = 10
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4
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t=6
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t=0
t = 4 END
From Off-chip
4
t=1
t = 10
Packet Injector
Invalid
t = 11
t=0
t=0
t = 11
Multi-Cast Tree
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6 5 t=6 0 t=7 6 0 t=8 W45 5 3 W23 + W43 t = 9 t = 10 2 W22 1 W21 + W41 t = 11 t = 12 0 W40 END t = 13 0
Invalid
Invalid
2 1 Invalid
END
Partial
- Current 0 0
ME Packets 0
Invalid
Index Partial Current
Partial - Current 0 0 Partial
- Current 0 0
0
Invalid
1
0
Index Partial Current
0
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0
Index Partial Current
Partial 0 Current 2 W32 Partial 1 Current 1 W21 Partial
- Current 0 0
0 1
2
0
Index Partial Current
0 1
1
W21
Index Partial Current
0
Invalid
1
0
Index Partial Current
End of Execution
0 0 0 W22 W21 0 0
0 1
END
0
t=6 t=7 t=8 t=9 t = 10 t = 11 t = 12
Merge Tree
t=8
Figure 4: Abstract representation of the execution dataflow of a sample SNN on SupraSNN for one timestep. 4.2
Data/Execution Flow Explanation
Figure 4 illustrates the execution dataflow of a simple SNN mapped onto the SupraSNN architecture during a single simulation timestep. The corresponding network topology, shown in the top-right corner of the figure, consists of seven neurons (indexed 0 to 6), where neuron 4 serves as an input neuron receiving spikes from off-chip. During the mapping stage, all synaptic connections are partitioned across the SPUs and stored in local Operation Tables, enabling parallel synaptic operations across distinct hardware units. Each entry encodes essential synaptic parameters, including preand post-synaptic neuron indices. For instance, the first entry of SPU 0 stores the synapse from neuron 2 to neuron 3 (synapse 2→3). Execution begins with the distribution of spike packets generated during the previous timestep. These AER-inspired [31] MC packets contain the source neuron index and are initially held in the Internal Buffer. Once all SPUs signal readiness, the Packet Injector sequentially transmits these packets into the MC Tree. In this example, neurons 4 and 2 fired in the preceding timestep; their corresponding MC packets are injected into the tree at t = 0 and t = 1, respectively. Here, t represents abstract execution step rather than concrete clock cycles, serving only to illustrate the ordering of execution within the architecture. The MC Tree routes these packets exclusively to targeted SPUs. As shown in Figure 4, the root node routes the packet for neuron 4 solely toward the left subtree, where it is duplicated to reach SPU 0 and SPU 1 at t = 2. Upon receiving a packet, each SPU registers the event in its local Spike Memory by asserting the corresponding neuron bit, holding it until the end of the current timestep. After distributing all spike events, the Packet Injector broadcasts an end packet as a synchronization barrier. Upon receiving this packet, all SPUs concurrently begin executing the synaptic operations ordered within their local Operation Tables. If a pre-synaptic neuron’s bit is active in the Spike Memory, the SPU accumulates the corresponding synaptic weight into a local partial current assigned to the target post-synaptic neuron. Because a neuron’s total fan-in may be spatially partitioned across multiple SPUs, these distributed partial contributions must be aggregated prior to the 8
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Table 1: MC packet types ctrl 00 01 10 11
Payload description Invalid data Index of neurons that spiked in the last timestep Index of unit targeted for initialization Initialization data for the selected unit
state update phase. For example, at t = 9, SPU 1 and SPU 3 concurrently generate partial currents W41 and W21 for post-neuron 1. An SPU forwards its accumulated partial current to the ME Tree immediately after processing its final synapse for a given post-synaptic neuron. For example, synapses 2→3 and 0→3 are both mapped to SPU 0. Although synapse 2→3 is computed at t = 5, SPU 0 wait until synapse 0→3 completes at t = 7, at which point the partial current for post-neuron 3 is injected into the ME Tree. The ME Tree aggregates distributed partial currents without intermediate hardware buffering, a feature sustained by a compile-time scheduler that synchronizes all SPU output injections for a given post-neuron. SPUs lacking synapses to a currently processing post-synaptic neuron perform a No-Operation (NOP) and transmit an invalid packet to maintain pipeline synchronization. To see this merging mechanism in action, consider post-neuron 1. At t = 9, SPU 1 and SPU 3 inject their valid partial currents W41 and W21 into the ME Tree, while SPU 0 and SPU 2 simultaneously emit invalid packets. At intermediate nodes of the tree, valid partial currents propagate forward unaffected when merged with invalid packets. These wavefronts converge at the root of the ME Tree at t = 10, delivering the fully resolved input current W41 + W21 to the Neuron Unit at t = 11. Following the completion of all local synaptic operations, each SPU issues an end packet into the ME Tree. These signals converge into a single global synchronization packet at the root node, indicating that all synaptic current accumulations for the timestep are finalized. The unified Neuron Unit receives these completed input currents and sequentially updates the state variables for all neurons. Utilizing a discrete-time LIF model, it computes the new membrane potential from the previously stored state and the incoming current. If the updated potential exceeds the firing threshold, the Neuron Unit generates an MC packet containing the firing neuron’s index and writes it into the Internal Buffer; in this trace, neurons 3 and 1 register spikes at t = 10 and t = 12, respectively. Once the end packet arrives from the ME Tree, the Neuron Unit forwards it to the Internal Buffer. Concurrently, off-chip input spikes are caught by the Spike Handler and placed in the Internal Buffer, capped by an external end packet. The timestep concludes when the Packet Injector encounters two distinct end packets in the Internal Buffer: one from the Neuron Unit signaling the completion of internal state updates, and one from the Spike Handler indicating the end of external inputs. Upon detecting both barriers, the Packet Injector issues a final end packet to the MC Tree, advancing the global system state to the subsequent simulation timestep. 4.3
MC and ME Communication Fabric
To realize a lightweight multicast fabric, SupraSNN appends a routing bitstring to each MC packet, explicitly specifying the target SPUs. A programmable SRAM within the Routing Unit stores one bitstring per neuron, where each bit corresponds to one SPU and indicates whether that SPU holds any synapse originating from that neuron. To utilize this bitstring for routing, as illustrated in Figure 5a, each MC switch divides it into two equal halves corresponding to the left and right sub-trees and applies a simple OR reduction to each half. The MC packet is forwarded to every direction whose associated half contains at least one set bit. This design avoids the overhead of embedding large routing tables inside switches, which would require 2N (M − 1) bits of routing memory for N neurons and M SPUs, compared with only N M bits required by the bitstring approach–a clear advantage for any practical design employing more than two SPUs. Beyond spike delivery, SPUs store synaptic attributes–including pre- and post-synaptic neuron indices and synaptic weights–which must be initialized prior to execution. SupraSNN extends the MC packet format to support highbandwidth, packet-based initialization through the MC Tree itself, reusing the communication fabric to significantly reduce initialization latency. Only small configuration fields are programmed via conventional bitstreams. Each MC packet contains a 2-bit control header (ctrl) and a data payload, enabling four distinct packet types summarized in Table 1. Packets with ctrl = 00 carry invalid data and allow the MC Tree to operate synchronously without handshaking, simplifying switch logic and reducing control overhead. When ctrl = 01, the payload contains the index of a neuron 9
SupraSNN
packet in
A P REPRINT
parent parent en clr
left packet en
ctrl
index
right packet
clr
bitstring
local index
MC Switch
current
local index
left index
Control Unit
index select
0
ctrl
index left packet
ctrl
bitstring left en
left clr
right right clr en
index
bitstring
current
right index packet en packet init
1
current
local index
en
ME Switch
init
right packet packet out
(a)
(b)
Figure 5: (a) Micro architecture of a MC switch (b) Micro architecture of a ME switch.
that generated a spike in the previous timestep. For initialization, packets with ctrl = 10 broadcast the target unit index to all programmable units–including SPUs, the routing bitstream unit, and the Neuron Unit–placing the matching unit into an initialization state. Subsequent packets with ctrl = 11 deliver the corresponding initialization data, which the selected unit consumes while others ignore. The ME Tree combines partial synaptic results generated by different SPUs through a simple bufferless adder-tree structure. Rather than employing complex buffering switches that wait for all partial results of a neuron to arrive–which incurs substantial area and power overhead–SupraSNN restricts SPUs to a pre-determined injection order so that all partial results for each neuron are injected simultaneously, eliminating buffering entirely. As illustrated in Figure 5b, each ME switch receives two packets per cycle from its left and right subtrees. If both packets carry the same neuron index, their currents are accumulated and forwarded as a single packet. If either input carries an invalid index, the valid packet is forwarded unchanged. To enable seamless communication across the MC and ME fabrics as explained in the Section 4.2, two reserved indices are defined: the end index and the invalid index. The end index is encoded with all bits set to one and serves as a termination marker in the dataflow. The invalid index follows the same encoding except that its least significant bit is cleared to zero. The paired multicasting-and-merging fabric draws inspiration from the Distribution Tree and Augmented Reduction Tree of MAERI [37], originally proposed for flexible DNN dataflow mapping, and adapts this paradigm to SNN-specific requirements including spike-based selective multicasting via routing bitstrings and bufferless synchronous partial current merging. 4.4
Parallel Synapse Processing Units (SPUs)
Figure 6 illustrates the architecture of a SPU. SPUs are responsible for performing synaptic computations in parallel and are designed to provide programmability, energy efficiency, and full flexibility with respect to network connectivity. 4.4.1
Spike Storage and Event Handling
Synaptic processing in each SPU begins with the Spike Memory, a bitmap SRAM that records the spiking activity of the previous timestep as conveyed by MC packets. Each neuron is represented by a single bit indicating whether it fired in the last timestep. The memory is organized into rows of WSM bits (set to 4 in Figure 6). To simplify addressing, WSM is chosen as a power of two: the log2 WSM least significant bits of the neuron index determine the bit position within a row, while the remaining index bits select the corresponding row. When an MC packet arrives, the Set/Clear Spike unit sets the corresponding bit in Spike Memory to reflect the received spike event. This bitmap organization scales as O(N ) in total memory, avoiding the O(N log N ) memory burden that buffering neurons’ indices would otherwise impose. 10
SupraSNN
A P REPRINT
MC Tree Packet SPU ID
Index
Control Unit (FSM)
ctrl
OpT ren
Fetch Stage
Post End Pre End
ctrl
Spike
cnt co
cnt en
saddr sel
Memory Stage set/clr
Set/Clr Spike read write line
waddr
update UM addr spike ren UM ren sel
Execution/Write-Back Stage
set/clr
line
spike wen
saddr sel
set/clr
Post End Pre End
wdata wen
Spike Memory raddr
Operation Table Post Addr
Weight Addr
Spike Addr
Pre Post End End
spike ren
0
raddr
1
ren
OpT ren
Spike
rdata
ren
Unified Memory Weight 0
Weight 1
Weight
2 Weight K-1 K-1
Local Index
Partial Current
raddr ren
Operation Counter
UM addr sel
co
en
cnt co
cnt en
Partial Current rdata
waddr
wdata
UM ren
Local Index
wen
update 1
0
Spike
Post End 1
0
0
Index
Current
ME Tree Packet
Figure 6: Micro-architecture of SPU. Reception of an MC packet carrying the end index indicates that all spike events for the current timestep have been delivered. At this point, the SPU can safely assume that Spike Memory contains a complete and consistent snapshot of presynaptic activity and can begin synaptic computation (as explained in section 4.2 and shown in Figure 4). 4.4.2
Pipeline Organization and Operation Table
Each SPU employs a three-stage pipeline composed of the Fetch, Memory, and Execution/Write-Back stages. During the Fetch stage, an Operation Counter iterates through entries in the Operation Table, which stores synaptic attributes in an indirect form by storing addresses rather than explicit data values. Each entry in the table specifies the information required to process a single synaptic operation and contains the following five fields: • Post Addr: the address of the post-synaptic neuron state in Unified Memory, • Weight Addr: the address of the synaptic weight in Unified Memory, • Spike Addr: the address of the corresponding pre-synaptic neuron, • Pre End: a flag indicating that this is the final operation associated with the given pre-synaptic neuron for the current timestep, enabling the reset of the corresponding bit in Spike Memory for the next timestep, • Post End: a flag indicating that this is the final operation associated with the given post-synaptic neuron for the current timestep. 11
SupraSNN
A P REPRINT
The proposed operation-based implementation provides several architectural advantages: 1. Mitigating Weight-Sparsity Overhead: Zero-weight synapses do not contribute to the postsynaptic neuron state and therefore have no effect on the final simulation results. In the proposed operation-based scheme, zero-weight synapses are simply omitted from the Operation Table. Consequently, both execution time and memory footprint are reduced. 2. Weight Reusability: The architecture stores each unique weight only once in the Unified Memory. Synapses sharing the same weight reference it through the Weight Addr field in the Operation Table, enabling efficient weight sharing across multiple synapses without duplication. Furthermore, for tasks requiring larger weight precision, referencing weights through compact addresses rather than storing explicit values substantially reduces the overall memory footprint. 3. Support for Irregular Connectivity: By explicitly storing the addresses of both pre- and post-synaptic neurons, the operation-style representation naturally supports arbitrary connectivity patterns. This flexibility enables the architecture to efficiently accommodate irregular network topologies commonly found in modern and advanced SNN models. 4. Overlapping Synaptic Computation and Merging: As illustrated in Figure 4, the architecture increases throughput by overlapping synaptic computation with current merging in the ME Tree. Each partial current generated by an SPU is forwarded to the ME Tree immediately after it is produced, facilitated by the Post End flag, which marks the final synapse associated with a particular post-synaptic neuron within that SPU. Since the ME Tree operates without internal buffering, the scheduling framework exploits the programmable execution order provided by the Operation Table to guarantee that partial currents targeting the same post-neuron are injected simultaneously across all SPUs. 4.4.3
Memory Access and Unified Memory
In the Memory stage, the Spike Addr field is used to read the corresponding bit from the Spike Memory, indicating whether the pre-synaptic neuron spiked in the previous timestep. In parallel, the Unified Memory is accessed to retrieve both the synaptic weight and the partial input current of the post-synaptic neuron, enabling both operands to be available for the subsequent execution stage. Rather than allocating separate memories for weights and neuron partial currents, SupraSNN employs a unified storage structure. This design choice increases flexibility for the co-design framework, which can trade storage capacity between weights and post-synaptic neuron states depending on the partitioning strategy. To further improve numerical robustness, K weights are packed into a single memory line, while post-synaptic neuron entries store a local neuron index along with a wider partial-current field. Local indices are assigned to internal neurons (excluding input neurons) to reduce index width and memory footprint. Assuming the Unified Memory size is SU M , the width of Post Addr should be log2 SU M to select a single entry from the Unified Memory. In contrast, Weight Addr requires an additional log2 K bits to select one weight among the K weights packed within a memory line, which is performed using a multiplexer (MUX). Ideally, the Unified Memory would provide two read ports (one for reading the weight and one for the partial current) and a single write port, thereby supporting a throughput of one operation per cycle. To reduce memory area and power consumption, especially in FPGA-based implementations, the Unified Memory is instead realized with a single read port, accompanied by a MUX that selects between the Weight Addr and Post Addr. Consequently, each operation is executed over two cycles: the SPU first reads and registers the synaptic weight, and then, in the subsequent cycle, reads the associated partial current. This results in an effective throughput of 0.5 operations per cycle. 4.4.4
Execution, Write-Back, and ME Packet Generation
In the Execution/Write-Back stage, the synaptic weight is conditionally added to the partial current depending on the spike status of the pre-synaptic neuron. If the pre-synaptic neuron spiked, the updated partial current is written back to Unified Memory. When the Pre End flag is asserted, the Set/Clear Spike module clears the corresponding spike bit in the associated Spike Memory line. The updated line is then written back to the Spike Memory, thereby resetting the spike state and preparing the memory for the next timestep. When the Post End flag is asserted, the partial current accumulated for the post-synaptic neuron represents the final synaptic contribution of that SPU for the current timestep. The partial current is therefore reset by selecting zero, rather than the updated value, through a MUX before the write data port of the Unified Memory. Moreover, an ME packet carrying the post-synaptic neuron’s local index and the partial current is injected into the ME Tree. 12
SupraSNN
A P REPRINT
ME Tree Packet Index Current
Thresholding & Write-Back Stage
Accumulation Stage
Leakage Stage
Loading State Stage
Threshold
Spike
state wen
a–b a
b
b
a>b a
waddr
wdata
wen
Neuron State SRAM Membrane Potential
Global Index Output
raddr
>> val
0
amount
Output
ren
State ren
Spike
Output
1
Spike
Global Neuron Index Output state wen state ren (Spike Packet) 01
Index
Vreset
Control Unit (FSM)
Shift Amount
ctrl
MC Tree Packet
Output Buffer Interface
Spike Handler Interface
Figure 7: Micro-architecture of Neuron Unit.
5
Centralized Neuron Unit
As discussed previously, neuronal computation in SupraSNN is performed by a centralized Neuron Unit, which time-multiplexes neuron updates and maintains all neuron state. The LIF dynamics are implemented using simple add-and-shift operations derived from (2)–(5), minimizing area and power consumption. Figure 7 presents the architecture of the Neuron Unit. A programmable Neuron State SRAM stores the membrane potential, its global index, and an output flag for each neuron. The global index is necessary because SPUs operate on local indices, while spike packets must reference the neuron’s global identifier. The output flag designates neurons whose spike events must be forwarded to both the internal and output buffers. Neuron-model parameters that are not commonly trained online, such as Vreset , the shift amount implementing α, and the firing threshold, are programmed through the hardware bitstream, while the Neuron State SRAM is initialized using MC packets explicitly routed to the Neuron Unit, enabling flexible post-fabrication configuration. The Neuron Unit implements a four-stage pipeline comprising the Loading State, Leakage, Accumulation, and Thresholding & Write-Back Stages. Processing is initiated in the Loading State Stage upon the arrival of an ME packet from the ME Tree, which carries the accumulated input current together with the local index of the target post-synaptic neuron. The corresponding neuron-state entry is then fetched from the Neuron State SRAM. In the subsequent Leakage Stage, the term (1 − α)Vm from (2) is computed, with the leak factor α approximated to the nearest power of two, replacing multiplications with programmable right-shift operations and reducing hardware complexity. This term is added to the input current in the Accumulation Stage to produce Vmupdated . 13
SupraSNN
A P REPRINT
During the Thresholding & Write-Back Stage, this value is compared against the firing threshold: if exceeded, a spike-event MC packet containing the neuron’s global index is generated and inserted into the Internal Buffer; when the output flag is asserted, the same packet is additionally forwarded to the output buffer. The membrane potential is then reset to Vreset upon a spike or updated to Vmupdated otherwise, selected through a MUX. Upon receiving an ME packet carrying the end index, the Neuron Unit generates a corresponding MC packet and inserts it into both buffers, signaling the Packet Injector that neuronal computation for the current timestep has completed.
6
Partitioning and Scheduling Framework
6.1
Problem Formulation
SupraSNN exposes parallelism at the synapse level, in contrast to neuromorphic processors that operate primarily at the neuron level. Each SPU contains a Unified Memory responsible for storing both synaptic weights and partial post-synaptic currents, while an Operation Table stores the mapped synapses and their execution order. We formulate the problem of partitioning synapses among SPUs and scheduling their execution such that memory constraints are satisfied and correctness of the ME Tree merging is preserved. We model a spiking neural network as a weighted directed graph G = (V, E, W ),
(6)
where V denotes the set of neurons, E ⊆ V × V denotes the set of directed synapses, and W : E → R assigns a weight to each synapse. Given M SPUs, a partitioning maps each synapse to an SPU via π : E → {1, . . . , M },
(7)
inducing a synapse cluster Di = {e ∈ E : π(e) = i}, (8) a post-synaptic neuron set Pi , and a weight set Qi for each SPU i. Synapse clusters are disjoint (∀i ̸= j : Di ∩ Dj = ∅), whereas post-synaptic neuron sets may overlap (Pi ∩ Pj ̸= ∅), since synapses targeting the same neuron may be distributed across multiple SPUs, generating partial results that must later be merged. This partitioning must satisfy the Unified Memory capacity constraint on each SPU: |Qi | + 1 + |Pi | ≤ L ∀i : K
(9)
where the Unified Memory contains L memory lines, and each line can store either one post-neuron state or K concatenated synaptic weights. This constraint defines a combinatorial optimization problem that is NP-complete in general, motivating the use of heuristic methods for large-scale SNNs. While any partitioning that satisfies this constraint is functionally valid, different solutions result in significantly different throughput characteristics. A naïve round-robin partitioning of synapses achieves near-perfect load balance but requires each SPU to store partial currents for almost all post-synaptic neurons, resulting in excessive memory usage. Conversely, grouping all synapses of each post-synaptic neuron onto a single SPU minimizes memory usage but produces severe load imbalance and reduced throughput. Following partitioning, a scheduling problem determines the execution order of synaptic operations within each SPU. Since SPUs overlap synaptic computation with merging, correctness of the ME Tree requires that the final synapse contributing to a given post-neuron completes in the same cycle across all SPUs storing its partial state. The scheduling therefore augments the partitioned representation with an execution order σi for each SPU i. While any order preserving this alignment is correct, the choice strongly affects throughput: scheduling high fan-in neurons early reduces available slack and increases the critical path, whereas deferring them allows greater overlap between computation and merging. Consequently, scheduling must jointly consider merge-alignment constraints and throughput optimization. To address these challenges, we propose a framework consisting of two components: Probabilistic Partitioning and Heuristic Scheduling, whose overall flow is illustrated in Figure 8. 6.2
Probabilistic Partitioning Algorithm
In large-scale SNNs, the number of synapses to be mapped onto the multiple SPUs of SupraSNN can be extremely large, making exhaustive optimization impractical due to the exponential complexity of the problem. To address this challenge, we propose a probabilistic partitioning algorithm that efficiently explores the performance–memory trade-off. 14
SupraSNN
A P REPRINT
End
Start
Input: SNN graph 𝐺 = 𝑉, 𝐸, 𝑊 Number of SPUs 𝑀 Unified Memory Capacity 𝐿 Weight Packing Factor 𝐾
Output: Synapse-to-SPU mapping 𝜋 𝐷𝑖 , 𝑃𝑖 , 𝑄𝑖 for all SPUs Operation Tables 𝑂
Probabilistic Partitioning
Heuristic Scheduling
Initialize probability tables
Generate execution orders O = 𝜎1 , … , 𝜎𝑀 (Minimizing NOPs)
Probabilistic Partitioning
Heuristic Scheduling
Assign synapses 𝐸 → 𝐷1 , … , 𝐷𝑀 Construct post-neuron sets 𝑃𝑖 Construct weight sets 𝑄𝑖
Determine ME-Packet commit order (Neurons with a greater number of synapses within a single SPU are placed later)
Probabilistic Partitioning
Update probability tables (Try to aggregate the post-neurons and exploit weight reuse) No
∀𝑖 ∶
𝑄𝑖 + 𝑃𝑖 ≤ 𝐿 𝐾
Yes
Figure 8: Flowchart of the software framework responsible for partitioning and scheduling. It has utilized a probabilistic partitioning along with a heuristic scheduling. The algorithm employs a binary tree structure, referred to as the Partitioning Tree, which mirrors the topology of the ME Tree and is composed of Probability Switches. As illustrated in Figure 9, all synapses are initially located at the root, grouped according to their post-neurons and awaiting distribution. Starting from the root, synapses are progressively sent through successive tree levels and Partitioning Switches until they reach a leaf SPU, producing a partitioned distribution of the workload. In other words, the switch specifies whether the synapse will ultimately be executed by an SPU located in the left or right subtree. Figure 9 illustrates this process for the network from Figure 4. To realize this mechanism, each Probability Switch maintains two tables of identical dimensions |V | × |V |, matching the SNN adjacency matrix: a Probability Table P , where entry Pij represents the probability of sending synapse i → j toward the left subtree, and a Random Numbers Table R, populated with values sampled uniformly from [0,1]. During partitioning, the destination subtree of each synapse is determined by comparing Rij against Pij : if Rij < Pij , the synapse is sent left; otherwise right. All Probability Tables are initialized to 0.5, providing an unbiased starting point that naturally produces a nearly balanced workload distribution across SPUs. The final assignment of synapses to SPUs, shown at the bottom of SPUs in Figure 9, demonstrates that the workload is distributed in a nearly balanced manner. After the initial partitioning stage, the memory constraint defined in (9) may be violated by one or more SPUs. To quantify this, a score is assigned to each SPU according to |Qi | + 1 ScoreSPUi = L − + |Pi | (10) K where L denotes the Unified Memory capacity, Qi represents the set of weights assigned to SPU i, and Pi denotes the set of post-synaptic neurons mapped to that SPU. A negative score indicates a memory violation. In the example shown in Figure 9, the parameters are assumed to be K = 2 and L = 5. Under this configuration, SPU 0 achieves the highest score of +1, while SPU 1 and SPU 2 satisfy the memory constraint with a score of 0. In contrast, SPU 3 exceeds the memory capacity L = 5, resulting in the lowest score of −2. The SPU with the minimum score is therefore identified as the overloaded unit (SPU 3), whereas SPUs with higher scores are candidates for receiving redistributed workload. To alleviate the memory violation, a synapse is selected from the overloaded SPU for reassignment. Preference is given to synapses whose post-neuron is not shared with any other synapse within the same SPU (i.e., the last synapse associated with that post-neuron in the SPU). Removing such a synapse eliminates both its corresponding weight and the associated post-neuron entry, thereby freeing an entire memory line plus an additional 1/K fraction of memory. For instance, if a synapse were to be selected from SPU 0, synapse 4 → 5 would not be preferred because the SPU also 15
SupraSNN
0
A P REPRINT
SPU 0
SPU 1
SPU 2
SPU 3
Unified Memory
Unified Memory
Unified Memory
Unified Memory
ZERO
ZERO
ZERO
ZERO
Post-Neuron 1 Post-Neuron 3
Post-Neuron 0 Post-Neuron 2 Post-Neuron 3
Post-Neuron 2 Post-Neuron 3 Post-Neuron 6
— Post-Neuron 10 Post-Neuron 31 Post-Neuron 93 Post-Neuron 6
1
2
2→1
3
5
6
0
4→5 6→5
1
4→0
2
3
5
6
0
1
2
3→2 4→3
3
5
2→2 2→3
6
0
5→6
Random Numbers
0.5
0.45
0.5 0.5 0.5 0.44
0.5
0.26 0.52
0.5
0.5
0.75
0.5
0.45
0.71
0.5
0.5
0.45 0.5 0.5 0.5
Update Probability
0.33 0.58
0.44
0.26
0.5
0.5 0.5
0.52
0.5
0.5
0.75
0.5
0
1
2
3
0.5
0.48
0.5 0.42 0.36 0.66
0.5
Probability Table
0.5
0.5 Probability Table
0.42 0.36 0.66
0.5 0.5
3
5
0→3
6 1→6
0.53 0.48
0.5
0.73 0.58
2
Random Numbers
0.39 0.55
1
1→0 4→1
0.55
Update Probability
0.5
5
6
0
4→0 2→1 3→2 4→3 4→5 6→5
1
2
3
1→0 4→1 2→2 0→3 2→3
Probability Switch 2
5
6 1→6 5→6
Probability Switch 1
Random Numbers 0.74 0.65
0.48
0.5 0.5
0.5 0.5
0.45
0.5 0.5 0.5
0.42 0.58
0.44
0.5
0.5 0.5
0.26 0.52
0.5
0.5
0.75
0.42
<
0.5
Probability Table
0.42 0.36 0.66
0.55
Update Probability
0.5
0.5 0
1
2
3
5
6
4→0
1→0 2→1 2→2 0→3 4→5 1→6 4→0 4→1 3→2 2→3 6→5 5→6 4→3
Synapse Spliting
Probability Switch 0
Figure 9: The overview of the probabilistic partitioning algorithm. The partitioning tree consists of switches with the probability table. contains synapse 6 → 5. In SPU 3, which is the most overloaded SPU in the example, synapse 0 → 3 is selected for reassignment. The algorithm then identifies the most suitable destination SPU among the higher-scored candidates using the following priority order: 1. the highest-scored SPU that already contains both the corresponding post-neuron and weight, 2. the highest-scored SPU that contains the post-neuron, 3. the highest-scored SPU that contains the weight, and 4. otherwise, the highest-scored SPU. This priority order exploits post-neuron sharing and weight reuse to minimize the additional memory overhead incurred by the reassignment, with post-neuron sharing given higher priority since storing a post-neuron state occupies a full memory line compared to only 1/K of a line for a weight. In our example, while SPU 0 has the highest score, SPU 1 and 2 are more favorable choices since they have already stored post-neuron 3 entry. Introducing an assumption that W03 = W32 , SPU 1 incurs no additional memory overhead and is identified as the most suitable destination for synapse 0 → 3. To enforce the reassignment probabilistically, the partitioning tree is traversed from both the overloaded SPU (SPU 3) and the selected destination SPU (SPU 1) toward their lowest common ancestor (Probability Switch 0). Along the path from the overloaded SPU, probability entries are adjusted to decrease the likelihood that the selected synapse is sent to that subtree (e.g. P03 is increased in Probability Switch 1). Conversely, the probabilities along the path toward the underloaded SPU are modified to increase the likelihood that the synapse is routed to that subtree. The partitioning process is then repeated using the updated tables, and this iterative procedure continues until all SPUs satisfy the memory constraint or a predefined iteration limit is reached. A key design consideration concerns whether the Random Numbers Tables should be regenerated at each iteration or kept fixed. Regenerating them increases exploration but makes probability updates ineffective, preventing convergence. Keeping them fixed preserves the feedback mechanism but risks convergence to a local minimum. We adopt the latter approach and incorporate a perturbation mechanism to escape local minima: the framework monitors the average 16
SupraSNN
A P REPRINT
Partitioned Syanpses SPU 0
SPU 1
SPU 2
SPU 3
0
1
2
3
2→1
0
1
4→0
0
1
0
1
1→0
4→1
5
Scheduled Synaptic Operations t=0
6
4→5 6→5
2
3
3→2
4→3 0→3
2
3
2→2
2→3
2
3
5
6
t=1
t=2
t=3
t=4
t=5
SPU 0
NOP 2 → 1 NOP
SPU 1
4 → 0 NOP 3 → 2 4 → 3 0 → 3 NOP
SPU 2
NOP
SPU 3
1 → 0 4 → 1 NOP 1 → 6 NOP
NOP 6 → 5 4 → 5
Heuristic Scheduling
5
6 5→6
5
6 1→6
ME Packets Sending Order
0
NOP 2 → 2 5 → 6 2 → 3 NOP
1
2
6
3
NOP
5
Figure 10: The overview of the heuristic scheduling algorithm. SPU scores over the previous 100 iterations, and if this value fluctuates within a range smaller than 0.2 – indicating stagnation – a uniformly distributed random value in [-0.1, 0.1] is added to each entry of the Random Numbers Tables. This controlled perturbation slightly alters the partitioning behavior, allowing the search to escape the local minimum and continue progressing toward a feasible solution. Overall, the algorithm starts from a balanced initial partitioning and progressively clusters synapses sharing postneurons and weights to reduce memory usage, at the necessary cost of more unbalanced synapse distribution and lower throughput. The use of probability tables within the partitioning tree enables smooth exploration of the design space while converging toward a feasible partitioning. 6.3
Heuristic Scheduling Algorithm
After the synapses are assigned to the SPUs, their execution order must be scheduled. The key constraint in this scheduling problem is that all SPUs must inject the ME packets associated with the same post-neuron into the ME Tree during the same clock cycle. This requirement ensures the correctness of the merging operation performed by the tree. Subject to this constraint, the objective of the scheduler is to minimize overall latency. Figure 10 illustrates the proposed scheduling strategy using the sample SNN depicted in the top-right corner of Figure 4. The left side of the figure shows the synapse partitions assigned to each SPU, organized according to their post-neurons. To schedule the assigned synapses while satisfying the synchronization constraint, the algorithm first determines the ME-packet sending order. To maximize the available slack for synaptic computations, post-neurons are sorted in ascending order based on the maximum number of synapses they have on any single SPU. This ordering delays the injection of post-neurons that require more synaptic operations on a particular SPU, giving that SPU additional cycles to complete its computations before transmission. In the example, Neuron 5 has two synapses on SPU 0, and Neuron 3 has two synapses on SPU 1. Consequently, these post-neurons are placed at the end of the sending sequence. All other post-neurons contain at most one synapse per SPU and therefore appear earlier. This heuristic produces the ME-packet sending order shown at the bottom of Figure 10: 0, 1, 2, 6, 3, and 5. Once the sending order is determined, the execution order of synapses is specified. As described in the SupraSNN architecture, each SPU transmits the ME packet of a post-neuron immediately after its last synapse is computed. Accordingly, one synapse of each post-neuron is scheduled at its corresponding sending time. If a post-neuron has no synapse in a given SPU, the corresponding time slot remains empty and can later be utilized by other synapses. The remaining synapses are scheduled backward in time, starting from the last post-neuron in the sending order. The 17
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algorithm traverses cycle by cycle in reverse, placing synapses in available empty slots. This process is repeated sequentially for each post-neuron in reverse sending order. For example, Neuron 5 has two synapses on SPU 0. Its final synapse (4 → 5) is placed at t = 5, the ME-packet time for Neuron 5. To schedule the second synapse (6 → 5), the scheduler searches backward from t = 5 and finds that t = 4 is empty on SPU 0 because that SPU contains no synapse for Neuron 3, which transmits at t = 4. Starting from the last post-neuron is logical because its final synapse has already been fixed at the sending time, and no further synapses of that neuron may be scheduled afterward. Finally, any remaining empty slots are filled with NOP operations to maintain cycle-level synchronization across all SPUs.
7
Experimental Evaluation
7.1
Baseline Results
SupraSNN addresses digit classification in two modalities: visual and auditory digit recognition. For evaluation, we employ two standard benchmark datasets: MNIST [20] for visual digits and SHD [21] for audio-based spike representations of spoken digits. MNIST is a widely used baseline for assessing AI hardware implementations, which makes it an ideal choice for comparing our design with existing accelerators. This dataset consists of 60,000 training and 10,000 test samples, each being a 28 × 28 grayscale image of handwritten digits from 0 to 9. On the other hand, SHD is a dataset specifically designed for SNN applications. It contains approximately 10,000 high-quality recordings from 12 speakers pronouncing the digits 0 to 9 in both English and German. These recordings are converted into spike trains using an artificial model of the inner ear and parts of the ascending auditory pathway. This dataset enables us to explore more complex network topologies, such as recurrent structures. For the MNIST dataset, we trained a SNN with the architecture of 784 input neurons, corresponding to the 28 × 28 pixels of the MNIST images, a hidden layer with 116 neurons, and 10 output neurons. This network follows a purely feedforward architecture and does not include recurrent connections. To deploy these datasets on SupraSNN, the parameters of the LIF neuron model are first configured as summarized in Table 2. For MNIST, rate encoding is used to convert each input pixel into a spike train proportional to its intensity, whereas SHD already provides spike-based input data. In both networks, classification is performed at the output layer by selecting the neuron with the highest accumulated spiking activity. The networks are implemented using snnTorch [2] and trained with the Back-Propagation Through Time (BPTT) algorithm. The surrogate gradient functions and other training hyperparameters are summarized in Table 2. After training, the models achieve classification accuracies of 96.30% on MNIST and 71.02% on SHD. To improve computational efficiency and better match the target hardware architecture, synaptic pruning is applied during training. Starting from an initially fully connected network containing 92,604 synapses for MNIST and 306,000 synapses for SHD, binary sparsity masks are used to remove a portion of connections before training. This process results in final sparsity levels of 51.89% for MNIST and 87.04% for SHD. To deploy the trained networks on SupraSNN, various hardware configurations are explored to achieve a suitable balance between performance and resource efficiency. The final hardware parameters selected for implementation are summarized in Table 2. Due to the larger network size, higher complexity of the SHD dataset, and larger number of timesteps, a wider numerical representation and a greater number of parallel SPUs are allocated compared with the MNIST configuration. The finalized hardware configurations for the MNIST and SHD networks are implemented on Xilinx Zynq XC7Z020 and XC7Z030 FPGAs, respectively, using the Vivado design suite. Resource utilization and power consumption are obtained through the built-in analysis tools provided by Vivado, summarized in Table 2. The XC7Z030 device is selected for the SHD implementation due to its larger available hardware resources, which accommodate the more demanding configuration required by the SHD network. 7.2
Comparison with Other Accelerators
Table 3 summarizes the results reported by state-of-the-art FPGA-based SNN accelerators that use MNIST as their evaluation benchmark. It reports the results of SNN accelerators designed for fully connected network topologies. The 18
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Table 2: Model, Training, Hardware and Implementation Results Parameter
MNIST
SHD
Model
α Vreset Vthreshold Architecture Timestep Encoding Network Type
0.25 0.0 1.0 784-116-10 10 Rate Code SFNN
0.03125 0.0 1.0 700-300-20 100 Custom SRNN
Training
Method Surrogate Function Learning Rate Optimizer Epoch Sparsity Accuracy
BPTT ReLU 5 × 10−4 Adam 20 51.89% 96.30%
BPTT Sigmoid 10−5 Adam 60 87.04% 71.02%
Hardware
SPU Unified Mem Depth Operation Table Weight Width Concentration Factor (K) Potential Width Max Neurons Max Post-Neurons Clock Frequency (MHz)
16 128 661 4 3 5 910 126 100
64 256 742 7 3 12 1020 320 100
Result
FPGA Avail LUT Used LUT Avail FF Used FF Avail BRAM Used BRAM Post-Quantization Sparsity Static Power (W) Dynamic Power (W) Total Power (W) Latency (ms) Accuracy
XC7Z020 53,200 3,092 (5.81%) 106,400 3,052 (2.87%) 140 33.5 (23.92%) 88.74% 0.106 0.066 0.172 0.149 93.44%
XC7Z030 78,600 14,995 (19.08%) 157,200 14,945 (9.51%) 265 131 (49.43%) 88.19% 0.130 0.416 0.546 1.41 71.82%
accuracy achieved by our implementation (93.44%) demonstrates competitive performance and remains comparable with other FPGA-based accelerators evaluated on the same benchmark. In terms of latency, SupraSNN achieves the best performance, classifying a single MNIST image with an average latency of 0.149 ms, which is 47.6% lower than the second-best design reported by Spiker [41]. This performance advantage stems from two key architectural characteristics. First, SupraSNN achieves high utilization of its parallel processing units by exploiting synapse-level parallelism. Second, it effectively leverages weight sparsity by avoiding the storage and execution of synapses with zero weights. The importance of these design choices can be illustrated by comparing SupraSNN with Spiker+ [32]. Spiker+ achieves a high level of hardware parallelism by assigning a dedicated processing unit to each neuron, resulting in 138 processing units, which is approximately nine times larger than the number of SPUs used in SupraSNN. However, this design leads to imbalanced workload distribution across processing units. In particular, processing units associated with the first layer are responsible for 784 synapses, whereas those in the output layer process only 128 synapses per timestep. This imbalance, combined with the execution of zero-valued weights and the use of larger simulation timesteps, results in a significantly higher inference latency—approximately 5.2× greater than that of SupraSNN. SupraSNN requires 33.5 BRAMs (23.93% of the device capacity), making it the second most memory-efficient design after Spiker+. Although synapse-level parallelism introduces additional memory overhead to store synaptic metadata in the Operation Table, the architecture simultaneously benefits from not storing zero-valued synapses, which effectively mitigates this overhead. Consequently, SupraSNN maintains a small memory footprint, particularly when executing sparse networks. 19
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Table 3: Comparison of SupraSNN to FPGA implementations of SNN accelerators Design Year Clk Frequency (MHz) Timestep Potential Width Weight Width Update Model FPGA Avail BRAM Used BRAM Avail DSP Used DSP Avail Logic Cells Used Logic Cells Architecture Synapses Latency/Image (ms) Power (W) Energy/Image (mJ) Energy/Synapse (nJ) Accuracy
Han et al. [38]
Gupta et al. [39]
Li et al. [40]
Spiker [41]
Spiker+ [32]
SupraSNN (This Work)
2020 200 N/R 16 16 Event LIF XC7Z045 545 40.5 900 0 655800 12690 784-1024-1024-10 1861632 6.21 0.477 2.96 1.59 97.06%
2020 100 N/R 24 24 Event LIF XC6VLX240T 416 162 768 64 452160 79468 784-16 12544 0.50 N/R N/R N/R N/R
2021 100 N/R 16 16 Hybrid LIF XC7VX485 2060 N/R 2800 N/R 485760 N/R 784-200-100-10 177800 3.15 1.6 5.04 28 92.93%
2022 100 3500 16 16 Clock LIF XC7Z020 140 45 220 0 159600 55998 784-400 313600 0.22 59.09 13 41 73.96%
2024 100 100 6 4 Clock LIF XC7Z020 140 18 220 0 159600 7612 784-128-10 101632 0.78 0.18 0.14 1.37 93.85%
2026 100 10 5 4 Clock LIF XC7Z020 140 33.5 220 0 159600 6144 784-116-10 92604 0.149 0.172 0.02563 0.27675 93.44%
For logic resources, we report utilization as the sum of LUTs and flip-flops, which are 3,092 LUTs (5.81% of the available) and 3,052 FFs (2.87% of the available) in our implementation. SupraSNN achieves the lowest logic utilization among all pure spiking accelerators listed in Table 3, reflecting its compact hardware footprint. The next most area-efficient design is Spiker+, which requires 7,612 logic cells on the same FPGA device, representing a 23.9% increase compared to SupraSNN. SupraSNN also exhibits the lowest power consumption among the fully connected accelerators considered in Table 3. Although the difference relative to Spiker+ is modest (approximately 0.008 W), the combination of lower power and the shortest latency enables SupraSNN to achieve the best energy efficiency per image by a substantial margin. The second-best design, Spiker+, requires approximately 5.6× more energy per inference. To account for the varying network sizes across different accelerators, we also report a normalized energy-per-synapse metric. SupraSNN consumes only 0.27675 nJ per synapse on average to classify a single MNIST image, demonstrating its high efficiency in utilizing available synaptic operations. 7.3
Weight Sparsity Evaluation in SupraSNN
In this section, we aim to study how effectively SupraSNN exploits weight sparsity regarding performance, memory, power, and energy. To this end, we trained a network using the parameters and methods mentioned in Table 2 on the SHD dataset across various sparsity levels. Figure 11a shows the software accuracy across all 2,264 SHD test samples for various sparsity levels. While the peak accuracy of 81.89% occurs at low sparsity (dense connectivity), networks with substantially fewer non-zero synapses still achieve strong performance. Notably, a network with 82.1% sparsity acquired 72.39% accuracy, representing the elbow point of the curve. Figure 11b compares three quantization configurations in terms of hardware accuracy. The configuration with 8-bit weights and 15-bit membrane potential generally achieves the highest accuracy, though performance differences become less pronounced as sparsity increases. Consequently, the configuration with 6-bit weights and 9-bit membrane potential represents a more practical choice for sparsity evaluation, as it significantly reduces memory requirements for weights, synaptic currents, and membrane potentials while maintaining acceptable accuracy at high sparsity levels. For each of the 18 trained SHD networks, the model is first processed by our Partitioning and Scheduling framework, which partitions synapses across the SPUs, schedules the execution sequence, determines a feasible mapping, identifies the minimum required Operation Table depth, and generates the initialization packets and bitstream. The framework also estimates the average classification latency per sample through cycle-accurate simulation. Hardware resource utilization and power consumption is obtained by synthesizing the generated designs in Vivado targeting the XC7Z030 Zynq FPGA. The results are presented in Figure 12. 20
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Accuracy - Sparsity 0.85 0.8 0.75
Accuracy
0.7 0.65 0.6
0.55 0.5 0.45 0.4 0.35 0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Non-Zero Weight Percentage
a)
Accuracy - Sparsity for Different Quantization 0.75 0.7 0.65
Accuracy
0.6 0.55 0.5 0.45 0.4 0.35 0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
None-Zero Weight Percentage Accuracy (W: 6-bit, M: 9-bit)
Accuracy (W: 7-bit, M: 12-bit)
Accuracy (W: 8-bit, M: 15-bit)
b) Figure 11: (a) Accuracy of the 700–300–20 SNN architecture at different sparsity levels. (b) Accuracy of the quantized SNN for three quantization bit widths across varying sparsity levels.
21
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Performance
Logic Cells 1800
3.5
1600
Operation Table Depth
14500 14000
13500 13000 12500
3
1400
2.5
1200 1000
2
800
1.5
600
1
400
12000
200
0.05
0.1
0.15
0.2
0.25
0.5
0.3
0
0.05
Non-Zero Weight Percentage LUT
0.1
FF
Operation Table Depth
1.8
0.57
400
1.6
0.56
350
1.4
0.55
300
1.2
0.54
Memory (KB)
450
Power (W)
Energy (mJ)
0.58
0.53 0.52
0.6
0.51
100
0.4
0.5
50
0.49
0
0.2
0.2
0.25
0.3
250
200 150
200
1
100
150 50
0 0
Non-Zero Weight Percentage Energy/sample (mJ)
Latency (ms)
250
0.8
0.15
0.3
Memory
Energy
0.1
0.25
b)
2
0.05
0.2
Non-Zero Weight Percentage
a)
0
0.15
Used BRAM
0
Latency (ms)
15000
0.05
0.1
0.15
0.2
0.25
0.3
Non-Zero Weight Percentage
Total Power (W)
Total Memory (KB)
c)
BRAM
d)
Figure 12: (a) Total number of LUTs and FFs utilized by the trained SNN at different sparsity levels (b) Operation Table depth and the average inference latency (in ms) based on the sparsity level (c) Total power on the FPGA and average energy per inference across different sparsity levels (d) Memory footprint in KB and the BRAM utilization for different sparsity levels.
Figure 12a shows that both LUT and FF utilization remain relatively constant across all sparsity levels, indicating that logic resource usage is primarily determined by architectural parameters such as the number of SPUs, rather than by the number of synaptic connections in the mapped network. In contrast, the required Operation Tables depth grows directly with the number of non zero synapses, as shown in Figure 12b, since only non-zero synapses are stored in the SPU memory units. Denser networks therefore require deeper Operation Tables and longer execution sequences. A 24.89% increase in the proportion of non-zero synapses leads to a 2.5352 ms increase in latency, highlighting the effectiveness of the design in exploiting weight sparsity to achieve significant latency reductions in sparse networks. Figure 12c shows that the measured FPGA power does not follow a perfectly monotonic trend, it generally increases as networks become denser. Combined with the latency trend observed in Figure 12-b, the per-sample classification energy consumption increases accordingly, since energy is proportional to the product of power and execution time. Conversely, sparser SNNs benefit from shorter execution latency and slightly lower power, leading to reduced energy per classified sample. To further evaluate how SupraSNN exploits weight sparsity, the overall memory footprint of the architecture must be analyzed as a function of the design parameters. Let the number of SPUs be M , the maximum number of neurons be N , the maximum number of post neurons be Np , the weight bit width be WW , the weight concatenation factor be K, the Operation Table depth be SOT , and the Unified Memory depth be SU M . 22
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Three components of the architecture contain memory structures: (1) the Routing Unit, (2) the SPUs, and (3) the Neuron Unit. The Routing Unit stores a routing bitstring for each neuron, where the bitstring width equals the number of SPUs (M ). Therefore, the total routing memory capacity is N × M bits. Each SPU contains two memory structures: the Operation Table and the Unified Memory. Every operation entry in the Operation Table stores several fields: • a Post Addr field requiring ⌈log2 SU M ⌉ bits, • a Weight Addr field requiring ⌈log2 SU M ⌉ + ⌈log2 K⌉ bits, • a Spike Addr field requiring ⌈log2 N ⌉ bits, and • two control bits indicating the Pre End and Post End conditions. Accordingly, the bit width of each Operation Table entry becomes: 2⌈log2 SU M ⌉ + ⌈log2 K⌉ + ⌈log2 N ⌉ + 2 Given an Operation Table depth of SOT , the total capacity of the Operation Table in each SPU is: SOT × (2⌈log2 SU M ⌉ + ⌈log2 K⌉ + ⌈log2 N ⌉ + 2) The Unified Memory stores concatenated weights. Its width is K × WW bits and its depth is SU M , leading to a total capacity of: K × W × SU M The Neuron Unit also includes a memory structure for storing neuron states. Each neuron state contains: • 1 bit indicating whether the neuron is an output neuron, • ⌈log2 N ⌉ bits for the neuron’s global index, and • KW − ⌈log2 Np ⌉ bits for the membrane potential. Since the neuron state memory has a depth of Np , its total capacity becomes: Np × (⌈log2 N ⌉ + KWW − ⌈log2 Np ⌉ + 1) By combining all memory components, the total memory requirement of the proposed architecture can be expressed as: M emtotal = N M + M SOT 2⌈log2 SU M ⌉ + ⌈log2 K⌉ (11) + ⌈log2 N ⌉ + 2 + KWW SU M + Np ⌈log2 N ⌉ + KWW − ⌈log2 Np ⌉ + 1 Figure 12d reports the total memory footprint and BRAM utilization across all evaluated networks. As networks become denser, the required memory increases from 78.68 KB to 396.96 KB – more than a fivefold increase – while the proportion of non-zero synapses rises by only 24.89%. BRAM utilization increases in three distinct steps as network density grows. This strong dependence of memory footprint on sparsity confirms that SupraSNN effectively reduces memory requirements for sparse networks, providing an opportunity to map larger SNN models onto resourceconstrained FPGA platforms. Overall, the results demonstrate that SupraSNN dynamically scales its latency, power, and memory footprint in direct proportion to network sparsity, while logic resources remain unaffected. This confirms the effectiveness of the operation-based execution model in translating algorithmic sparsity into tangible hardware efficiency gains across all key metrics. 23
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Partitioning and Scheduling Evaluation in SupraSNN
To evaluate the effectiveness of the proposed partitioning and scheduling framework, we utilize an SNN configuration with 9-bit weight width and 18-bit membrane potential width. A larger weight precision is intentionally chosen to better demonstrate the framework’s weight reuse capability: with smaller widths such as 4 bits, the number of distinct weight values is severely limited, making weight storage overhead negligible compared to neuron state storage and obscuring the benefits of weight reuse. After quantization, the resulting network contains 33,457 non-zero synapses, achieves 70.71% classification accuracy on hardware, and includes 289 unique weight values. To evaluate the proposed framework, we execute it under different Unified Memory depth constraints, which represent the primary resource limitation of the mapping problem. In total, 48 configurations are examined, with Unified Memory depths ranging from 46 to 360. For each configuration, the framework determines the minimum required Operation Table depth – which directly relates to execution latency. 7.4.1
Comparison with Baselines
We compare the proposed framework against three baseline partitioning strategies. (1) The post-neuron round-robin approach assigns fan-in synapses of each neuron to SPUs in round-robin order, ensuring each neuron’s partial current is maintained within a single SPU and avoiding neuron state duplication. However, varying fan-in counts across neurons produce imbalanced synaptic workloads, increasing the required Operation Table depth and execution latency. (2) The synapse round-robin strategy assigns individual synapses in round-robin fashion, achieving balanced workload distribution but requiring partial currents of neurons to be stored across all SPUs, causing widespread neuron state duplication that significantly increases Unified Memory requirements. (3) The weight round-robin baseline clusters synapses sharing the same weight value and distributes these clusters across SPUs, maximizing weight reuse but tending to increase neuron duplication and workload imbalance. Figure 13a illustrates the relationship between Unified Memory depth and the minimum required Operation Table depth for all approaches. The proposed framework begins from a fully balanced synaptic distribution and incrementally adjusts the mapping to satisfy the Unified Memory constraint. As the constraint relaxes, the framework maintains a more balanced distribution, reducing the required Operation Table depth and therefore latency. Specifically, at a Unified Memory depth of 46, the framework requires an Operation Table depth of 1096, while increasing the depth to 360 reduces this to 536. The synapse round-robin baseline requires a Unified Memory depth of 359 and an Operation Table depth of 539, nearly identical to the proposed framework under the same constraint, confirming that the framework converges to the best achievable balanced solution under relaxed memory conditions. The weight round-robin strategy requires a Unified Memory depth of 260 with an Operation Table depth of 916, approximately 17.5% larger than the framework under a similar constraint, reflecting its less efficient workload distribution. The post-neuron round-robin approach performs strongly under tight constraints, requiring only a Unified Memory depth of 57 with an Operation Table depth of 857, compared with 990 by the proposed framework — a 15.5% improvement. However, this advantage exists only under tight constraints: once the Unified Memory depth exceeds approximately 144, all solutions produced by the proposed framework outperform post-neuron round-robin in latency, as the latter cannot adapt its workload balance to exploit additional available memory. Furthermore, the framework is capable of generating valid mappings for smaller Unified Memory capacities (e.g., a depth of 46). Figure 13b compares total memory footprints. The proposed framework fluctuates between 222.12 KB and 261.32 KB across all configurations. The weight round-robin strategy produces a memory footprint of 300.91 KB – approximately 15% larger compared with the framework under similar constraint – due to additional neuron duplication. The postneuron round-robin approach achieves a footprint nearly 12% lower than the framework at its optimal constraint point of depth 57, mirroring its latency advantage under the same condition. However, beyond this point, its Operation Table memory capacity remains fixed despite increases in Unified Memory depth, while the proposed framework continues reducing Operation Table size by exploiting additional memory for better balance. Consequently, for Unified Memory depths beyond 57, the post-neuron round-robin memory footprint becomes inferior to that of the framework. 7.4.2
Utilization Evaluation
In the next step, we evaluate how effectively the proposed framework balances the synaptic workload among SPUs. Figure 14a presents the maximum and minimum synapse counts per SPU across configurations. Under relaxed memory constraints, the synaptic workload remains nearly identical across SPUs, producing a minimal gap between maximum and minimum counts. As the constraint tightens, the framework introduces controlled imbalance to satisfy memory requirements, widening the gap between maximum and minimum synapse counts per SPU progressively. Figure 14b confirms this through the standard deviation of synapse counts, which steadily decreases as Unified Memory depth 24
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Latency 1150
1050
Operation Table Depth
950
850
This Work Synapse Round-Robin
750
Post-Neuron Round-Robin Weight Round-Robin
650
550
450 40
90
140
190
240
290
340
Unified Memory Depth
a) Memory Footprint 310 290
Memory (KB)
270 250 This Work
230
Synapse Round-Robin
210
Post-Neuron Round-Robin Weight Round-Robin
190
170 150 40
90
140
190
240
290
340
Unifed Memory Depth
b)
Figure 13: (a) Minimum required Operation Table depth determined by the proposed framework (directly related to inference latency) for different Unified Memory depths, compared with three baseline solutions. (b) Required memory of the framework’s solutions for different Unified Memory depths, compared with three baseline solutions.
increases, approaching zero under fully relaxed constraints and demonstrating convergence toward an almost perfectly balanced allocation. 7.4.3
Post-Neuron Centralization and Weight Reusability
Finally, we analyze how the proposed framework reduces post-neuron duplication while simultaneously exploiting weight reusability to satisfy different Unified Memory constraints. Figure 15a illustrates the average number of postneurons assigned to each SPU across different Unified Memory depths. This value grows steadily and nearly linearly as memory capacity increases, reflecting the framework’s ability to distribute synapses more evenly when Unified Memory depth permit, while limiting post-neuron duplication under tighter constraints to maintain feasible mappings. Figure 15b shows the average number of weights assigned to each SPU for the same set of configurations. For Unified Memory depths larger than approximately 80, the average weight count remains relatively stable around 116.5, indicating that the framework maintains a consistent level of weight reuse under moderate and relaxed constraints. However, when the Unified Memory depth becomes smaller than this threshold, the average weight count decreases noticeably to approximately 114.375, as the framework shifts priority toward weight reusability once post-neuron centralization reaches its limit. This behavior reflects the embedded priority rules within the partitioning phase: since storing a 25
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Synapse Range 1000 900 800
Synapse Count
700
This Work (Max Syanpse) This Work (Min Synapse)
600
Synapse Round-Robin (Max)
500
Synapse Round-Robin (Min)
400
Post-Neuron Round-Robin (Max) Post-Neuron Round-Robin (Min)
300
Weight Round-Robin (Max) 200
Weight Round-Robin (Min)
100 0 40
90
140
190
240
290
340
Unified Memory Depth
a) Synapse Standard Deviation 160 140
Standard Deviation
120 100 This Work
80
Synapse Round-Robin
60
Post-Neuron Round-Robin Weight Round-Robin
40 20 0 40
90
140
190
240
290
340
Unified Memory Depth
b)
Figure 14: (a) Maximum and minimum numbers of synapses mapped to a single SPU for different Unified Memory depths. (b) Standard deviation of the number of synapses mapped to SPUs across different Unified Memory depths.
post-neuron consumes memory equivalent to K weights, post-neuron sharing is prioritized first, with weight reuse becoming the key mechanism under the tightest constraints – enabling the framework to produce valid mappings even below the minimum Unified Memory depth required by the post-neuron round-robin strategy. In conclusion, these results demonstrate that the proposed framework systematically leverages post-neuron centralization and weight reusability to address the performance–memory trade-off, consistently outperforming all baselines under moderate and relaxed constraints while remaining viable under tight memory conditions.
8
Conclusion
This paper presents SupraSNN, a highly parallel and energy-efficient hardware accelerator, together with a software codesign framework for partitioning and scheduling. Inspired by superscalar processors, SupraSNN provides synapse-level parallelism by decoupling synaptic and neuronal computation and exploiting network sparsity to improve both memory efficiency and computational performance through Operation-Style execution in SPUs. The architecture integrates parallel SPUs for synaptic processing, a centralized Neuron Unit for state updates, a lightweight high-throughput MC tree for spike distribution, and a bufferless ME tree for merging partial results. To satisfy memory constraints while maintaining high throughput, the probabilistic partitioning software tool employs post-neuron centralization and weight 26
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Average Post Neuron Count 350
300
Post Neuron Count
250
200
This Work Synapse Round-Robin
150
Post-Neuron Round-Robin
Weight Round-Robin
100
50
0 40
90
140
190
240
290
340
Unified Memory Depth
a) Average Weight Count 118
117.5
Weight Count
117 116.5 This Work
116
Synapse Round-Robin
115.5
Post-Neuron Round-Robin 115 114.5 114 40
90
140
190
240
290
340
Unifed Memory Depth
b)
Figure 15: (a) Average number of post-neurons mapped to each SPU for different Unified Memory depths. (b) Average number of weights mapped to each SPU across different Unified Memory depths. reusability to transform an initially performance-optimal but memory-intensive mapping into a memory-efficient yet well-balanced solution. A complementary heuristic scheduling stage further enhances throughput by exploiting slack periods across post-neuron workloads, effectively overlapping synaptic execution with partial-result merging. This co-design strategy enables competitive performance on digit-classification benchmarks and achieves state-of-the-art results among fully connected SNN accelerators, including a latency of 0.149 ms/image and an energy consumption of 0.02563 mJ/image on MNIST, while also demonstrating reliable performance on SHD. Future work will focus on the primary bottleneck of SupraSNN–memory overhead–and incorporate temporal sparsity-aware mechanisms, a defining characteristic of SNNs, to enhance latency, scalability, and support for large-scale SNN deployments.
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