1
Brain-inspired AI for Edge Intelligence: a systematic review
arXiv:2603.26722v1 [cs.NE] 19 Mar 2026
Yingchao Cheng, Meijia Wang, Zhifeng Hao, Senior Member, IEEE, Rajkumar Buyya, Fellow, IEEE
Abstract—While Spiking Neural Networks (SNNs) promise to circumvent the severe Size, Weight, and Power (SWaP) constraints of edge intelligence, the field currently faces a “Deployment Paradox” where theoretical energy gains are frequently negated by the inefficiencies of mapping asynchronous, event-driven dynamics onto traditional von Neumann substrates. Transcending the reductionism of algorithm-only reviews, this survey adopts a rigorous system-level hardware-software codesign perspective to examine the 2020–2025 trajectory, specifically targeting the “last mile” technologies—from quantization methodologies to hybrid architectures—that translate biological plausibility into silicon reality. We critically dissect the interplay between training complexity (the dichotomy of direct learning vs. conversion), the “memory wall” bottlenecking stateful neuronal updates, and the critical software gap in neuromorphic compilation toolchains. Finally, we envision a roadmap to reconcile the fundamental “Sync-Async Mismatch,” proposing the development of a standardized Neuromorphic OS as the foundational layer for realizing a ubiquitous, energy-autonomous Green Cognitive Substrate. Index Terms—Spiking Neural Networks (SNNs), HardwareSoftware Co-design, Deployment Paradox, Edge Intelligence, Neuromorphic OS, Event-Driven Processing, Green Cognitive Substrate, Toolchains.
I. I NTRODUCTION
T
HE exponential proliferation of Internet of Things (IoT) devices has catalyzed a seismic paradigm shift, migrating Artificial Intelligence (AI) from hyperscale cloud infrastructures to the resource-constrained network edge [1]–[3]. This migration is driven not merely by preference but by necessity; we are currently witnessing a global “data deluge,” where the sheer velocity and volume of sensory data generation are outpacing available transmission bandwidth. With global data creation projected to reach zettabyte scales, the traditional cloud-centric model faces critical bottlenecks: bandwidth saturation and unpredictable transmission latency. Relying on centralized servers to process raw, high-fidelity streams (e.g., 4K video surveillance or autonomous driving LiDAR) This work was supported in part by the National Key R&D Program of China (2025YFC3410000) and the Guangdong Basic and Applied Basic Research Foundation (2023B1515120020). (Corresponding author: Yingchao Cheng.) Y. Cheng is with the Guangdong Laboratory of Artificial Intelligence and Digital Economy (SZ), Shenzhen, 518107, China. (e-mail: [email protected]). M. Wang is with the Cloud Computing and Distributed Systems (CLOUDS) Lab, School of Computing and Information Systems, University of Melbourne, Melbourne, VIC 3010, Australia, and also with the Guangdong Laboratory of Artificial Intelligence and Digital Economy (SZ), Shenzhen, 518107, China. (e-mail: [email protected]). Z. Hao is with the College of Mathematics and Computer Science, Shantou University, Shantou, 515063, China. (e-mail: [email protected]) R. Buyya is with the Cloud Computing and Distributed Systems (CLOUDS) Lab, School of Computing and Information Systems, University of Melbourne, Melbourne, VIC 3010, Australia (e-mail: [email protected]).
is no longer sustainable, necessitating a push towards “Edge Intelligence” where data is processed in situ [4]–[7]. However, this transition faces a fundamental physical impasse: the deployment of traditional Deep Neural Networks (DNNs) on battery-operated edge devices is increasingly constrained by the von Neumann bottleneck. The inherent requirement of DNNs for continuous, dense matrix multiplications necessitates massive and frequent data shuttling between physically separated memory and processing units. This creates a “memory wall” that induces latency and power consumption metrics often prohibitive for real-time, missioncritical applications [8]–[10]. In response to these hardware limitations, Spiking Neural Networks (SNNs) have transcended their origins as biological curiosities to become a pragmatic computational imperative for the next generation of Edge Intelligence. Diverging from the frame-based, synchronous processing of conventional DNNs, SNNs operate on an asynchronous, event-driven paradigm that mirrors the efficiency of biological neural substrates. By encoding information into discrete binary spikes, SNNs leverage extreme spatio-temporal sparsity to decouple computation from the clock cycle—effectively achieving a state of “computational parsimony”. This mechanism fundamentally transforms the dominant workload from power-hungry Multiply-Accumulate (MAC) operations to significantly more energy-efficient Accumulate (AC) operations [11]–[14], as illustrated in Fig. 1. Consequently, SNNs represent not just an algorithmic optimization, but a structural alignment between AI models and the sparse, event-driven nature of real-world sensory data. Nevertheless, bridging the chasm between theoretical algorithmic efficiency and physical hardware deployment remains a critical challenge. The field is currently encumbered by a “Deployment Paradox”: while SNN algorithms demand event-driven substrates, the dominant commercial off-the-shelf (COTS) edge hardware—such as NVIDIA Jetson series or Edge TPUs—remains architecturally optimized for dense, synchronous matrix operations. This inefficiency stems from a fundamental mismatch in Single Instruction, Multiple Data (SIMD) parallelism. GPUs achieve peak throughput via lockstep execution of dense threads and coalesced memory access; however, the stochastic, irregular firing patterns of SNNs introduce severe control-flow divergence (breaking SIMD lockstep) and non-contiguous memory requests. This Memory Access Granularity mismatch implies that fetching a single weight for a sparse spike often triggers the transfer of an entire cache line, resulting in low effective bandwidth utilization. Consequently, mapping sparse SNNs onto these general-purpose accelerators forces the use of inefficient simulation layers that frequently negate the inherent energy benefits of spiking models [15]–[17].
2
Traditional DNN (Frame-based)
Spiking Neural Network (Event-driven)
From Dense to Sparse: Breaking the Von Neumann Bottleneck Frame-based Input Static Data
Event Stream Asynchronous Spikes t y
Neuron
� = �(
! Weights(W)
Memory Bank (DRAM)
Activations(X)
The MAC Bottleneck ALU
Leaky Integrate-and-Fire (LIF)
Continuous Activation 0.75 Synchronous
�� �� )
Integrate-and-Fire
Neuron
Case Input=0
MAC
(MultiplyAccumulate)
Input Spike (0 or 1)
Event-Driven Binary Output
�� ��� =− �� (� − �� ) + ���� ��
THE CRITICAL LAYER Bypass:
No Read
The AC Advantage ALU
Case Input=1 Weight(�� )
High Memory Access Constant Data Movement
High
x
Potential += �� (when spike=1)
Event-Triggered Read Sparse Memory Access
Energy Footprint Continuous Values vs. Binary Spikes Synchronous vs. Asynchronous
AC (Accumulate Only)
Memory Bank (DRAM)
No Multiplier Required
Ultra-Low
MAC(Multiply-Accumulate) vs. AC(Accumulate Only) Constant Memory Access vs. Sparse Memory Access
Fig. 1. Overview of the paradigm shift from Traditional DNNs to Spiking Neural Networks (SNNs). (Top) Data Representation: DNNs process redundant frame-based image sequences, whereas SNNs process sparse, asynchronous event streams represented in a spatiotemporal volume (x, y, t). (Middle) Neuron Dynamics: Unlike static activation functions (e.g., Sigmoid) in DNNs, SNNs employ biologically plausible Leaky Integrate-and-Fire (LIF) neurons that integrate temporal information governed by differential equations. (Bottom) Energy Efficiency: The shift from dense MAC operations to event-driven Accumulate (AC) logic results in an ultra-low energy footprint, making SNNs highly suitable for edge intelligence.
Conversely, native neuromorphic processors capable of unlocking the full potential of SNNs, such as Intel Loihi 2 or BrainChip Akida, operate on the requisite asynchronous paradigms but are largely restricted to research prototypes or niche vertical markets. This dichotomy creates a significant deployment gap, where advanced algorithms lack suitable, ubiquitous hardware hosts [18]–[21]. Ultimately, the widespread adoption of edge SNNs is currently stalled not by algorithmic incapacity, but by the inertia of a hardware ecosystem optimized for the previous generation of dense deep learning models. While prior surveys have attempted to chart this territory, the existing literature has predominantly bifurcated the landscape, treating SNN algorithms and hardware implementations as distinct, isolated domains. One category of reviews focuses heavily on algorithmic innovations—such as surrogate gradient learning or plasticity rules—while abstracting away the physical constraints of deployment platforms [22], [23]. Conversely, hardware-centric surveys often delve into emerging devices (e.g., memristors) or circuit designs without adequately addressing the scalability of the algorithms required to run on them [24]–[26]. This separation obscures the practical intricacies of the deployment gap, leaving a void in understanding how algorithmic sparsity interacts with hardware primitives. To bridge this divide, the present article adopts a holistic hardware-software co-design perspective. This approach posits that the efficacy of Edge Intelligence is not determined solely by synaptic precision, but by the seamless orchestration of algorithmic sparsity and hardware architecture.
Accordingly, this work articulates three primary contributions: • Critical Synthesis of Training Paradigms (2020–2025): We provide a comparative analysis of recent breakthroughs in direct training mechanisms (e.g., Surrogate Gradients) versus ANN-to-SNN conversion techniques. The discussion evaluates these methodologies not in isolation, but through the lens of edge suitability—balancing training latency against inference energy efficiency [27]– [31]. • Deployment-Centric System Analysis: Distinguished from generic algorithmic overviews, this survey addresses the “last mile” challenges of physical realization. We scrutinize the often-overlooked bottlenecks of posttraining quantization, heterogeneous mapping toolchains, and inter-chip communication overheads that govern realworld performance [32]–[35]. • Prospective Roadmap for Connected Intelligence: Extending beyond standard computer vision benchmarks, the scope is broadened to emerging frontiers. We delineate the role of SNNs in distributed edge learning frameworks and their potential integration with next-generation 6G networks, identifying the trajectory towards ubiquitous, ultra-low-power cognitive radio systems [36]–[38]. The structural organization of this survey is distinctively predicated on the principle of Hardware-Software Co-design. Departing from the dichotomy observed in extant literature—where algorithmic sparsity and neuromorphic substrates are often dissected in isolation—this work posits that bridging the “last mile” of edge deployment necessitates a unified
3
Sec. II: History From Bio-models to Eng.
PART I:
Sec. III: Core Concepts
FOUNDATIONS
Encoding & Learning
Sec. IV: The Synergy SWaP & Deployment Gap Training Paradigms
PART II: FRONTIERS
Sec. V: Advancements The Full Stack
Neuromorphic HW
Toolchains & Systems
Brain-inspired AI for Edge Intelligence
Computer Vision
Robotics & UAVs PART III: REALIZATION
Sec. VI: Applications Healthcare Sec. VII: Challenges Systemic Friction Industrial IoT
PART IV:
Sec. VIII: Roadmap
SYNTHESIS
Neuromorphic OS
Sec. IX: Conclusion The Final Verdict
Fig. 2. Hierarchical Organization of the Survey. The article is structured into four main pillars: Part I establishes the theoretical foundations and defines the “Deployment Paradox”; Part II explores the technical frontiers across algorithms, hardware, and toolchains (2020–2025); Part III examines real-world realization in key edge applications; and Part IV synthesizes challenges to propose a roadmap towards a unified Neuromorphic OS.
taxonomy. Under this framework, algorithmic parameters (e.g., sparsity levels, neuron models) are treated as inextricably linked to hardware constraints (e.g., fan-in limits, memory hierarchy), thereby establishing a cohesive roadmap for ubiquitous edge intelligence [39]–[41]. To systematically unravel these interdependencies, the remainder of this article is structured as follows (visually summarized in Fig. 2): • Foundations and Motivation (Sections II–IV): The narrative begins by tracing the evolutionary trajectory of SNNs from biophysical roots to modern computational primitives (Section II). This is followed by a rigorous definition of core concepts, including encoding schemes and a comparative analysis against DNNs (Section III). Subsequently, Section IV elucidates the intrinsic alignment between SNN dynamics and the energy-latency
constraints of edge environments. Technological Frontier (Section V): Representing the core technical synthesis (2020–2025), this section comprehensively evaluates the state-of-the-art across the full stack: from novel training paradigms and hardwareaware optimizations to the mapping toolchains required to bridge the software-hardware gap. • Realization and Reflection (Sections VI–IX): The theoretical discussion transitions into practice in Section VI, exploring deployment in computer vision, robotics, and IoT. Section VII then adopts a critical lens to examine persistent bottlenecks in scalability and training. Finally, Section VIII projects the field’s trajectory towards 6G integration and ethical AI, before concluding the survey in Section IX. •
4
Ultimately, this structure is designed to guide the reader from microscopic neuron dynamics to macroscopic systemlevel deployment, highlighting that the future of edge AI lies in the optimization of the interface between these two scales. II. BACKGROUND AND F OUNDATIONS : T HE SNN PARADIGM The theoretical trajectory of Spiking Neural Networks (SNNs) is defined by a central dichotomy: the pursuit of biological isomorphism versus the necessity of engineering tractability. Unlike the continuous activation landscapes of second-generation Artificial Neural Networks (ANNs), SNNs operate on the premise of discrete, event-driven information processing. This section delineates the evolution of this paradigm, tracing the shift from rigorous biophysical modeling to the modern era of algorithmic differentiation and hardware co-design. A. Modeling Dynamics: From Ion Channels to Abstraction The classification of SNNs as the third generation of neural networks is predicated on their ability to encode information in the precise timing of spikes, theoretically offering superior computational power over rate-based counterparts [42]–[44]. However, realizing this potential required a fundamental compromise in modeling granularity. The roots of neuronal modeling are established in the rigorous description of action potential generation via ion channel conductance, typified by the Hodgkin-Huxley formalism [45]– [47]. While biophysically accurate, such high-dimensional differential equations proved prohibitively expensive for networklevel simulations. This computational bottleneck necessitated a strategic pivot toward phenomenological abstraction. The Leaky Integrate-and-Fire (LIF) model emerged as the standard for efficient simulation, reducing dynamics to a linear membrane integration process reset by a hard threshold [48]– [51]. To bridge the gap between the simplistic LIF and the complex Hodgkin-Huxley models, hybrid approaches were developed. Notably, models that capture diverse firing patterns (e.g., bursting, chattering) through bifurcations in reduceddimensional phase systems offered a critical trade-off, enabling rich dynamics with the computational cost of simple maps [52]–[55]. Parallel to these algorithmic abstractions, the hardware substrate underwent a similar philosophical shift. The concept of “neuromorphic” engineering was originally conceived to exploit the physics of subthreshold analog VLSI to directly emulate neurobiological ion flow [56]–[58]. Over time, this evolved into digital and mixed-signal implementations, prioritizing the energy efficiency of sparse, event-driven communication over strict analog emulation. The evolution of neuron models illustrates a clear trend toward functional minimalism. The field has largely converged on the realization that for neuromorphic computing, capturing the “essential nonlinearity” of the spike mechanism is more critical than replicating the precise ionic currents of the biological soma.
B. The Renaissance: Overcoming the Differentiability Barrier Despite a strong theoretical bedrock, the practical deployment of SNNs was historically impeded by the nondifferentiable nature of the spike generation function, which rendered standard backpropagation ineffective. The initial era of SNN learning was dominated by biologically grounded, local learning rules, most notably SpikeTiming-Dependent Plasticity (STDP) and Hebbian variations [59]–[61]. While these unsupervised mechanisms excelled at local feature extraction and pattern recognition in shallow architectures, they struggled to scale to the supervised complexity required for deep, hierarchical representations comparable to modern Convolutional Neural Networks (CNNs) [62]–[65]. The contemporary renaissance of SNNs—and their subsequent proliferation in edge computing—was catalyzed by the formalization of Surrogate Gradient (SG) methods. By approximating the non-differentiable Dirac delta function with a smooth auxiliary function during the backward pass, SG paradigms enabled the direct application of gradient descent to temporal dynamics, effectively linking the energy efficiency of SNNs with the training efficacy of Deep Learning [66]–[70]. This algorithmic breakthrough coincided with the maturation of industrial-scale neuromorphic hardware [71]–[74]. The validation that event-driven architectures could achieve ordersof-magnitude power reduction over von Neumann systems provided the physical imperative for deploying these deep spiking architectures in resource-constrained environments. The resurgence of SNNs is not merely a return to biological inspiration, but a pragmatic response to the “memory wall” and power constraints of modern computing. The shift from pure STDP to Gradient-based learning represents a compromise: accepting non-biological training methods to achieve biological levels of energy efficiency in inference. III. C ORE C ONCEPTS OF SNN S : A N E NGINEERING P ERSPECTIVE SNNs represent a paradigm shift from continuous-valued activation to discrete, event-driven computation. Unlike conventional ANNs that rely on frame-based, synchronous processing, SNNs leverage the temporal dynamics of spike trains to encode information. This fundamental difference enables asynchronous processing and significant energy reductions, particularly in edge scenarios where power budgets are strictly constrained. A. Spiking Neuron Models: Fidelity vs. Cost The selection of a neuron model in neuromorphic engineering is a strategic trade-off between bio-fidelity and computational efficiency. Models range from biophysically accurate descriptions of ionic channels to simplified abstractions optimized for large-scale hardware implementation [24], [39], [44], [75]. 1) Leaky Integrate-and-Fire (LIF): The Simulation Standard: The LIF model is the widely adopted abstraction for large-scale SNN simulations due to its linear subthreshold dynamics. It captures the essential “integration” and “firing”
5
mechanism without modeling complex channel kinetics. Mathematically, it is described as: dV (t) = −(V (t) − Vrest ) + Rm Isyn (t), (1) dt where τm = Rm Cm is the membrane time constant. While simplistic, the LIF model provides a convex optimization landscape for surrogate gradient learning, making it the de facto standard for Deep SNNs [76]. 2) Izhikevich Model: The Computational Bridge: The Izhikevich model serves as a computational bridge, capturing diverse firing patterns (e.g., bursting, chattering) typically associated with complex biophysical models, yet retaining the efficiency of coupled first-order differential equations: τm
dv = 0.04v 2 + 5v + 140 − u + I, dt (2) du = a(bv − u). dt where v is the membrane potential, u is the recovery variable, and I is the input current. By tuning parameters a, b, c, d, this model reproduces cortical dynamics with floating-point operations (FLOPs) comparable to simple integrators [77]. 3) Hodgkin–Huxley (HH): The Biophysical Gold Standard: The HH model explicitly describes ionic conductance (Na+ , K+ ). While it remains the gold standard for understanding neurophysiology, its high computational cost (requiring the solution of four non-linear differential equations) renders it impractical for edge intelligence applications, serving primarily as a validation benchmark [65], [78]. The engineering objective in SNN design is not maximizing biological realism, but maximizing the ratio of information processing capability to energy consumption. Consequently, simple models like LIF dominate hardware implementations because they minimize the silicon area required per neuron, allowing for massive parallelism. B. Encoding Taxonomies: Rate vs. Temporal Information encoding in SNNs dictates the system’s latency and bandwidth efficiency. These schemes generally fall into two categories: rate-based and temporal coding [79]–[82]. 1) Rate-Based Encoding: Derived from classical neurophysiology, rate coding represents information via the mean firing frequency over a time window. While it offers high robustness against noise and stochasticity, it inherently incurs high latency (requiring time to average) and reduced energy efficiency due to redundant spiking. 2) Temporal Encoding: Temporal schemes exploit the precise timing of spikes to carry information, offering superior sparsity and bandwidth efficiency. Time-to-First-Spike (TTFS) encodes information inversely to the latency of the first spike, allowing for ultra-fast decision-making often termed “latency coding” [39], [83]. Other methods include Phase Coding, where spikes are timed relative to a periodic background oscillation, and Delta Modulation, which is widely used in asynchronous sensors (e.g., DVS cameras) to encode only intensity changes, naturally filtering out static redundancy [84], [85].
The transition from Rate to Temporal coding represents the critical leap from “emulating biology” to “exploiting sparsity.” Temporal codes maximize the information content per bit (spike), which is the theoretical foundation for SNNs’ ultra-low power consumption. C. Learning Dynamics: Local to Global Learning in SNNs is bifurcated into biologically plausible local rules and performance-oriented global optimization. 1) Local Unsupervised Learning (STDP): Spike-TimingDependent Plasticity (STDP) modifies synaptic weights based on the causal latency ∆t = tpost − tpre . It enables selforganizing feature extraction without labeled data: ( A+ e−∆t/τ+ if ∆t > 0 (LTP) ∆w = (3) −A− e∆t/τ− if ∆t < 0 (LTD) Variants such as R-STDP (Reward-modulated) and mSTDP (Mirrored) have been developed to introduce supervision signals into this local process [26], [86], [87]. 2) Global Supervised Learning (Surrogate Gradients): To overcome the non-differentiability of binary spikes, modern SNNs utilize Surrogate Gradient (SG) methods. This approach smooths the Heaviside step function during backward propagation, allowing SNNs to be trained with the same efficacy as DNNs using backpropagation through time (BPTT) [24], [62], [88]. A convergence is emerging where “local” plasticity (STDP) is used for efficient pre-training or hardware adaptation, while “global” gradients (SG) fine-tune the network for task-specific accuracy. This hybrid approach balances the autonomy of biological systems with the precision of engineering control. D. Architectural Comparison: SNNs vs. DNNs Table I and Fig. 3 synthesize the architectural distinctions. The decisive advantage of SNNs lies in replacing Multiplyand-Accumulate (MAC) operations with Accumulate (AC) operations. Since spikes are binary (S(t) ∈ {0, 1}), the synaptic weighting becomes a conditional addition: Vj (t) = P Vj (t − 1) + i wij · Si (t). This bypasses the need for highprecision multipliers, reducing silicon footprint and dynamic power consumption [89], [90]. IV. T HE E DGE -SNN S YNERGY: A RCHITECTURAL A LIGNMENT The deployment of Artificial Intelligence at the edge is not merely a software optimization challenge; it is a physical struggle against the strict limitations of Size, Weight, and Power (SWaP). While traditional approaches attempt to compress continuous-valued Deep Neural Networks (DNNs) to fit these boundaries, Spiking Neural Networks (SNNs) offer a fundamental divergence in design philosophy. Rather than being a scaled-down approximation of data-center models, SNNs exhibit an intrinsic architectural alignment with the sporadic, event-driven nature of the physical world. This section deconstructs this synergy across three critical dimensions: the physics of SWaP, the demands of always-on sensing, and the elimination of synchronous overhead in the processing pipeline.
6
TABLE I C OMPARISON OF SNN S AND DNN S Feature
SNNs
DNNs
Neuron Model
Biologically inspired (e.g., LIF, Izhikevich); discrete spikes
Abstracted; continuous activation values (e.g., ReLU, sigmoid)
Information Encoding
Temporal patterns of spikes (rate, latency, phase, population)
Magnitude of activations
Computation
Event-driven, asynchronous, sparse; primarily Accumulate (AC) ops
Synchronous, dense; primarily Multiply-Accumulate (MAC) ops
Energy Efficiency
Potentially very high, especially on neuromorphic hardware
Generally lower, can be power-intensive
Temporal Processing
Intrinsic capability to process temporal data
Often requires recurrent architectures (RNNs, LSTMs)
Biological Plausibility
Higher; mimics neural dynamics and learning rules like STDP
Lower; learning (e.g., backpropagation) often not bio-plausible
Training Complexity
Challenging due to non-differentiable spikes; STDP, surrogate grads
Well-established (backpropagation), but can be data-hungry
Hardware Suitability
Neuromorphic processors, FPGAs
GPUs, TPUs, CPUs
Data Sparsity Handling
Naturally exploits input and activation sparsity
Less efficient with sparse data unless specifically designed
Noise Robustness
Potentially higher due to temporal dynamics and population coding
Can be sensitive to noisy inputs
Latency
Potentially very low due to fast spike propagation and sparse events
Can be higher, especially for deep architectures
Primary Use Cases (Edge)
Real-time sensor processing, low-power wearables, event-based vision
General AI tasks, often with higher resource availability
Traditional DNN
Spiking NN
Frame Input
Event Input
Continuous Values
Binary Spikes Vth
f (·)
LIF
If S = 1
Act
×
Fetch W
Shared Weights W
+
+
← No Mult!
DRAM
MAC (High Power)
AC Only (Low Power)
Fig. 3. Dataflow Contrast: Continuous vs. Event-Driven. (Left) DNN Dataflow: Relies on dense Matrix-Vector Multiplication (MAC), creating a continuous “Memory Wall” as weights are fetched unconditionally. (Right) SNN Dataflow: Utilizes a conditional trigger mechanism where memory access and computation occur only upon spike arrival. This sparsity-aware processing significantly reduces off-chip memory bandwidth requirements.
A. The SWaP Imperative: Beyond Just Energy The constraints of edge computing are multidimensional. The suitability of SNNs must be evaluated not only through
the lens of energy consumption but through the interconnected triad of Size (Silicon Area), Weight (Battery Constraints), and Power (Thermal Design). As illustrated in Fig. 4, this multidimensional comparison reveals that SNNs offer a favorable architectural alignment for constrained environments, balancing a marginal drop in accuracy with significant gains in efficiency metrics. 1) Power and Thermal Constraints: In conventional CMOS scaling, the industry faces the “Dark Silicon” phenomenon, where power density limits prevent all transistors on a chip from operating simultaneously without inducing thermal throttling [91]–[94]. Standard DNN accelerators, which rely on dense matrix multiplications, risk violating these Thermal Design Power (TDP) envelopes. SNNs mitigate this through activation sparsity. By processing information only when salient events occur, SNNs effectively “light up” dark silicon only on demand, maintaining high functional density without breaching thermal limits [65], [77]. 2) Weight and Mobility: For mobile edge agents, such as micro-UAVs or wearable health monitors, the primary constraint is often weight—specifically, the battery mass required for sustained operation. There is a direct correlation between algorithmic efficiency and flight time or operational lifespan. By reducing the inference energy cost by orders of magnitude (often exceeding 100× reduction in neuromorphic implementations [95], [96]), SNNs allow for significantly smaller battery payloads. This reduction in energy storage requirements directly translates to enhanced mobility and longer mission durations for weight-critical autonomous systems. 3) Size and Silicon Real Estate: SNNs facilitate compact physical implementations. The binary nature of spikes elim-
7
Neuromorphic SNN
C. The Sensor-Algorithm-Hardware Pipeline: End-to-End Asynchrony
Traditional DNN
Energy Efficiency (Power)
10
8
Low Latency (Speed)
Always-on Suitability 6
4
2
Silicon Compactness
Static Accuracy
(Size)
Sparsity (Bandwidth)
Fig. 4. Radar chart illustrating the multidimensional trade-offs between Neuromorphic SNNs and a traditional Edge DNN baseline. While the DNN maintains a marginal advantage in static accuracy, the SNN demonstrates superior performance in SWaP-constrained metrics—specifically Energy Efficiency, Sparsity, and Always-on Suitability. This architectural alignment identifies SNNs as the optimal candidate for resource-limited edge deployment despite the accuracy trade-off.
inates the need for complex floating-point units (FPUs) and large multipliers. Instead, synaptic operations can be reduced to simple accumulations (AC), drastically shrinking the logic gate count and silicon area required per neuron compared to traditional Multiply-Accumulate (MAC) units used in DNNs.
The efficiency of SNNs is fully realized only when the algorithm is part of a holistic, asynchronous pipeline that spans from the sensor to the silicon substrate. 1) Seamless Sensory Integration: SNNs interface naturally with event-based sensors, such as Dynamic Vision Sensors (DVS) [97], [98]. Unlike frame-based cameras that flood the processor with redundant pixel data at fixed intervals (e.g., 60 Hz), DVS pixels operate asynchronously, outputting data only upon detecting intensity changes. This creates a “spike-in, spike-out” data path, avoiding the computationally expensive transcoding of sparse events into dense frames required by traditional ANNs. 2) Eliminating the Clock Overhead: Perhaps the most profound advantage is the potential for End-to-End Asynchrony. In traditional digital design, the global clock distribution network can consume up to 30–40% of a chip’s dynamic power [99], [100]. SNNs, particularly when implemented on neuromorphic substrates like Intel Loihi 2 or asynchronous FPGA architectures [76], [101], do not require global synchronization. They operate on local handshakes. This eliminates the “von Neumann bottleneck” of waiting for memory fetches in lockstep with a clock cycle, allowing the hardware to mirror the continuous, asynchronous dynamics of the physical world. The transition from DNNs to SNNs at the edge represents more than a gain in efficiency; it marks a paradigm shift from “High-Precision Computing”—where the goal is exact numerical reconstruction of the input—to “Actionable Intelligence.” By discarding redundant temporal data and prioritizing salient events, SNNs align the computational cost directly with the complexity of the action required, making them the critical enabler for pervasive, autonomous edge intelligence.
B. The “Always-On” Sensing Paradigm A quintessential edge workload is the “always-on” monitor—systems that must continuously analyze the environment for specific triggers (e.g., keyword spotting, seismic anomaly detection, or security surveillance) while remaining in a deep sleep state. 1) The Zero-Input, Zero-Energy Advantage: DNNs suffer from high static power consumption in these scenarios. Even when processing silence or a static image, a traditional Convolutional Neural Network (CNN) executes a fixed number of operations per frame to confirm the absence of a target. Conversely, SNNs offer a “Zero-input, Zero-energy” characteristic. In the absence of sensory change, no spikes are generated, and the dynamic power consumption drops to near zero. 2) Temporal Sparsity: This makes SNNs uniquely suited for wake-up controllers. The network remains quiescent, consuming negligible power, until the membrane potential of input neurons accumulates sufficient charge from a valid signal to cross the firing threshold [48]. This event-driven wake-up mechanism stands in stark contrast to the pollingbased architecture of conventional AI, ensuring that energy is expended only when information is actually present.
V. R ECENT A DVANCEMENTS IN A LGORITHMS AND O PTIMIZATION The landscape of SNNs for edge computing has evolved rapidly from theoretical exploration to system-level deployment. Moving beyond simple conversion methods, the field has witnessed a paradigm shift towards hardware-aware direct training, heterogeneous architecture design, and multidimensional co-optimization. To systematically navigate these diverse developments, we structure our review around the taxonomy presented in Fig. 5, categorizing the field into four pillars: training paradigms, optimization strategies, neuromorphic hardware, and system integration. A. Training Paradigms: From Gradient Approximation to Fast Conversion The training landscape of SNNs has evolved from biological mimicry to high-performance computing. We categorize recent advancements into two distinct eras: the Gradient-based Era, which solves the non-differentiability of spikes for direct learning, and the Low-Latency Conversion Era, which redefines the speed-accuracy trade-off.
8
• High-Speed Vision (DVS, Vidar )
System & Apps
• Distributed SNNs (Federated Learning) • Orchestration (Scheduling, Offloading)
• Quantization (Weight & Temporal )
Co-design & Opt.
• NAS (Spiking Neural Architecture Search) • Mapping Toolchains (Graph Partitioning)
Brain-inspired Edge Intelligence (SNNs)
• Native Digital (Loihi, Akida, SpiNNaker)
Neuromorphic HW
• Hybrid Architecture (Tianjic, Fusion) • FPGA Accelerators (Streaming, NoC) • Emerging Devices (Memristors/CIM) • Direct Training (SG, STBP, tdBN )
Training Paradigms
• Indirect Training (ANN-to-SNN) • Local Learning (STDP, R-STDP)
Fig. 5. Taxonomy of Brain-inspired Edge Intelligence. The survey is structured around four pillars: (1) Training Paradigms: Highlighting the shift from conversion to direct training algorithms like STBP and tdBN; (2) Neuromorphic Hardware: Covering native digital chips, FPGA accelerators, and hybrid architectures like Tianjic; (3) Co-design Strategies: Focusing on NAS and temporal quantization; (4) System & Applications: Emphasizing high-speed vision (Vidar) and edge-cloud orchestration.
1) Gradient-based Era: Surmounting Non-Differentiability: The fundamental obstacle in training deep SNNs is the nondifferentiable nature of the Heaviside step function used for spike generation, which blocks gradient flow during backpropagation. To address this, the Surrogate Gradient (SG) methodology was proposed to approximate the derivative of the spike function with a continuous pseudo-derivative (e.g., sigmoid or triangular shapes) during the backward pass [23], [62], [67], [69]. Pioneering this direction, the SpatioTemporal Backpropagation (STBP) algorithm [66], [102] was introduced to explicitly aggregate gradients along both spatial and temporal dimensions. Unlike traditional BPTT, which often neglects spatial layer-wise dependencies, STBP enables the training of high-performance SNNs directly on complex datasets and has become the standard for modern SNN optimization. However, scaling SG-based training to deep architectures (e.g., ResNet-50) introduced a secondary challenge: gradient vanishing or exploding due to the binary nature of spike propagation. To tackle this, Threshold-dependent Batch Normalization (tdBN) [103] was proposed. By normalizing the membrane potential along the temporal dimension with a threshold-aware scaling factor, tdBN ensures that neurons maintain a healthy firing rate, effectively regulating gradient magnitude. Further refining the learning dynamics, recent works have moved beyond fixed surrogate shapes. The Dspike framework [67] allows the steepness of the surrogate gradient to be learned adaptively, dynamically balancing the trade-off
between accurate gradient estimation and training stability. Addressing the high memory cost of unrolling SNNs over time in SG methods, research is pivoting towards Event-Driven Learning. To bridge the gap between highperformance backpropagation and always-on edge constraints, Spike-Timing-Dependent Event-Driven (STD-ED) algorithms [90] have been developed. These methods trigger weight updates only upon spike events rather than at every global timestep, reducing energy consumption by approximately 30×. 2) Low-Latency Conversion Era: Breaking the Time Barrier: While direct training offers temporal efficiency, it often lags behind ANNs in absolute accuracy on large-scale tasks. ANN-to-SNN conversion traditionally bridged this accuracy gap but suffered from a severe limitation: extreme inference latency (hundreds of timesteps) required to approximate continuous activation values via rate coding. To mitigate this latency bottleneck, recent efforts have shifted focus from simple firing rate approximation to temporal information compression [104]–[106]. Techniques such as calibrating forward temporal bias and introducing burst spikes have been employed to shorten the inference window. Taking a more radical approach to eliminate the iterative nature of conversion, a parallel conversion learning framework [107] was recently introduced. By establishing a mapping between parallel neuron timesteps and cumulative spike rates, this method achieves 72.90% top-1 accuracy on ImageNet-1k (ResNet-34) in merely 4 timesteps, marking a milestone where conversion-based methods finally rival the low-latency advantages of direct training.
9
A convergence of paradigms is emerging. The strict dichotomy between “Direct Training” and “Conversion” is dissolving into Hybrid Training strategies. Recent frameworks [108], [109] demonstrate that SNNs are no longer solitary models but are increasingly deployed as “Neural Front-ends” for feature extraction, coupled with ANN back-ends for semantic classification, or optimized via ANN-guided knowledge distillation. Future training algorithms will likely prioritize this heterogeneous synergy over pure standalone performance.
accuracy. To resolve this, the QUEST framework [116] introduced a co-design approach involving adaptive precision and quantization-aware training. By unifying low-bit weights (2-bit) with reduced timesteps, QUEST achieves a ∼93x energy improvement over equivalent ANNs. Similarly, for autonomous agents where response time is critical, SNN4Agents [117] demonstrates that jointly quantizing weights (to 10-bit) and reducing attention windows can yield a 4× efficiency gain, validating that multi-dimensional quantization is essential for real-time edge intelligence.
B. Optimization: Hardware-Aware Model Compression
The trajectory of SNN optimization is shifting from singlevariable compression (weight pruning only) to MultiDimensional Co-Optimization. Future frameworks will likely treat weight sparsity, bit precision, and temporal resolution (timesteps) as coupled variables, optimizing them jointly to align with the specific constraints of non-Von Neumann neuromorphic hardware.
Deploying SNNs on resource-constrained edge devices requires navigating a complex trade-off between model accuracy, memory footprint, and energy consumption. Recent research has unified these objectives under hardware-aware compression, targeting three critical dimensions: connectivity (Pruning), topology (NAS), and precision (Quantization). 1) Pruning: Minimizing Redundant Connectivity: Standard SNNs often inherit dense connectivity patterns that are computationally redundant for sparse spiking data. To address this, Adaptive Pruning strategies have been developed to dynamically adjust pruning rates based on neural activity. For instance, dynamic rollback mechanisms [110] have been utilized to achieve sub-µW power consumption on neuromorphic hardware. However, unstructured pruning often leads to irregular memory access patterns that are difficult to accelerate. Consequently, recent works like the Optimal Spiking Brain Compression (OSBC) [111] have adapted Optimal Brain Compression (OBC) theory to SNNs. By minimizing the loss on the membrane potential rather than just weights, OSBC achieves 97% sparsity with negligible accuracy loss (e.g., < 2% drop on DVS128-Gesture), proving that SNN redundancy is significantly higher than that of ANNs. 2) Neural Architecture Search (NAS): Automating Topology Design: Manual heuristic design of SNNs (e.g., simply copying VGG or ResNet) often fails to capture the intrinsic temporal dynamics of spikes. To overcome this human bias, Neural Architecture Search (NAS) has been introduced to automate the discovery of spike-friendly topologies [39], [112]. Early approaches like SNAS [113] relaxed the discrete search space into a continuous domain. However, a unique challenge in SNN-NAS is the mismatch between topology search and the surrogate gradients used for training. Addressing this, SpikeDHS [114] proposed a joint optimization framework that simultaneously searches for the network topology and the optimal shape of the surrogate gradient. Furthermore, as deployment targets diversify, the field has evolved towards Hardware-Aware NAS. Recent neuroevolutionary approaches [115] explicitly incorporate hardware metrics—such as latency and energy—into the search objective, ensuring the discovered architectures are located on the Pareto-optimal frontier of the target device. 3) Quantization: Compressing Precision and Time: While traditional quantization reduces weight bit-width, optimizing SNNs offers a unique additional dimension: temporal quantization (reducing simulation timesteps T ). Reducing T provides linear gains in latency but typically degrades
C. Neuromorphic Hardware: Evolution of Computational Substrates Deploying SNNs at the edge necessitates hardware that transcends the energy-latency trade-offs inherent in the von Neumann bottleneck. The evolution of neuromorphic hardware has transitioned from simple biological mimicry to sophisticated, domain-specific architectures. We categorize recent advancements into four distinct architectural philosophies: Digital Asynchronous primitives, Hybrid paradigms, Scaleout Systems, and FPGA-based reconfigurable accelerators. Table II summarizes these platforms, contrasting their capacity, learning plasticity, and suitability for edge deployment against standard commercial-off-the-shelf (COTS) hardware. 1) Digital Asynchronous Architectures: The Efficiency Baseline: The foundational philosophy of neuromorphic engineering prioritizes energy efficiency through event-driven asynchronous communication. Prominent examples, such as Intel Loihi and IBM TrueNorth, utilize fine-grained power gating where cores remain idle until a spike event occurs [71], [122], [123]. Contrast with Edge GPUs: Unlike edge GPUs (e.g., NVIDIA Jetson), which rely on batch processing and continuous memory access (high static power), asynchronous architectures achieve orders-of-magnitude lower dynamic power consumption for sparse workloads. However, their rigid adherence to SNN dynamics often limits their ability to support standard DNN layers effectively, necessitating the shift toward hybrid designs. 2) Hybrid Architectures: Cross-Paradigm Fusion: To address the rigidity of pure neuromorphic designs, Hybrid Architectures have emerged, aiming to bridge Computer Science (CS) accuracy with Neuroscience (NS) efficiency. A seminal breakthrough is the Tianjic chip [73], which introduces a unified functional core (FHC) capable of concurrent multimode operation. By integrating configurable unified buffers and adaptable axons, Tianjic allows diverse models—from biologically plausible SNNs to standard CNNs—to coexist on the same substrate. Following this paradigm, several emergent designs have adopted this heterogeneous strategy to support ANN-SNN conversion natively on-chip [121], [124]–[126].
10
TABLE II P ROMINENT N EUROMORPHIC H ARDWARE P LATFORMS R ELEVANT FOR E DGE SNN S (2023-2025 U PDATES )
Platform
Dev.
Key Features for Edge SNNs
Capacity
Learn.
Eff.
Loihi 2
Intel
Programmable spiking neurons, dynamic synapses, async processing
>1 M
Yes
Hala Point
Intel
System of 1,152 Loihi 2 chips, massive parallelism
1.15 B
Yes
G #
Darwin3
ZJU
Rack-scale system, specialized SNN ISA, DarwinOS support
>2 B
Yes
NorthPole
IBM
In-memory computing, inference-only optimization
N/A
Akida 2
BrainChip
Event-based, IP for SoC integration, TENNs support
SpiNNaker2
Manch.
Tianjic
Tsinghua
Scale
Edge Relevance
Ref.
Robotics, AI control
[95]
+
Large-scale AI research
[118]
# G
+
Brain simulation, AGI
[119]
No
+
N/A
Ultra-low-power AI
[101]
Scalable
Yes
+
IoT, wearables, smart home
[120]
ARM cores, custom spike routing
>1 M/bd
Soft.
#
Robotics, embedded sys.
[121]
Hybrid ANN-SNN architecture
105
Yes
G #
Autonomous driving
[73]
+
Legend: Eff. = Power Efficiency; Scale = Scalability. Ratings: + = Best (Ultra Low Power/High Scale); = Very High; # G= High; #= Moderate. Note: M: Million neurons, B: Billion neurons. Capacity varies by specific implementation.
Contrast with Edge CPUs: While embedded CPUs offer general-purpose flexibility, they lack the massive parallelism required for real-time sensor fusion. Hybrid chips fill this gap, enabling systems like autonomous robots to utilize SNNs for low-latency reflex (obstacle avoidance) and ANNs for highlevel cognition (semantic recognition) simultaneously. 3) Scale-out Systems: From Chip to Brain-Scale: While edge inference focuses on single-chip efficiency, a parallel track of research addresses the scalability challenges of wholebrain simulation. The Darwin series [127] represents a significant effort in this direction. The evolution from early prototypes to the massive Darwin3 chip [119] reflects a specialized Instruction Set Architecture (ISA) optimized for spiking dynamics and on-chip plasticity. Crucially, the focus has shifted to system-level integration. The Darwin Monkey (“Wukong”) system integrates nearly 1,000 Darwin3 chips via high-speed distinct interconnects, achieving a scale of over 2 billion neurons and 100 billion synapses. This surpasses many existing platforms, including recent Intel Hala Point configurations, by focusing on addressing the interconnect bottlenecks inherent in massive-scale neuromorphic clusters [72], [74], [128], [129]. Contrast with Data Center GPUs: Unlike GPU clusters that suffer from communication overhead during sparse spike exchange, Darwin Monkey utilizes specialized routing to support brain-inspired operating systems (DarwinOS) efficiently. 4) FPGA-based Accelerators: The Pragmatic Middle Ground: Field-Programmable Gate Arrays (FPGAs) have emerged as a vital “middle ground,” offering the reconfigurability absent in ASICs and the deterministic latency lacking in GPUs. Recent research focuses on overcoming the unique mapping challenges of SNNs on synchronous fabrics [76]. Breaking the Memory Wall: SNNs require persistent state storage (membrane potentials, Vmem ), creating significant
bandwidth pressure. To mitigate this, the S2N2 streaming architecture [130] was proposed to optimize BRAM usage by restricting state updates to active neurons. Challenging the event-driven dogma, SyncNN [131] demonstrated that a synchronous dataflow on FPGAs can actually outperform asynchronous mapping, improving throughput by 4.6× and energy efficiency by 2.3× compared to state-of-the-art eventdriven accelerators. Similarly, the Weight-Stationary LocalOutput-Stationary (WS-LOS) dataflow [132] was developed to maximize data reuse, achieving ultra-low energy consumption (24.3 µJ/Image). Sparsity-Aware Pipelines: Addressing the irregular sparsity of spikes, FireFly v2 [133] introduces a spatiotemporal dataflow that eliminates storage conflicts, achieving a clock frequency of 600 MHz. Furthermore, SpikeX [134] proposes a hardware-software co-optimization framework for unstructured sparsity. By dynamically rebalancing systolic arrays, SpikeX reduces the Energy-Delay Product (EDP) by over 15× compared to dense baselines. The trajectory of neuromorphic hardware is undergoing a fundamental shift from “strict biological mimicry” to “functional heterogeneity.” Early designs prioritized the faithful replication of neuronal dynamics, often at the cost of computational flexibility. Current trends, however, favor softwaredefined architectures where hardware resources can be dynamically reallocated between synchronous (ANN-like) and asynchronous (SNN-like) modes. This evolution suggests that the future of edge intelligence lies not in replacing von Neumann architectures entirely, but in augmenting them with domain-specific, event-driven accelerators that can seamlessly integrate into standard computing stacks.
11
D. The Software Gap: Toolchains and Compilers While neuromorphic hardware has seen rapid acceleration, the software ecosystem remains the primary bottleneck hindering widespread adoption. Unlike the mature CUDA ecosystem for GPUs, the SNN landscape currently suffers from severe fragmentation. Developers are often forced to manually optimize spiking dynamics for specific hardware architectures due to the absence of a unified Intermediate Representation (IR) and a standardized compiler stack. 1) Mapping Toolchains: Solving the Embedding Problem: The translation of a logical SNN graph (neurons and synapses) onto a physical neuromorphic fabric (cores and Networkon-Chip routers) is a non-trivial combinatorial optimization problem known as the “Mapping Problem” [22], [135], [136]. Recent advancements focus on bridging this gap through automated toolchains that balance communication bandwidth, energy consumption, and latency. NeuMap addresses the challenge of mapping SNNs to multicore architectures by treating the network partition as a cluster-to-core allocation problem. By analyzing spike communication patterns and hardware constraints, it employs meta-heuristics to optimize placement, achieving an energy reduction of up to 84% and latency improvements of 55% compared to prior baselines like SpiNeMap. EdgeMap extends this logic specifically for resourceconstrained edge devices [137]. It introduces a streamingbased partitioning method that rigorously accounts for fanin/fan-out limits. Utilizing NSGA-II-based multi-objective optimization, EdgeMap navigates the trade-off between energy and communication costs. Benchmark results highlight its efficacy, demonstrating a 1225x enhancement in execution time and a 57% reduction in energy compared to conventional mapping schemes. 2) Software Frameworks and Fragmentation: The current development environment is bifurcated into vendor-specific toolchains and general-purpose libraries, as summarized in Table III. Vendor-Specific Ecosystems: Intel’s Lava represents a shift towards modularity, offering an open-source framework for Loihi and other neuro-inspired processors. It supports hyper-granular parallelism and dynamic neural fields (DNF), yet its full potential is tightly coupled with the Loihi architecture [139]. Similarly, frameworks like MetaTF remain bound to Akida hardware. General-Purpose Libraries: On the algorithmic front, PyTorch-based libraries such as SpikingJelly and SNNTorch have lowered the entry barrier for researchers by integrating SNN dynamics into standard deep learning workflows [24]. Other established simulators like Brian2 and Nengo continue to serve the computational neuroscience community [143]– [145]. To navigate this fragmented ecosystem, a comprehensive multimodal benchmark [146] has recently provided a quantitative evaluation of frameworks including SpikingJelly, BrainCog, and Lava. This study highlights critical trade-offs in energy efficiency and latency across diverse tasks, offering a data-driven basis for selecting appropriate toolchains for edge deployment. Crucially, these tools primarily address intra-node
algorithmic fidelity. To bridge the gap towards realistic deployment, system-level simulators like iFogSim [147] are increasingly essential for modeling the inter-node latency, bandwidth limits, and energy consumption inherent in distributed edge environments. However, the lack of a seamless compilation path from these high-level Python libraries to heterogeneous neuromorphic chips remains a critical “Software Gap.”
E. System-Level Integration: Cloud, Edge, and IoT The maturation of SNN algorithms has enabled a transition from standalone acceleration to Distributed Edge Intelligence. This paradigm shifts focus from single-chip inference to collaborative systems where SNNs operate within broader IoT and cloud ecosystems. Distributed Wireless Intelligence: Deploying SNNs across distributed sensor nodes introduces unique challenges in bandwidth and synchronization. Recent work models this as a joint optimization problem, minimizing energy under strict spikeloss constraints over wireless channels [15]. This ensures that distributed SNNs can maintain high inference accuracy even in noisy IoT environments. Edge-Cloud Collaboration: To balance the limited capacity of edge devices with the computational power of the cloud, hierarchical architectures have emerged (Fig. 6). To facilitate such hierarchical collaboration, lightweight integration frameworks like FogBus [148] have been proposed to manage the heterogeneity and data flow between resource-constrained edge nodes and the cloud. Building on this paradigm, frameworks like ECC-SNN leverage knowledge distillation, where a complex cloud-based ANN acts as a “teacher” guiding lightweight edge SNN “students” [108]. A key innovation here is the confidence-based offloading mechanism: edge nodes process real-time event streams locally, transmitting only lowconfidence “hard examples” to the cloud for high-precision analysis. This strategy significantly reduces communication overhead while preserving global system accuracy. Federated Learning for SNNs: Addressing data privacy and the “data island” problem, Federated Learning (FL) has been adapted for spiking domains. Techniques such as FedLEC tackle the issue of non-IID (label-skewed) data in neuromorphic networks. By employing intra-client label weight calibration and inter-client distillation, these methods mitigate model drift, allowing SNNs to learn collaboratively without sharing raw event data [149]–[152]. The trajectory of SNN software is approaching an inflection point similar to the early days of GPU computing. The current fragmentation—characterized by isolated vendor toolchains and disconnected mapping algorithms—is unsustainable. The future lies in Standardization. The community must converge towards a unified neuromorphic Intermediate Representation (IR) and a cross-platform compiler stack (analogous to LLVM or TVM). Only when a high-level description in PyTorch can be seamlessly compiled to any underlying neuromorphic substrate—be it Loihi, TrueNorth, or FPGA-based accelerators—will SNNs achieve the ubiquity necessary for nextgeneration ubiquitous computing.
12
TABLE III S ELECTED SNN S OFTWARE F RAMEWORKS AND M APPING T OOLCHAINS (2020–2025)
Framework (Developer)
Core Features & Purpose
Edge-Relevant Capabilities
Ref.
Hardware Mapping Toolchains NeuMap (NUDT)
Mapping SNNs to multicore HW; Comm. pattern calculation; Meta-heuristic cluster-to-core mapping
Optimized for NoC latency and energy on multicore edge hardware
[138]
EdgeMap (SJTU)
Optimized mapping for edge; Streaming-based partitioning; Multi-objective optimization (NSGA-II)
Significant reduction in latency, energy, and comm. cost for edge deployment
[137]
Deep Learning & Deployment Frameworks Lava (Intel)
Neuro-inspired app dev; Modular; Platform-agnostic; Supports deep learning (lava-dl)
Native deployment on Loihi chips; Optimized for energy/speed efficiency
[139]
SNNTorch (UCSC)
PyTorch-based training; Surrogate gradients; Temporal dynamics; GPU acceleration
Facilitates training of deep SNNs deployable on edge; Seamless PyTorch integration
[23]
SpikingJelly (PKU)
PyTorch-based; LIF/PLIF neurons; Direct training (SG); Rich encoding methods
Enables development of deep SNNs suitable for direct edge deployment
[89]
Bio-inspired Simulation & Prototyping Nengo (ABR)
Large-scale modelling (NEF); Supports multiple backends (Loihi, SpiNNaker, CPU/GPU)
Real-time control applications verified on diverse neuromorphic platforms
[140]
BindsNET (UMass)
Bio-plausible simulation; STDP/R-STDP rules; Eventdriven dynamics
Prototyping SNNs with on-device online learning potential
[141]
Brian2 (Sorbonne)
Biophysical simulation; Flexible model definition; Code generation
Simulating complex, biologically detailed SNNs prior to hardware mapping
[142]
VI. A PPLICATIONS SNNs are transitioning from theoretical models to deployable solutions, driven specifically by the rigid constraints of edge computing environments. Rather than merely offering an alternative to ANNs, SNNs address distinct physical and operational bottlenecks: extreme power budgets (battery life), communication bandwidth (saturation from raw data transmission), latency (safety-critical feedback loops), and data privacy (local processing). This section analyzes recent implementations (2023–2025) through the lens of these constraints. Table IV provides a quantitative comparison of these applications against DNN baselines in terms of accuracy, energy efficiency, and latency. A. Computer Vision: High-Speed and Event-Based Sensing Vision systems generate the highest data volume at the edge, creating a massive bandwidth and energy burden. SNNs mitigate this by processing information only when changes occur in the scene. 1) High-Speed Retinomorphic Sensing: Standard framebased cameras suffer from motion blur and high data redundancy. While Dynamic Vision Sensors (DVS) address this, they often discard static texture information. To bridge this gap, the Spike Camera (Vidar) architecture was introduced [161], [162]. By employing a fovea-like sampling mechanism where pixels fire continuous spikes based on luminance intensity, this paradigm achieves ultra-high temporal resolution (up to 40,000 Hz). This allows SNNs to reconstruct high-speed
motion (e.g., rapid mechanical rotation) that is invisible to traditional cameras, while significantly compressing the data stream compared to high-speed video [163]–[165]. 2) Low-Power Gesture and Activity Recognition: For battery-powered Human-Machine Interfaces (HMI), the primary constraint is energy consumption. SNNs exploit the spatial sparsity of gesture events to minimize computation. Implementations on neuromorphic hardware have demonstrated power consumption as low as 178 mW during active inference [166]. Recent advancements have extended this capability from simple hand gestures to complex Human Activity Recognition (HAR) [167]. Notably, a February 2025 study proposed a multimodal framework combining event cameras with Spiking Graph Convolutional Networks (SGCN). By processing skeleton data locally, this system avoids the transmission of intrusive raw video feeds, effectively resolving privacy concerns in smart home environments while maintaining high recognition fidelity [111], [156]. B. Beyond Vision: Auditory and Olfactory Sensing Non-visual modalities are naturally sparse. SNNs leverage this property to solve the “Always-On” power dilemma. 1) Neuromorphic Auditory Processing: In smart speakers and hearing aids, the wake-word engine must run continuously. SNNs provide a zero-dynamic-power solution during silence. Benchmarking on the Intel Loihi chip has demonstrated that SNNs outperform GPU-based DNNs in Keywords Spotting (KWS) within a milliwatt envelope [168]. Advancing this bio-inspired approach, recurrent SNN architectures have been
13
Cloud Server (Teacher ANN)
Hard Examples Offloading
High Precision / Complex Training
n tio illa hts) t s g Di Wei ge ed ssed l ow re Kn omp (C
Edge Layer (Low Latency) Edge Node 1 (Student SNN) Real-time Inference
Local Gradient Aggregation
Edge Node 2 (Student SNN) Low Power / Event-driven
Spikes
Events
DVS Sensor
IoT Device
Fig. 6. Proposed SNN-based Cloud-Edge Collaboration Framework. The cloud server hosts a complex Teacher ANN to guide lightweight Student SNNs on edge nodes via knowledge distillation. Edge nodes process real-time event streams and only offload low-confidence “hard examples” to the cloud, significantly reducing bandwidth usage.
utilized to extract fine-grained temporal features, achieving state-of-the-art accuracy [169]. Crucially, an April 2025 study reported <1ms latency in keyword recognition on commodity neuromorphic processors [157]. Beyond speech, SNNs are also transforming Environmental Sound Classification (ESC). By mimicking human auditory pathways, bio-inspired models can classify background scenes with minimal power, enabling the long-term deployment of acoustic sensors in remote areas without frequent battery replacement [168], [170], [171]. 2) Neuromorphic Olfaction (E-Nose): Olfactory data is high-dimensional but sparse, posing a challenge for standard classifiers that require massive training sets. SNNs address the constraint of data scarcity. Mimicking the mammalian olfactory bulb, neural circuits have been implemented to enable “One-Shot Learning” of hazardous chemicals [172]. Unlike DNNs, such systems can learn a new odor signature from a single exposure. Further industrial validation confirmed that SNNs effectively handle sensor drift in gas identification systems, a common failure point for traditional algorithms [173]. C. Robotics and Autonomous Systems In robotics, the trade-off between on-board computational weight and flight time/operation time is critical. SNNs offer a solution via neuromorphic control loops. 1) UAVs and Navigation: For Unmanned Aerial Vehicles (UAVs), processing power directly competes with battery
life. The SNN4Agents framework achieved a 4.03x energy efficiency improvement on the NCARS dataset [117]. Additionally, Modular SNNs for Visual Place Recognition (VPR) have enabled scalable mapping on resource-constrained drones [155], providing sub-millisecond reaction times to obstacles—a critical safety feature when ground communication is lost [174], [175]. 2) Edge-Cloud Orchestration: While edge SNNs handle reflex tasks, complex queries require cloud support. The ECC-SNN framework (May 2025) illustrates this hierarchy, reporting a 4.15% accuracy improvement on CIFAR-10 by dynamically offloading low-confidence “hard examples” to the cloud [108]. This architecture balances local energy constraints with global Quality of Service (QoS). D. Healthcare and Wearables Medical applications face a dual constraint: extreme energy efficiency for implants and strict data privacy for wearables. 1) Bio-signal Monitoring: SNNs are increasingly applied to ECG classification and arrhythmia detection on FPGAs [76]. A June 2024 review further corroborates this trajectory, noting that SNN-based implementations are rapidly closing the accuracy gap with DNNs while maintaining a fraction of the power budget [176]. By processing raw bio-signals locally, these systems ensure that sensitive waveforms are never transmitted wirelessly, significantly reducing the attack surface for data breaches [177], [178].
14
TABLE IV E XEMPLARY A PPLICATIONS OF SNN S IN E DGE C OMPUTING (2022–2025) Domain
Task
Approach / Model
Hardware
Key Performance Metrics
Ref.
CV
Neural Rendering
Spiking-NeRF (Hybrid SNN)
GPU/Simulated
Quality: Comparable PSNR; Energy: 2.27× reduction vs. NeRF
[153]
Gesture Recog.
OSBC (One-shot Pruning)
DVS128-Gesture
Sparsity: 97%; Acc Loss: 1.7%; Method: Post-training Quant.
[154]
Visual Place Recog.
Modular SNN Ensembles
Resource Constrained
Compact modules (1.5k neurons); Sequence matching improves R@1
[155]
Autonomous Agents
SNN4Agents (Quantization)
Event Sensors
Acc: 84.1%; Mem: −68.8%; Eff: 4.0× gain
[117]
HAR (Multimodal)
SNN-driven fusion (Event + Skeleton); SNN-Mamba
N/A
High efficiency via sparse multimodal fusion
[156]
Keyword Recog.
On-chip learning SNN
Commodity Neuro.
Latency: < 1 ms
[157]
Neural Decoding
Adaptively Pruned SNNs
SENECA
Power: 0.18 µW/step; Eff: > 10× vs. dense SNNs
[110]
ECG Class.
SNN on FPGA
FPGA / Neuro.
Acc: 98.2% (MIT-BIH); Ultra-low power matching DNN acc.
[158]
Defect Detection
SNN Model Strengthening
Ind. Datasets
Speed: 11–27× faster unlearning vs. retraining
[159]
Fault Diagnosis
Deep Spiking ResNet/GNN
Ind. Sensors
Robust spatiotemporal modeling; High efficiency
[160]
Classification
ECC-SNN (Joint Training)
Edge + Cloud
Acc: +4.1%; Energy: −79%; Lat: −39%
[108]
Robotics
IoT
Healthcare
Industrial
Edge-Cloud
2) Implantable Interfaces: For intracortical neural decoding, heat dissipation is the limiting factor to prevent tissue damage. An April 2025 study on adaptive pruning of SNNs demonstrated sub-µW power consumption (0.18 µW/timestep) [110]. This level of thermal efficiency is unattainable with standard Von Neumann architectures and represents a key enabling technology for long-term brainmachine interfaces. E. Industrial Detection and Smart Infrastructure In large-scale infrastructure, the primary bottlenecks are bandwidth saturation and data sovereignty. 1) Industrial Fault Diagnosis (IFD): Transmitting highfrequency vibration data from thousands of machines to a central cloud is often impractical due to bandwidth costs. SNNs enable Edge Learning, where models adapt to new defects locally. Recent methodologies demonstrate SNN model strengthening for surface defect detection directly on the edge node [159], [179]. This eliminates the need to expose proprietary production line data to external networks. 2) Smart City and Public Safety: In traffic management, transmitting raw video streams saturates networks. SNNs allow for “Semantic Compression,” where only metadata (e.g., “accident detected”) is transmitted rather than raw pixels [180]. Beyond traffic, SNN-equipped UAVs are proving vital for disaster evacuation monitoring [181]. In such scenarios, reliance on potentially damaged cellular infrastructure is risky, necessitating the autonomous, on-board intelligence that SNNs provide. Furthermore, by processing video at the sensor level
and discarding personally identifiable information instantly, these systems inherently adhere to stricter privacy standards [182], [183]. Across these domains, a clear pattern emerges regarding the viability of SNNs. Spiking networks demonstrate distinct superiority in scenarios characterized by event-driven dynamics, critical latency requirements, and severe power constraints (e.g., neuromorphic control, always-on sensing). Conversely, in tasks requiring high-precision static pattern recognition with relaxed power budgets (e.g., static ImageNet classification), the advantages of SNNs over traditional CNNs remain less pronounced.
VII. G RAND C HALLENGES : S YSTEMIC F RICTION Despite the theoretical allure of Spiking Neural Networks (SNNs) for edge intelligence, their transition from academic curiosities to mainstream deployment is impeded by significant systemic friction. This friction arises not merely from engineering bugs, but from a fundamental mismatch between current deep learning paradigms, silicon limitations, and the discrete nature of spiking dynamics. We categorize these challenges into three critical dimensions: the algorithmic learning dilemma, the hardware-software gap, and the operational realities of deployment. Table V provides a structured taxonomy of these barriers, mapping specific technical pain points (e.g., dead neurons, memory wall) to current research thrusts and representative literature.
15
TABLE V M AJOR C HALLENGES IN D EPLOYING SNN S AT THE E DGE AND C URRENT R ESEARCH T HRUSTS
Challenge Area
Training Complexity
Specific Challenge
Current Research Approaches & Thrusts
Key Refs.
Non-differentiable spike events
Surrogate Gradients (SG); Event-Driven Learning (STD-ED, MPD-ED); Differentiable Spike (Dspike) Learnable SGs; Adaptive Gradient Rules; Threshold-dependent Batch Norm (tdBN); Activity regularization Hybrid learning (e.g., R-STDP); Supervised STDP variants; Combining STDP with backprop
[24], [90]
Gradient vanishing & “Dead neuron”
Bio-plausible scalability (STDP)
Scalability
Hardware Constraints
[24], [184]
[64], [89]
Performance on large datasets (e.g., ImageNet)
ANN-to-SNN Conversion; SNN-specific deep architectures (Spiking Transformers); Hybrid models
[107], [185]
Memory Wall & Fan-in/out limits
Co-design Frameworks (e.g., QUEST); In-memory computing; SNN-specific pruning/quantization (OSBC) Optimized NoC designs; Standardized IR (e.g., NIR); Platform-agnostic frameworks (Lava)
[111], [116]
Inter-chip comm. & Heterogeneity
[109], [138]
Energy/Latency
Accuracy vs. Efficiency Trade-offs
Joint Optimization (e.g., SNN4Agents); Edge-cloud collaboration (ECC-SNN); Early exit mechanisms
[108], [117]
Standardization
Fragmented ecosystem & Benchmarks
Unifying Frameworks (Lava, Nengo); Federated SNN learning (FedLEC); Neuromorphic benchmarking suites
[109], [149]
A. The Learning Dilemma: Optimization in a Discrete World The primary obstacle impeding SNN adoption is the algorithmic struggle to train deep, spiking architectures effectively. 1) The Fundamental Schism of Non-Differentiability: A fundamental schism exists between the gradient-based optimization dominant in Deep Learning (e.g., Backpropagation) and the discrete dynamics of SNNs. The generation of a spike is inherently an all-or-nothing event, typically modeled by a non-differentiable Heaviside step function. This discrete nature renders direct differentiation impossible, breaking the chain rule required for standard backpropagation. While Surrogate Gradients (SG)—which approximate the spike derivative with a continuous function (e.g., sigmoid or arctan) during the backward pass—have become the standard workaround, they introduce a gradient mismatch. This approximation error accumulates as network depth increases, often leading to suboptimal convergence compared to ANNs. 2) Training Stability: The “Dead Neuron” and BPTT: Deep SNNs face severe stability issues. First, the “Dead Neuron” problem implies that neurons may fail to cross the firing threshold due to poor initialization or insufficient stimulus, rendering them silent [186]. Unlike ReLUs in ANNs, a silent spiking neuron provides no gradient information and consumes time-steps without contributing to inference. Second, training relies on Backpropagation Through Time (BPTT) to capture temporal dependencies. BPTT unfolds the network over time steps, drastically increasing the memory footprint and exacerbating vanishing/exploding gradient problems, making the training of ultra-deep SNNs (e.g., ResNet-100+) computationally prohibitive. 3) Scalability and the Conversion Debate: A contentious debate persists regarding the optimal path to scalability:
ANN-to-SNN Conversion: This approach leverages mature ANN training pipelines and converts weights to SNNs. While stable, it often suffers from high latency (requiring long simulation windows to approximate rate coding) and fails to exploit the rich temporal dynamics of single spikes [187]. • Direct Training: Direct optimization (via SG) captures temporal features and enables low-latency inference. However, it struggles with the scalability issues mentioned above. Consequently, while SNNs excel on neuromorphic benchmarks (e.g., CIFAR10-DVS), they struggle to match State-ofthe-Art (SOTA) ANN accuracy on large-scale static datasets like ImageNet without incurring excessive latency costs. •
B. The Hardware-Software Gap: Breaking the Memory Wall The theoretical energy efficiency of SNNs is often predicated on idealized hardware. In reality, physical implementation faces strict constraints regarding memory hierarchy and interconnects. 1) The State-Memory Wall: A Double Bottleneck: SNNs introduce a unique challenge compared to stateless DNNs: the requirement to maintain the dynamic state (membrane potential, Vmem ) of every neuron at every timestep [188]. This creates a “double bottleneck” of storing both synaptic weights and neuron states. As visually explained in Fig. 7, solving this requires architectural divergence: • Von Neumann Bottleneck (Fig. 7a): Traditional architectures separate processing units (CPU/GPU) from memory. Data must traverse the system bus, leading to the “Memory Wall,” where energy consumption is
16
Co-located Memory & Logic Core
Core
Core
Mem+Comp
Mem+Comp
Mem+Comp
System Bus
Memory (DRAM)
Limit
Processing (CPU/GPU)
Storage
Core
Core
Core
Mem+Comp
Mem+Comp
Mem+Comp
Compute
Core
Core
Core
Mem+Comp
Mem+Comp
Mem+Comp
Von Neumann Bottleneck Data Movement Cost
(a) Von Neumann Architecture
(b) Neuromorphic Architecture
Fig. 7. Architectural Comparison. (a) Traditional Von Neumann architecture separates memory and processing. The data bus (shown as parallel lines) becomes a bottleneck. (b) Neuromorphic architecture integrates memory and computation (M+C) into distributed cores.
dominated by data movement (100× ∼ 1000× higher than computation) rather than arithmetic logic. • Neuromorphic Locality (Fig. 7b): Neuromorphic chips (e.g., Intel Loihi, TrueNorth) adopt a non-Von Neumann approach by co-locating memory and computation within distributed cores. By storing states locally (SRAM), they minimize off-chip data movement. However, this locality introduces a capacity constraint. High-speed on-chip SRAM is expensive and limited [72], [73], [189]–[191]. When deep SNN models exceed on-chip capacity, the system is forced to access off-chip DRAM, causing energy consumption to spike drastically and negating the benefits of event-driven processing. 2) Connectivity and Fragmentation: Fan-in/Fan-out Sparsity: Unlike the all-to-all connectivity in theoretical models, physical chips have limited routing resources. Mapping dense networks onto sparse hardware graphs necessitates “multihop” spike routing [137], which introduces non-deterministic latency and congestion. The Software Stack Void: Perhaps the most critical barrier is the absence of a unified software stack comparable to NVIDIA’s CUDA. The landscape is fragmented into heterogeneous architectures (asynchronous, mixed-signal, digital), preventing the development of standardized compilation toolchains [192]. This forces researchers into labor-intensive, hardware-specific optimization.
C. The Deployment Reality: Security and Operational Tradeoffs As SNNs migrate from labs to exposed edge environments, new operational vulnerabilities emerge.
1) Adversarial Robustness: The Temporal Vulnerability: SNNs were historically hypothesized to possess inherent robustness due to stochasticity and discrete filtering. However, recent scrutiny reveals a false sense of security. It has been demonstrated that SNNs are highly vulnerable to temporal perturbations [193]. Attackers can imperceptibly shift the timing of input spikes, causing membrane potentials to miss firing thresholds. Recent surveys indicate that gradient-based attacks can be adapted to the temporal domain, necessitating robust defense mechanisms like discrete adversarial training [194], [195]. 2) Privacy and Side-Channels: While Federated Neuromorphic Learning (FNL) offers privacy by transmitting only weight updates [50], hardware implementations remain vulnerable. Physical side-channel attacks can monitor the distinct power signatures of spike events to reverse-engineer input stimuli or model architectures [196], demanding hardwarelevel masking countermeasures. 3) The Energy-Accuracy Trade-off: Finally, deployment involves a harsh trade-off. Achieving the ultra-low energy promised by SNNs often requires aggressive quantization (e.g., 4-bit weights) or extremely short simulation windows, which can severely degrade accuracy. Frameworks like ECC-SNN attempt to mitigate this by offloading difficult samples to the cloud; however, this reintroduces a dependency on network connectivity. Ultimately, the future of SNNs does not lie in simply replacing DNNs for all tasks, but in identifying and dominating the “Niche of Spatio-Temporal Sparsity”—scenarios involving asynchronous event streams, ultra-low latency control loops, and constrained power budgets. The “Grand Challenge” is to bridge the schism between software flexibility and hardware
17
Optimization Phase
Map to Qubits
Quantum Accelerator (QPU)
Input Performance Feedback
Complex Optimization Problem (e.g., NAS, Routing)
Grover’s Search / QAOA Optimal Configuration (Hyperparameters)
Neuromorphic Chip (Deployment) Spiking Neural Network
Inference Phase Fig. 8. Conceptual Quantum-Neuromorphic Synergy. Quantum algorithms (e.g., QAOA) are utilized to solve NP-hard optimization problems inherent in SNN design, such as Neural Architecture Search (NAS) or synaptic routing, enabling the deployment of highly optimized SNNs on neuromorphic hardware.
primitives, transforming theoretical efficiency into operational reality. VIII. F UTURE ROADMAP : T OWARDS U BIQUITOUS I NTELLIGENCE As we look beyond the current hurdles, the trajectory of SNNs in edge computing is not merely about incremental improvements but represents a fundamental architectural shift. If the previous section outlined the friction points, this roadmap serves as a blueprint for the next generation of edge intelligence. We structure this vision into three cohesive pillars: the Algorithmic Frontier, the Hardware-Software Continuum, and the Convergence of emerging technologies. A. The Algorithmic Frontier: From Rules to Reasoning To bridge the gap between biological efficiency and Artificial General Intelligence (AGI), we must move beyond simple classification tasks toward complex spatio-temporal reasoning [197]. This leap requires a symbiotic evolution of learning rules and model scale. 1) Unifying Learning Paradigms: The dichotomy between biological plausibility and gradient-based optimization must be resolved. Future algorithms will likely employ a hybrid strategy: using Advanced Surrogate Gradients for offline meta-learning of deep architectures (e.g., Spiking Transformers), while leveraging biologically inspired rules (such as advanced STDP variants) for rapid, energy-efficient On-Chip Adaptation [157]. The goal is to develop “Direct Training” methods robust to the vanishing gradient problem, enabling SNNs to capture long-range dependencies without the excessive computational cost of BPTT [185], [198].
2) Large-Scale Spiking Models: Just as LLMs have revolutionized NLP, the era of Large Spiking Models (LSMs) is approaching. By integrating mechanisms like the Temporal Shift Module and attention mechanisms directly into the spiking domain, future models will orchestrate complex multimodal tasks on the edge. This shifts the paradigm from static datasets to dynamic, event-stream processing, where the sparsity of SNNs provides a decisive advantage in FLOPs reduction [186]. B. The Hardware-Software Continuum The potential of algorithms can only be realized if the underlying substrate—both physical and virtual—is optimized for event-driven dynamics. 1) Next-Gen Neuromorphic Hardware: The integration of Emerging Non-Volatile Memories (eNVMs) is pivotal. Devices such as Memristors (RRAM) and Phase-Change Memory (PCM) allow for the physical emulation of high-fanout synaptic connectivity [199]–[201]. Unlike traditional Von Neumann architectures, these devices enable analog Computein-Memory (CIM), where synaptic accumulation occurs directly within the memory array, virtually eliminating the energy cost of data movement [202]. 2) The Neuromorphic OS: Orchestration and Virtualization: Perhaps the most critical yet underexplored frontier is the system-level software stack. Current cloud orchestration frameworks (e.g., Kubernetes) suffer from a fundamental “Sync-Async Mismatch”: they force asynchronous, finegrained spike streams into inefficient, synchronous fixed-time batches. This mismatch creates a “Bottleneck of Causality,” where the latency benefits of SNNs are negated by the waiting time of the orchestration layer.
18
To address this, future edge systems must evolve into a true Neuromorphic OS underpinned by three core mechanisms: 1) Event-Driven Scheduling: A transition from framebased scheduling to interrupt-driven policies that respect the causality of neural events [72], [203]. 2) Dynamic Heterogeneity: Schedulers must quantify the Price of Converting (PoC)—the latency and energy cost of transcoding between spiking (neuromorphic) and nonspiking (CPU/GPU) domains. Decisions to offload tasks should be based on minimizing this PoC dynamically [73], [198], [204]. 3) SLA-Aware Spiking Containerization: To enable multi-tenancy, we envision lightweight virtualization technologies optimized for stateful neurons. This requires novel mechanisms for “State Saving/Restoring” of membrane potentials, allowing context switching between SNN models without performance degradation [205]–[207]. C. The Convergence: Quantum, 6G, and Ethics SNNs will not exist in isolation but will serve as the cognitive engine within a broader technological ecosystem. 1) The 6G Nexus: As 6G networks introduce ultra-low latency and semantic communications, SNNs are positioned to become the native processing dialect of the network edge [208], [209]. Comprehensive 6G visions and surveys have highlighted neuromorphic computing as a key enabler for processing the unprecedented volume of sensor data directly at the infrastructure level [210]. 2) Quantum-Neuromorphic Synergy: While currently exploratory, the intersection of quantum computing and SNNs offers a path to transcend classical limitations. As illustrated in Fig. 8, we propose a synergistic paradigm where Quantum Machine Learning (QML) algorithms (e.g., QAOA) serve as offline accelerators. These quantum agents solve NP-hard optimization problems inherent in SNN design—such as Neural Architecture Search (NAS) or complex synaptic routing. The optimized configuration is then mapped onto neuromorphic hardware for real-time, ultra-low-power inference [211]. 3) Ethical and Secure Intelligence: The ubiquity of “always-on” edge AI demands rigorous ethical guardrails. Beyond efficiency, SNNs must be designed for privacy (via Federated Learning, e.g., FedLEC [149]) and resilience against adversarial attacks targeting spike timing [159], [212]. Ultimately, we envision that the strict boundary between SNNs and DNNs will dissolve. The future of edge intelligence lies in a “Unified Neuromorphic Continuum,” where SNNs function as the “ultra-low power gear” for continuous monitoring, seamlessly shifting to the DNN “high-performance gear” only when deeper cognitive resolution is required. This seamless gear-shifting represents the holy grail of adaptive edge computing. IX. C ONCLUSION This survey began by interrogating the “Deployment Paradox” facing neuromorphic computing: the tension between the
theoretical efficiency of bio-inspired models and the practical rigidity of contemporary von Neumann hardware. Throughout this review, we have demonstrated that this paradox is not an inherent flaw, but a transitional friction that is effectively resolvable through the lens of hardware-software co-design. By reconciling algorithmic sparsity with physical silicon constraints, we have shown that Spiking Neural Networks (SNNs) are transitioning from theoretical curiosities to robust operational realities. Crucially, the significance of SNNs extends beyond mere energy conservation. They represent a fundamental paradigm shift from “processing data”—the legacy of static, framebased analysis—to “processing changes.” This event-driven philosophy aligns computation with the dynamic nature of the physical world, offering a path to fundamentally eliminate the temporal redundancy that plagues conventional frame-based Deep Learning. However, realizing this potential requires more than incremental optimization. As we argued, the immediate frontier for the community lies in dismantling the “Sync-Async Mismatch.” The development of a unified Neuromorphic OS is imperative to orchestrate asynchronous spiking workloads within the synchronous infrastructure of modern computing systems. Only by abstracting these hardware complexities can we enable the widespread adoption of neuromorphic solutions. Ultimately, as we stand on the precipice of the 6G era and the Internet of Everything, the demand for pervasive, low-latency intelligence has never been greater. SNNs are poised to transcend their role as a niche technology to become the “Green Cognitive Substrate” of our digital infrastructure—ensuring that the future of edge intelligence is not only ubiquitous but also sustainable. R EFERENCES [1] W. Shi, J. Cao, Q. Zhang, Y. Li, and L. Xu, “Edge computing: Vision and challenges,” IEEE Internet of Things Journal, vol. 3, no. 5, pp. 637–646, 2016. [2] Z. Zhou, X. Chen, E. Li, L. Zeng, K. Luo, and J. Zhang, “Edge intelligence: Paving the last mile of artificial intelligence with edge computing,” Proceedings of the IEEE, vol. 107, no. 8, pp. 1738–1762, 2019. [3] R. Buyya, S. N. Srirama, G. Casale, R. Calheiros, Y. Simmhan, B. Varghese, E. Gelenbe, B. Javadi, L. M. Vaquero, M. A. Netto et al., “A manifesto for future generation cloud computing: Research directions for the next decade,” ACM computing surveys (CSUR), vol. 51, no. 5, pp. 1–38, 2018. [4] D. R.-J. G.-J. Rydning, J. Reinsel, and J. Gantz, “The digitization of the world from edge to core,” Framingham: International Data Corporation, vol. 16, pp. 1–28, 2018. [5] J. Chen and X. Ran, “Deep learning with edge computing: A review,” Proceedings of the IEEE, vol. 107, no. 8, pp. 1655–1674, 2019. [6] M. Satyanarayanan, “The emergence of edge computing,” Computer, vol. 50, no. 1, pp. 30–39, 2017. [7] A. Botta, W. De Donato, V. Persico, and A. Pescapé, “Integration of cloud computing and internet of things: a survey,” Future generation computer systems, vol. 56, pp. 684–700, 2016. [8] F. Dong, X. Si, and M.-F. Chang, “Design methodology and trends of sram-based compute-in-memory circuits,” in 2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT), 2022, pp. 1–4. [9] C. Ramı́rez, A. Castelló, H. Martı́nez, and E. S. Quintana-Ortı́, “Communication-avoiding fusion of gemm-based convolutions for deep learning in the risc-v gap8 mcu,” IEEE Internet of Things Journal, vol. 11, no. 21, pp. 35 640–35 653, 2024.
19
[10] Y. Sun, T. Chen, Q. V. H. Nguyen, and H. Yin, “Tinyad: Memoryefficient anomaly detection for time-series data in industrial iot,” IEEE Transactions on Industrial Informatics, vol. 20, no. 1, pp. 824–834, 2024. [11] C. Fang, Z. Shen, Z. Wang, C. Wang, S. Zhao, F. Tian, J. Yang, and M. Sawan, “An energy-efficient unstructured sparsity-aware deep snn accelerator with 3-d computation array,” IEEE Journal of Solid-State Circuits, vol. 60, no. 3, pp. 977–989, 2025. [12] F. Liu, Z. Wang, W. Zhao, N. Yang, Y. Chen, S. Huang, H. Li, T. Yang, S. Pei, X. Liang, and L. Jiang, “Exploiting temporal-unrolled parallelism for energy-efficient snn acceleration,” IEEE Transactions on Parallel and Distributed Systems, vol. 35, no. 10, pp. 1749–1764, 2024. [13] S. Kim, S. Kim, S. Hong, S. Kim, D. Han, J. Choi, and H.-J. Yoo, “C-dnn: An energy-efficient complementary deep-neural-network processor with heterogeneous cnn/snn core architecture,” IEEE Journal of Solid-State Circuits, vol. 59, no. 1, pp. 157–172, 2024. [14] H. Chu, Y. Yan, L. Gan, H. Jia, L. Qian, Y. Huan, L. Zheng, and Z. Zou, “A neuromorphic processing system with spike-driven snn processor for wearable ecg classification,” IEEE Transactions on Biomedical Circuits and Systems, vol. 16, no. 4, pp. 511–523, 2022. [15] Y. Liu, Z. Qin, and G. Y. Li, “Energy-efficient distributed spiking neural network for wireless edge intelligence,” IEEE Transactions on Wireless Communications, vol. 23, no. 9, pp. 10 683–10 697, 2024. [16] Z. Yan, Z. Bai, K. Tang, and W.-F. Wong, “Reconsidering the energy efficiency of Spiking Neural Networks,” arXiv preprint arXiv:2409.08290, 2024. [17] M. Li, J. Ding, Z. Yue, Y. Li, Z. Luo, Z. Fan, W. Zhao, H. Min, F. Liu, X. Yang, X. Liang, and L. Jiang, “A high energy-efficiency multi-core neuromorphic architecture for Deep SNN training,” arXiv preprint arXiv:2412.05302, 2024. [18] G. Zhang, L. Feng, F. Zhou, Z. Yang, Q. Zhang, A. Saleh, P. K. Donta, and C. K. Dehury, “Spiking neural networks in intelligent edge computing,” IEEE Consumer Electronics Magazine, vol. 14, no. 4, pp. 66–75, 2025. [19] G. Li, L. Deng, H. Tang, G. Pan, Y. Tian, K. Roy, and W. Maass, “Brain-inspired computing: A systematic survey and future trends,” Proceedings of the IEEE, vol. 112, no. 6, pp. 544–584, 2024. [20] S. M. Meyer, P. Weidel, P. Plank, L. Campos-Macias, S. B. Shreshta, P. Stratmann, J. Timcheck, and M. Richter, “A diagonal structured state space model on loihi 2 for efficient streaming sequence processing,” in 2025 Neuro Inspired Computational Elements (NICE), 2025, pp. 1–9. [21] S. Varadarajulu, M. O. K. Mendonça, G. Eappen, J. Querol, and S. Chatzinotas, “Enhanced demodulator for 5g ntn using spatiotemporal attention convolutional autoencoder and akida brainchip snn,” in 41st International Communications Satellite Systems Conference (ICSSC 2024), vol. 2024, 2024, pp. 99–104. [22] C. D. Schuman, S. R. Kulkarni, M. Parsa, J. P. Mitchell, P. Date, and B. Kay, “Opportunities for neuromorphic computing algorithms and applications,” Nature Computational Science, vol. 2, no. 1, pp. 10–19, 2022. [23] J. K. Eshraghian, M. Ward, E. Neftci et al., “Training spiking neural networks using lessons from deep learning,” Proceedings of the IEEE, vol. 111, no. 9, pp. 1016–1054, 2023. [24] C. Zhou, H. Zhang, L. Yu, Y. Ye, Z. Zhou, L. Huang, Z. Ma, X. Fan, H. Zhou, and Y. Tian, “Direct training high-performance deep spiking neural networks: A review of theories and methods,” Frontiers in Neuroscience, vol. 18, p. 1383844, 2024. [25] S. GHOSH-DASTIDAR and H. ADELI, “Spiking neural networks,” International Journal of Neural Systems, vol. 19, no. 04, pp. 295–308, 2009. [26] S. Shen, R. Zhang, C. Wang, R. Huang, A. Tuerhong, Q. Guo, Z. Lu, J. Zhang, and L. Leng, “Evolutionary spiking neural networks: A survey,” Journal of Membrane Computing, pp. 1–12, 2024. [27] M. Xiao, Q. Meng, Z. Zhang, D. He, and Z. Lin, “Online training through time for spiking neural networks,” in Advances in Neural Information Processing Systems, S. Koyejo, S. Mohamed, A. Agarwal, D. Belgrave, K. Cho, and A. Oh, Eds., vol. 35. Curran Associates, Inc., 2022, pp. 20 717–20 730. [28] T. Bu, W. Fang, J. Ding, P. Dai, Z. Yu, and T. Huang, “Optimal ANNSNN conversion for high-accuracy and ultra-low-latency spiking neural networks,” arXiv preprint arXiv:2303.04347, 2023. [29] S. Hwang, S. Lee, D. Park, D. Lee, and J. Kung, “Spikedattention: Training-free and fully spike-driven transformer-to-snn conversion with winner-oriented spike shift for softmax operation,” in Advances in Neural Information Processing Systems, A. Globerson, L. Mackey,
D. Belgrave, A. Fan, U. Paquet, J. Tomczak, and C. Zhang, Eds., vol. 37. Curran Associates, Inc., 2024, pp. 67 422–67 445. [30] R.-J. Zhu, Q. Zhao, G. Li, and J. K. Eshraghian, “SpikeGPT: Generative pre-trained language model with spiking neural networks,” arXiv preprint arXiv:2302.13939, 2023. [31] Z. Zhou, K. Che, W. Fang, K. Tian, Y. Zhu, S. Yan, Y. Tian, and L. Yuan, “Spikformer V2: Join the high accuracy club on ImageNet with an SNN ticket,” arXiv preprint arXiv:2401.02020, 2024. [32] S. Snyder, S. R. Risbud, and M. Parsa, “Neuromorphic Bayesian optimization in Lava,” in Proceedings of the 2023 International Conference on Neuromorphic Systems (ICONS). New York, NY, USA: ACM, 2023, pp. 1–5. [33] J. E. Pedersen, S. Abreu, M. Jobst, G. Lenz, V. Fra, F. C. Bauer, D. R. Muir et al., “Neuromorphic intermediate representation: A unified instruction set for interoperable brain-inspired computing,” Nature Communications, vol. 15, no. 1, p. 8122, 2024. [34] D. Rasmussen, “Nengodl: Combining deep learning and neuromorphic modelling methods,” Neuroinformatics, vol. 17, no. 4, pp. 611–628, 2019. [35] A. Carpegna, A. Savino, and S. Di Carlo, “Spiker+: A framework for the generation of efficient spiking neural networks FPGA accelerators for inference at the edge,” IEEE Transactions on Emerging Topics in Computing, 2024, early Access. [36] K. R. KM, T. R. Babu, E. Albalawi, M. TR, S. B. Khan, and O. Saidani, “Spiking neural dynamics and federated routing for ultralow-latency in 6G industry 5.0,” Journal of Sensors, vol. 2025, p. 5491672, 2025. [37] H. Huang and Y. Liu, “Attention-aware neuromorphic semantic communications,” in 2024 IEEE 34th International Workshop on Machine Learning for Signal Processing (MLSP). IEEE, 2024, pp. 1–6. [38] M. Wang, J. Li, M. Ma, and X. Fan, “SNN-SC: A spiking semantic communication framework for collaborative intelligence,” IEEE Transactions on Vehicular Technology, vol. 73, no. 9, pp. 12 891–12 906, 2024. [39] K. Svoboda and T. Adegbija, “Spiking neural network architecture search: A survey,” arXiv preprint arXiv:2510.14235, 2025. [40] H. Shao, J. Lu, M. Wang, and Z. Wang, “An efficient training accelerator for Transformers with hardware-algorithm co-optimization,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 31, no. 11, pp. 1788–1801, 2023. [41] I. Aliyev, K. Svoboda, T. Adegbija, and J.-M. Fellous, “Sparsityaware hardware-software co-design of spiking neural networks: An overview,” in 2024 IEEE 17th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC). IEEE, 2024, pp. 413–420. [42] W. Maass, “Networks of spiking neurons: The third generation of neural network models,” Neural Networks, vol. 10, no. 9, pp. 1659– 1671, 1997. [43] W. Maass and H. Markram, “On the computational power of circuits of spiking neurons,” Journal of Computer and System Sciences, vol. 69, no. 4, pp. 593–616, 2004. [44] E. M. Izhikevich, “Which model to use for cortical spiking neurons?” IEEE Transactions on Neural Networks, vol. 15, no. 5, pp. 1063–1070, 2004. [45] A. L. Hodgkin and A. F. Huxley, “A quantitative description of membrane current and its application to conduction and excitation in nerve,” The Journal of Physiology, vol. 117, no. 4, pp. 500–544, 1952. [46] H. Markram, E. Muller, S. Ramaswamy, M. W. Reimann, M. Abdellah, C. A. Sanchez, A. Ailamaki et al., “Reconstruction and simulation of neocortical microcircuitry,” Cell, vol. 163, no. 2, pp. 456–492, 2015. [47] P. Poirazi and A. Papoutsi, “Illuminating dendritic function with computational models,” Nature Reviews Neuroscience, vol. 21, no. 6, pp. 303–321, 2020. [48] W. Gerstner and W. M. Kistler, Spiking neuron models: Single neurons, populations, plasticity. Cambridge University Press, 2002. [49] C. Teeter, R. Iyer, V. Menon, N. Gouwens, D. Feng, J. Berg, A. Szafer et al., “Generalized leaky integrate-and-fire models classify multiple neuron types,” Nature Communications, vol. 9, no. 1, p. 709, 2018. [50] N. Skatchkovsky, H. Jang, and O. Simeone, “Federated neuromorphic learning of spiking neural networks for low-power edge intelligence,” in ICASSP 2020 - 2020 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP). IEEE, 2020, pp. 8524–8528. [51] J. L. Lobo, J. Del Ser, A. Bifet, and N. Kasabov, “Spiking neural networks and online learning: An overview and perspectives,” Neural Networks, vol. 121, pp. 88–100, 2020. [52] E. M. Izhikevich, “Simple model of spiking neurons,” IEEE Transactions on Neural Networks, vol. 14, no. 6, pp. 1569–1572, 2003.
20
[53] R. Brette and W. Gerstner, “Adaptive exponential integrate-and-fire model as an effective description of neuronal activity,” Journal of Neurophysiology, vol. 94, no. 5, pp. 3637–3642, 2005. [54] R. Naud, N. Marcille, C. Clopath, and W. Gerstner, “Firing patterns in the adaptive exponential integrate-and-fire model,” Biological Cybernetics, vol. 99, no. 4-5, pp. 335–347, 2008. [55] R. Jolivet, R. Kobayashi, A. Rauch, R. Naud, S. Shinomoto, and W. Gerstner, “A benchmark test for a quantitative assessment of simple neuron models,” Journal of Neuroscience Methods, vol. 169, no. 2, pp. 417–424, 2008. [56] C. Mead and M. Ismail, Eds., Analog VLSI Implementation of Neural Systems, ser. The Kluwer International Series in Engineering and Computer Science. Boston, MA: Springer, 1989, vol. 80. [57] C. Mead, “Neuromorphic electronic systems,” Proceedings of the IEEE, vol. 78, no. 10, pp. 1629–1636, 1990. [58] G. Indiveri, B. Linares-Barranco, T. J. Hamilton, A. van Schaik, R. Etienne-Cummings, T. Delbruck, S.-C. Liu et al., “Neuromorphic silicon neuron circuits,” Frontiers in Neuroscience, vol. 5, p. 73, 2011. [59] H. Markram, J. Lübke, M. Frotscher, and B. Sakmann, “Regulation of synaptic efficacy by coincidence of postsynaptic APs and EPSPs,” Science, vol. 275, no. 5297, pp. 213–215, 1997. [60] S. Song, K. D. Miller, and L. F. Abbott, “Competitive hebbian learning through spike-timing-dependent synaptic plasticity,” Nature Neuroscience, vol. 3, no. 9, pp. 919–926, 2000. [61] G.-q. Bi and M.-m. Poo, “Synaptic modifications in cultured hippocampal neurons: Dependence on spike timing, synaptic strength, and postsynaptic cell type,” Journal of Neuroscience, vol. 18, no. 24, pp. 10 464–10 472, 1998. [62] E. O. Neftci, H. Mostafa, and F. Zenke, “Surrogate gradient learning in spiking neural networks: Bringing the power of gradient-based optimization to spiking neural networks,” IEEE Signal Processing Magazine, vol. 36, no. 6, pp. 51–63, 2019. [63] B. A. Richards, T. P. Lillicrap, P. Beaudoin, Y. Bengio, R. Bogacz, A. Christensen, C. Clopath et al., “A deep learning framework for neuroscience,” Nature Neuroscience, vol. 22, no. 11, pp. 1761–1770, 2019. [64] A. Tavanaei, M. Ghodrati, S. R. Kheradpisheh, T. Masquelier, and A. Maida, “Deep learning in spiking neural networks,” Neural Networks, vol. 111, pp. 47–63, 2019. [65] K. Roy, A. Jaiswal, and P. Panda, “Towards spike-based machine intelligence with neuromorphic computing,” Nature, vol. 575, no. 7784, pp. 607–617, 2019. [66] Y. Wu, L. Deng, G. Li, J. Zhu, and L. Shi, “Spatio-temporal backpropagation for training high-performance spiking neural networks,” Frontiers in Neuroscience, vol. 12, p. 331, 2018. [67] Y. Li, Y. Guo, S. Zhang, S. Deng, Y. Hai, and S. Gu, “Differentiable spike: Rethinking gradient-descent for training spiking neural networks,” in Advances in Neural Information Processing Systems, vol. 34. Curran Associates, Inc., 2021, pp. 23 426–23 439. [68] G. Bellec, F. Scherr, A. Subramoney, E. Hajek, D. Salaj, R. Legenstein, and W. Maass, “A solution to the learning dilemma for recurrent networks of spiking neurons,” Nature Communications, vol. 11, no. 1, p. 3625, 2020. [69] F. Zenke and S. Ganguli, “SuperSpike: Supervised learning in multilayer spiking neural networks,” Neural Computation, vol. 30, no. 6, pp. 1514–1541, 2018. [70] S. B. Shrestha and G. Orchard, “SLAYER: Spike layer error reassignment in time,” in Advances in Neural Information Processing Systems, vol. 31. Curran Associates, Inc., 2018, pp. 1412–1421. [71] P. A. Merolla, J. V. Arthur, R. Alvarez-Icaza, A. S. Cassidy, J. Sawada, F. Akopyan, B. L. Jackson et al., “A million spiking-neuron integrated circuit with a scalable communication network and interface,” Science, vol. 345, no. 6197, pp. 668–673, 2014. [72] M. Davies, N. Srinivasa, T.-H. Lin, G. Chinya, Y. Cao, S. H. Choday, G. Dimou et al., “Loihi: A neuromorphic manycore processor with on-chip learning,” IEEE Micro, vol. 38, no. 1, pp. 82–99, 2018. [73] J. Pei, L. Deng, S. Song, M. Zhao, Y. Zhang, S. Wu, G. Wang, Z. Zou, Z. Wu, W. He et al., “Towards artificial general intelligence with hybrid tianjic chip architecture,” Nature, vol. 572, no. 7767, pp. 206–211, 2019. [74] S. B. Furber, F. Galluppi, S. Temple, and L. A. Plana, “The SpiNNaker project,” Proceedings of the IEEE, vol. 102, no. 5, pp. 652–665, 2014. [75] K. Yamazaki, V.-K. Vo-Ho, D. Bulsara, and N. Le, “Spiking neural networks and their applications: A review,” Brain Sciences, vol. 12, no. 7, p. 863, 2022.
[76] M. Karamimanesh, E. Abiri, M. Shahsavari, K. Hassanli, A. van Schaik, and J. Eshraghian, “Spiking neural networks on FPGA: A survey of methodologies and recent advancements,” Neural Networks, p. 107256, 2025. [77] C. Iaboni and P. Abichandani, “Event-based spiking neural networks for object detection: A review of datasets, architectures, learning rules, and implementation,” IEEE Access, vol. 12, pp. 180 532–180 596, 2024. [78] R. Brette, M. Rudolph, T. Carnevale, M. Hines, D. Beeman, J. M. Bower, M. Diesmann, A. Morrison, P. H. Goodman, F. C. Harris et al., “Simulation of networks of spiking neurons: A review of tools and strategies,” Journal of Computational Neuroscience, vol. 23, no. 3, pp. 349–398, 2007, discusses the numerical stiffness and high computational cost of conductance-based models. [79] S. Thorpe, A. Delorme, and R. Van Rullen, “Spike-based strategies for rapid processing,” Neural Networks, vol. 14, no. 6-7, pp. 715–725, 2001. [80] J. Gautrais and S. Thorpe, “Rate coding versus temporal order coding: a theoretical approach,” BioSystems, vol. 48, no. 1-3, pp. 57–65, 1998. [81] H. Mostafa, “Supervised learning based on temporal coding in spiking neural networks,” IEEE Transactions on Neural Networks and Learning Systems, vol. 29, no. 7, pp. 3227–3235, 2018. [82] D. Auge, J. Hille, E. Mueller, and A. Knoll, “A survey of encoding techniques for signal processing in spiking neural networks,” Neural Processing Letters, vol. 53, no. 6, pp. 4693–4710, 2021. [83] K. Malcolm and J. Casco-Rodriguez, “A comprehensive review of spiking neural networks: Interpretation, optimization, efficiency, and best practices,” arXiv preprint arXiv:2303.10780, 2023. [84] Y. Liang, W. Wei, A. Belatreche, H. Cao, Z. Zhou, S. Wang, M. Zhang, and Y. Yang, “Towards accurate binary spiking neural networks: Learning with adaptive gradient modulation mechanism,” in Proceedings of the AAAI Conference on Artificial Intelligence, vol. 39, no. 2, 2025, pp. 1402–1410. [85] W. Guo, M. E. Fouda, A. M. Eltawil, and K. N. Salama, “Neural coding in spiking neural networks: A comparative study for robust neuromorphic systems,” Frontiers in Neuroscience, vol. 15, p. 638474, 2021. [86] S. H. Jo, T. Chang, I. Ebong, B. B. Bhadviya, P. Mazumder, and W. Lu, “Nanoscale memristor device as synapse in neuromorphic systems,” Nano Letters, vol. 10, no. 4, pp. 1297–1301, 2010. [87] C. Frenkel, “Bottom-up and top-down neuromorphic processor design: Unveiling roads to embedded cognition,” Ph.D. dissertation, Université catholique de Louvain, Louvain-la-Neuve, Belgium, 2020. [88] J. Gygax and F. Zenke, “Elucidating the theoretical underpinnings of surrogate gradient learning in spiking neural networks,” Neural Computation, vol. 37, no. 5, pp. 886–925, 2025. [89] B. Huo, F. Li, S. Peng, H. Chen, S. Xin, and H. Wang, “Research on snn learning algorithms and networks based on biological plausibility,” IEEE Access, vol. 13, pp. 95 243–95 256, 2025. [90] W. Wei, M. Zhang, J. Zhang, A. Belatreche, J. Wu, Z. Xu, X. Qiu, H. Chen, Y. Yang, and H. Li, “Event-driven learning for spiking neural networks,” arXiv preprint arXiv:2403.00270, 2024. [91] H. Esmaeilzadeh, E. Blem, R. St. Amant, K. Sankaralingam, and D. Burger, “Dark silicon and the end of multicore scaling,” in Proceedings of the 38th annual international symposium on Computer architecture, 2011, pp. 365–376. [92] M. B. Taylor, “Is dark silicon useful? harnessing the four horsemen of the coming dark silicon apocalypse,” in Proceedings of the 49th annual design automation conference, 2012, pp. 1131–1136. [93] N. Hardavellas, M. Ferdman, B. Falsafi, and A. Ailamaki, “Toward dark silicon in servers,” IEEE Micro, vol. 31, no. 4, pp. 6–15, 2011. [94] M. Shafique, S. Garg, J. Henkel, and D. Marculescu, “The eda challenges in the dark silicon era: Temperature, reliability, and variability perspectives,” in Proceedings of the 51st Annual Design Automation Conference, 2014, pp. 1–6. [95] M. Davies, A. Wild, G. Orchard, Y. Sandamirskaya, G. A. F. Guerra, P. Joshi, P. Plank, and S. R. Risbud, “Advancing neuromorphic computing with Loihi: A survey of results and outlook,” Proceedings of the IEEE, vol. 109, no. 5, pp. 911–934, 2021. [96] N. Rathi and K. Roy, “Diet-snn: A low-latency spiking neural network with direct input encoding and leakage and threshold optimization,” IEEE Transactions on Neural Networks and Learning Systems, vol. 34, no. 6, pp. 3174–3182, 2023. [97] G. Gallego, T. Delbrück, G. Orchard, C. Bartolozzi, B. Taba, A. Censi, S. Leutenegger et al., “Event-based vision: A survey,” IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 44, no. 1, pp. 154–180, 2022.
21
[98] S. H. Ahmed, J. Finkbeiner, and E. Neftci, “Efficient event-based object detection: A hybrid neural network with spatial and temporal attention,” in Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR), June 2025, pp. 13 970–13 979. [99] M. Horowitz, “1.1 computing’s energy problem (and what we can do about it),” in 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC). IEEE, 2014, pp. 10–14. [100] J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital integrated circuits. Prentice Hall Englewood Cliffs, 2002, vol. 2. [101] D. S. Modha, F. Akopyan, A. Andreopoulos, R. Appuswamy, J. V. Arthur, A. S. Cassidy, P. Datta et al., “Neural inference at the frontier of energy, space, and time,” Science, vol. 382, no. 6668, pp. 329–335, 2023. [102] Y. Wu, L. Deng, G. Li, J. Zhu, and L. Shi, “Direct training for spiking neural networks: Faster, larger, and better,” Proceedings of the AAAI Conference on Artificial Intelligence, vol. 33, no. 01, pp. 1311–1318, 2019. [103] H. Zheng, Y. Wu, L. Deng, Y. Hu, and G. Li, “Going deeper with directly-trained larger spiking neural networks,” in Proceedings of the AAAI Conference on Artificial Intelligence, vol. 35, no. 12, 2021, pp. 11 062–11 070. [104] J. Ding, Z. Yu, Y. Tian, and T. Huang, “Optimal ann-snn conversion for fast and accurate inference in deep spiking neural networks,” arXiv preprint arXiv:2105.11654, 2021. [105] T. Bu, M. Li, and Z. Yu, “Inference-scale complexity in ann-snn conversion for high-performance and low-power applications,” in Proceedings of the Computer Vision and Pattern Recognition Conference, 2025, pp. 24 387–24 397. [106] X. Song, A. Song, R. Xiao, and Y. Sun, “One-step spiking transformer with a linear complexity,” in Proceedings of the Thirty-Third International Joint Conference on Artificial Intelligence, 2024, pp. 3142–3150. [107] Z. Hao, Z. Yu, and T. Huang, “Faster and stronger: When ANNSNN conversion meets parallel spiking calculation,” arXiv preprint arXiv:2412.13610, 2024. [108] D. Yu, C. Lv, X. Du, L. Jiang, W. Tong, Z. Liao, X. Zheng, and S. Deng, “Ecc-snn: Cost-effective edge-cloud collaboration for spiking neural networks,” in Proceedings of the Thirty-Fourth International Joint Conference on Artificial Intelligence (IJCAI-25), J. Kwok, Ed. International Joint Conferences on Artificial Intelligence Organization, Aug. 2025, pp. 6904–6912. [109] J. Seekings, P. Chandarana, M. Ardakani, M. Mohammadi, and R. Zand, “Towards efficient deployment of hybrid SNNs on neuromorphic and edge AI hardware,” in 2024 International Conference on Neuromorphic Systems (ICONS). IEEE, 2024, pp. 71–77. [110] F. Rivelli, M. Popov, C. S. Kouzinopoulos, and G. Tang, “Adaptively pruned spiking neural networks for energy-efficient intracortical neural decoding,” arXiv preprint arXiv:2504.11568, 2025. [111] L. Shi, A. Li, and B. Ward-Cherrier, “Optimal spiking brain compression: Improving one-shot post-training pruning and quantization for spiking neural networks,” arXiv preprint arXiv:2506.03996, Jun. 2025. [112] B. Na, J. Mok, S. Park, D. Lee, H. Choe, and S. Yoon, “Autosnn: Towards energy-efficient spiking neural networks,” in International conference on machine learning. PMLR, 2022, pp. 16 253–16 269. [113] Y. Kim, Y. Li, H. Park, Y. Venkatesha, and P. Panda, “Neural architecture search for spiking neural networks,” in European conference on computer vision. Springer, 2022, pp. 36–56. [114] K. Che, L. Leng, K. Zhang, J. Zhang, and J. Cheng, “Differentiable hierarchical and surrogate gradient search for spiking neural networks,” in Advances in Neural Information Processing Systems (NeurIPS), vol. 35, 2022, pp. 24 975–24 990. [115] J. Yik, Z. Ahmed, and A. G. Anderson, “Neuroevolutionary learning for hardware-aware spiking neural networks,” IEEE Transactions on Pattern Analysis and Machine Intelligence (TPAMI), vol. 46, no. 5, pp. 2845–2858, 2024. [116] S. Li, L. Chen, Y. Zhang, Z. Zhang, A. Du, B. Pan, Z. Wang, L. Wen, and W. Zhao, “QUEST: A quantized energy-aware SNN training framework for multi-state neuromorphic devices,” arXiv preprint arXiv:2504.00679, 2025. [117] R. V. W. Putra, A. Marchisio, and M. Shafique, “SNN4Agents: A framework for developing energy-efficient embodied spiking neural networks for autonomous agents,” Frontiers in Robotics and AI, vol. 11, p. 1401677, 2024. [118] Intel Labs, “Intel builds world’s largest neuromorphic system to enable more sustainable ai,” 2024, press Release. Available at: https://www.intel.com/. [119] D. Ma, X. Jin, S. Sun, Y. Li, X. Wu, Y. Hu, F. Yang, H. Tang, and G. Pan, “Darwin3: A large-scale neuromorphic chip with a novel isa
and on-chip learning,” National Science Review, vol. 11, no. 5, p. nwae102, 2024. [120] BrainChip Holdings Ltd, “Akida neural processor ip technical reference manual,” 2024, available at: https://brainchip.com/akida-neuralprocessor-soc/. [121] C. Mayr, S. Hoeppner, and S. Furber, “Spinnaker 2: A 10 million core processor system for brain simulation and machine learning-keynote presentation,” in Communicating Process Architectures 2017 & 2018. IOS Press, 2019, pp. 277–280. [122] G. Orchard, E. P. Frady, D. B. D. Rubin, S. Sanborn, S. B. Shrestha, F. T. Sommer, and M. Davies, “Efficient neuromorphic signal processing with loihi 2,” in 2021 IEEE Workshop on Signal Processing Systems (SiPS). IEEE, 2021, pp. 254–259. [123] F. Akopyan, J. Sawada, A. Cassidy, R. Alvarez-Icaza, J. Arthur, P. Merolla, N. Imam, Y. Nakamura, P. Datta, G.-J. Nam et al., “Truenorth: Design and tool flow of a 65 mw 1 million neuron programmable neurosynaptic chip,” IEEE transactions on computeraided design of integrated circuits and systems, vol. 34, no. 10, pp. 1537–1557, 2015. [124] P. Yao, H. Wu, B. Gao, J. Tang, Q. Zhang, W. Zhang, J. J. Yang, and H. Qian, “Fully hardware-implemented memristor convolutional neural network,” Nature, vol. 577, no. 7792, pp. 641–646, 2020. [125] D. Zhao, Y. Li, Y. Zeng, J. Wang, and Q. Zhang, “Spiking capsnet: A spiking neural network with a biologically plausible routing rule between capsules,” Information Sciences, vol. 610, pp. 1–13, 2022. [126] D. V. Christensen, R. Dittmann, B. Linares-Barranco, A. Sebastian, M. Le Gallo, A. Redaelli, S. Slesazeck, T. Mikolajick, S. Spiga, S. Menzel et al., “2022 roadmap on neuromorphic computing and engineering,” Neuromorphic Computing and Engineering, vol. 2, no. 2, p. 022501, 2022. [127] D. Ma, J. Shen, Z. Gu, M. Zhang, X. Zhu, Q. Xu, Q. Shen, and G. Pan, “Darwin: A neuromorphic hardware co-processor based on spiking neural networks,” Journal of Systems Architecture, vol. 77, pp. 43–51, 2017. [128] C. Pehle, S. Billaudelle, B. Cramer, J. Kaiser, K. Schreiber, Y. Stradmann, J. Weis, A. Leibfried, E. Müller, and J. Schemmel, “The brainscales-2 accelerated neuromorphic system with hybrid plasticity,” Frontiers in Neuroscience, vol. 16, p. 795876, 2022. [129] L. Chen, X. Xiong, and J. Liu, “A survey of intelligent chip design research based on spiking neural networks,” IEEE Access, vol. 10, pp. 89 663–89 686, 2022. [130] A. Li, Y. Liu, and R. Kastner, “S2n2: A fpga accelerator for streaming spiking neural networks,” in Proceedings of the 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2021, pp. 1–11. [131] S. Panchapakesan, Z. Fang, and J. Li, “Syncnn: Evaluating and accelerating spiking neural networks on fpgas,” in 2021 31st International Conference on Field-Programmable Logic and Applications (FPL), 2021, pp. 286–293. [132] L. Kang and X. Yang, “A 24.3 µj/image snn accelerator for dvsgesture with ws-los dataflow and sparse methods,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 10, pp. 3802– 3806, 2023. [133] J. Li et al., “Firefly v2: Advancing hardware support for highperformance spiking neural network with a spatiotemporal fpga accelerator,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 43, no. 9, pp. 1–14, 2024. [134] B. Xu et al., “Spikex: Exploring accelerator architecture and networkhardware co-optimization for sparse spiking neural networks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025, (Early Access / arXiv:2505.12292). [135] A. Balaji, A. Das, Y. Wu, K. Huynh, F. G. Dell’Anna, G. Indiveri, J. L. Krichmar, N. D. Dutt, S. Schaafsma, and F. Catthoor, “Mapping spiking neural networks to neuromorphic hardware,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 1, pp. 76–86, 2019. [136] G. Urgese, F. Barchi, E. Macii, and A. Acquaviva, “Optimizing network traffic for spiking neural network simulations on densely interconnected many-core neuromorphic platforms,” IEEE Transactions on Emerging Topics in Computing, vol. 6, no. 3, pp. 317–329, 2016. [137] J. Xue, L. Xie, F. Chen, L. Wu, Q. Tian, Y. Zhou, R. Ying, and P. Liu, “EdgeMap: An optimized mapping toolchain for spiking neural network in edge computing,” Sensors, vol. 23, no. 14, p. 6548, 2023. [138] C. Xiao, J. Chen, and L. Wang, “Optimal mapping of spiking neural network to neuromorphic hardware for Edge-AI,” Sensors, vol. 22, no. 19, p. 7248, 2022.
22
[139] W. G. Gomez, A. Pignata, R. Pignari, V. Fra, E. Macii, and G. Urgese, “First steps towards micro-benchmarking the Lava-Loihi neuromorphic ecosystem,” in 2023 IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), 2023, pp. 462–469. [140] T. Bekolay, J. Bergstra, E. Hunsberger et al., “Nengo: a python tool for building large-scale functional brain models,” Frontiers in Neuroinformatics, vol. 7, p. 48, 2014. [141] H. Hazan, D. J. Saunders, H. Khan et al., “Bindsnet: A machine learning-oriented spiking neural networks library in python,” Frontiers in Neuroinformatics, vol. 12, p. 89, 2018. [142] M. Stimberg, R. Brette, and D. F. Goodman, “Brian 2, an intuitive and efficient neural simulator,” eLife, vol. 8, p. e47314, 2019. [143] S. R. Kulkarni, M. Parsa, J. P. Mitchell, and C. D. Schuman, “Benchmarking the performance of neuromorphic and spiking neural network simulators,” Neurocomputing, vol. 447, pp. 145–160, 2021. [144] D. L. Manna, A. Vicente-Sola, P. Kirkland, T. J. Bihl, and G. Di Caterina, “Frameworks for snns: a review of data science-oriented software and an expansion of spyketorch,” in International Conference on Engineering Applications of Neural Networks. Springer, 2023, pp. 227–238. [145] S. Al Abdul Wahid, A. Asad, and F. Mohammadi, “A survey on neuromorphic architectures for running artificial intelligence algorithms,” Electronics, vol. 13, no. 15, p. 2963, 2024. [146] Y.-C. Cheng, W.-X. Hu, Y.-L. He, and J. Z. Huang, “A comprehensive multimodal benchmark of neuromorphic training frameworks for spiking neural networks,” Engineering Applications of Artificial Intelligence, vol. 159, p. 111543, 2025. [147] H. Gupta, A. Vahid Dastjerdi, S. K. Ghosh, and R. Buyya, “ifogsim: A toolkit for modeling and simulation of resource management techniques in the internet of things, edge and fog computing environments,” Software: Practice and Experience, vol. 47, no. 9, pp. 1275–1296, 2017. [148] S. Tuli, R. Mahmud, S. Tuli, and R. Buyya, “Fogbus: A blockchainbased lightweight framework for edge and fog computing,” Journal of Systems and Software, vol. 154, pp. 22–36, 2019. [149] D. Yu, X. Du, L. Jiang, and Y. Li, “FedLEC: Effective federated learning algorithm with spiking neural networks under label skews,” arXiv preprint arXiv:2404.14488, 2024. [150] M. Abbasihafshejani, A. Maiti, and M. Jadliwala, “Spiking neural networks in vertical federated learning: Performance trade-offs,” in NOMS 2025-2025 IEEE Network Operations and Management Symposium. IEEE, 2025, pp. 1–5. [151] D. Aksu, J. M. del Rincon, and I. Alouani, “Privacy in federated learning with spiking neural networks,” arXiv preprint arXiv:2511.21181, 2025. [152] M. V. Nguyen, L. Zhao, B. Deng, and S. Wu, “Sparsified federated learning with spiking neural networks: Resistance against byzantine attacks while lowering communication traffics,” in 2025 IEEE 101st Vehicular Technology Conference (VTC2025-Spring). IEEE, 2025, pp. 1–5. [153] Z. Li, Y. Ma, J. Zhou, and P. Zhou, “Spiking-nerf: Spiking neural network for energy-efficient neural rendering,” J. Emerg. Technol. Comput. Syst., vol. 20, no. 3, Aug. 2024. [154] L. Shi, A. Li, and B. Ward-Cherrier, “Spiking brain compression: Exploring one-shot post-training pruning and quantization for spiking neural networks,” in OPT2025: 17th Annual Workshop on Optimization for Machine Learning, 2025, arXiv:2506.03996. [155] S. Hussaini, M. Milford, and T. Fischer, “Applications of spiking neural networks in visual place recognition,” IEEE Transactions on Robotics, vol. 41, pp. 518–537, 2025. [156] N. Zheng and H. Xia, “SNN-driven multimodal human action recognition via event camera and skeleton data fusion,” arXiv preprint arXiv:2502.13385, 2025. [157] R. V. W. Putra, P. Wickramasinghe, and M. Shafique, “Enabling efficient processing of spiking neural networks with on-chip learning on commodity neuromorphic processors for edge AI systems,” arXiv preprint arXiv:2504.00957, 2025. [158] M. Hizem, L. Bousbia, Y. Ben Dhiab, M. O.-E. Aoueileyine, and R. Bouallegue, “Reliable ECG anomaly detection on edge devices for Internet of Medical Things applications,” Sensors, vol. 25, no. 8, p. 2496, 2025. [159] D. Zhou, W. Chen, K. Chen, and B. Mi, “Fast and accurate SNN model strengthening for industrial applications,” Electronics, vol. 12, no. 18, p. 3845, 2023. [160] H. Wang, Y.-F. Li, and K. Gryllias, “Brain-inspired spiking neural networks for industrial fault diagnosis: A survey, challenges, and opportunities,” arXiv preprint arXiv:2401.02429, 2023.
[161] L. Zhu, S. Dong, T. Huang, and Y. Tian, “Ultra-high temporal resolution visual reconstruction from a fovea-like spike camera,” IEEE Transactions on Pattern Analysis and Machine Intelligence (TPAMI), vol. 44, no. 11, pp. 7785–7799, 2022. [162] S. Dong, L. Zhu, D. Duan, T. Huang, and Y. Tian, “Spike cameras: A review,” arXiv preprint arXiv:2401.13490, 2024. [163] Y. Hu, Q. Zheng, and G. Pan, “Bitsnns: revisiting energy-efficient spiking neural networks,” IEEE Transactions on Cognitive and Developmental Systems, vol. 16, no. 5, pp. 1736–1747, 2024. [164] X. Shi, J. Ding, Z. Hao, and Z. Yu, “Towards energy efficient spiking neural networks: An unstructured pruning framework,” in The Twelfth International Conference on Learning Representations, 2024. [165] V. Sudevan, F. Zayer, R. Kausar, S. Javed, H. Karki, G. De Masi, and J. Dias, “Underwater image enhancement by convolutional spiking neural networks,” arXiv preprint arXiv:2503.20485, 2025. [166] A. Amir, B. Taba, D. Berg, T. Melano, J. McKinstry, C. Di Nolfo, T. Nayak, A. Andreopoulos, G. Garreau, M. Mendoza et al., “A low power, fully event-based gesture recognition system,” in Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition (CVPR), 2017, pp. 7243–7252. [167] H. Sabbella, A. Mukherjee, T. Kandappu, S. Dey, A. Pal, A. Misra, and D. Ma, “The promise of spiking neural networks for ubiquitous computing: A survey and new perspectives,” arXiv preprint arXiv:2506.01737, 2025. [168] P. Blouw, X. Choo, E. Hunsberger, and C. Eliasmith, “Benchmarking keyword spotting efficiency on neuromorphic hardware,” in Proceedings of the 7th annual neuro-inspired computational elements workshop, 2019, pp. 1–8. [169] B. Yin, F. Corradi, and S. M. Bohté, “Accurate and efficient timedomain classification with adaptive spiking recurrent neural networks,” Nature Machine Intelligence, vol. 3, no. 10, pp. 905–913, 2021. [170] S. Baek and J. Lee, “SNN and sound: A comprehensive review of spiking neural networks in sound,” Biomedical Engineering Letters, vol. 14, no. 5, pp. 981–991, 2024. [171] S. Y. A. Yarga and S. U. Wood, “Neuromorphic keyword spotting with pulse density modulation mems microphones,” arXiv preprint arXiv:2408.05156, 2024. [172] N. Imam and T. A. Cleland, “Rapid online learning and robust recall in a neuromorphic olfactory circuit,” Nature Machine Intelligence, vol. 2, no. 3, pp. 181–191, 2020. [173] J. Guo, X. Li, X. Li, Z. Liang, J. Cao, and X. Wei, “Anti-drift gas detection algorithm based on neural network,” IEEE Transactions on Instrumentation and Measurement, 2024. [174] A. Mompó Alepuz, D. Papageorgiou, and S. Tolu, “Brain-inspired biomimetic robot control: a review,” Frontiers in Neurorobotics, vol. 18, p. 1395617, 2024. [175] Z. Bing, C. Meschede, F. Röhrbein, K. Huang, and A. C. Knoll, “A survey of robotics control based on learning-inspired spiking neural networks,” Frontiers in neurorobotics, vol. 12, p. 35, 2018. [176] H. Choi, J. Park, J. Lee, and D. Sim, “Review on spiking neural network-based ECG classification methods for low-power environments,” Biomedical Engineering Letters, vol. 14, no. 5, pp. 917–941, 2024. [177] S. H. Choi, “Spiking neural networks for biomedical signal analysis,” Biomedical Engineering Letters, vol. 14, no. 5, pp. 955–966, 2024. [178] Y. Xing, L. Zhang, Z. Hou, X. Li, Y. Shi, Y. Yuan, F. Zhang, S. Liang, Z. Li, and L. Yan, “Accurate ecg classification based on spiking neural network and attentional mechanism for real-time implementation on personal portable devices,” Electronics, vol. 11, no. 12, p. 1889, 2022. [179] A. Alzarooni, E. Iqbal, S. U. Khan, S. Javed, B. Moyo, and Y. Abdulrahman, “Anomaly detection for industrial applications, its challenges, solutions, and future directions: A review,” arXiv preprint arXiv:2501.11310, 2025. [180] S. H. H. DolatAbadi, S. M. H. Hashemi, M. Hosseini, and M.-A. AliHosseini, “Revolutionizing traffic management with AIPowered machine vision: A step toward smart cities,” arXiv preprint arXiv:2503.02967, 2025. [181] O. K. Pal, M. S. H. Shovon, M. F. Mridha, and J. Shin, “A comprehensive review of AI-enabled unmanned aerial vehicle: Trends, vision, and challenges,” arXiv preprint arXiv:2310.16360, 2023. [182] R. Wolniak and K. Stecuła, “Artificial intelligence in smart cities—applications, barriers, and future directions: A review,” Smart Cities, vol. 7, no. 3, pp. 1346–1389, 2024. [183] A. d. J. Pugliese Viloria, A. Folini, D. Carrion, and M. A. Brovelli, “Hazard susceptibility mapping with machine and deep learning: A literature review,” Remote Sensing, vol. 16, no. 18, p. 3374, 2024.
23
[184] J. Jiang, L. Wang, R. Jiang, J. Fan, and R. Yan, “Adaptive gradient learning for spiking neural networks by exploiting membrane potential dynamics,” arXiv preprint arXiv:2505.11863, 2025. [185] K. Yu, T. Zhang, Q. Xu, G. Pan, and H. Wang, “TS-SNN: Temporal shift module for spiking neural networks,” arXiv preprint arXiv:2505.04165, 2025. [186] W. Maass, “To spike or not to spike: That is the question,” Proceedings of the IEEE, vol. 103, no. 12, pp. 2219–2224, 2015. [187] M. Schmolli, M. Baronig, R. Legenstein, and O. Ozdenizci, “Adversarially robust spiking neural networks with sparse connectivity,” in Proceedings of the Conference on Parsimony and Learning (CPAL), ser. Proceedings of Machine Learning Research, B. Chen, S. Liu, M. Pilanci, W. Su, J. Sulam, Y. Wang, and Z. Zhu, Eds., vol. 280. PMLR, Mar. 2025, pp. 865–883. [188] C. D. Schuman, T. E. Potok, R. M. Patton, J. D. Birdwell, M. E. Dean, G. S. Rose, and J. S. Plank, “A survey of neuromorphic computing and neural networks in hardware,” arXiv preprint arXiv:1705.06963, 2017. [189] D. Le, B. Arig, M. Isik, I. C. Dikmen, and T. Karadag, “A review of memory wall for neuromorphic computing,” in 2025 IEEE 4th International Conference on Computing and Machine Intelligence (ICMI). IEEE, 2025, pp. 1–6. [190] M. Hellenbrand, I. Teck, and J. L. MacManus-Driscoll, “Progress of emerging non-volatile memory technologies in industry,” MRS communications, vol. 14, no. 6, pp. 1099–1112, 2024. [191] J. Pan, Z. Wang, B. Zhao, J. Yin, P. Guo, Y. Yang, and T.-L. Ren, “Recent progress of non-volatile memory devices based on twodimensional materials,” Chips, vol. 3, no. 4, pp. 271–295, 2024. [192] B. Vogginger, A. Rostami, V. Jain, S. Arfa, A. Hantsch, D. Kappel, M. Schäfer, U. Faltings, H. A. Gonzalez, C. Liu et al., “Neuromorphic hardware for sustainable AI data centers,” arXiv preprint arXiv:2402.02521, 2024. [193] L. Liang, X. Hu, L. Deng, Y. Wu, G. Li, Y. Ding, P. Li, and Y. Xie, “Exploring adversarial attack in spiking neural networks with spikecompatible gradient,” IEEE Transactions on Neural Networks and Learning Systems (TNNLS), vol. 34, no. 5, pp. 2569–2583, 2023. [194] B. K. Baghbaderani and H. Shahinzadeh, “Adversarial attacks and defense mechanisms in spiking neural networks: A comprehensive review,” in 2025 29th International Computer Conference, Computer Society of Iran (CSICC). IEEE, 2025, pp. 01–07. [195] A. Ghosh and S. Ghosh, “Invited paper: Toward secure in-sensor intelligence: Threats and defenses in snns,” in 2025 IEEE/ACM International Conference On Computer-Aided Design (ICCAD), 2025, pp. 1–7. [196] Q. Huang, Z. Yang, K. Ni, M. Imani, C. Zhuo, S. Yu, and F. Koushanfar, “Neural network structure through remote fpga side-channel analysis,” IEEE Transactions on Information Forensics and Security (TIFS), vol. 16, pp. 4377–4388, 2021. [197] N. Rathi, I. Chakraborty, A. Kosta, A. Sengupta, A. Ankit, P. Panda, and K. Roy, “Exploring neuromorphic computing based on spiking neural networks: Algorithms to hardware,” ACM Computing Surveys, vol. 55, no. 12, Mar. 2023. [198] A. Aydin, M. Gehrig, D. Gehrig, and D. Scaramuzza, “A hybrid ANNSNN architecture for low-power and low-latency visual perception,” in Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR), 2024, pp. 5701–5711. [199] G. S. Syed, M. Le Gallo, and A. Sebastian, “Phase-change memory for in-memory computing,” Chemical Reviews, 2025. [200] X. Wang, Y. Zhu, Z. Zhou, X. Chen, and X. Jia, “Memristor-based spiking neuromorphic systems toward brain-inspired perception and computing,” Nanomaterials, vol. 15, no. 14, p. 1130, 2025. [201] S. Yu, “Neuro-inspired computing with emerging nonvolatile memorys,” Proceedings of the IEEE, vol. 106, no. 2, pp. 260–285, 2018. [202] J. Seekings, M. Ardakani, P. Chandarana, A. Eslami, M. Mohammadi, and R. Zand, “Integrated algorithm and hardware design for hybrid neuromorphic systems,” npj Unconventional Computing, vol. 2, no. 1, p. 20, Aug. 2025. [203] E. Müller, E. Arnold, O. Breitwieser, M. Czierlinski, A. Emmel, J. Kaiser, C. Mauch, S. Schmitt, P. Spilger, R. Stock et al., “A scalable approach to modeling on accelerated neuromorphic hardware,” Frontiers in neuroscience, vol. 16, p. 884128, 2022. [204] G. Wang, S. Ma, Y. Wu, J. Pei, R. Zhao, and L. Shi, “End-to-end implementation of various hybrid neural networks on a cross-paradigm neuromorphic chip,” Frontiers in neuroscience, vol. 15, p. 615279, 2021. [205] Y. Xue, Y. Liu, L. Nai, and J. Huang, “Hardware-assisted virtualization of neural processing units for cloud platforms,” in 2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 2024, pp. 1–16.
[206] A. Beloglazov, J. Abawajy, and R. Buyya, “Energy-aware resource allocation heuristics for efficient management of data centers for cloud computing,” Future generation computer systems, vol. 28, no. 5, pp. 755–768, 2012. [207] A. Shrestha, H. Fang, Z. Mei, D. P. Rider, Q. Wu, and Q. Qiu, “A survey on neuromorphic computing: Models and hardware,” IEEE Circuits and Systems Magazine, vol. 22, no. 2, pp. 6–35, 2022. [208] E. Zeydan, C. D. Alwis, R. Khan, Y. Turk, A. Aydeger, T. R. Gadekallu, and M. Liyanage, “Quantum technologies for beyond 5g and 6g networks: Applications, opportunities, and challenges,” IEEE Open Journal of the Communications Society, vol. 6, pp. 6383–6420, 2025. [209] L. Barbieri, A. Menina, R. Bassoli, and F. H. Fitzek, “The security of quantum computing in 6G: From technical perspectives to ethical implications,” arXiv preprint arXiv:2504.10040, 2025. [210] C.-X. Wang, X. You, X. Gao, X. Zhu, Z. Li, C. Zhang, H. Wang, Y. Huang, Y. Chen, H. Haas, J. S. Thompson, E. G. Larsson, M. D. Renzo, W. Tong, P. Zhu, X. Shen, H. V. Poor, and L. Hanzo, “On the road to 6G: Visions, requirements, key technologies, and testbeds,” IEEE Communications Surveys & Tutorials, vol. 25, no. 2, pp. 905– 974, 2023. [211] B. Narottama, Z. Mohamed, and S. Aı̈ssa, “Quantum machine learning for Next-G wireless communications: Fundamentals and the path ahead,” IEEE Open Journal of the Communications Society, vol. 4, pp. 2204–2224, 2023. [212] X. Wang, Z. Tang, J. Guo, T. Meng, C. Wang, T. Wang, and W. Jia, “Empowering edge intelligence: A comprehensive survey on on-device AI models,” ACM Computing Surveys, vol. 57, no. 9, pp. 1–39, 2025.