PuDGhost: Experimental Analysis of Computation Result Corruption in Processing-using-DRAM Operations on Real DRAM Chips and Implications for Future Systems

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PuDGhost: Experimental Analysis of Computation Result Corruption in Processing-using-DRAM Operations on Real DRAM Chips and Implications for Future Systems

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PuDGhost: Experimental Analysis of Computation Result Corruption in Processing-using-DRAM Operations on Real DRAM Chips and Implications for Future Systems

arXiv:2606.19119v1 [cs.AR] 17 Jun 2026

Daichi Tokuda1 İsmail Emir Yüksel2 Tatsuya Kubo1,4 Ataberk Olgun2 Haocong Luo2 Nisa Bostanci2 Jikun Wang2 A. Giray Yağlıkçı3 Shinya Takamaeda-Yamazaki1,4 Onur Mutlu2 1 The University of Tokyo 2 ETH Zurich 3 CISPA 4 RIKEN Processing-using-DRAM (PuD) is a promising computation paradigm to alleviate the frequent data movement between main memory and processing units. The PuD paradigm provides a substrate for highly parallel computation by using each DRAM column as a computation engine via simultaneous multiple-row activation (SiMRA). Unfortunately, DRAM density scaling might hinder PuD’s benefits. This is because denser cell arrays bring rows and columns closer, making even regular DRAM operations susceptible to noise and interference from neighboring cells. PuD repurposes DRAM from a storage device into a parallel computing substrate, yet no prior work investigates whether interference from rows or columns that are not intended to participate in the computation can compromise PuD robustness. In this work, we reveal an interference phenomenon affecting PuD computations, which we call PuDGhost, where a PuD operation in a given column produces erroneous results due to interference from 1) data stored in non-activated DRAM rows and 2) data stored in other columns that perform computations concurrently under the same SiMRA operation. PuDGhost violates the ideal picture of PuD computations, where each column’s computation should depend solely on its own operand data. Thus, PuDGhost threatens the robustness of future PuD systems. We present the first extensive characterization of PuDGhost using 96 real DDR4 DRAM chips from 12 modules, systematically quantifying the impact of these two interference sources under various conditions (i.e., data patterns, temperature, and spatial properties). Among our 15 new empirical observations, we highlight two major results: 1) data in physically adjacent non-activated rows affects SiMRA outputs by up to 10% for random inputs, and 2) data in columns that perform computations concurrently affects SiMRA outputs by up to 48% for random inputs. Guided by these findings, we propose countermeasures against PuDGhost across multiple layers of the PuD computing stack (i.e., microarchitectural, architectural, and system levels). Specifically, we propose and evaluate on real DDR4 DRAM chips: 1) robust column screening that reduces the risk of mistakenly using unreliable columns in the presence of PuDGhost, and 2) a compute row layout that mitigates PuDGhost via dedicated rows between compute rows. Our solutions greatly improve PuD computation accuracy. We hope that our findings provide a foundation for developing solutions to enable future PuD systems that are robust.

1. Introduction Data movement between main memory (DRAM) and processors has become a major bottleneck, consuming a large share of execution time and energy in many real workloads [1– 21]. Processing-using-DRAM (PuD) [21–71] is a promising paradigm that can alleviate this bottleneck by leveraging the

existing operational principles of DRAM to realize massively parallel computation within DRAM. Prior work demonstrates the potential of this approach to substantially improve throughput and energy efficiency compared to conventional systems for a wide range of applications, including databases, web search, data analytics, graph processing, genome analysis, cryptography, optimization solvers, hyperdimensional computing, and LLMs [26, 33, 35, 37, 38, 40–42, 48, 49, 51, 55–59, 61, 72–75]. The core computational capability of various PuD architectures relies on Simultaneous Multiple-Row Activation (SiMRA), a DRAM operation that simultaneously activates multiple DRAM rows within a subarray [23, 26, 33, 38, 40–43, 46–48, 50– 52,54–58,61,63,64,67,68,76]. Figure 1a shows how performing SiMRA across the cells of simultaneously activated DRAM rows (R1, R2, and R3) results in a majority operation (MAJX) to be computed on the values stored in the multiple simultaneously activated DRAM cells in two DRAM columns (C0 and C1) in three key steps. First, the MAJX input operands are initialized ( 1 ). Second, the SiMRA operation starts, enabling charge sharing among activated DRAM rows and columns ( 2 ). Third, the sense amplifier (SA in Figure 1a) kicks in and samples the MAJX result ( 3 ) based on its operational principles (see 2.2). Depends Solely on Operands C0

Assumes Isolation of Each Computation

Correct Outputs

Violates Isolation of Each Computation

Interference from

1 Non-Activated Rows 2 Other Columns C1

Erroneous Outputs

R3 SA

Operands Operands for C0 for C1

1 Initial State

Charge Sharing & 2 Amplification

3 Restoration

(a) Ideal MAJ3

1 Initial State

Charge Sharing & Amplification

3 Restoration

(b) MAJ3 under PuDGhost

Figure 1: (a) Ideal MAJ3. (b) MAJ3 under PuDGhost.

Ideally, as illustrated in Figure 1a, the MAJX result in each DRAM column is determined solely by the activated cells used as operands. With each column performing its own MAJX, each one of the many (e.g., 65536) DRAM columns acts as a computing unit, enabling the massive parallelism of PuD. We hypothesize that this ideal picture of PuD computations might be challenged by ongoing DRAM density scaling. With rapid DRAM scaling and denser cell arrays, even regular DRAM operations can become susceptible to noise and interference from neighboring cells, violating memory isolation (i.e., memory access to one location should not affect data stored in other memory locations) [77–167]. Prior work [78, 81–84, 86] demonstrates that accessing one DRAM location can corrupt data in other locations, even in systems where DRAM is used

solely as a storage device. As PuD repurposes DRAM from a storage device to a computation device, the notion of isolation should extend beyond between memory accesses to each computation (i.e., a computation’s result should not be affected by data that is not intended to participate in the computation). Unfortunately, to our knowledge, no prior work investigates the impact of interference from rows or columns that are not intended to participate in the computation on the reliability of PuD computation results. This work is the first to reveal an interference phenomenon corrupting PuD computation results, which we call PuDGhost, on real DRAM chips. PuDGhost causes a PuD operation in a given column to produce erroneous results due to interference from non-operand data (i.e., data not intended to participate in the computation) stored in (1) non-activated rows and (2) other columns that perform computations concurrently under the same SiMRA operation. Figure 1b illustrates how PuDGhost causes PuD computation errors. Rows R1, R2, and R3 are simultaneously activated to perform a MAJ3 operation. In column C1, the inputs are 1, 1, and 0, so the ideal MAJ3 output should be 1 (Figure 1a). Due to PuDGhost, column C1 suffers interference from non-activated rows (e.g., R0) ( 1 ) and other columns (e.g., C0) ( 2 ), resulting in an erroneous output. We conduct the first extensive characterization of PuDGhost using 96 real DDR4 DRAM chips (12 modules). We systematically study interference from non-operand data under a wide range of operational conditions (e.g., data patterns, temperature, and spatial properties). Among our 15 key observations, we highlight two major findings. First, non-operand data in non-activated rows that are physically adjacent to simultaneously activated rows affects SiMRA outputs. Storing logic-0 (logic-1) in the adjacent rows biases the SiMRA output toward logic-0 (logic-1), affecting SiMRA outputs by up to 10% for random inputs. The bias increases monotonically as the fraction of logic-1 in adjacent rows increases (detailed in §5). Second, non-operand data in other columns that concurrently perform computations under the same SiMRA operation (i.e., the inputs of these concurrent computations) also affects SiMRA outputs by up to 48% for random inputs. Unlike adjacent-row interference, column-wise interference is both stronger and exhibits a non-monotonic relationship with the fraction of logic-1 in these columns’ inputs (detailed in §6). Our real DRAM chip characterization results suggest that PuDGhost is an important consideration for designing future PuD systems that are robust. Building on our empirical insights, we analyze PuDGhost’s impact on PuD reliability and present robust PuD solution directions across multiple layers of the PuD computing stack. At the system level, we reveal that PuD systems that are unaware of adjacent-row data during column screening and PuD execution can mislabel unreliable columns as reliable. We propose robust column screening methods that control the data in rows adjacent to compute rows during both screening and PuD execution, reducing the risk of mistakenly using unreliable columns in the presence of PuDGhost. At the architecture level, we propose a compute row layout that uses dedicated isolation rows with fixed data patterns between compute rows, ensuring that the rows adjacent to compute rows store fixed data that does not change during PuD execution.

We evaluate our solutions on real DRAM chips for two use cases: general matrix-vector multiplication (GEMV) and true random number generation (TRNG). Our results demonstrate that our solutions significantly reduce the impact of PuDGhost, providing 1) 413× lower normalized mean squared error (NMSE) in GEMV and 2) preventing 93% of the entropy loss in TRNG, compared to PuDGhost-unaware systems. Our main contributions are as follows. • We perform the first experimental study of a new interference phenomenon in DRAM that corrupts Processing-usingDRAM (PuD) computation results, which we call PuDGhost, on real DRAM chips. • Our experimental results on real DDR4 DRAM chips reveal that PuD computation results in a given column can be affected by data stored in 1) non-activated rows adjacent to the rows used for computation and 2) other columns that perform computations concurrently. PuDGhost violates the expectation that each computation depends solely on its own operand data. • We propose and discuss solutions across multiple layers of the PuD computing stack to reduce PuDGhost-induced PuD computation errors. • We evaluate our solutions on real DRAM chips for two use cases: general matrix-vector multiplication (GEMV) and true random number generation (TRNG). Our results demonstrate that our solutions significantly reduce the impact of PuDGhost on these real use cases. • We believe and hope that our results and analyses will enable and inspire future research to reduce computation errors in PuD, and to design future PuD systems that are robust.

2. Background 2.1. DRAM Organization and Operation Dynamic Random Access Memory (DRAM) is organized in a hierarchical structure consisting of channels, ranks, chips, banks, and subarrays of memory cells (Figure 2). A module contains one or more ranks, and each rank consists of multiple DRAM chips. Each chip has multiple banks (e.g., 8–16), and each bank is further divided into multiple subarrays. Within each subarray, DRAM cells form a two-dimensional grid of rows (wordlines) and columns (bitlines). Each cell consists of a single transistor paired with a capacitor, and stores one bit of data, based on the charge level held in the capacitor. The DRAM cells in the same column are connected to the sense amplifier (SA) via a bitline. Modern DRAM employs an open bitline architecture [168–171], where half of the bitlines in a subarray share SAs with the upper adjacent subarray and the other half share SAs with the lower adjacent subarray. The memory controller integrated in the CPU die generates a sequence of DRAM commands to access data in DRAM. The ACT command opens a specific row and copies its data into the row buffer. The PRE command closes the active row. These commands operate on all columns in a row.

2.2. Processing-using-DRAM Computational Capability of PuD. Processing-usingDRAM (PuD) [21–71] is a paradigm that can alleviate the bottleneck caused by frequent data movement between processing elements (e.g., CPUs) and main memory. PuD enables massively

Chip

Memory Channel

DRAM Module Chip Chip Chip Chip

Bank Subarray Sense Amplifier Sense Amplifier

Subarray Sense Amplifier

3. Methodology

SA DRAM Cell

Row Decoder

Processor Memory Controller

wordline

Capacitor bitline

Figure 2: DRAM Organization.

parallel computation within DRAM by leveraging the intrinsic analog operational properties of DRAM circuitry. Many PuD architectures perform computation through two primitives: 1) in-DRAM data copy from one row to another (RowCopy) using consecutive multiple-row activation [22,23,26,30,43,50,64], and 2) in-DRAM bitwise operations using simultaneous multiplerow activation (SiMRA) [23,26,33,38,40–43,46–48,50–52,54–58, 61,63,64,67,68,76]. In bitwise operations using SiMRA, simultaneously activating multiple DRAM rows within the same subarray induces charge sharing of activated cells in each bitline, resulting in a majority-of-X operation (MAJX) in each column. For example, when three rows are simultaneously activated, the charges of cells on the same bitline combine through charge sharing to produce the MAJ3 result (see Figure 1a). MAJX can implement basic Boolean operations such as AND and OR, and by chaining multiple MAJX operations, PuD can accelerate a wide range of computations, from basic arithmetic to complex kernels including general matrix-vector multiplication (GEMV) for LLM inference [26,33,35,37,38,40–42,48,49,51,55–59,61,72–75]. In Ambit [23, 26, 30] and its successor architectures [33, 38, 48], six compute rows per subarray are reserved to execute MAJ3. The row decoder is modified to allow specific triplet combinations of these six rows to be simultaneously activated, enabling a MAJ3 operation. The remaining rows in the same subarray serve as storage rows, holding data that is loaded into compute rows via RowCopy when needed for computation. PuD on COTS DRAM Chips. Prior work [41, 43–47, 50, 51, 54, 61–69, 76] demonstrates that commercial off-the-shelf (COTS) DRAM chips possess PuD computation capability. Specifically, prior work [62–65, 67] experimentally shows that COTS DDR4 chips from SK Hynix [172] can simultaneously activate 2, 4, 8, 16, or 32 rows within a subarray by violating nominal timing parameters. The memory controller can perform SiMRA on these chips by issuing an ACT-PRE-ACT command sequence (APA sequence) with very short intervals of 3ns or less between each command. PuD Computation Errors. Prior work focuses primarily on process variation in DRAM circuit components as the mechanism for MAJX errors. Prior work [26, 33, 62, 64] shows through circuit-level simulations that MAJ3 operations produce erroneous results when process variation of subarray components (e.g., cell capacitance) is large. Characterization studies using COTS DRAM chips [46, 47, 50, 62–64] experimentally show that the success rate of MAJX on real DRAM chips is below 100%, and that error susceptibility varies across columns. In these prior studies, the causes of SiMRA-based MAJX errors have been attributed to process variation of cell capacitance, access transistors, and SAs in each column.

We describe our COTS DRAM chip testing infrastructure (§3.1) and the COTS DDR4 chips tested for our characterization study (§3.2).

3.1. COTS DRAM Testing Infrastructure We conduct COTS DRAM chip experiments using DRAM Bender [173–176], an FPGA-based DDR4 testing infrastructure that provides precise control of DDR4 commands. Figure 3 shows our experimental setup that consists of four main components: 1) a host machine that generates the test program and collects results, 2) an FPGA development board [177], programmed with DRAM Bender, 3) thermocouple temperature sensors and heater pads pressed against the DRAM chips to maintain target temperature levels, and 4) a temperature controller that keeps the temperature at the desired level. (3) DRAM Module with Heater Pads

(4) Temperature Controller

(1) PCI-e to Host Machine

(2) Memory Controller on FPGA

Figure 3: Our FPGA-based PuD testing infrastructure (DRAM Bender [173, 174]) with DDR4 modules.

3.2. COTS DDR4 DRAM Chips Tested Table 1 lists the 96 COTS DDR4 DRAM chips from 12 modules, showing chip manufacturer (Chip Mfr.), module manufacturer (Module Mfr.), module count (#Modules), chip count (#Chips), die revision (Die Rev.), density, and chip organization (Org.). All tested chips are from SK Hynix, as prior work reports that only SK Hynix modules can perform SiMRA [41, 43–47, 50, 61–65, 67]. We test modules from various module manufacturers, die revisions, and chip densities so that our findings apply across different DRAM designs and manufacturing processes.1 Table 1: Summary of DDR4 DRAM chips tested.

Chip Mfr.

Module Mfr.

SK Hynix

TimeTec TeamGroup SK Hynix

#Modules Die (#Chips) Rev. 3 (24) 7 (56) 2 (16)

A M A

Chip Chip Density Org. 4Gb 4Gb 8Gb

x8 x8 x8

Logical-to-Physical Row Mapping. DRAM manufacturers use mapping schemes to translate logical to physical row addresses. To account for in-DRAM row address mapping, we reverse engineer the physical row address layout in all tested chips by analyzing RowHammer-induced bitflip patterns, following prior methodologies [63–65, 82, 84]. Subarray Boundaries. Following prior methodologies [50, 63–65, 90], we identify subarray boundaries using RowCopy, which only succeeds when source and destination rows are in 1 Prior work [61–64] hypothesizes that the hierarchical row decoder design is the primary enabler of SiMRA on COTS DRAM chips: reducing the intervals between APA sequence allows the local wordline decoder to latch the subsequent row address without de-asserting the previous one. We believe that chips from other vendors are also fundamentally capable of SiMRA, as SiMRA leverages the hierarchical row decoder design that is common across high-performance DRAM chips and is likely to persist in future generations.

the same subarray. By attempting RowCopy across consecutive row pairs, we reconstruct each chip’s subarray map. True/Anti Cells. DRAM cells are classified as true-cell or anti-cell based on how a fully charged capacitor is interpreted: in a true-cell (anti-cell), a charged capacitor represents logic-1 (logic-0) and a discharged capacitor represents logic-0 (logic-1). Prior work [90, 178] on DRAM retention failure commonly assumes that retention-induced errors are from the charged to discharged state. We identify the cell type of our chips following these works. Throughout this paper, logic-1 denotes a charged capacitor and logic-0 denotes a discharged capacitor. Even/Odd Columns. In an open-bitline layout [168–171], adjacent subarrays share sense amplifiers (SAs). Bitlines alternate their connections: even columns connect to SAs on one side while odd columns connect to SAs on the other side. We identify this even/odd column assignment by analyzing RowCopy outcomes and charge-sharing across subarray boundaries, following prior work [63, 90].2 Verification of Simultaneously Activated Rows. Prior work [62–65, 67] demonstrates that an APA sequence can simultaneously activate 2, 4, 8, 16, and 32 DRAM rows, and a subsequent WRITE command overwrites these rows with the written data.3 We follow this methodology to verify which rows are activated during SiMRA. First, we initialize an entire subarray with a predefined pattern. Second, we issue an APA sequence to activate multiple target rows, immediately followed by a WRITE command with a distinct pattern. After issuing a PRE, we read back each row in the subarray. Rows that were activated during APA will contain the written pattern, allowing us to identify which rows participated in SiMRA. To ensure non-activated rows remain unchanged, we extend the delay between the WRITE command following APA and the subsequent PRE command beyond the nominal tWR timing. We test delays of tWR, tWR+50ns, tWR+100ns, and tWR+200ns to rigorously verify that non-activated rows are not overwritten.

3.3. Overview of Experiments 3.3.1. Study Scope. We test whether a key expectation of PuD computations holds on real DRAM chips: that each column’s output depends solely on its own operand data. We investigate two sources of interference from non-operand data by addressing the following research questions, RQ1 and RQ2. RQ1: How does data stored in non-activated rows affect SiMRA outputs? (§4 and §5) RQ2: How does data stored in other columns that concurrently perform computations under the same SiMRA operation affect SiMRA outputs? (§6) We provide hypothetical explanations for the phenomena observed on real DRAM chips in §7. 3.3.2. Terminology and Metric. Figure 4 illustrates the six key terms we use in SiMRA experiments. SiMRA rows ( 1 ) refers to a set of rows that are simultaneously activated during 2 For some modules, the even/odd column assignment could not be reliably

determined (i.e., the expected parity-dependent pattern was not consistently observed) using the RowCopy-based method of [63, 90]. We exclude these modules from experiments involving even/odd column parity. 3 For some modules, SiMRA is unreliable at certain activation row counts (i.e., some intended rows are not activated). We exclude such modules from the results of the affected row counts.

a SiMRA operation; these rows contain the input operands on which the operation is performed. Adjacent rows ( 2 ) are the rows that are not activated during SiMRA and physically adjacent to the SiMRA rows. Target subarray ( 3 ) refers to the subarray that contains the SiMRA rows. Adjacent subarrays ( 4 ) are physically adjacent subarrays of the target subarray, one above and one below the target subarray. We define the term controlled rows (or controlled cells) ( 5 ) to refer to rows (or cells) whose data pattern is intentionally configured to observe how the SiMRA output changes in response to different data patterns. These data patterns include fixed patterns (all zeros, all ones, and random patterns) and patterns that depend on the inputs to the SiMRA rows. For random patterns, we define pc as the probability that each bit in controlled cells independently takes logic-1. Target columns ( 6 ) refer to a specified subset of columns over which we evaluate the SiMRA output. By default, all columns in the subarray serve as target columns. For column-wise interference experiments (shown in Figure 8 and §6), we randomly select 1/8th of all columns in the subarray as target columns. The SiMRA-row cells in the remaining 7/8th columns serve as controlled cells, whose data patterns we vary to analyze their impact on SiMRA outputs of the target columns. 1) Base 2) S-all 3) S-tar 4) S-adj 5) R-adj

6) R-far

SiMRA Rows

Adjacent Rows

6 3

Target Columns

Target Subarray

Fixed Data [Pr(bit=1) = 0.5]

Adjacent Subarray

Random Input [Pr(bit=1) = 0.5]

Fixed Data [Pr(bit=1) = pc ] 5

Controlled Rows (Cells)

Pr(bit=1) denotes the probability that each bit equals logic-1.

Figure 4: Experimental setup for evaluating interference from non-activated rows.

We define po1 as the fraction of output bits that equal logic-1 when SiMRA is executed with random inputs over the target columns. For example, if target columns cover all 64K columns in a bank and we collect 128 samples, po1 = 0.60 means that 60% of the 64K × 128 output bits are logic-1. We use po1 to quantify the effect of PuDGhost on the SiMRA operation in three key steps. First, as a baseline, we set all data other than the operand data in the target columns to random patterns (i.e., pc = 0.5). Second, we vary the data pattern of specific controlled rows or cells and measure the resulting change in po1 relative to this baseline. A change in po1 indicates that the controlled non-operand data affects the computation output, and the direction and magnitude of the shift quantify the interference. Third, we report the ratio of po1 under each condition to the baseline po1 , which we call Norm. po1 . A Norm. po1 closer to 1.0 indicates less interference from the controlled cells, while values below (above) 1.0 indicate that the controlled cells bias the SiMRA output toward logic-0 (logic-1).

4. Interference from Non-Activated Rows In this section, we examine how non-activated rows in the target and adjacent subarrays, which share bitlines with the SiMRA rows, affect SiMRA outputs.

4.1. Experimental Methodology Metric. We designate several rows in the target subarray and adjacent subarrays as controlled rows. For each experimental

4.2. COTS DRAM Chip Characterization Figure 5 shows how non-activated rows affect SiMRA outputs under six conditions.4 The y-axis shows the distribution of Norm. po1 across all tested modules, banks, and subarrays and the x-axis shows each tested condition. Figure 5a shows when all controlled rows store all-zeros (pc = 0.0), and Figure 5b shows when all controlled rows store all-ones (pc = 1.0). Each subplot represents a different number of SiMRA rows (i.e., 2-, 4-, 8-, 16-, and 32-row activation). 4 Throughout §4, §5, and §6, box-and-whisker plots show box boundaries representing the first and third quartiles (Q1 and Q3), and circle markers indicating the mean values. Each box shows the distribution across all tested instances (one SiMRA row group per subarray, across 12 modules × 16 banks × 3 subarrays).

S-all

S-tar

S-adj

R-adj

R-far

2-Row Activation 4-Row Activation 8-Row Activation 16-Row Activation 32-Row Activation 1.00

Norm. po1

1.000 0.975 0.950

0.95 S-all S-tarS-adjR-adjR-far

S-all S-tarS-adjR-adjR-far

1.00

0.95

0.98

0.90

0.96 S-all S-tarS-adjR-adjR-far

S-all S-tarS-adjR-adjR-far

Conditions of Controlled Rows

(a) All controlled rows store an all-zero pattern.

Norm. po1

condition, we collect 128 samples with random inputs to the SiMRA rows while keeping the data in the controlled rows fixed across samples. In this section, we use all the columns in a subarray (i.e., 65536 columns) as target columns to perform SiMRA operations. Thus, we generate a total of 65536×128 SiMRA output bits per condition. We report Norm. po1 as defined in §3.3.2 to quantify the interference from the controlled rows. Conditions. Figure 4 illustrates six different conditions that we define to progressively understand which non-activated rows affect the SiMRA output in the scope of three consecutive subarrays, the target subarray ( 3 ) and its adjacent subarrays ( 4 ). 1) Base is the baseline configuration. 2) S-all designates all rows except the SiMRA rows in both the target ( 3 ) and adjacent subarrays ( 4 ) as controlled rows. 3) S-tar designates all rows except the SiMRA rows in the target subarray as controlled rows, while 4) S-adj designates all rows in the adjacent subarrays. 5) R-adj designates all adjacent rows ( 2 ) as controlled rows, while 6) R-far designates all rows in the target subarray except the SiMRA rows ( 1 ) and the adjacent rows ( 2 ). Experimental Control. Across all conditions, the 128 sets of random input data applied to the SiMRA rows are identical, and the fixed data in all non-controlled rows are also kept identical. This design enables us to attribute observed differences in po1 to the data patterns in the controlled rows. Experimental Protocol. For each of the 128 random-input samples per condition, we execute four key steps: (i) write the specified data patterns to all controlled rows in the target and adjacent subarrays; (ii) write random input data to the SiMRA rows; (iii) execute SiMRA; and (iv) read out the SiMRA rows to record the outputs. Controlled rows retain the same data pattern across all 128 random-input samples, while random inputs to the SiMRA rows are independently generated for each sample. We ensure that the time per sample is well within the DRAM refresh window to eliminate the influence of retentiontime failures. Number of Instances Tested. To keep the total testing time reasonable, for each DRAM module, we select three subarrays per bank (one from the upper, one from the middle, and one from the lower region of the bank). Within each selected subarray, we randomly choose a group of SiMRA rows for each activation count: 2-, 4-, 8-, 16-, and 32-row activation. Temperature. Unless stated otherwise, all experiments are conducted at 50◦ C.

2-Row Activation 4-Row Activation 8-Row Activation 16-Row Activation 32-Row Activation

1.04 1.02 1.00

1.10

1.050

S-all S-tarS-adjR-adjR-far

1.04

1.025

1.05

1.000

1.00

S-all S-tarS-adjR-adjR-far

1.02 1.00 S-all S-tarS-adjR-adjR-far

Conditions of Controlled Rows

S-all S-tarS-adjR-adjR-far

(b) All controlled rows store an all-one pattern. Figure 5: Row-type characterization under controlled patterns.

Obsv. 1. Non-activated adjacent rows bias SiMRA outputs toward logic-0 (logic-1) when the adjacent rows store logic-0 (logic-1). In Figure 5a, we observe that S-all, S-tar, and R-adj produce Norm. po1 of approximately 0.97–0.98 on average across all five activation counts, reaching as low as 0.90. This indicates that adjacent-row data set to all-zeros biases SiMRA outputs for random inputs toward logic-0 by an average of 2–3% and up to 10%. Similarly, in Figure 5b, S-all, S-tar, and R-adj produce Norm. po1 of 1.02–1.03 on average across all five activation counts, reaching as high as 1.10. This indicates that adjacentrow data set to all-ones biases SiMRA outputs for random inputs toward logic-1 by an average of 2–3% and up to 10%. Obsv. 2. Interference from non-activated rows is highly localized to physically adjacent rows. The R-adj condition shows similar Norm. po1 values to S-all and S-tar, with means of approximately 0.97–0.98 in Figure 5a and 1.02–1.03 in Figure 5b, demonstrating that adjacent rows account for essentially all observed interference. In contrast, conditions without adjacent-row control (S-adj and R-far) show at most 0.7% deviation from the baseline in both Figure 5a and Figure 5b, indicating that non-adjacent rows have a small impact on SiMRA outputs. Obsv. 3. Interference from non-activated adjacent rows can strengthen as the number of SiMRA rows increases. We observe that the magnitude of bias can increase with more SiMRA rows. For example, in the R-adj condition, Norm. po1 reaches as low as 0.95 in Figure 5a and as high as 1.05 in Figure 5b for 2-row activation, while for 8-row activation, it reaches as low as 0.90 in Figure 5a and as high as 1.10 in Figure 5b.

5. Characterization of Interference from Adjacent Rows Building on the result of §4, this section provides a detailed characterization of adjacent-row interference from several perspectives (e.g., data patterns, spatial locality, and temperature sensitivity). We reuse the experimental control, the number of instances, and the default temperature setup from §4 and describe only the methodology specific to the experiment.

5.1. Experimental Methodology Metric. As in the R-adj setup in Figure 4, we designate all adjacent rows ( 2 ) as controlled rows ( 5 ) and use normalized

(Norm.) po1 to quantitatively evaluate their impact on the SiMRA output (the common baseline condition fills all adjacent rows with independent random data with pc = 0.5). For each experimental condition, we collect 128 samples with random inputs to the SiMRA rows ( 1 ). Except for the experiment shown in Figure 12, the data in the controlled rows ( 5 ) are kept fixed across all samples. Unless otherwise noted, all columns are designated as target columns ( 6 ). Experimental Protocol. For each of the 128 random-input samples, we execute the following four steps: (i) write the specified data pattern to all adjacent rows; (ii) write random input data to the SiMRA rows; (iii) execute SiMRA; and (iv) read out the SiMRA rows to record the outputs.

rows to random (pc = 0.5) and partition columns into two sets based on the fraction of logic-1 in each column’s adjacent-row cells (see Figure 8a): 1 Hi-Cols (columns where more than half of the adjacent-row cells store logic-1) and 2 Lo-Cols (columns where fewer than half of the adjacent-row cells store logic-1). Columns where the adjacent-row cells store the same number of logic-0 and logic-1 are not classified into either 1 or 2 . We measure Norm. po1 separately for Hi-Cols and Lo-Cols as target columns. 2

Lo-Cols

Controlled Cells Logic-0 Logic-1 Fixed Data [Pr(bit=1) = 0.5] Fixed Data [Pr(bit=1) = pc ]

5.2. COTS DRAM Chip Characterization Results

2-Row Activation

1.00 0.95

4-Row Activation

8-Row Activation

1.116-Row Activation 1.0532-Row Activation

1.05

1.1

1.00

1.0

1.00

0.95

0.9

0.95

0.0 0.250.75 1.0

Figure 6: Sensitivity to fraction of logic-1 in adjacent rows.

Obsv. 4. Data stored in non-activated adjacent rows more strongly biases SiMRA outputs toward logic-1 (logic-0) as the fraction of logic-1 (logic-0) in the adjacent rows increases. As pc increases, Norm. po1 increases monotonically, demonstrating a clear positive correlation between the fraction of logic-1 in adjacent rows and the bias in SiMRA outputs. For example, with 32-row activation, the mean Norm. po1 rises monotonically from 0.98 (pc = 0.0) to 1.02 (pc = 1.0). Structured Data Patterns. To study the impact of structured (i.e., non-random) data patterns in adjacent rows, we vary the byte pattern among {0x00, 0xF0, 0x55, 0xAA, 0xFF}. Figure 7 shows Norm. po1 distribution (y-axis) for various data patterns written to the adjacent rows (x-axis), across different numbers of SiMRA rows (each subplot). 0x00

0xF0

0x55

0xAA

0xFF

2-Row Activation 4-Row Activation 8-Row Activation 1.116-Row Activation1.0532-Row Activation 1.1

1.05

1.00

1.0

1.00

0.95

0.9

0.95

Norm. po1

1.05

0.95

Adjacent Rows' Data Pattern

Figure 7: Sensitivity to the data patterns in the adjacent rows.

Obsv. 5. Non-activated adjacent rows bias SiMRA outputs based on the fraction of logic-1 they store rather than on the specific structured data pattern. Data patterns with the same fraction of logic-1 in adjacent rows produce similar Norm. po1 regardless of the structured pattern used. 0xF0, 0x55, and 0xAA all have a fraction of logic-1 of 0.5 and produce Norm. po1 of approximately 1.0. Column-Local Interference. We test whether interference from adjacent rows is uniform across all columns or depends on each column’s own adjacent-row cells. We set data in adjacent

Pr(bit=1) denotes the probability that each bit equals logic-1.

Target Columns

(b) Column-wise Interference from Adjacent Rows

Figure 8: (a) Column-local interference. (b) Adjacent-row interference across columns.

Figure 9 shows the Norm. po1 distribution (y-axis) separately for Hi-Cols and Lo-Cols (x-axis) across different numbers of SiMRA rows (each subplot). 2-Row Activation 4-Row Activation 8-Row Activation 16-Row Activation 32-Row Activation 1.02 1.00 0.98

1.02

0.0 0.250.75 1.0

Hi-Cols

(a) Column-Local Interference

1.00 0.98

Lo-Cols Hi-Cols

1.025

1.02

1.000

1.00 0.98

0.975

Lo-Cols Hi-Cols

Conditions of Column Type

1.02 1.00 0.98 0.96

Lo-Cols Hi-Cols

Figure 9: Column-local interference.

Obsv. 6. Interference from non-activated adjacent rows is not uniform across all columns: each column’s SiMRA output is affected by its own adjacent-row cells. Hi-Cols and Lo-Cols show opposite trends: Hi-Cols produce a mean Norm. po1 above 1.0 while Lo-Cols produce below 1.0. For example, with 2-row activation, the mean Norm. po1 is 1.004 for Hi-Cols and 0.996 for Lo-Cols. This means that columns whose own adjacent-row cells contain more logic-0 (logic-1) are biased toward logic-0 (logic-1), confirming that adjacent-row interference is not uniform across all columns. Adjacent-Row Interference Across Columns. To evaluate whether a given column’s SiMRA output is affected by data stored in other columns’ adjacent-row cells, we randomly select 1/8th of all columns as target columns ( 1 ) (see Figure 8b). For the remaining 7/8th columns, we designate their adjacent-row cells as controlled cells ( 2 ) and set them to all-zeros (pc = 0.0) or all-ones (pc = 1.0). Figure 10 shows the Norm. po1 distribution of the target columns (y-axis) for different pc values of the controlled cells in non-target columns (x-axis), across different numbers of SiMRA rows (each subplot). Norm. po1

Norm. po1

1.05

Norm. po1

Sensitivity to Fraction of Logic-1. To examine how the fraction of logic-1 stored in adjacent rows affects the SiMRA output, we sweep pc ∈ {0.0, 0.25, 0.75, 1.0}. Note that pc = 0.5 corresponds to the baseline condition. Figure 6 shows Norm. po1 distribution (y-axis) for each pc value of the adjacent rows (xaxis), across different numbers of SiMRA rows (each subplot).

Random Input [Pr(bit=1) = 0.5]

1.025 1.000 0.975

2-Row Activation 1.05 4-Row Activation 1.00

0.0

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16-Row Activation

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1.00

1.000

0.95

0.0

1.0

32-Row Activation

1.05

0.0

1.0

0.975

0.0

1.0

Figure 10: Adjacent-row interference across columns.

Obsv. 7. A given column’s SiMRA output is affected by data stored in other columns’ adjacent-row cells. When the controlled cells in non-target columns store logic0 (logic-1), the mean Norm. po1 of target columns is biased

baseline

(0, 0)

(1, 0)

(0, 1)

(1, 1)

= (bitin , bitadj) 2 bit

adj = Logic-1

1 bit = Logic-1 in

Logic-0 Logic-1 Fixed Data [Pr(bit=1) = 0.5] Pr(bit=1) denotes the probability that each bit equals logic-1.

Figure 11: Input-dependent adjacent-row patterns.

Figure 12 shows Norm. po1 distribution (y-axis) for all four combinations (bitin , bitadj ) ∈ {(0, 0), (1, 0), (0, 1), (1, 1)} (xaxis), across different numbers of SiMRA rows (each subplot). (0,0)

(1,0)

(0,1)

2-Row Activation 4-Row Activation 8-Row Activation 16-Row Activation 32-Row Activation

1.025

1.000

Norm. po1

toward logic-0 (logic-1), confirming that data in other columns’ adjacent-row cells affects a given column’s SiMRA output. For example, with 2-row activation, the mean Norm. po1 shifts to 0.99 at pc = 0.0 and 1.01 at pc = 1.0. Input-Dependent Adjacent-Row Patterns. To quantify how a SiMRA input bit and its corresponding adjacent-row bit jointly affect the output, we define bitin as the value of a SiMRA input bit in a given column and bitadj as the value of the adjacent-row cell in the same column. For each random-input sample, we first initialize all adjacent rows with a random base pattern (pc = 0.5). We then modify the adjacent-row cells based on a specified (bitin , bitadj ) combination: for each column where the SiMRA input equals bitin , we set its corresponding adjacent-row cell to bitadj ; all other adjacent-row cells retain the base pattern. Figure 11 illustrates the adjacent-row data patterns for the baseline and all four combinations in a given random-input sample. For example, for (bitin , bitadj ) = (1, 1), each column where the SiMRA input is logic-1 ( 1 ) has its corresponding adjacentrow cell set to logic-1 ( 2 ), while the remaining adjacent-row cells retain the random base pattern. Because the random inputs differ across samples, the spatial distribution of modified adjacent-row cells changes accordingly. This experiment uses configurations where each adjacent row borders only one SiMRA row, making bitadj well-defined.

0.975

50 60 70 80

Norm. po1

1.000 0.975

1.05 1.00 0.95

1.00 0.95

Values of (bitin, bitadj)

Temperature ( 50 ) 60 70 80

6. Interference from Columns that Concurrently Perform Computations In this section, we investigate whether data stored in columns that concurrently perform computations under the same SiMRA operation affects the SiMRA outputs.

6.1. Experimental Methodology We reuse the experimental protocol, the experimental control, the number of instances, and the temperature setup from §5 and describe only the methodology specific to §6. Metric. We select 1/8th of all columns as target columns and designate the SiMRA-row cells in the remaining 7/8th columns as controlled cells. By default, target columns are randomly selected from all columns regardless of even/odd column parity, as illustrated in Figure 14a. We measure Norm. po1 over the target columns using 128 random-input samples. The baseline condition sets each controlled cell independently to logic-1 with probability pc = 0.5. 1

Opposite-Parity Sense Amplifier

Same-Parity Sense Amplifier

1.00

Target Columns

Controlled Cells

Fixed Data [Pr(bit=1) = 0.5]

0.95

Fixed Data [Pr(bit=1) = pc ] Sense Amplifier

Figure 12: Input-dependent adjacent-row interference.

When bitin = 0, the mean Norm. po1 remains approximately 1.0 regardless of bitadj across all tested numbers of SiMRA rows, indicating negligible interference. In contrast, when bitin = 1, the SiMRA output is sensitive to the adjacent-row cell: bitadj = 0 decreases the mean Norm. po1 to approximately 0.97–0.98, while bitadj = 1 increases it to 1.02–1.03. Temperature Sensitivity. To study the temperature dependence of interference from adjacent rows, we set the temperature to 50◦ C, 60◦ C, 70◦ C, and 80◦ C. At each temperature, we set all adjacent rows to all-zeros (pc = 0.0) or all-ones (pc = 1.0). Figure 13 shows the mean Norm. po1 (y-axis) across temperatures ranging from 50◦ C to 80◦ C (x-axis) when all adjacent rows are set to all-zeros (pc = 0.0) or all-ones (pc = 1.0), across different numbers of SiMRA rows (each subplot).5

50 60 70 80

We observe no significant temperature dependence in adjacent-row interference. For example, with 8-row activation under pc = 1.0, the mean Norm. po1 remains at approximately 1.02 across all tested temperatures (50◦ C–80◦ C).

1.05

Obsv. 8. Cells in simultaneously activated rows storing logic-1 are substantially more susceptible to interference from non-activated adjacent rows than cells storing logic-0.

pc=0.0 pc=1.0

Obsv. 9. Temperature has a small effect on interference from non-activated adjacent rows.

(1,1)

1.05

50 60 70 80

1.025 1.000 0.975

Figure 13: Adjacent-row interference vs. temperature.

2-Row Activation 4-Row Activation 8-Row Activation 16-Row Activation 32-Row Activation 1.025

1.025 1.000 0.975

(a) Default Setup

Even Columns

6 Odd Columns

Sense Amplifier

Random Input [Pr(bit=1) = 0.5] Pr(bit=1) denotes the probability that each bit equals logic-1.

(b) Even/Odd Columns Setup

Figure 14: Experimental setup for evaluating interference from concurrently computing columns: (a) Default setup, (b) Even/odd column setup.

6.2. COTS DRAM Chip Characterization Results Fraction of Logic-1. Using the default setup (Figure 14a), we sweep pc ∈ {0.0, 0.25, 0.75, 1.0} to examine how the fraction of logic-1 in the controlled cells affects the SiMRA outputs of target columns. Note that pc = 0.5 corresponds to the baseline. Figure 15 shows the Norm. po1 distribution of the target columns (y-axis) across all tested modules, banks, and subarrays, for each pc value of the controlled cells (x-axis), across different numbers of SiMRA rows (each subplot). 5 Throughout §5 and §6, the line plots show mean values with shaded bands representing the interquartile range (IQR), computed across all tested instances (one SiMRA row group per subarray, across 12 modules × 16 banks × 3 subarrays).

0.0 0.25 0.75 1.0

1.0 0.8 0.6

0.8

0.0 0.25 0.75 1.0

1.2

32-Row Activation

1.0 0.8

0.0 0.25 0.75 1.0

Figure 15: Sensitivity to the fraction of logic-1 in concurrently computing columns’ inputs.

Obsv. 10. SiMRA output is affected by data stored in other columns that concurrently perform computations. For 2–4 simultaneously activated rows, these columns’ inputs bias SiMRA outputs toward logic-1 (logic-0) as their fraction of logic-1 increases (decreases). For 8+ rows, the bias direction reverses at high fractions of logic-1, where SiMRA outputs are biased toward logic-0. The observed trend of the interference from columns that concurrently perform computations varies with the number of simultaneously activated rows. For small row counts (2–4 rows), Norm. po1 increases monotonically with the fraction of logic-1 in the inputs of columns that concurrently perform computations. For example, with 4-row activation, the mean Norm. po1 increases from 0.94 (pc = 0.0) to 1.04 (pc = 1.0). For larger row counts (8+ rows), the relationship becomes nonmonotonic: Norm. po1 peaks at intermediate pc values and decreases toward both extremes. For example, with 32-row activation, the mean Norm. po1 is 0.89, 1.11, 1.05, and 0.86 at pc = 0.0, 0.25, 0.75, and 1.0, respectively, with the maximum deviation occurring at pc = 0.25. Obsv. 11. Interference from columns that concurrently perform computations strengthens as the number of simultaneously activated rows increases. The magnitude of interference grows substantially with more SiMRA rows. For 2-row activation, the mean Norm. po1 ranges from approximately 0.95 to 1.06. For 32-row activation, it ranges from approximately 0.86 to 1.11. The maximum deviation from the baseline reaches up to 48%, observed at 16-row activation with pc = 0.0. Obsv. 12. Interference from columns that concurrently perform computations is stronger than interference from non-activated adjacent rows. The interference observed in Figure 15 is significantly larger than the interference from non-activated rows observed in Figure 6, where the mean Norm. po1 stays within the range of approximately 0.97–1.03. Even/Odd Columns. To understand the spatial characteristics of inter-column interference, we distinguish between even and odd columns. We refer to whether a column is even or odd as its parity; two columns have opposite parity if one is even and the other is odd, and same parity if both are even or both are odd. We select target columns from only even columns or only odd columns, randomly choosing 1/8th of all columns (i.e., 1/4th of the columns of the chosen parity) as target columns, and define two configurations, illustrated in Figure 14b. In Opposite-Parity ( 1 ), the controlled cells are the SiMRA-row cells in all columns of the opposite parity (e.g., in Figure 14b, target columns ( 3 ) are selected from odd columns ( 6 ), so the SiMRA-row cells in all even columns ( 5 ) serve as controlled cells ( 4 )). In Same-Parity ( 2 ), the controlled cells

are the SiMRA-row cells in all non-target columns of the same parity (e.g., in Figure 14b, target columns ( 3 ) are selected from odd columns ( 6 ), so the SiMRA-row cells in all nontarget odd columns serve as controlled cells ( 4 )). We sweep pc ∈ {0.0, 0.25, 0.75, 1.0} for both configurations. Figure 16 shows the Norm. po1 distribution of the target columns (y-axis) for each pc value of the controlled cells (xaxis), across different numbers of SiMRA rows (each subplot). Figure 16a shows results for the Opposite-Parity configuration, and Figure 16b for the Same-Parity configuration. 1.05

2-Row Activation 1.05 4-Row Activation

1.00

0.95

Norm. po1

0.9

8-Row Activation 1.2 16-Row Activation 1.0

0.0 0.250.75 1.0

1.050 1.025 1.000 0.975

Norm. po1

1.0

4-Row Activation 1.1 1.0 0.9 0.8

2-Row Activation

8-Row Activation 1.02 1.00 0.98 0.96

0.0 0.250.75 1.0

16-Row Activation

1.02 1.00 0.98

0.0 0.250.75 1.0

(a) Opposite-Parity configuration. 1.04 1.02 1.00 0.98

0.0 0.25 0.75 1.0

4-Row Activation

8-Row Activation

1.00 0.98

0.0 0.25 0.75 1.0

16-Row Activation

1.05 1.00 0.95 0.90

32-Row Activation

1.02 1.00 0.98 0.96

0.0 0.250.75 1.0

32-Row Activation 1.0 0.9

0.0 0.25 0.75 1.0

0.8

0.0 0.25 0.75 1.0

(b) Same-Parity configuration. Figure 16: Interference from concurrently computing columns by parity: (a) Opposite-Parity, (b) Same-Parity.

Obsv. 13. Interference from columns of the opposite parity biases SiMRA outputs toward logic-0 (logic-1) when their inputs store logic-0 (logic-1). In Figure 16a, the mean Norm. po1 of the target columns increases monotonically with pc across all five activation counts in the Opposite-Parity configuration. For example, with 2-row activation, the mean Norm. po1 increases from approximately 0.97 at pc = 0.0 to approximately 1.02 at pc = 1.0. Obsv. 14. Interference from columns of the same parity biases SiMRA outputs in the same direction as their inputs for 2–4 activated rows, but the bias direction reverses at high fractions of logic-1 for 8+ rows. In the Same-Parity configuration (Figure 16b), for 2-row activation, the mean Norm. po1 increases monotonically from approximately 0.99 (pc = 0.0) to 1.02 (pc = 1.0). For larger row counts (8+ rows), the bias direction can reverse at high fractions of logic-1: for example, with 32-row activation, the mean Norm. po1 is 0.96, 1.02, 0.99, and 0.93 at pc = 0.0, 0.25, 0.75, and 1.0, respectively. This non-monotonic trend contrasts with the Opposite-Parity configuration, which remains monotonic across all row counts. Temperature Sensitivity. To study the temperature dependence of inter-column interference, we use the default setup (Figure 14a). At each temperature, we set the controlled cells to all-zeros (pc = 0.0) or all-ones (pc = 1.0). Figure 17 shows the mean Norm. po1 (y-axis) across temperatures ranging from 50◦ C to 80◦ C (x-axis), for pc = 0.0 and pc = 1.0 (each line), across different numbers of SiMRA rows (each subplot). 2-Row Activation 4-Row Activation 8-Row Activation 16-Row Activation 32-Row Activation

Norm. po1

2-Row Activation

1.1

1.05

1.05 0.95

1.0

1.00

0.95

50 60 70 80

0.9

50 60 70 80

1.0

0.9

0.8

Temperature ( 50) 60 70 80

pc=0.0 pc=1.0

50 60 70 80

Figure 17: Inter-column interference vs. temperature.

The interference varies monotonically with temperature. For example, with 16-row activation at pc = 0.0, the mean Norm. po1 increases from 0.87 to 0.89 as temperature rises from 50◦ C to 80◦ C, reducing the deviation from the baseline. In contrast, with 16-row activation at pc = 1.0, the mean Norm. po1 decreases from 0.953 to 0.947, slightly increasing the deviation from the baseline.

7. Hypothetical Explanation for PuDGhost We hypothesize that the interference phenomena observed in §4–§6 arise from electrical coupling during SiMRA charge sharing and sensing. Interference from non-activated rows. The directional bias observed in §5 (i.e., adjacent rows storing logic-0 (logic-1) bias SiMRA outputs toward logic-0 (logic-1) (Obsv. 4)) suggests electrical coupling between activated and non-activated rows, where the charge state of non-activated adjacent-row cells affects the charge sharing process. We hypothesize that the asymmetric sensitivity observed in Figure 12, where cells in SiMRA rows storing logic-1 are more susceptible to interference from adjacent rows than cells storing logic-0 (Obsv. 8), arises because cells storing logic-1 (i.e., charged cells) have their charge drained to the bitline during SiMRA, which may make them more vulnerable to interference. Interference from columns that concurrently perform computations. We hypothesize that the monotonic trend in the Opposite-Parity configuration (Figure 16a) arises from electrical coupling between bitlines of opposite parity. The non-monotonic trend in the Same-Parity configuration (Figure 16b) may reflect interactions through sense-amplifier (SA) circuitry, as columns of the same parity connect to SAs on the same side of the subarray. We hypothesize that the overall patterns observed in Figure 15 (Obsv. 10) emerge from the combination of these two effects. We hope that our findings motivate future device-level studies to uncover the precise root causes of PuDGhost, similar to how device-level studies [150, 167, 179–185] provided insight into RowHammer [81, 84, 93] and RowPress [82, 88, 151] after the two phenomena were first demonstrated and analyzed in real DRAM chips.

8. Challenges For Reliable PuD Systems Building on the detailed characterization of PuDGhost in §4, §5, and §6, this section discusses key implications for designing future PuD systems that are robust.

and employ solutions such as post-manufacturing column screening to use only reliable columns, a lack of awareness of PuDGhost can still lead to unreliable systems. We demonstrate in §10.1 that column screening without accounting for PuDGhost can mislabel unreliable columns as reliable, as the non-operand data during screening may not reflect the actual non-operand data during PuD execution.

8.2. Ineffectiveness of Disturbance Mitigations PuDGhost is qualitatively different from DRAM read disturbance phenomena [65, 81–83, 88, 151] in three key aspects. Interference source. Read disturbance is caused by an activated aggressor row. PuDGhost is caused by data stored in 1) non-activated adjacent rows and 2) columns that concurrently perform computations under the same SiMRA operation. Triggering mechanism. Read disturbance requires repeatedly activating an aggressor row (RowHammer) or keeping it open for a prolonged period (RowPress). PuDGhost requires no aggressor row activation; data stored in non-activated rows affects computation results within a single SiMRA operation. Manifestation. Read disturbance manifests as persistent bitflips in victim DRAM cells through gradual charge injection or leakage. PuDGhost manifests as transient errors in SiMRA outputs during charge sharing and sensing. These differences render prior read disturbance mitigations [65, 79, 82, 83, 85, 147–149, 152, 160, 161, 164–166, 186–204] ineffective against PuDGhost. To experimentally verify that refreshing data before SiMRA execution does not mitigate PuDGhost, we vary the time interval (0ms, 30ms, 60ms, or 120ms) between writing data to SiMRA rows and executing SiMRA. If the interference is related to charge leakage over time, shorter time intervals should result in weaker interference. We follow the same setup as pc = 0.0 and pc = 1.0 in Figure 6 for adjacent-row interference (left plot) and Figure 15 for inter-column interference (right plot), and test 8-row activation on one DRAM chip from each of the three module types. Figure 18 shows the mean Norm. po1 (y-axis) as a function of the waiting time before SiMRA execution (x-axis). Across all conditions, the mean Norm. po1 remains approximately constant regardless of the waiting time (e.g., 0.98 at pc = 0.0 and 1.02 at pc = 1.0 in the left plot; 0.92 at pc = 0.0 and 1.02 at pc = 1.0 in the right plot), showing that refreshing data more frequently before SiMRA execution does not mitigate PuDGhost.

Norm. po1

Obsv. 15. Interference from columns that concurrently perform computations varies monotonically with the temperature.

1.025 1.000 0.975

Adjacent-Row Interference

1.0 0.9

Inter-Column Interference

pc=0.0 pc=1.0

120 0 30 120 Write-to-SiMRA Interval [ms] 60 Figure 18: Time interval between writing data and SiMRA.

8.1. Reliability Challenges Induced by NonOperand Data

8.3. Broader Implications

We demonstrate that SiMRA outputs are affected by interference from data stored in non-activated adjacent rows and columns that concurrently perform computations. These results obtained on real DRAM chips violate the expectation of PuD computations that each column’s computation should depend solely on its own operand data.6 Even when PuD system architects are aware that PuD computations can produce errors (e.g., due to process variation)

6We believe PuDGhost would manifest in any SiMRA-capable chip regardless of manufacturer or DRAM type, as PuDGhost is based on fundamental analog operational properties of DRAM (e.g., charge sharing) and DRAM array design (e.g., hierarchical row decoders, open-bitline architecture) shared across manufacturers and DRAM types. We already observe consistent interference patterns across 12 modules with three different die revisions and densities, lending support to this hypothesis.

8.3.1. Security Concerns for PuD Systems. PuDGhost exposes two attack vectors in multi-tenant PuD environments

where multiple users share the same DRAM bank. First, an attacker can (1) allocate memory in DRAM rows adjacent to the victim’s SiMRA rows and (2) write specific patterns to these rows to bias the victim’s PuD computation results. Second, conversely, the attacker could infer statistical properties of the victim’s adjacent-row data by observing bias patterns in the attacker’s own computation results. 8.3.2. Other SiMRA-based Operations. PuDGhost can degrade the reliability of a broad spectrum of SiMRA-based operations. For example, SiMRA-based true random number generation (TRNG) [44, 61, 67], SiMRA-based physically unclonable functions (PUFs) [68], and other potential future SiMRA-based operations could also be affected. In §10.3, we demonstrate that PuDGhost can significantly degrade the randomness quality of SiMRA-based TRNG. This implies that PuDGhost is a critical consideration for TRNG and cryptographic applications that rely on it. 8.3.3. PuD Simulation Frameworks. Our characterization reveals that PuD computations performed concurrently under the same SiMRA operation are not independent: a given column’s SiMRA output depends on data stored in columns that concurrently perform computations. This finding has critical implications for PuD simulation frameworks. Prior PuD simulation models [42, 49] assume that errors occur independently in each column. Since whether or not a column produces a computation error also depends on the inputs of concurrent computations, these models may not accurately capture application-level output quality.

9. PuDGhost-Aware Error Mitigation Techniques As discussed in §8, PuDGhost poses a fundamental reliability challenge for PuD systems. Since PuDGhost arises from inherent analog operational properties of DRAM and DRAM array design, fully eliminating PuDGhost would be difficult. One promising direction is to design DRAM from the ground up for reliable PuD. However, such fundamental redesign is not the only path. Prior characterization studies [79, 81, 82, 84, 88] of DRAM reliability challenges have led to practical mitigations [65, 79, 82, 83, 85, 147–149, 152, 160, 161, 164–166, 186–204] without requiring DRAM redesign. In this section, we discuss mitigation strategies across multiple layers of the PuD computing stack. In §9.1, we discuss potential DRAM cell array-level modifications as directions for future research. In §9.2, we discuss the relationship between process variation of DRAM circuitry and PuDGhost. We propose two mitigation techniques for PuDGhost: 1) new column screening methods (§9.3), and 2) a new interference-aware compute row layout (§9.4). In §9.5, we discuss how practical PuD systems can likely be enabled through complementary approaches: 1) PuD ECC schemes and 2) error-tolerant applications.

9.1. Cell Array-Level Modifications One approach to mitigating PuDGhost is to add modifications to the DRAM cell array to reduce interference during SiMRA. We discuss three potential directions for future research. Each approach requires modifications to the DRAM array,

DRAM interface, or memory controller, and occupies a distinct point in the design tradeoff space of reliability, area overhead, and performance. We leave comprehensive evaluation and comparison of these techniques for future work. Isolation Transistors. Inserting isolation transistors [170,171, 205] between compute rows and storage rows could electrically disconnect these regions before SiMRA execution, reducing interference from non-activated rows. However, modern DRAM is implemented with high density [5, 90, 206, 207], and adding transistors incurs area overhead, potentially eating into PuD’s advantage of throughput per unit area. Staged Activation. Our characterization shows that the impact of PuDGhost strengthens with the number of simultaneously activated rows. This motivates exploring staged activation [39], where rows are activated in smaller groups sequentially with sensing performed only after the final group, potentially reducing the impact of PuDGhost while preserving exact PuD computations. While the feasibility of mitigating PuDGhost requires further investigation, staged activation could offer a useful knob for trading throughput for reliability. Reference Voltage Adjustment. Adjusting precharge or reference voltages [32] is a promising direction to compensate for the shift in bitline voltage caused by PuDGhost. For example, if adjacent rows are expected to store mostly logic-0 during execution, lowering the reference voltage could compensate for the resulting bias toward logic-0. Performing such adjustments at runtime to account for the dynamically varying direction and magnitude of PuDGhost could entail significant circuit complexity and power overhead.

9.2. Reducing Process Variation Prior work [26, 33, 62, 64] demonstrates that process variation in DRAM circuitry can induce PuD computation errors in SPICE simulations. While reducing process variation can alleviate some sources of PuD computation errors, it alone might be insufficient to eliminate them. PuDGhost arises from data-dependent interference from non-operand data, which is fundamentally different from errors caused by process variation. The interference itself would persist even if process variation were entirely eliminated, potentially still causing PuD computation errors.

9.3. Interference-Aware Column Screening 9.3.1. Naive Column Screening. A fundamental approach to handling PuD computation errors is to use only identified reliable columns during PuD execution, or to use only DRAM modules where all columns qualify as reliable [26, 33, 41, 47]. A prior study [47] proposes post-manufacturing screening using large sets of random inputs for SiMRA to identify and filter out unreliable columns. Our experimental findings suggest that screening that does not account for PuDGhost can fail to ensure the reliability of screened columns during PuD execution. The key challenge is that PuDGhost-induced interference is dynamic: non-operand data in adjacent rows can change during PuD execution, and therefore columns labeled as reliable during screening can later produce errors, potentially causing significant application-level errors. Since column screening with random inputs naturally varies the data in concurrently computing columns across samples of inputs, sufficiently large

sets of random inputs can, in principle, capture the effect of interference from concurrently computing columns. However, PuDGhost suggests that column screening that does not account for data in adjacent rows can fail to ensure the reliability of screened columns during PuD execution (see §10.1). 9.3.2. Robust Column Screening and System-Level Support. To address this challenge, we propose two PuDGhostaware column screening methods, CS-1 and CS-2. • (CS-1) Vary data in adjacent rows during screening. This approach screens columns under multiple data patterns in adjacent rows and retains only columns that are labeled reliable across all tested patterns. It requires no runtime support to control data in adjacent rows during PuD execution, but tends to reduce the number of usable columns because columns must pass screening under all tested patterns. • (CS-2) Fix data in adjacent rows from screening through execution. This approach uses the same fixed data pattern in adjacent rows during both screening and PuD execution. Since columns are screened and operated under a single consistent data pattern in adjacent rows, it can preserve more usable columns than CS-1 (see §10.1). It requires runtime support to maintain fixed data in adjacent rows during PuD execution, as well as a compute row layout that ensures adjacent rows remain fixed, as discussed in §9.4. We provide a quantitative evaluation of these two column screening methods using real DRAM chips in §10.1.

9.4. Interference-Aware Compute Row Layout

Computation Row Computation Row Computation Row Computation Row

Storage Row

Unexpected Interference from Dynamic Data

a) Contiguous Computation Row Layout

Storage Row

1015 Rows

Storage Row Isolation Row

1020 Rows Row Dec. for Comp Rows

Local Row Dec.

. . .

Row Dec. for Comp Rows

Storage Row

...

Local Row Dec.

Mitigating PuDGhost requires careful physical arrangement of compute rows. In Ambit [23, 26, 30] and its successors [33, 38, 48], a small number of compute rows (e.g., six rows) are reserved for MAJ3 operations, and the row decoder is modified to simultaneously activate certain triplets of these rows to perform MAJ3. The physical arrangement of these compute rows determines which rows become adjacent to them, directly affecting the requirements for column screening methods. With CS-1, since screening tests columns under varying data patterns in adjacent rows, any layout is acceptable. In contrast, CS-2 relies on fixed data in adjacent rows during both screening and PuD execution, making certain compute row layouts incompatible with CS-2. Problem with Contiguous Layouts. A contiguous layout (Figure 19a), where all compute rows are placed adjacent to each other, is incompatible with CS-2. In this layout, compute rows participating in one MAJX execution are adjacent to compute rows that can participate in other MAJX executions. Because these adjacent compute rows are overwritten with new operands in other MAJX executions, the fixed data pattern required by CS-2 cannot be maintained. Computation Row Isolation Row Computation Row Isolation Row Computation Row Isolation Row Computation Row Isolation Row

Expected Interference from Fixed Data

b) Interference-Aware Computation Row Layout with Isolation Rows

Figure 19: Compute row layouts in a 1024-row subarray with four compute rows: (a) contiguous layout, (b) isolation-row layout ensuring fixed adjacent-row data.

Interleaved Layout with Isolation Rows. We propose a compute row layout where each compute row group is placed between rows with fixed data patterns, called isolation rows (Figure 19b). Isolation rows are initialized once with a fixed data pattern and refreshed normally, ensuring that the rows adjacent to compute rows store fixed data that does not change during PuD execution. This layout introduces no additional latency beyond the one-time initialization. The area overhead is also low: following Ambit with six compute rows, this layout requires seven isolation rows, adding only 0.68% row-count overhead per 1024-row subarray. Combined with CS-2 column screening, this layout effectively reduces the impact of PuDGhost (as we demonstrate using real DRAM chips in §10.1).

9.5. Path to Practical PuD Systems Our solutions significantly reduce the PuD computation errors (see §10.1). To further reduce residual errors toward practical deployment, PuD systems can combine our solutions with two complementary approaches: 1) PuD ECC schemes and 2) error-tolerant applications. First, PuD ECC research is advancing [42, 49]. For instance, Count2Multiply [42] proposes a lightweight ECC scheme that detects and corrects bit errors in PuD computations. Such ECC schemes for PuD can handle residual errors that remain after applying our mitigations. Second, several important PuD applications, such as deep neural networks (DNNs) [14] and genomic sequence search [55, 56, 208–210], have intrinsic error tolerance. For example, EDEN [14] enables DNN inference on approximate DRAM by retraining models for error resilience. These errortolerant applications can operate with sufficiently high accuracy even in the presence of some residual errors.

10. Case Studies This section evaluates on real DRAM chips: 1) our mitigations and their tradeoffs (§10.1), and their impact on 2) general matrix-vector multiplication (GEMV) (§10.2) and 3) true random number generation (TRNG) (§10.3).7

10.1. Impact of Mitigations on System Tradeoffs We evaluate PuD systems equipped with our column screening methods (§9.3) and compute row layout (§9.4) on real chips, focusing on data patterns and tradeoffs between reliability, throughput, and capacity overhead. Experimental Setup. Building on the mitigation techniques in §9.3 and §9.4, following prior work [47], we conduct a twostage experiment targeting MAJ3, the most fundamental PuD primitive.8 In Stage 1 (screening), each configuration is tested with 8192 samples of random MAJ3 inputs, and a column is labeled reliable only if it exhibits zero errors across all samples. In Stage 2 (execution), we target the columns that passed Stage 1 screening, mimicking how a PuD system would operate 7 To maintain reasonable testing time, we test three DRAM modules from different chip density and die revision pairs. 8 Since representative PuD architectures [23, 26, 30, 33, 38, 48] do not rely on Frac operations [46] to execute MAJ3, we also exclude Frac from our experiments. This ensures that MAJ3 errors caused by non-operand data can be attributed to its impact on SiMRA, rather than on Frac. We use 8-row SiMRA: each of the three operands is duplicated across two rows for redundancy, occupying six rows in total, and the remaining two rows store constant logic-0 and constant logic-1.

Results. Figure 20 shows the distribution across all tested modules of three metrics (a) CPR, (b) CBR, and (c) BER9 for the six configurations (x-axis). Without PuDGhost-aware mitigations (Base), columns that passed screening still exhibit a CBR of 2.1% and a BER of 9.2 · 10−5 on average, demonstrating that PuDGhost-unaware screening fails to filter out unreliable columns. Our best configuration (CS-2-1) improves CPR (i.e., throughput of PuD execution) by 1.06× compared to Base, while achieving 125× lower CBR and 91× lower BER on average. We estimate that this BER reduction translates to approximately 8.3 · 103 × lower ECC correction failure rate under the typical configuration of a prior PuD ECC study [42]. For CS-1, we observe no significant difference between CS-101 and CS-1-sweep, suggesting that screening with only two extreme patterns (all-zeros and all-ones) is sufficient to identify unreliable columns affected by interference from adjacent rows. Among CS-2 variants, CS-2-1 achieves the highest CPR, improving it by up to 1.15× over other CS-2 variants. Comparing CS-2-1 and CS-1-01, CS-2-1 achieves 1.14× higher CPR than CS-1-01, at the cost of capacity overhead due to isolation rows (§9.4), providing a trade-off between capacity and throughput. 9 Bar height represents the median, circles indicate the geometric mean,

and whiskers show the interquartile range.

CS-1-sweep 6 4 2 0

80 60 40

(b)

CS-2-0

CS-2-1

CS-2-check

(c)

10 4 10 5 10 6

Bit Error Rate

CS-1-01

(a)

Column Break Rate [%]

Cols Passed Screening [%]

100

Figure 20: Evaluation of column screening methods.

10.2. Application-Level Study: GEMV Kernel We evaluate the application-level impact of PuDGhost and the effectiveness of our mitigations (§9.3, §9.4) using general matrix-vector multiplication (GEMV), one of the primary target workloads for PuD [40–42, 49, 211]. Experimental Setup. We execute GEMV kernels on real DRAM chips using MAJ3, following prior PuD GEMV implementations [41]. We use randomly generated matrices with dimensions 4096 × N , where N ∈ {4, 8, 16, 32, 64} at 8-bit precision.10 For each configuration, we use 32,768 columns (i.e., 4096 × 8 bits) that passed the respective column screening. Configurations. We compare four configurations (see §10.1 for detailed screening methodology). 1) Base-rand uses the same PuDGhost-unaware configuration as Base in §10.1. 2) Base-worst represents a PuDGhost-unaware baseline designed to maximize the mismatch between screening and execution: data in adjacent rows is set to all-ones during Stage 1 but changes to all-zeros during Stage 2. 3) CS-1 adopts the CS-1-01 configuration. 4) CS-2 adopts CS-2-1. Results. Figure 219 shows the normalized mean squared error (NMSE) of GEMV output and the average MAJ3 BER for each configuration (x-axis). The first five subplots show NMSE for each matrix dimension (N ∈ {4, 8, 16, 32, 64}), and the sixth subplot shows the average MAJ3 BER. NMSE increases with larger N due to longer MAJ3 operation chains, which accumulate more errors. Without our mitigations, Base-worst NMSE reaches 2.2 · 10−2 at N = 16 and 5.8 · 10−2 at N = 64, demonstrating that PuDGhost can cause severe degradation in GEMV accuracy. Our mitigations reduce NMSE below 10−3 across all tested matrix dimensions. Compared to Base-rand, our mitigations (averaged over CS-1 and CS-2) reduce NMSE by 36× (N = 32) and 14× (N = 64), and BER by 55×. Compared to Base-worst, the reductions are 413× (N = 32) and 114× (N = 64) for NMSE, and 1.3 · 103 × for BER. 10 34 10 5 10 10 67 10 8 10 9 10 10 10

4096 × 4

10 2 10 3 10 4 10 5 10 6 10 7

Base-rand 4096 × 8 10 2 10 3 10 4 10 5

Base-worst CS-1 4096 × 16 10 1 4096 × 32 10 2 10 3 10 4

10 1 10 2 10 3 10 4

CS-2 4096 × 64

BER of MAJ3

10 2 10 3 10 4 10 5 10 6

BER

Configurations. We compare six configurations in three groups, which differ in how data in adjacent rows is managed across Stage 1 and Stage 2. 1) Base corresponds to PuDGhostunaware screening. In Stage 1, all adjacent rows store a single fixed random pattern. In Stage 2, adjacent rows are overwritten before each MAJ3 sample with a random pattern whose fraction of logic-1 is uniformly drawn from {0.0, 0.25, 0.50, 0.75, 1.0}, simulating unpredictable changes during runtime. CS-1 varies the data in adjacent rows during Stage 1 to identify columns that remain reliable across multiple patterns. 2) CS-1-01 divides Stage 1 screening into two halves: all-zeros and all-ones. 3) CS-1-sweep divides Stage 1 screening into five segments with fraction of logic-1 in {0.0, 0.25, 0.50, 0.75, 1.0}. We compare these two to test whether screening with only two extreme patterns (CS-1-01) is as effective as a finer-grained sweep (CS1-sweep). Stage 2 uses the same dynamically changing patterns as Base. CS-2 fixes the data in adjacent rows to the same pattern in both Stage 1 and Stage 2. 4) CS-2-0 uses all-zeros, 5) CS-2-1 uses all-ones, and 6) CS-2-check uses a checkerboard pattern. We test multiple patterns to identify which fixed pattern provides the best tradeoff between reliability and throughput.

Base

NMSE

using only reliable columns. We run 128 additional randominput samples on these columns. For each MAJ3 execution, we (i) write the designated data pattern to adjacent rows, (ii) write random inputs to the SiMRA rows, (iii) execute SiMRA, and (iv) read outputs from the SiMRA rows. We report three metrics. 1) Column Passing Rate (CPR) is the fraction of columns that pass Stage 1, which determines the effective throughput of the PuD system. 2) Column Break Rate (CBR) is the fraction of columns labeled reliable in Stage 1 that produce at least one error in Stage 2. 3) Bit Error Rate (BER) is the bit error rate of MAJ3 in Stage 2 among the columns that passed Stage 1 screening.

Figure 21: Effect of PuDGhost and our solutions on GEMV.

10.3. PuDGhost’s Impact on SiMRA-based TRNG We demonstrate the risks of designing SiMRA-based TRNG without accounting for PuDGhost on real DRAM chips. SiMRAbased TRNG exploits columns that exhibit non-deterministic outputs under fixed SiMRA input [44, 61, 67]. These columns, which we refer to as source columns, produce outputs that fluctuate due to metastability near the sensing threshold during charge sharing, serving as entropy sources for TRNG. We investigate how data in adjacent rows and data in non-source columns affect the entropy of source column outputs. 10 The performance advantage of PuD over processor-centric GEMV execution becomes more pronounced as N grows, since a larger N allows PuD to reduce more data transfer between DRAM and the processor [41].

Experimental Setup. To measure entropy under each condition, we collect 128 SiMRA output samples with fixed inputs throughout this experiment. We conduct a two-step experiment. In Step 1, following prior work [67], we search up to 100 candidate input patterns for the SiMRA rows to identify the pattern that maximizes the sum of Shannon entropy [61,67,71] across all columns, with data in adjacent rows fixed to a random pattern throughout. We then identify source columns that exhibit randomness under this pattern. In Step 2, we fix the input pattern found in Step 1 and measure the entropy of source columns while varying data in adjacent rows or non-source columns according to the conditions described below. Conditions. We define seven conditions for Step 2, which differ in what data is changed from Step 1. 1) Fixed is the baseline: data in adjacent rows and non-source columns remains identical to Step 1. This condition corresponds to our mitigation that fixes data in adjacent rows and non-source columns during TRNG operation. For adjacent-row interference, we modify only the data in adjacent rows from Step 1 while keeping all column data identical to Step 1: 2) Row-rand overwrites adjacent rows with freshly generated random data, 3) Row-0 with all-zeros, and 4) Row-1 with all-ones. For inter-column interference, we modify only the data in SiMRA rows of non-source columns from Step 1 while keeping source column inputs and data in adjacent rows identical to Step 1: 5) Col-rand sets them to random data, 6) Col-0 to all-zeros, and 7) Col-1 to all-ones. Results. Figure 22 shows the Norm. Entropy (y-axis), normalized to the entropy under the Fixed condition, for the six non-baseline conditions (x-axis), across different numbers of SiMRA rows (each subplot). Adjacent-row interference reduces entropy compared to Fixed. The worst case is Row-1, which reduces Norm. Entropy to 0.35 on average across the five activation counts. Inter-column interference causes even more severe entropy loss. The worst case is Col-1, which reduces Norm. Entropy to 0.07 on average, meaning that approximately 93% of the original entropy is lost. Col-0 and Col-rand also drastically reduce entropy to 0.12 and 0.15 on average, respectively. These results indicate that SiMRA-based TRNG designs that do not account for PuDGhost could unknowingly lose up to 93% of the entropy that is preserved under Fixed (i.e., our mitigation that maintains the same data in adjacent rows and non-source columns as used during the pattern search). Norm. Entropy (Fixed = 1.0)

Row-rand

Row-0

Row-1

Col-rand

Col-0

Col-1

2-Row Activation 4-Row Activation 8-Row Activation 16-Row Activation 32-Row Activation

1.00 0.75 0.50 0.25 0.00

Interference Condition

1.00 0.75 0.50 0.25 0.00

Figure 22: Impact of PuDGhost on the entropy of SiMRA-based TRNG for different numbers of SiMRA rows.

11. Related Work To our knowledge, this is the first experimental study demonstrating that non-operand data affects PuD computation results on real DRAM chips. DRAM Read Disturbance. Many works experimentally characterize read disturbance phenomena on real DRAM chips [65, 69, 81–84, 86–94, 150–158, 167]. RowHammer [81, 84, 93] is the most widely studied example: high-frequency activation of a

DRAM row causes bitflips in physically adjacent rows. Related phenomena include RowPress [82,88,151], which causes bitflips by keeping rows open for extended periods, PuDHammer [65], which induces bitflips through repeated PuD operations, and ColumnDisturb [83], a bitline-based read disturbance that can induce bitflips in cells sharing the same columns. Various works present efficient, wide-ranging attacks and sophisticated mitigations [77–167]. Multiple-Row Activation-based PuD Operations on COTS DRAM Chips. Prior work demonstrates PuD computations on COTS DRAM using multiple-row activation [41, 43–47, 50, 51, 54, 61–69, 76]. ComputeDRAM [50] performs MAJ3 and two-input AND and OR operations in DDR3 chips. FracDRAM [46] shows that DRAM cells in DDR3 chips can store fractional values. DRAM Bender [173, 174] (based on SoftMC [175, 176]) provides an FPGA-based infrastructure for conducting experiments on real DRAM chips by enabling direct, fine-grained control over DRAM commands. PiDRAM [43, 212] provides an FPGA-based framework for end-to-end system evaluation of PuD techniques. Prior work [61, 67, 68] executes SiMRA in DDR4 chips to generate true random number and physically unclonable functions. FC-DRAM [63] demonstrates up to 16-input Boolean operations by performing SiMRA on up to 48 rows in neighboring subarrays. PuDTune [47] proposes a methodology to improve the reliability of PuD operations on DDR4 chips using Frac operations. While these prior works on PuD using COTS DRAM report errors in PuD operations, none of them investigates interference from non-operand data that is not supposed to participate in PuD computations.

12. Conclusion We reveal PuDGhost, a new interference phenomenon in real DRAM chips where data in non-activated adjacent rows and columns that concurrently perform computations affects Processing-using-DRAM (PuD) computation results, violating the expectation that each column’s computation depends solely on its own operand data. Via rigorous experimental characterization using 96 real DDR4 DRAM chips, we present 15 new observations quantifying how non-operand data affects PuD computations. We propose and evaluate solutions to PuDGhost across multiple layers of the PuD computing stack. We hope our work motivates and guides solutions to enable future PuD systems that are robust.

Acknowledgments We thank the anonymous reviewers of ISCA 2026 for their valuable feedback. We also thank the SAFARI Research Group at ETH Zurich and the members of CASYS at UTokyo for providing a stimulating intellectual environment. We acknowledge the generous gifts from our industrial partners, including Google, Huawei, Intel, and Microsoft. This work is supported in part by the Semiconductor Research Corporation (SRC), the ETH Future Computing Laboratory (EFCL), and the AI Chip Center for Emerging Smart Systems (ACCESS), a Google Security and Privacy Research Award, the Microsoft Swiss Joint Research Center, JST CREST (JPMJCR21D2), JSPS KAKENHI (23H00467), and JST ACT-X (JPMJAX25CC).

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