Memory-Centric Computing: Security Benefits and Challenges of Processing-in-DRAM

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Memory-Centric Computing: Security Benefits and Challenges of Processing-in-DRAM

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Memory-Centric Computing: Security Benefits and Challenges of Processing-in-DRAM İsmail Emir Yüksel

F. Nisa Bostancı

Ataberk Olgun

Onur Mutlu

arXiv:2606.20786v1 [cs.CR] 18 Jun 2026

SAFARI Research Group ETH Zürich Today’s computing systems are processor-centric: they require frequent data movement between processing elements (e.g., CPU) and main memory (DRAM), leading to significant inefficiencies in performance and energy consumption. Memorycentric computing instead moves computation to the data, enabling computation capability in and near all places where data is generated and stored, and greatly reducing the performance and energy overheads of data access and data movement. This shift from a processor-centric to a memory-centric paradigm has important and underexplored consequences for system security. Turning memory from a dumb, inactive store into an active computing substrate introduces benefits as well as challenges for system security: it can provide new in-memory security primitives and also reduce data exposure, but it can also expose new attack surfaces. This work discusses the security benefits and challenges of memory-centric computing, specifically Processing-in-DRAM (PiD), a paradigm where the operational characteristics of a DRAM chip are exploited and enhanced to perform computation on data stored in DRAM. Specifically, we describe 1) new stateof-the-art DRAM-based true random number generators that provide up to 16.05 Gb/s throughput and physical unclonable functions with 5.75% lower evaluation latency than the prior state-of-the-art, both on off-the-shelf DRAM chips and 2) two key security challenges of PiD: amplified DRAM read disturbance (e.g., 158x reduction in the minimum number of DRAM accesses required to induce the first bitflip) and high throughput memory timing channels (e.g., a communication throughput of 14.8Mb/s). We believe it is time to design, use, and program DRAM, and in general memory, not as an inactive storage substrate, but as a combined computation, storage, and security substrate, where computational capability, storage density, and security are all key goals.

alytics, memory becomes an even larger performance, energy, robustness, and system scaling bottleneck in processor-centric computing systems [4, 6–37]. The memory-centric computing (MCC) paradigm [1, 2, 5, 38, 39] can fundamentally solve data movement bottlenecks. The key idea is to place computation mechanisms in or near where the data is stored (i.e., inside the memory chips, in the logic layer of 3D-stacked memory, in the memory controllers, inside large caches, inside storage units or inside sensing units), so that data movement between where the computation is done and where the data is stored is reduced or eliminated, compared to contemporary processor-centric systems [3, 4, 8, 17, 27, 28,30,34,37,40–122]. MCC can be implemented in (i.e., using or near) different memory technologies [1, 2, 5], including SRAM (e.g., [57, 58, 97–107, 123]), DRAM (e.g., [3, 4, 19, 22, 27–30, 34, 36, 37, 44–46, 48–53, 56, 60–63, 65, 71–78, 82, 84, 117–119, 124– 184]), NAND flash (e.g,. [20, 21, 68, 85–96, 185]), or emerging (e.g., [47, 54, 55, 64, 66, 69, 70, 80, 81, 83, 115, 186]). We focus on DRAM [187] due to its dominance as the main memory technology that can house large amounts of data. We broadly call MCC implemented in DRAM as Processing-in-DRAM (PiD). PiD greatly reduces the performance and energy overheads of data access and data movement, and provides other benefits, e.g., improving system security and reducing system complexity. PiD can improve system security by providing new inDRAM security primitives, reducing exposure of securitycritical data, and accelerating security workloads (e.g., fully homomorphic encryption (FHE) [101, 188–195]). A growing body of work demonstrates that real, unmodified commercial off-theshelf DRAM chips can provide two key security primitives: by carefully violating DRAM access timing parameters and taking advantage of the resulting characteristics of different DRAM cells (i.e., whether they always/never fail or fail randomly), it is possible to use DRAM to create physical unclonable functions (PUFs) and true random number generators (TRNGs) at high throughput and low latency [71–74, 82, 118, 196–218], accelerating secure computation (FHE). Unfortunately, PiD can also create new attack surfaces. Since PiD provides a direct, fast way to access and operate on memory, it can cause robustness (i.e., safety, security, reliability, availability) issues and unforeseen information leakage. Recent works demonstrate two such risks [219, 220].First, Processingusing-DRAM (i.e., using DRAM cells to perform computation) relies on multiple-row activation, where multiple rows are activated either simultaneously or in quick succession, which can exacerbate DRAM read disturbance vulnerabilities [221–223].

1. Security of Memory-Centric Computing Modern computing systems are processor-centric. In this paradigm, memory is treated as a dumb, inactive component: it serves the load and store requests of processing units (e.g., CPU, GPU, TPU, FPGA, ASIC), but cannot operate on the data it holds or manage itself. Computation can therefore happen only after data moves across the memory hierarchy to the processor. Such data movement is far more costly than computation, in terms of energy, latency, and bandwidth [1–5]. With the increasingly data-centric nature of contemporary and emerging applications such as generative artificial intelligence, large machine learning models, genome analysis, and video an1

Second, processing-in-memory provides direct main memory access to userspace applications such that they can bypass the cache hieararchy, which can be exploited to establish high throughput covert and side channels through the shared DRAM row buffer [220]. In this paper, we describe examples from both security benefits and security challenges of Processing-in-DRAM. For security benefits, we cover 1) the state-of-the-art DRAM-based TRNG, SiMRA-TRNG [118] and 2) the state-of-the-art DRAMbased PUF, SiMRA-PUF [218]. For security challenges, we cover 1) a recent experimental study on read disturbance effects of Processing-in-DRAM, PuDHammer [219], and 2) a set of high throughput main memory-based timing attacks that exploit the characteristics of Processing-in-DRAM, IMPACT [220]. We believe that the future of memory-centric systems is very bright and promising, yet many exciting challenges remain to be solved across the computing stack to enable their secure, widespread, and easy adoption.

TRNGs can benefit memory-centric systems: a low-latency, high throughput DRAM-based TRNG can enable memorycentric system applications to source random values directly within the memory itself, thereby enhancing the overall potential, security, and privacy of such architectures. Prior DRAM-based TRNG designs use DRAM data retention failures [196, 197], DRAM startup values [198, 199], and nondeterminism in DRAM command scheduling [201] to generate true random numbers. Unfortunately, these approaches do not fully satisfy these requirements because they either do not exploit a fundamentally non-deterministic entropy source (e.g., DRAM command scheduling) or are too slow for continuous high throughput operation (e.g., DRAM data retention failures, DRAM startup values). Recent works [71, 72, 118] enable high throughput, lowlatency true random number generation in commodity offthe-shelf DRAM chips by exploiting the failures induced by violating DRAM access timing parameters and activating multiple DRAM rows simultaneously. D-RaNGe [72] reduces the DRAM row activation latency below manufacturerrecommended specifications to induce activation failures and demonstrates that the resulting TRNG cells fail truly randomly. D-RaNGe [72] provides over two orders of magnitude higher throughput than the prior state-of-the-art DRAM-based TRNG at that time. QUAC-TRNG [71] activates four DRAM rows simultaneously, causing the bitline sense amplifiers to nondeterministically converge to random values, and achieves lower latency and higher throughput than D-RaNGe. The state-of-the-art DRAM-based TRNG, SiMRA-TRNG [118], generalizes quadruple-row activation [71] to simultaneous N-row activation [119], where N can be up to 32.

2. Security Benefits of Processing-in-DRAM: In-DRAM Security Primitives Secure computation is of critical importance in modern computing systems. Therefore, it is important for a memory-centric system to support fundamental security primitives that enable secure computation and security functions. Doing so would enable memory-centric systems to execute a wider range of workloads securely. We focus on two key security primitives that DRAM provides: 1) true random number generation and 2) physical unclonable functions.

2.1. In-DRAM True Random Number Generation

2.2. State-of-the-Art DRAM-based TRNG: SiMRA-TRNG

Random number generators (RNGs) are critical components in many different applications, including cryptography, scientific simulation, industrial testing, and recreational entertainment [224–236]. In particular, for modern cryptographic applications, a random number generator is critical to prevent information leakage to a potential adversary [229–237]. RNGs are broadly classified into two categories [238–241]: pseudo-random number generators (PRNGs) [242–246], which deterministically generate numbers starting from a seed value to approximate a true random sequence, and true random number generators (TRNGs) [71, 72, 74, 118, 196–201, 209, 229, 247–269], which generate random numbers by sampling nondeterministic physical phenomena. An effective TRNG must 1) produce truly random numbers, 2) provide a high throughput of random numbers at low latency, and 3) be practically implementable at low cost. DRAM offers a promising substrate for developing an effective and widely-available TRNG due to the prevalence of DRAM throughout all modern computing systems, ranging from microcontrollers to supercomputers. A high throughput DRAM-based TRNG would help enable widespread adoption of applications that are today limited to only select architectures equipped with dedicated high-performance TRNG engines. In addition to traditional computing paradigms, DRAM-based

Key Idea. Fig. 1 shows the command sequence for true random number generation using SiMRA, with eight DRAM cells connected to a bitline. Initially, four cells have a voltage level of VDD, the remaining four are at ground (GND), and the bitline has a voltage level of VDD/2. To generate random numbers, SiMRA-TRNG issues one ACT→PRE→ACT command sequence with reduced DRAM timings. Doing so activates the cells simultaneously and enables charge sharing between them and their bitline. Hence, the bitline voltage is perturbed by the simultaneously activated cells, where some try to pull up the bitline voltage, and the others try to pull it down. As a result, these opposing contributions of simultaneously activated cells can randomly perturb the bitline from the reference voltage. The sense amplifier then kicks in and tries to amplify the voltage on the bitline, which results in sampling a random value based on the random perturbations on the bitline voltage. Design. SiMRA-TRNG generates true random numbers using four banks in five steps: 1) selecting a high-entropy simultaneously activated row (SAR) group based on the characterization, 2) initializing the rows that are used to generate true random numbers by performing the RowClone operation [50, 56, 75, 119, 219] in quick succession, 3) performing 2

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streams for all tested numbers of simultaneously activated rows. SiMRA-TRNG designs based on 2-, 8-, 16-, and 32-row activation outperform the state-of-the-art DRAM-based TRNG (QUAC-TRNG, which uses 4-row activation), achieving up to 1.15×, 1.99×, 1.82×, and 1.39× higher throughput, respectively (Fig. 3). The 2-, 4-, 8-, 16-, and 32-row activation-based designs provide average throughputs of 9.90, 13.81, 16.05, 13.94, and 10.81 Gb/s, respectively. There is a tradeoff between TRNG latency and the entropy produced by SiMRA: while simultaneously activating more rows tends to generate more entropy, it also increases the TRNG latency, so the higher entropy of 32-row activation does not lead to higher throughput, because the latency of initializing the simultaneously activated rows is doubled compared to 16-row activation. SiMRA-TRNG outperforms the state-of-the-art DRAM-based TRNG in throughput and offers a promising approach to generating true random numbers with high throughput, directly inside real, unmodified COTS DRAM chips.

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ACT→PRE→ACT command sequence with reduced DRAM timings to activate the high-entropy SAR group, thereby generating random bits in the sense amplifiers of four DRAM banks concurrently, 4) reading from the four banks until 256 bits of Shannon entropy is obtained, and 5) post-processing the extracted bitstream using the SHA-256 cryptographic hash function [270] to eliminate bias & correlation. Real DRAM Chip Characterization. We conduct a rigorous experimental characterization of 96 COTS DDR4 chips using an FPGA-based DRAM testing infrastructure [271, 272] (built on top of SoftMC [273, 274]). We sweep the number of simultaneously activated rows, the data pattern, temperature, and spatial location, showing that SiMRA can generate random values with all the tested numbers of simultaneously activated rows. We highlight three new empirical observations from this experiment. First, entropy tends to increase with the number of simultaneously activated rows: across all tested chips, SiMRA generates 22.87, 25.17, 29.47, 34.54, and 40.41 average cache-block entropy with 2-, 4-, 8-, 16-, and 32-row activation, respectively (Fig. 2). Second, entropy also depends strongly on the data pattern, and is highest when the data pattern has an equal number of logic-1s and logic-0s. We hypothesize this is because during charge sharing, logic-1 cells attempt to raise the bitline voltage while logic-0 cells attempt to lower it; thus, the bitline voltage converges to the reference voltage, the differential voltage falls well below the sense amplifier’s reliable sensing margin, and the sense amplifier non-deterministically settles to logic-1 or logic-0. Third, temperature affects the SiMRA’s entropy. For example, for 32-row activation, as the temperature increases from 50 ◦ C to 90 ◦ C, average cache-block entropy decreases by 1.53×. Quality and Throughput. True random numbers generated by SiMRA-TRNG pass all NIST STS tests [275], and SiMRA-TRNG reliably produces high-quality true random bit-

2.3. In-DRAM Physical Unclonable Functions A physically unclonable function (PUF) maps a set of input parameters to unique, device-specific signatures that can be generated repeatably and reliably. The resulting signature reflects a device’s inherent, random physical variations introduced during manufacturing, which makes it practically impossible to predict or replicate without access to the device itself [276,277]. These characteristics enable PUFs to be frequently used in security applications, such as low-cost authentication against security attacks and prevention of integrated-circuit counterfeiting, typically through a challenge-response protocol in which a trusted server challenges a device and verifies its PUF response [197, 202]. A runtime-accessible PUF, i.e., one that an application can evaluate on demand during online operation, must additionally be evaluated with low latency and cause low system interference. DRAM-based PUFs are attractive for two key reasons. First, DRAM is already widely used in modern systems, ranging from embedded to server. Second, DRAM’s large address space provides a greater challenge-response space than smaller components such as SRAM. Prior DRAM PUF proposals exploit variations in DRAM start-up values, DRAM access latencies, and DRAM cell retention failures, and DRAM read disturbance to generate PUF responses [196–198, 202–212, 278]. Unfortunately, these proposals are unsuitable as runtime-accessible PUFs: start-up-value PUFs require a DRAM power cycle for every authentication, write-latency PUFs require additional circuitry in the DRAM chip, and retention-failure PUFs are too slow, taking on the order of minutes to evaluate at typical 3

operating temperatures. Recent works [73, 82, 217, 218] enable fast, reliable, runtimeaccessible PUFs even in modified and commodity off-the-shelf DRAM chips by exploiting the error patterns induced by violating DRAM access timing parameters. The DRAM Latency PUF [73] is a fast, reliable, runtime-accessible DRAM-based PUF whose key idea is to reduce the DRAM read access latency below the reliable manufacturer-recommended specifications. Doing so results in error patterns that reflect the compound effects of manufacturing variations in various DRAM structures (e.g., capacitors, transistors, sense amplifiers): some DRAM cells fail always after repeated accesses with violated timing parameters and some others never fail at all, and a combination of such consistently failing or never failing cells generates a unique identifier for the device. An experimental characterization of 223 LPDDR4 chips from all three major manufacturers shows that these error patterns are quickly generated (at 88.2 ms) irrespective of operating temperature, without any modification to the DRAM chip. Another line of work generates signatures by controlling DRAM’s internal circuitry and sensing cells at fractional voltage levels. CODIC [82] is a lowcost DRAM substrate that enables fine-grained control over four previously fixed internal DRAM signals, including those that trigger the sense amplifiers; by controlling when the sense amplifiers fire, CODIC senses cells at fractional voltage levels, and its CODIC-sig command generates digital signatures that depend on process variation. A CODIC-based PUF that uses these signatures provides 1.8× higher throughput than the best prior DRAM-based PUF at that time, with similar resilience to temperature changes and more repeatable responses. The Fracbased PUF [217], the prior state-of-the-art DRAM-based PUF, builds on top of CODIC to leverage fractional voltage levels on commodity off-the-shelf chips without any modification: it initializes a target row with all ones and repeatedly applies the Frac operation (back-to-back ACT→PRE command pairs with reduced timing) to drive the DRAM cells toward VDD /2, after which a subsequent activation resolves each cell to logic-0 or logic-1 according to the manufacturing process variation. The current state-of-the-art DRAM-based PUF, SiMRA-PUF [218], leverages simultaneous multiple-row activation to generate device-specific signatures and outperforms the Frac-based PUF in evaluation latency, which we describe in detail next.

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slightly different from, the reference voltage. The sense amplifiers then resolve the bitlines to logic-0 or logic-1: for some bitlines, the perturbation falls below the reliable sensing margin and the sense amplifier resolves the bitline randomly across SiMRA trials, whereas for others the perturbation exceeds the margin and the sense amplifier resolves the bitline to a single, stable value across trials. These stable, device-specific bits form the signature. Challenge and Response. SiMRA-PUF defines each challenge as a (bank, subarray) pair. To generate a response, it initializes a simultaneously-activated-row (SAR) group with a balanced data pattern, issues an APA command sequence, and reads the sense amplifier outputs as the signature; the PUF response is the signature read from the selected SAR group. Real DRAM Chip Characterization. SiMRA-PUF is characterized on 112 COTS DDR4 chips (from 10 modules), using the intra-Jaccard index (response stability, higher is better) and the inter-Jaccard index (response uniqueness, lower is better). SiMRA-PUF provides average inter-Jaccard indices of 3.98%, 2.37%, 3.44%, 2.92%, and 3.24%, and average intra-Jaccard indices of 89.02%, 89.81%, 93.03%, 94.06%, and 94.86%, for 2-, 4-, 8-, 16-, and 32-row activation, respectively (Fig. 4). SiMRAPUF thus produces unique and repeatable responses across all tested activation counts. Comparison with the Prior State-of-the-Art. SiMRAPUF provides intra-Jaccard indices similar to the Frac-based PUF [217] (95.62%), with the gap narrowing as the number of simultaneously activated rows increases. Most importantly, 2-row activation-based SiMRA-PUF has 5.75% lower evaluation latency than the Frac-based PUF, although evaluation latency grows with the number of activated rows. For example, 32-row activation reaches 3.84× the latency of Frac-based PUF [217]. These results show that SiMRA generates device-specific signatures suitable for high-quality, reliable PUF responses, and that 2-row SiMRA-PUF achieves lower evaluation latency than the prior state-of-the-art DRAM-based PUF, directly on real, unmodified COTS DRAM chips.

2.4. State-of-the-Art DRAM-based PUF: SiMRA-PUF Key Idea. The key idea of SiMRA-PUF is to generate devicespecific signatures by exploiting the charge-sharing process that arises from simultaneously activating multiple DRAM rows holding opposing data patterns. An ACT→PRE→ACT (APA) command sequence with reduced timings simultaneously activates multiple rows initialized with a balanced data pattern, enabling charge sharing between the activated cells and the bitlines. Because the cells hold opposing values, the resulting bitline perturbation does not strongly deviate from the reference voltage. However, due to process- and designinduced variations, each bitline settles at a voltage near, but

3. Security Challenges in Processing-in-DRAM As a new processing paradigm, Processing-in-DRAM introduces new security considerations related to its integration in real-world computing systems. We focus on two of them, one affecting reliability and one affecting confidentiality. First, modern DRAM is subject to read disturbance, a worsening safety, security, and reliability phenomenon in which 4

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repeatedly accessing one DRAM row induces bitflips in physically nearby, unaccessed rows [39, 219, 221–223, 271, 279–304]. RowHammer [221] and RowPress [222] are two prominent examples, where a row (victim row) experiences bitflips when a nearby row (aggressor row) is repeatedly activated (hammered) or kept open for a long period (pressed). Since PuD operations rely on multiple-row activation, where multiple DRAM rows are activated simultaneously or in quick succession, they can exacerbate DRAM read disturbance, as PuDHammer [219] shows. Second, the adoption of processing-in-memory provides applications with a new, direct, and fast way to access main memory, which malicious applications can exploit. Naively providing such access may lead to unforeseen information leakage and other confidentiality and integrity issues. In particular, it opens high throughput timing attack vectors that are hard to mitigate without significant performance overhead, as IMPACT [220] shows.

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across 60 five-core multiprogrammed workloads, showing that extending existing RowHammer defenses to PuD is costly and that read-disturbance-resilient PuD systems call for new solutions.

3.2. Timing Attacks in Processing-in-DRAM: IMPACT IMPACT [220] is a set of high throughput main memory-based timing attacks that leverage characteristics of processing-inmemory (PiM) architectures to establish covert and side channels. Key Idea. The adoption of PiM provides userspace applications with fast and reliable direct access to main memory that bypasses the cache hierarchy. IMPACT observes and exploits the shared DRAM row buffer: because a row-buffer conflict takes measurably longer than a row-buffer hit, an application can infer whether a row was recently accessed by timing its accesses. IMPACT achieves high throughput by (i) eliminating the expensive cache-bypassing steps required by processorcentric timing attacks and (ii) leveraging the intrinsic parallelism of PiM operations. Attacks. IMPACT is demonstrated with three case studies. First, IMPACT-PnM is a covert channel that exploits PiMenabled instructions [28], a PnM mechanism that executes simple operations in compute units near DRAM: the sender encodes a message as row-buffer conflicts at selected addresses, and the receiver detects them by timing how long a PiMenabled instruction takes to operate on those rows. Second, IMPACT-PuM is a covert channel that instead exploits RowClone [50], a PuM operation that performs bulk in-DRAM row copy: the sender transmits bits by copying rows in different DRAM banks in parallel, and the receiver decodes them by issuing its own row-copy operations and measuring their latency. Third, IMPACT’s side-channel attack uses PiM-enabled instructions to leak the private information of a concurrentlyrunning application by observing its memory access patterns. IMPACT side channel attack is demonstrated on a genomic privacy proof-of-concept attack, where the attacker leaks private characteristics of a user’s query genome by observing the memory access patterns of a read mapping application. Example: the IMPACT-PuM Covert Channel. We use IMPACT-PuM to illustrate IMPACT’s end-to-end flow (Fig. 6). Before the attack, the sender and receiver co-locate their data in the same set of DRAM banks. The sender then transmits the message in M -bit batches: it maps each bit of a batch to a separate DRAM bank and builds a mask, so that a single

3.1. Read Disturbance Effects of Processing-using-DRAM: PuDHammer PuDHammer [219] presents the first experimental characterization of the read disturbance effects of Processing-using-DRAM (PuD) operations, on 316 real DDR4 chips from four major manufacturers. Key Idea. PuD operations leverage an analog DRAM operation called multiple-row activation, where multiple DRAM rows are activated simultaneously or in quick succession. PuDHammer characterizes the read-disturbance effects of its two types: consecutive multiple-row activation (CoMRA), used for in-DRAM data copy & initialization, and simultaneous multiple-row activation (SiMRA), used for in-DRAM bitwise operations. To hammer with CoMRA, PuDHammer repeatedly performs consecutive activation of a source and a destination row; to hammer with SiMRA, it issues an ACT→PRE→ACT command sequence with reduced DRAM timings to simultaneously activate multiple rows. In both cases, the activated rows become aggressor rows and their neighboring rows become victim rows; when two activated rows sandwich a victim row, this forms a double-sided attack. Takeaway from Real DRAM Chip Characterization. Both CoMRA and SiMRA greatly increase a DRAM chip’s readdisturbance vulnerability, decreasing the minimum hammer count required to induce the first bitflip (HCf irst ) in all tested DRAM chips from four manufacturers. The effect is strongest for SiMRA: across all tested chips, the lowest HCf irst observed with double-sided SiMRA is up to 158.58× lower than with double-sided RowHammer (Fig. 5), while the lowest HCf irst with double-sided CoMRA is up to 13.98× lower than with double-sided RowHammer. PuD operations thus make a DRAM chip far more vulnerable to read disturbance than conventional read disturbance access patterns (e.g., RowHammer). Mitigation. PuDHammer adapts and evaluates the industry’s state-of-the-art RowHammer mitigation, Per-Row Activation Counting (PRAC) [305], and finds that the adapted PRAC solution incurs an average system performance overhead of 48.26% 5

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We firmly believe that it is time to architect principled computing systems where DRAM (and in general, memory; see [1, 2, 5] for a broad discussion) is designed, used, and programmed not as an inactive storage substrate, but instead as a combined computation, storage, and security substrate where computational capability, storage density, and security are key goals. Although many challenges remain to enable widespread adoption of Processing-in-DRAM (and memory-centric systems in general), we believe the mindset and infrastructure shift necessary to enable such a secure computation-storage paradigm remains to be the largest challenge. Overcoming this mindset and infrastructure shift can unleash a fundamentally more secure, energy-efficient, and high-performance way to design, use, and program computing systems. We therefore believe the future of memory-centric systems is very bright and promising, yet there needs to be many exciting challenges to be solved across the computing stack to facilitate widespread and easy adoption.

RowClone (S_src, S_dst, mask)

Receiver Figure 6: PuM covert-channel attack flow (IMPACT-PuM).

RowClone operation transmits an entire M -bit batch in parallel (where M is the number of banks). To send a 1, the sender triggers RowClone in the corresponding bank, activating a different row from the receiver’s and causing interference; to send a 0, it issues no RowClone and does not interfere. The receiver decodes the batch by issuing one RowClone operation per bank and measuring its latency: a high latency indicates a row-buffer conflict (logic-1), and a low latency indicates a row-buffer hit (logic-0). Result. IMPACT-PuM achieves a communication throughput of 14.8 Mb/s, 6.5× higher than the state-of-the-art main memory-based covert channel, and the side-channel attack on genomic read mapping leaks the private characteristics of a user’s query genome at 7.6 Mb/s with 96% accuracy. Mitigation. IMPACT evaluates four defense mechanisms that attempt to eliminate the timing channel, but finds that mitigating IMPACT incurs high performance overheads, concluding that more research is needed to find low-overhead solutions.

Acknowledgments We thank the SAFARI Research Group members for providing a stimulating intellectual and scientific environment. We acknowledge the generous gifts from our industrial partners, including Google, Huawei, Intel, and Microsoft. This work, along with our broader work in Processing-in-Memory and memory systems [1,2,5,8,17,35,38,39,221,284–286,306–321], is supported in part by the Semiconductor Research Corporation (SRC), the ETH Future Computing Laboratory (EFCL), ACCESS – AI Chip Center for Emerging Smart Systems, a Google Security and Privacy Research Award, and the Microsoft Swiss Joint Research Center.

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