arXiv:2606.23548v1 [physics.acc-ph] 22 Jun 2026
S UPER C OND -GNN: S CALABLE G RAPH N EURAL N ETWORK S URROGATE FOR S UPERCONDUCTING C IRCUIT S IMULATIONS
Nandana Menon Acclerator Technology & Applied Physics Division Lawrence Berkeley National Laboratory Berkeley, CA [email protected]
Giorgio Vallone Engineering Division Lawrence Berkeley National Laboratory Berkeley, CA [email protected]
June 23, 2026
A BSTRACT This paper presents SuperCond-GNN, a graph neural network-based surrogate model for predicting the voltage distribution in high-temperature superconducting (HTS) magnets. HTS magnets are modeled as lumped-element equivalent circuits and mapped onto graph representations, enabling message passing GNNs to learn the electrical response as a function of circuit topology, material properties, and operating current. As a proof of concept, tape stacks of up to 10 tapes are considered across a range of circuit topologies and operating conditions. The surrogate is trained on data generated from circuit simulations and achieves a mean MAPE of 4.3% within the prescribed design space. The predicted nodal voltages enable fast and scalable inference of current redistribution and local operating conditions across a wide range of circuit configurations. The effect of incorporating physicsinformed regularization via Kirchhoff’s current law is also evaluated, and generalizability to unseen topologies is assessed through zero-shot inference and few-shot fine-tuning. While demonstrated on tape stack circuits, the graph-based framework is topology-agnostic and naturally extensible to more complex HTS cable and magnet configurations, offering a scalable alternative to conventional circuit solvers for downstream applications such as design space exploration, current sharing analysis, and real-time magnet monitoring.
1
Introduction
High-temperature superconducting (HTS) magnets based on REBCO conductors offer unprecedented performance for accelerator, fusion, and high-field applications, but protecting them remains a major challenge. Because slow normal-zone propagation and high heat capacity severely limit the effectiveness of conventional protection strategies [1], voltage-based detection systems often identify a quench only after it has already occurred. This delay leaves magnets vulnerable to damage from localized heating and high voltages. Additional complications arise current sharing in cable and coil systems which is governed by a complex interplay of termination resistance, contact resistance, conductor non-uniformity, local defects, magnet history, and architecture-dependent redistribution pathways. Together, these factors can delay quench onset and make global voltage-current characteristics exceedingly difficult to interpret at the global magnet level. Transitioning from reactive to predictive protection requires both improved sensing and real-time models capable of capturing the magnet’s state to anticipate failure. This need motivates the broader goal of developing an AI-enabled, physics-informed digital twin [2] for the diagnostics, protection, and control of HTS magnet systems. A critical first step toward this framework is the ability to reproduce relevant electromagnetic behavior at the cable or subscale level with high fidelity and computational efficiency. Currently, lumped-element circuit models implemented in SPICE simulators are a standard tool for understanding and predicting these behaviors in both steady-state [3–5] and transient [6, 7] regimes. Given accurate parameter measurements, they can reliably predict real device behavior [5,6]. Yet, scaling these models from individual tapes to cables and full magnets drastically increases circuit complexity and simulation cost. Parametric studies compound this issue by requiring thousands of individual simulations. Consequently, SPICE-based
A PREPRINT - J UNE 23, 2026
Figure 1: (a) Circuit model for tape stack cable with nt REBCO tapes, each divided into mt segments. The contact resitances between the tapes are denoted by Rci,j . Rtini and Rtouti are the termination resistances. (b) Heatmap showing the number of variables as nt and mt are varied.
models lack the scalability needed to serve as real-time estimators in a digital twin environment. Furthermore, GPUaccelerated implementations like CUSPICE [8] are restricted to linear circuit components, making them insufficient for accurately representing superconducting circuits. A widely adopted strategy for accelerating simulations and augmenting experiments is the use of machine-learningbased (ML) surrogates, an approach that has proven highly effective across numerous domains. In the context of HTS magnets, existing work has focused primarily on forecasting models for quench detection from experimental sensor signals [9, 10]. Despite these advances, relatively little work has addressed true physics surrogates capable of real-time deployment within a broader digital twin framework. Xiao et al. [11] represent the closest effort in this direction, developing an FEM surrogate to predict current density distributions in REBCO solenoids. However, conventional architectures such as feedforward neural networks employed in [11] operate on fixed-dimensional input spaces, requiring the entire magnet or its circuit representation to be encoded into a vector of predetermined size. Consequently, such surrogate models are inherently design-specific, trained for a fixed magnet topology and capable only of interpolating within the parameter space seen during training. From a circuit model perspective, this is a fundamental limitation since the number of components varies with design and hence raises a natural question: how should the circuit be represented such that a surrogate can generalize across variable-size configurations and learn the underlying physical behavior? This limitation becomes evident even in fundamental scenarios, such as simulating the transport measurement of a single REBCO tape. Assuming a highly simplified, lumped-parameter model, the necessary inputs to predict the measured voltage (V ) are restricted to the applied transport current, terminal resistances (Rt ), critical current (Ic ), and power-law exponent (n). While a conventional neural network can be trained on a design-of-experiments dataset to map this fixed input space to the resulting voltage, its rigid architecture fundamentally breaks down when scaling. Extending this model to a stack of two tapes alters the required input dimensionality by introducing an entirely new set of Ic and n values, alongside contact resistances (Rc ) that dictate current sharing between the tapes. Furthermore, achieving high-fidelity simulations requires discretizing the tapes into segments to capture localized spatial variations in Ic and n, as well as the distributed influence of their contact. Figure 1(a) illustrates the resulting electric circuit model for an nt -tape stack divided into mt segments. As shown in Figure 1(b), the total parameter space grows rapidly with the addition of tapes and segments, even when restricted to steady-state circuit parameters (Rt , Rc , transport current Iin , Ic , and n). This dimensional scaling becomes even more severe for complex geometries, such as CORC cables, which necessitate the inclusion of winding pitch and tape radius [6, 12]. Consequently, employing a conventional neural network would require either imposing an arbitrary maximum circuit size to fix the input dimensionality, or training a separate model for every distinct geometry. Neither approach is practical or generalizable. Additionally, omitting parameters to artificially enforce a fixed input size is physically unsound, as nodal voltages depend on the global interaction of all circuit elements. Ultimately, the inherently variable dimensionality of superconducting circuit models renders standard neural networks unsuitable as generalizable surrogates for these systems. Graph neural networks (GNNs) overcome this limitation by operating directly on graph-structured data composed of nodes and edges. Through permutation-invariant aggregation over node and edge feature spaces, GNNs can process graphs of arbitrary size without architectural modification, requiring only that the node and edge features lie within a fixed feature space irrespective of the number of nodes or edges. By employing message passing mechanisms to learn relationships between components, GNNs enable predictions at the node, edge, or graph level, making them a natural fit for a truly generalizable circuit surrogate. GNNs have been broadly adopted across diverse domains, including drug discovery, recommendation systems, traffic forecasting, and materials property prediction. In high-energy physics, 2
A PREPRINT - J UNE 23, 2026
GNNs have seen widespread use in charged-particle tracking, real-time data filtering and compression, and particle-flow reconstruction [13]. In electronics, their use has been comparatively limited, with most applications concentrated in digital and analog circuit design. More recently, GNNs have been applied to graph-level regression for predicting circuit performance metrics [14]. Most pertinent to the present work is the study by Hakhamaneshi et al. [15], who employed a deep graph convolutional network to predict DC nodal voltages in resistor-based and operational-amplifier circuits. Beyond demonstrating node-level prediction accuracy, their work showed that GNN generalizability extends to few-shot learning scenarios where a model pretrained on smaller circuits could be successfully transferred to larger, unseen topologies through fine-tuning on a substantially reduced dataset. This finding is particularly relevant to the present work, where generalization across variable circuit sizes is a primary objective. This work presents SuperCond-GNN (SC-GNN), a graph neural network (GNN)-based surrogate model for predicting the steady-state behavior of HTS magnets and cables represented as lumped-element circuit models. By representing the circuit as a graph, SC-GNN naturally accommodates variable topologies and sizes without retraining or architectural modification, addressing a fundamental limitation of conventional surrogate approaches. As a proof of concept, REBCO tape stack cables are considered, which capture the essential current-sharing and nonlinear resistive behavior characteristic of practical HTS systems. The target quantity of interest is the nodal voltage distribution, which is the natural output of circuit simulations as well as measurements. Predicting these voltages is directly relevant to voltage-based quench detection systems, representing a key step toward the ultimate goal of integrating this surrogate within a real-time digital twin framework for HTS magnet protection. The key contributions of this work are: (i) a graph-based circuit representation for HTS tape stacks enabling topology-agnostic surrogate modeling, (ii) a physics-informed GNN trained with Kirchhoff’s current law (KCL) regularization, (iii) comprehensive benchmarking against ngspice across the full topology space, and (iv) an assessment of zero-shot and few-shot generalizability to out-of-distribution circuit configurations.
2
Methodology
2.1
Electric-circuit model of tape stack cable
The circuit model employed in this work is the 2D network model developed by Martínez et al. [3] for steady-state simulation of a tape stack cable consisting of nt REBCO tapes. Each tape is divided into mt segments, such that the conductor is represented as a serial chain of current-dependent voltage sources governed by the power law relation describing the current-voltage characteristics of an HTS conductor: ni,j Ii,j Vi,j (Ii,j ) = Vc (1) Ici,j where i and j denote the tape and segment indices, respectively, Ii,j is the current flowing in that element, Ici,j is the critical current, and ni,j the n-value for that element. The criterion voltage Vc is derived from the standard electric field criterion of 1 µV/cm, applied under the assumption that each tape has a total length of 10 cm divided into equal segments. All tapes within the stack are assumed to be of equal length. Therefore, each element SCi,j in Figure. 1(a) represents the aforementioned voltage source. Circuits are simulated using DC analysis in ngspice [16], an open source SPICE simulator, with no time dependence. The transport current is ramped to a target value, Itarget = 0.8 × nt Ic , that captures the transition of the stack while ensuring numerical convergence of the nonlinear solver [17]. Nodal voltages are then extracted from the solver to produce V − I curves characteristic of short sample tests of such conductors. 2.2
Graph representation of circuits for GNNs
While circuits are natural graph representations, for the purpose of adapting them to GNNs, selecting an appropriate form graph representation is critical. In the context of GNNs, a graph, G, is defined by a set of nodes, V , and a set of edges, E, encoding the pairwise relationships between them, i.e., G = (V, E). Each node is associated with a feature vector while edges may or may not be. Unlike more established application domains, no unified convention currently exists for encoding electrical circuits as graphs for GNN. The most intuitive and physically grounded approach follows classical graph theory, in which circuit nodes map to graph nodes and circuit elements map to edges [18], and this convention is adopted here in preference to alternative representations [14, 15]. Each node and edge is then assigned a set of features encoding its physical and topological information. Two binary node features are defined to encode boundary conditions which identifies whether a node serves as the ground reference, or the terminal at which the external current is injected. Together, these features identify the boundary points of the circuit. The ground node also serves as a node whose voltage is known a priori. To encode topological information, three additional features are introduced: normalized degree of the node, normalized distance from the 3
A PREPRINT - J UNE 23, 2026
Table 1: Summary of node and edge features used in the graph representation of the HTS tape stack circuit model. Categorical features are binary indicators encoded as one-hot vectors, while numeric features are continuous physical quantities passed directly as scalars.
Index 1 2 3 4 5 6 7 8
Node feature Ground node Input node Normalized node degree Normalized ground distance Normalized current source distance – – –
Type Categorical Categorical Numeric Numeric Numeric – – –
Edge Features Resistor Superconductor Current source R Ic n Iin Iin /Ic
Type Categorical Categorical Categorical Numeric Numeric Numeric Numeric Numeric
ground and normalized distance from the current source. The normalized degree captures the local connectivity of a node, while the latter two features convey global structural information by quantifying the node’s distance from the ground node and the current-injection node, respectively, thereby characterizing the overall current-flow path through the circuit. These distances are computed via breadth-first search (traversing along segments within a tape rather than across tapes) originating from the ground node or the current-injection node and are subsequently normalized by the maximum distance observed in the graph. Edge features encode the physical properties of the components in the circuit. These features must capture both the element type and its associated electrical parameters. The circuit elements are one-hot encoded (binary vector representation in which a single entry is set to one to indicate the element type and all others are set to zero) to identify if it is a resistor, superconducting element or the current source. Depending on the element type, the corresponding physical parameters are then populated. For resistive elements, which include contact resistances and terminal resistances, the associated resistance value is recorded. For the current source, the input current magnitude Iin is recorded. For superconducting elements, the critical current Ic , the power-law exponent n, and the normalized operating ratio Iin /Ic are specified, where the latter provides a dimensionless measure of how close the element is to its critical current and thus captures its nonlinear operating regime. All unused parameter fields for a given element type are set to zero. Each edge is, therefore, described by an eight-dimensional feature vector jointly encoding the element type and its governing physical parameters. The features are summarized in Table. 1. Figure 2 illustrates the graph representation of a circuit, where panel (a) shows the schematic and panel (b) shows the corresponding graph. Panel (c) shows the node and edge feature matrices of the graph. Connectivity is defined using a Coordinate List (COO) format, where each edge is represented as a pair of node indices. Since edges are undirected to reflect the mutual relationship between circuit components, each coordinate pair appears twice in the COO table, once for each direction. An ablation study justifying the choice of input features is provided in Appendix A. 2.3
Model architecture
The surrogate model in this study, SuperCond-GNN (SC-GNN), is based on the MeshGraphNet architecture [19] originally developed for learning mesh-based simulations. The architecture consists of three stages: an encoder that projects raw node and edge features into a shared latent space, a processor that performs iterative message passing to propagate information across the graph, and a decoder that maps the updated latent node representations to the target output, in this case, the nodal voltages. In the encoding stage, the node feature vector and edge feature vector are each independently projected into a common hidden dimension dh through dedicated two-layer multilayer perceptrons (MLPs) with ReLU activation and layer normalization. This shared dimensionality enables the subsequent processor layers to operate uniformly over node and edge representations regardless of the original feature sizes. The processor consists of L sequential message-passing layers, each of which simultaneously updates both edge and node latent representations. Within each processor layer, the edge update is performed first. For every edge (i, j), the latent features of the source node hi , the destination node hj , and the current edge embedding eij are concatenated and passed through the edge encoder to produce an updated edge embedding. A residual connection is applied by adding the input edge embedding to the MLP output, yielding e′ij = M LPedge ([hi ∥hj ∥eij ]) + eij . Following the edge update, messages are constructed for each edge by concatenating the neighboring node features hj with the updated edge features e′ij . These messages are aggregated at each destination node using a summation operator, producing a fixed-size 4
A PREPRINT - J UNE 23, 2026
Figure 2: Graph representation of a tape stack circuit model with two tapes without any discretizations. (a) Schematic of a 2 × 1 tape stack, comprising terminal resistances Rtin and Rtout , superconducting elements SC11 and SC21 , and contact resistances Rc11 and Rc12 , driven by a transport current Iin . (b) Corresponding graph representations, where circuit nodes (red) and elements (green edges) map directly to graph nodes and edges respectively. (c) The associated node feature matrix, edge feature matrix, and COO-style edge index, where each edge appears twice to reflect the undirected connectivity of the graph.
aggregated message vector for each node irrespective of its degree. The aggregated messages are then concatenated with the node’s own latent features and passed through the node encoder. A residual connection is again applied, so the updated node representation is h′i = M LPnode ([hi ∥mi ]) + hi , where mi denotes the aggregated incoming messages at node i. The residual connections in both the edge and node updates stabilize training and facilitate gradient flow through the processor layers. Finally, since the objective here is to predict nodal voltages, the SC-GNN formulation operates at the node level, with the ground node masked out since its voltage is a known constant of 0 V. While graph-level predictions were also explored to directly obtain cable-level V-I characteristics, node-level predictions are more informative, as they provide spatially resolved voltage distributions across the circuit which are essential for protection-based system development where localized fault detection and response are critical. After L rounds of message passing, the final latent node embeddings are passed through a decoder MLP consisting of three linear layers with ReLU activations between the first two and no activation on the final layer, allowing the output to span the full range of physically meaningful voltage values. The decoder produces a scalar output per node corresponding to the predicted nodal voltage. The model is trained using a scale-normalized mean squared error (MSE) loss. Since nodal voltages in superconducting circuit simulations are typically sparse and concentrated near zero, raw MSE can vary significantly across batches, which leads to vanishing gradients and poor optimization. For the design space considered in this work, target values lie in the range (0, 10−5 ), determined by the critical electric field Ec = 1 µV/cm and the tape length of 10 cm. Normalizing the MSE by the squared mean absolute target value therefore ensures stable and well-conditioned training. A mask is applied to exclude nodes whose voltages as boundary conditions (ground node) from the loss Pare prescribed vˆi −vi 2 1 computation. The loss is computed as Ldata = M ) , where M is the set of non-ground nodes, vˆi and vi ( i∈M sP 1 are the predicted and target voltages respectively, and s = M i∈M |vi | is the scaling factor equal to the mean absolute target voltage over the masked nodes. 2.4
Physics-based loss
To enforce physical consistency in the model predictions, a physics-informed loss term based on Kirchhoff’s Current Law (KCL) is incorporated alongside the data-driven regression loss. This term penalizes violations of current conservation at each node. The current at each node is calculated using the predicted nodal voltages and the known constitutive relations of each circuit element. The voltage difference across each edge is computed from the predicted nodal voltages. Element-wise currents are then derived according to the governing relation for each element type, i.e., Ohm’s law I = V /R for resistive elements, and the prescribed source current for current source elements. 5
A PREPRINT - J UNE 23, 2026
Figure 3: Supernode merging for KCL residual calculation. On the left is a schematic of a 2 × 1 tape stack with superconducting elements connecting nodes n2–n3 and n4–n5. When Iin results in a current through the branches that is below the critical current of both SC11 and SC21 , the voltage drop across each superconducting element is approximately zero, making n2 and n3 electrically equivalent, and similarly n4 and n5. The supernode merging exploits this equivalence by combining such node pairs, producing the reduced circuit shown on the right.
Superconducting elements require fundamentally different treatment because their constitutive relation V = Vc (I/Ic )n cannot be directly inverted to obtain current from voltage in a numerically stable manner. For a resistor, the mapping from voltage to current is linear and bijective, yielding a unique and well-defined current for any voltage difference. For a superconductor operating in the sub-critical regime, however, the voltage across the element is vanishingly small because a large range of currents from zero to nearly Ic all produce near-zero voltages when raised to a high power-law exponent n. Inverting the relation to obtain I = Ic (V /Vc )1/n is therefore severely ill conditioned. Minute differences in the predicted voltage map to extremely different currents, and the gradient of the inverse with respect to voltage becomes vanishingly small, providing almost no useful learning signal to the network. To circumvent this, superconducting elements that are operating in the near-zero voltage regime are handled via a “supernode merging” procedure. Specifically, if the predicted voltage difference across a superconducting edge falls below a threshold voltage, εSC (set to 0.01 · Vc ), the two nodes connected by that edge are treated as electrically equivalent and merged into a single “supernode”. This reflects the physical reality that a superconductor carrying sub-critical current behaves as an ideal short circuit, imposing equal potential at both terminals. Prior to the KCL evaluation, the edge list is filtered to unique directed edges with a fixed current flow convention, such that the source node always has a smaller index than the target node, i.e. u < v (except the edge between ground node and current input node). The supernode merging therefore becomes a direct node reassignment. First, a supernode mapping ϕ : i 7→ i is initialized such that every node represents itself. For each short-circuited superconducting edge (u, v), i.e. the Vu,v < εSC , the target node is redirected by setting ϕ(v) = u, so that both nodes share the same representative. Once the map ϕ is fully constructed, every node appearing in the edge list is replaced by its supernode representative such that source node u becomes ϕ(u) and target node v becomes ϕ(v). This process is schematically descirbed in Figure. 3. KCL residuals are then accumulated at the supernode level rather than the individual node level. The ground node is excluded from the residual by construction, since its voltage is a fixed boundary condition. The KCL residual at each node (or supernode) i is, therefore, defined as ri = Iout,i − Iin,i
(2)
where the first part is the sum of currents leaving node i and the second collects currents arriving. The residuals are normalised by the mean source current Iavg present in the circuit to make the loss dimensionless and comparable across circuits of different operating scales. The physics-based loss is then the mean squared normalised residual over all non-ground nodes: Lphysics =
1 X M
i∈M
ri Iavg
2 (3)
This term is added to the primary regression loss with a tunable weight λ, giving the combined training objective L = Ldata + λLphysics . Since model predictions are largely random in the early epochs of training, the KCL residuals can be arbitrarily large and the physics loss can dominate the total loss, obscuring the regression signal. To mitigate this, the physics loss is only introduced after an initial training phase of fixed epochs, once the network has learned a basic fit to the data. 2.5
Dataset generation
Training a supervised surrogate model requires a dataset of input-output pairs generated by running the underlying simulation across a well-define representative range of circuit configurations and parameters. The training dataset 6
A PREPRINT - J UNE 23, 2026
Table 2: Design space for circuit parameters.
Variable nt mt Rt (Ω) Rc (Ω) Ic (A) n
Range 1–10 1–6 [10−9 , 10−8 ] [10−9 , 10−8 ] [100 , 500] [10, 25]
is constructed from a mixed discrete–continuous design space. A full factorial grid is employed over the discrete variables (nt , mt ), while the remaining circuit parameters are sampled randomly. The parameter domain is summarized in Table 2. Ranges for the parameters are selected from typical values observed in literature [3]. Additionally, for every (nt , mt ) pair, K independent samples of the continuous parameters are drawn from uniform distributions over their respective ranges: ∀(nt , mt ) ∈ {1, . . . , 10} × {1, . . . , 6}, (k)
i.i.d.
{Rt , Rc(k) , Ic(k) , n(k) }K k=1 ∼
(4)
U(10−9 , 10−8 ) × U (10−9 , 10−8 ) × U (100, 500) × U(10, 25) For each tape, a nominal critical current Ic is first sampled and then perturbed to reflect realistic local variations along the tape and across the stack. Specifically, additive noise is introduced such that ϵ ∼ N (0, σ 2 ),
Ic ← Ic + ϵ,
(5)
where σ = 3 A, corresponding to approximately 1% of the mean source current E[Ic ] = 300 A. To train an SC-GNN capable of generalizing across configurations ranging from 1 × 1 to 10 × 6, K = 20 samples are drawn per configuration, yielding a training set of 2000 circuits. Validation uses K = 2 samples per configuration, corresponding to 200 circuits in total. The sweep is discretized into T operating points. At the t-th operating point (t = 1, . . . , T ), the input current is defined as Iin = Tt Itarget . For each circuit, this results in T graph instances corresponding to different operating points along the current ramp. Across these graphs, the circuit topology remains unchanged. Only the edge features corresponding to the input current Iin and the normalized operating ratio Iin /Ic vary. For the current study, T is set at 50. Once encoded as graphs, each circuit is stored as a Python dictionary containing node features, edge features, edge index, nodal voltages, and circuit metadata. For training, these are converted to PyTorch Geometric (PyG) format, where the numeric features are standardized. 2.6
Workflow and training
An overview of the proposed SC-GNN framework for predicting nodal voltages is shown in Figure. 4. The pipeline begins with a predefined architecture for a tape stack, specifying the number of tapes and segments per tape, from which a netlist file is generated. The netlist corresponds to SPICE formatted .cir file for DC operating point simualtion where the current is swept to Itarget in T steps. Simultaneously, the netlist is parsed into a circuit graph G = (V, E), represented as a set of T graph instances. The graph representation is passed to the SC-GNN consisting of the encoder, that projects raw node and edge features into latent embeddings, the processor implementing iterative message passing to propagate information across the graph topology, and finally the decoder that maps the updated node embeddings to the predicted nodal voltages. During training, predicted nodal voltages are compared against SPICE-simulated ground truth values via a loss function, and model parameters are updated through backpropagation using a gradient-based optimizer, defining the supervised training loop. All model training was performed on the GPU partition of LBNL’s Lawrencium cluster, utilizing a node equipped with an AMD EPYC 7742 processor (4 cores) and an NVIDIA A40 GPU. Hyperparameter optimization was performed using the Optuna framework [20] to efficiently explore the model hyperparameter search space across two stages. In Stage 1, the GNN was optimized without a physics-based loss term, establishing the baseline model and representing the primary contribution of this work. Stage 2, which introduces a physics-informed loss to further constrain predictions, is currently ongoing and preliminary results are presented here to demonstrate the potential of incorporating physical priors into the learning objective. Further details on the hyperparameter search space and optimization procedure are provided in Appendix B. 7
A PREPRINT - J UNE 23, 2026
Figure 4: Overview of the SC-GNN framework. Starting from an input tape stack configuration, a SPICE netlist is generated and simulated using ngspice under a ramped input current Iin = Tt Itarget to produce true nodal voltages V(t). The circuit is simultaneously represented as a graph G = (V, E) across T current steps, which is passed through the encoder-processor-decoder based GNN. The encoder comprising a node encoder and edge encoder produces latent embeddings that is sent through the message passing processor, and finally the decoder produces predicted nodal voltages V̄(t). The model is trained by minimizing a loss function via gradient-based optimization. Table 3: Optimized hyperparameters identified via Bayesian optimization for Stage 1 and 2.
Stage
1
2
Parameter Message passing layers (L) Hidden dimension (dh ) Learning rate Weight decay Batch size Optimizer Warmup epochs for physics loss Physics loss weight (λ)
3
Results
3.1
Inference performance of baseline model
Value 6 64 6.89×10−4 2.85e×10−6 64 Adam 50 5.62e×10−3
The best Stage 1 model, i.e., baseline model, trained using the optimized hyperparameters in Table 3, converged after 850 epochs with early stopping (patience of 10 epochs on validation loss) and a total wall time of 3.58 h. Figure. 5(a) shows the loss curves with the training and validation loss plotted over epochs. The validation loss closely follows the training loss indicating the model generalizes well and there is no significant overfitting. To evaluate the performance of the trained SuperCond-GNN surrogate, inference results are examined on the held-out test data spanning the full topology space of tapes and segments per tape, with circuit parameters sampled uniformly within the design space using K = 50 samples per topology, pP yielding 3,000 circuits in total. Model predictions were evaluated 2 using the root mean squared error (RMSE = i∈M (vi − v̂i ) /M) and the mean absolute percentage error (MAPE P vi −v̂i 1 = M × 100). The heatmaps in Figure 5(b) and (c) show the RMSE and MAPE, respectively, of the i∈M vi SC-GNN evaluated across the full topology space of 1 × 1 to 10 × 6. Each cell represents the mean error averaged over the 50 independently sampled test sets, providing a robust estimate of model performance across circuit configurations. Overall, the model achieves a mean RMSE of 0.04 µV (± 0.01 µV) and a mean MAPE of 4.30% (± 0.66%), demonstrating strong predictive accuracy across the majority of circuit configurations. Performance is broadly consistent across mid-to-large topologies, with RMSE values typically in the range 0.03–0.04 µV and MAPE values between 3–5%, indicating that the SC-GNN generalizes well to unseen parameter combinations within these configurations. 8
A PREPRINT - J UNE 23, 2026
Figure 5: Baseline model performance. (a) Training and validation loss curves showing the evolution of the baseline SC-GNN over 850 epochs with the inset showing the same on logarithmic scale. Inference performance evaluated on the held-out test set across the full topology space (1 × 1 to 10 × 6 tapes × segments per tape). (b) RMSE (µV) and (c) MAPE (%) heatmaps, where each cell represents the mean error averaged over K = 50 independently sampled circuit parameter sets. Bar charts alongside each axis show the row-wise, i.e., tape-wise, (red) and column-wise, i.e., segment-wise, (blue) marginal distributions of the respective error metric.
Notably, performance does not degrade monotonically with circuit size, with several larger topologies achieving comparable or lower error than mid-range configurations, suggesting the message passing framework scales effectively with graph size. The marginal distributions shown in the bar charts alongside each axis summarize performance trends across individual dimensions. The row-wise marginal (red) captures performance as a function of the number of tapes, while the column-wise marginal (blue) captures trends across the number of segments per tape. Along the tape axis, mean MAPE remains broadly stable for configurations with 4 or more tapes. Along the segment axis, the marginal distributions are comparatively flat with no strong systematic trend, though modest increases in MAPE are observed at higher segment counts for lowest and highest tape configurations. A modest degradation in performance is observed for circuits with low tape counts, where RMSE reaches up to 0.10 µV and MAPE up to 6.18% for the 1 × 1 topology. Importantly, this degradation is driven primarily by tape count rather than segment count, as the 1-tape row exhibits consistently elevated errors across all segment configurations (MAPE ranging from 4.48–6.18%), rather than being confined to small topologies in both dimensions simultaneously. This may reflect the greater sensitivity of small circuits to parameter variations, where a single segment transitioning between the superconducting and resistive state has a proportionally larger effect on the overall operating point. Additionally, the graph structure for these small circuits provides fewer neighboring nodes from which to aggregate information during message passing. This limited local context may reduce the expressiveness of the learned node representations, making accurate prediction harder despite the apparent simplicity of these configurations. Regardless, 9
A PREPRINT - J UNE 23, 2026
Figure 6: SC-GNN inference results for a representative 2 × 2 tape stack. (a) Equivalent circuit schematic showing the nodal structure with 2 tapes and 2 segments per tape, with nodes n1–n5 labelled (n0 is the ground). (b)–(f) Predicted versus true nodal voltages V̂n1 to V̂n5 as a function of input current Iin , with RMSE and MAPE reported for each node. (g) Residual errors V − V̂ across all nodes as a function of Iin , illustrating the distribution and magnitude of prediction errors. The nonlinear voltage response at high current values, associated with the superconducting to resistive transition, is well captured by the model across all nodes.
the performance on the single tape topologies are of less concern since they do not qualify as a stack and can therefore be avoided in future training campaigns. A similar, though less pronounced, degradation is observed at high tape counts, with MAPE values reaching up to 5.94% for the 9 × 6 topology, particularly at larger segment counts, while RMSE remains broadly consistent. This discrepancy is partly attributable to the metric computations itself where larger circuits contain more nodal points, increasing the likelihood of encountering nodes with small absolute voltage values where even small absolute errors yield disproportionately large percentage contributions to MAPE, while the RMSE remains relatively unaffected as it aggregates absolute errors uniformly across all nodes. Regardless, the higher MAPE is also a result of the increased complexity of larger graphs, where the fixed number of message passing layers L = 6 limits the receptive field of each node, potentially preventing full aggregation of information across the graph diameter. Figure. 6 shows the predicted and true nodal voltages for a representative 2-tape, 2-segment circuit (panel a) across a sweep of cable current values. For each node, the SC-GNN predictions (red) closely track the true ngspice solutions (blue) across the full current range, including the nonlinear transition region between approximately 600 − 900 A where segments begin switching from the superconducting to the resistive state. MAPE values across the five nodes range from 1.55% to 4.81%, and corresponding RMSE values between 0.016 and 0.078 µV , with the highest errors at the input node. Additionally, the input node voltages correspond to the voltage response of the tape stack as a whole. An RMSE of 0.078 µV translates to an equivalent electric-field error of 0.0078 µV/cm for a 10 cm tape. This is less than 1% of the conventional 1 µV/cm critical-current criterion, indicating that the surrogate error is negligible relative to experimentally relevant voltage levels. Panel (g) shows the residuals across all nodes as a function of cable current, revealing that prediction errors are largest within the transition region, where the voltage response is most nonlinear. 10
A PREPRINT - J UNE 23, 2026
Figure 7: Computational performance of the SC-GNN surrogate relative to ngspice across the full topology space. (a) ngspice-to-CPU speedup ratio and (b) ngspice-to-GPU speedup ratio heatmaps across the topology space of 1 × 1 to 10 × 6 tapes × segments per tape, where values greater than 1 indicate the SC-GNN is faster than ngspice. (c) Time per iteration (ms) as a function of graph size (2 + (mt + 1) · nt nodes) for ngspice, SC-GNN on CPU, and SC-GNN on GPU, with power-law fits indicating the scaling behaviour of each method. All benchmarks were performed on an AMD EPYC 7742 CPU with an NVIDIA A40 GPU and averaged over three runs.
Despite this, the residuals remain small in magnitude, demonstrating that the SC-GNN captures the essential physics of the DC operating point across both the superconducting and resistive regimes. 3.2
Computational performance and scalability
Benchmarking study on a hold-out test dataset was carried out across CPU inference, GPU inference, and ngspice. All benchmarks were performed on the same hardware node (AMD EPYC 7742, 4 cores, NVIDIA A40 GPU) to ensure a fair comparison. Each benchmark was repeated three times and the reported values represent the mean over these runs. ngspice timing was measured as the total wall-clock time of the DC sweep divided by the number of operating points, with file I/O and netlist generation excluded, capturing only the time taken by the ngspice solver itself. SC-GNN inference timing includes data preparation, transfer of node and edge features to the target device, batching of all operating points for a given circuit into a single forward pass, and model inference. For the inference, warmup passes were performed prior to timing for both CPU and GPU to exclude one-time compilation and JIT overhead from the reported measurements. It is important to note that ngspice does not natively support complete multi-core parallelism or GPU acceleration (limited to certain rudimentary elements such as capacitors and resistors), and all ngspice runs were therefore executed on a single CPU core. Figure. 7 presents a comprehensive benchmarking comparison between SC-GNN surrogate inference on CPU and GPU, and ngspice, across the full topology space. The heatmaps in panels (a) and (b) show the pairwise speedup ratios across the topology space. CPU inference times range from approximately 0.1 ms/iter for small circuits to around 1.0 ms/iter for the largest topologies, growing monotonically with circuit size. GPU inference is substantially faster and remains largely flat across the topology space at approximately 0.15 ms/iter. ngspice times range from approximately 0.2 ms/iter for small circuits to 0.14–0.4 ms/iter for the largest topologies, following a similar trend to CPU inference. Panel (a) shows that CPU inference offers no consistent speedup over ngspice across the circuit sizes tested, with the ngspice/CPU ratio remaining close to or below 1 for most configurations. However, as seen in panel (b),GPU inference is competitive with or faster than ngspice across the majority of configurations, achieving a peak ngspice/GPU speedup of 2.5× for larger circuits. This is consistent with the GPU’s ability to exploit parallelism across the batched operating points more effectively as graph size increases. Notably, GPU inference time remains largely insensitive to circuit size. This is clearer in panel (c) which shows inference time per operating point as a function of graph size (total nodes) on a logarithmic scale, with power law fits revealing distinct scaling behaviours across the three approaches. GPU inference exhibits near-constant scaling with an exponent of 0.008, remaining at approximately 0.15 ms/iter across the entire range of circuit sizes tested. ngspice scales linearly with an exponent of 1.08, consistent with the direct matrix solving characteristic of SPICE simulators, while CPU inference scales most steeply with an exponent of 0.496. These scaling exponents directly imply that the GPU surrogate will become increasingly advantageous over both ngspice and CPU inference as circuit complexity grows to larger magnet configurations. While this work represents a proof-of-concept on circuit representations of tape stacks of up to 10 tapes and 6 segments per tape, larger and more complex configurations are expected to yield more pronounced speedup advantages on GPU as indicated by the empirical scaling analysis. 11
A PREPRINT - J UNE 23, 2026
Figure 8: SC-GNN inference results following physics-informed Stage 2 training. (a) Evolution of the training loss, validation loss, and physics loss (Lphysics ) over 1080 epochs, with the inset showing the convergence behaviour on a logarithmic scale. (b)–(c) Inference performance on the held-out test set across the full topology space (1 × 1 to 10 × 6 tapes × segments per tape): (b) RMSE (µV) and (c) MAPE (%) heatmaps, where each cell represents the mean error averaged over K = 50 independently sampled circuit parameter sets. Bar charts alongside each axis show the row-wise (red) and column-wise (blue) marginal distributions of the respective error metric. The physics-regularized model achieves a mean RMSE of 0.04 ± 0.01 µV and a mean MAPE of 4.39 ± 0.77%, comparable to the baseline SC-GNN.
12
A PREPRINT - J UNE 23, 2026
3.3
Evaluation of physics-based regularization
Figure. 8 (a) shows the training curves along with the unweighted physics loss evolution for the SC-GNN with physics-based loss using parameters listed in Table. 3. The physics-informed Stage 2 training yields a modest but measurable improvement in best validation loss from 2.87 × 10−3 to 2.75 × 10−3 , corresponding to a ∼4% reduction in normalized error. However, this comes at the cost of nearly doubled training time from 3.58 h to ∼7 h. Subsequent inference on the held-out test set (same as Section 3.1) reveals that the physics-regularized model performs comparably to the baseline SC-GNN, with both variants achieving a mean RMSE of 0.04 ± 0.01 µV and a mean MAPE of 4.39 ± 0.67%, as seen in Figure. 8(b) and (c). Rather than indicating a limitation of the physics-informed approach, this suggests that the SC-GNN architecture already possesses a strong inductive bias toward the underlying electrical physics through its graph topology alone, such that explicit KCL regularization in its current implementation provides limited additional benefit on the test set, beyond what the supervised loss achieves. While the physics-informed approach provides theoretical robustness, the current formulation introduces a significant computational overhead compared to a similar architecture without physics loss, despite optimal tuning of the hyperparameters. This computational bottleneck is primarily attributed to the circuit remapping to supernodes, which is currently necessary to calculate the implicit KCL residuals from the predicted nodal voltages. It is worth noting that KCL was deliberately selected over Kirchhoff’s Voltage Law (KVL) for this regularization, since the message aggregation inherent in the SC-GNN’s message passing layers effectively mirrors KVL satisfaction. Specifically, in a circuit graph where edge features encode branch voltages, the aggregation of messages along any closed loop naturally enforces voltage consistency, as the sum of voltage drops around any cycle is implicitly constrained to zero through the iterative message passing updates. An explicit KVL loss would therefore provide redundant information with limited incremental value to the training process. Given the computational cost of the supernode mapping and the strong performance of the unregularized baseline, alternative strategies for integrating physics constraints are being explored. A primary future direction is reformulating the framework as an edge-based graph problem in which branch currents are directly predicted, allowing KCL residuals to be computed directly without the supernode remapping step. Another alternative is to dynamically weight the physics loss to target nodes with the highest KCL violations, rather than averaging uniformly across the circuit. This may provide more targeted gradients and better realize the potential of physics-informed learning in this domain. 3.4
Evaluating model generalizability
A key requirement for the broader applicability of SC-GNN to unseen magnet configurations is its ability to generalize. To assess this, generalizability is evaluated on larger tape stack topologies representing out-of-distribution (OOD) conditions. Zero-shot generalization is first tested on these unseen topologies, followed by few-shot finetuning. For the latter, training samples are progressively increased and the pre-trained surrogate is fine-tuned under six configurations: all processor layers unfrozen, followed by iterative freezing of processor layers from 1 to 5, the latter leaving only the final layer and decoder trainable. Freezing a layer means its weights are held fixed during training, preventing them from being updated. Both standard and physics-informed fine-tuning variants are evaluated. Three OOD tape stack topologies are considered: (1) 15 × 6, (2) 10 × 10, and (3) 15 × 10. The pretrained model was trained on tape stack configurations from 1 × 1 to 10 × 6. Case (1) corresponds to an extension in the number of tapes, introducing more parallel branches in the circuit. Case (2) represents a horizontal expansion in which the number of segments per branch is increased while the number of parallel branches remains within distribution. Case (3) represents the most challenging scenario, as the tape stack configuration exceeds the training distribution in both dimensions simultaneously. In terms of graph size, the pretrained SC-GNN was exposed to graphs with 3 to 602 nodes during training and is now applied to graphs of 1352, 1002, and 2252 nodes for cases (1), (2), and (3), respectively. For each case, reported metrics are averaged over three runs on 10 test circuits. 3.4.1
Zero-shot inference
For zero-shot inference, the pretrained model is applied directly without any fine-tuning. Average MAPE values for 15 × 6, 10 × 10, and 15 × 10 are 30.49%, 17.41%, and 44.20%, respectively, while corresponding average RMSE values are 0.59 µV, 0.28 µV, and 0.99 µV. The physics-informed zero-shot variant achieves lower errors in all three cases, with RMSE of 0.43 µV, 0.21 µV, and 0.53 µV and MAPE of 22.50%, 15.74%, and 24.64% for cases (1), (2), and (3), respectively, suggesting that KCL regularization improves generalization to OOD topologies even without fine-tuning. Zero-shot performance is considerably worse than that reported in Section 3.1 for in-distribution test data, as expected. Among the three OOD cases, zero-shot performance is best for 10 × 10, where only the number of segments per tape is increased. This is expected for two reasons. First, edge features remain within distribution since none are dependent on the number of segments per branch. Second, this case corresponds to a comparatively moderate 13
A PREPRINT - J UNE 23, 2026
Figure 9: Few-shot generalization results for three out-of-distribution (OOD) tape stack topologies: 15 × 6 (a–c), 10 × 10 (d–f), and 15 × 10 (g–i). For each topology, RMSE (µV) (a, d, g), MAPE (%) (b, e, h), and percentage of remaining error reduced relative to zero-shot performance (c, f, i) are shown as a function of the number of frozen processor layers, with the number of trainable parameters indicated along the top axis. Results are shown for 5, 10, and 15 fine-tuning samples, with and without physics-informed loss. Horizontal annotations indicate zero-shot RMSE and MAPE for both standard and physics-informed inference. All results are averaged over three runs on 10 test circuits.
14
A PREPRINT - J UNE 23, 2026
increase in graph size without affecting the tape stack behavior much, making it the simplest of the three scenarios. The variance across iterations is also considerably tighter for this case. Performance on 15 × 6 ranks second, as increasing the number of tapes alters the physical configuration of the tape stack by increasing current-carrying capacity and introducing greater current sharing. These two sources of OOD shift compound in complexity when combined, which explains why zero-shot performance is worst for 15 × 10. 3.4.2
Few-shot fine-tuning
Fine-tuning generally improves performance over zero-shot inference across the three OOD topologies, as reflected in the percentage of remaining error reduced shown in Figure 9(c, f, i), though the degree of improvement varies considerably across cases and fine-tuning configurations. These improvements are further increased when the more samples are provided for training which also reduces the observed variance across the runs. For 15 × 6 and 10 × 10, the benefit of increasing from 10 to 15 samples is less clear, with some configurations exhibiting an opposite trend, suggesting sensitivity to the specific parameter combinations sampled in the small training sets. However, for 15 × 10, increasing the number of training samples consistently yields further improvement, with 15 samples outperforming 5 and 10 across most configurations and variance reducing with more data. Nevertheless, the results demonstrate that SuperCond-GNN can adapt to unseen topologies through fine-tuning on relatively small datasets. Regarding the effect of processor layer freezing, no single strategy consistently dominates across all cases and firm conclusions cannot be drawn at this stage. As the number of frozen layers increases, the number of trainable parameters is approximately halved with each step, yet performance does not degrade monotonically. For 15 × 6, variance across freezing configurations is particularly high, with some configurations performing worse than zero-shot inference, indicating strong sensitivity to which layers are left trainable for this topology. For 10 × 10, error reduction is consistently positive and variance is tighter across freezing levels, suggesting that adaptation to horizontal segment expansion is a more tractable fine-tuning task. The error reduction is also consistently positive across configurations for 15 × 10. More generally, minimal freezing appears favorable across cases, preserving the model’s ability to adapt while still benefiting from the pretrained representations. However, given the high variance and limited number of fine-tuning samples, the effect of freezing configuration remains inconclusive and warrants more systematic investigation. An important distinction especially emerges between the zero-shot and fine-tuning behaviour of the physicsinformed variant. While the physics-informed model achieves consistently lower zero-shot errors across all three OOD cases, the gains from fine-tuning are comparatively smaller than those observed for the baseline. For 15 × 6 specifically, fine-tuning the physics-informed model degrades performance relative to its own zero-shot baseline, in contrast to the baseline model which fine-tunes readily despite its higher zero-shot error. This suggests a trade-off between zero-shot generalization and fine-tuning adaptability, where KCL regularization improves out-of-distribution robustness but may constrain plasticity during adaptation. Notably, this degradation is not observed for 15 × 10 despite both cases exceeding the training distribution in tape count, which remains an open question. Generalizability to larger circuits is expected to benefit from increased model depth, as additional processor layers would better capture the long-range dependencies present in larger graphs, and from more diverse training topologies to improve the robustness of few-shot adaptation.
4
Conclusion
This work presented SuperCond-GNN, a graph neural network-based surrogate model designed as a systemagnostic framework for predicting nodal voltage distributions in HTS magnets. As a proof of concept, tape stack circuits were represented as equivalent electrical networks and converted into graph representations, from which nodal voltages were learned using a message passing GNN trained on ngspice-generated data across the full topology space of 1 × 1 to 10 × 6 configurations, where nt × mt denotes the number of tapes and segments per tape respectively. The proposed surrogate achieved a mean RMSE of 0.04 µV and a mean MAPE of 4.30% on the held-out test set, demonstrating strong predictive accuracy across the full topology space. Performance degraded only modestly at the lowest tape counts and at the upper extreme of the design space, consistent with the limited local graph context available to the message passing layers in these regimes. Crucially, these error margins translate to an equivalent electric-field error that is well below 1% of the conventional 1 µV/cm critical-current criterion, demonstrating that the model’s accuracy is within the tolerances required for practical experimental measurements. SuperCond-GNN also exhibits near-constant scaling with graph size ∝ N 0.008 , compared to the linear scaling of ngspice ∝ N 1.08 , where N is the number of graph nodes. This demonstrates the scalability advantage of the surrogate for larger circuits and establishes it as a viable tool for downstream applications including design space exploration, current sharing analysis, optimization, and real-time simulation. The incorporation of a physics-informed loss targeting KCL as a regularizer yielded a modest improvement in validation loss but comparable test set performance to the baseline, suggesting that the graph topology alone provides a 15
A PREPRINT - J UNE 23, 2026
strong inductive bias toward the underlying electrical physics. However, the physics-informed variant demonstrated a more pronounced advantage in zero-shot generalization to OOD tape stack topologies, consistently achieving lower RMSE and MAPE than the baseline across all three OOD cases evaluated. Both variants were further assessed under few-shot fine-tuning across varying dataset sizes and processor layer freezing configurations, demonstrating that SuperCond-GNN can adapt to unseen topologies with as few as 5 to 10 training samples. Future work will scale SuperCond-GNN to larger tape stacks and more complex magnet topologies. To support this scaling, the framework will be enhanced with deeper, attention-driven architectures and more efficient physics-informed training, such as dynamic loss weighting for KCL violations. Ultimately, the long-term objective is to transition from simulation to real-world magnet state estimation. By incorporating physical coil measurements, the model can be deployed onto hardware platforms like FPGAs to serve as a real-time voltage predictor for practical magnet protection.
Appendices A
Ablation studies
This section reports the ablation studies performed to justify key architectural design choices for the graph representation of tape stack circuits. Specifically, the following features are evaluated: 1. One-hot encoding of circuit elements in the edge features (as opposed to weighted encoding). 2. Normalized distance from the current source as a node feature. 3. Normalized distance from the ground as a node feature. 4. Node degree as a node feature. To isolate the effects of each feature, changes were applied to the baseline model one at a time. The combinatorial influence of altering multiple features simultaneously was not studied, as their interactions were assumed to be minimal. The study utilized a smaller design space comprising of 1 × 1 to 4 × 4 tape stack configurations, maintaining an 80:10:10 ratio for the training, validation, and test splits. Each model configuration was trained three times with independent initializations, and results are reported as averages across these runs. The baseline model (M0) utilizes one-hot encoding for edges and includes all aforementioned node features. To test the effect of edge encodings, M0 was compared against two weighted variants: M1 utilizes hierarchical edge weights (resistor: 1, current source: 2, superconductor: 3), and M2 utilizes extreme edge weights (resistor: 1, current source: 5, superconductor: 10). To evaluate the importance of node features, features were systematically removed from the baseline. M3 removes the distance from the current source, M4 removes the distance from the ground, and M5 removes the node degree. Figures. 10(a) and (b) illustrate the training and validation loss curves across all model variants. M0 exhibits the most stable loss reduction and trains for the longest duration, with M2 performing as a close second. Notably, all configurations exhibit a similar degree of overfitting, with training loss converging to approximately one order of magnitude below the validation loss. Panel (c) presents the best validation loss achieved by each variant, with error bars reflecting variance across three training runs. M0 yields the strongest performance overall. Modifications to the edge representation consistently degrade performance. The hierarchical edge weight encoding (M1) increases validation loss by 31.3% relative to the baseline, while the extreme edge weight encoding (M2) results in a 16.6% increase. Removing node features similarly impairs performance. Omitting the normalized distances from the current source (M3) and ground (M4) leads to validation loss increases of 9.1% and 32.5%, respectively. Together, these features encode the primary determiners of current flow through a node. The most severe degradation arises from removing node degree (M5), a feature that captures local topological context, resulting in a 41.6% increase in validation loss. Test performance, evaluated on held-out data, is summarized in panels (d) and (e). Interestingly, M1 achieves the lowest RMSE despite its comparatively higher validation loss, with M0 remaining a close second. This apparent contradiction may be explained by the scale of the target values, which span several orders of magnitude. RMSE penalizes absolute errors and is therefore dominated by the largest predictions in this range, meaning a model that better fits high-magnitude samples can achieve lower RMSE while performing worse overall. MAPE, by contrast, evaluates relative error uniformly across the prediction range and is consequently a more informative metric in this setting. By this measure, M0 achieves the best performance. The edge encoding variants M1 and M2 attain comparable MAPE values to M0, albeit with slightly higher variance, suggesting that the choice of edge encoding may have a marginal and test-case-dependent effect on final accuracy. In contrast, the performance degradation caused by removing node features remains pronounced in testing, reinforcing their importance to the model’s predictive capacity. 16
A PREPRINT - J UNE 23, 2026
Figure 10: Ablation study results on 1 × 1 to 4 × 4 tape stack configurations across model variants M0–M5 (M0: Baseline, M1: Hierarchical edge feature, M2: Extreme edge features, M3: Normalized distance from current source removed from node feature, M4: Normalized distance from ground removed from node feature, and M5: Node degree removed from node features) . (a) Training loss and (b) validation loss curves over for all variants, shown on a logarithmic scale with shaded regions indicating the standard deviation across runs. (c) Best validation loss, (d) test RMSE (µV), and (e) test MAPE (%) for each variant, with error bars denoting the standard deviation. All variants converge to comparable training and validation loss trajectories, with differences in generalization performance more apparent in the test metrics.
B
Hyperparameter optimization
Hyperparameter optimization was performed using the Optuna framework [20], employing a Tree-structured Parzen Estimator-based Bayesian optimization to efficiently explore a nine-dimensional hyperparameter search space. Optimization was conducted in two sequential stages. Stage 1 focused on standard architectural and training hyperparameters, comprising: • Number of message-passing layers L ∈ {2, . . . , 6} • Hidden layer dimension dh ∈ {64, 128, 256, 512} • Batch size ∈ {32, 64, 128, 256} • Optimizer ∈ {Adam, RMSProp, SGD} • Learning rate ∈ [10−5 , 10−2 ] (log scale) • Learning rate scheduler ∈ {none, cosine annealing, ReduceLROnPlateau} • Weight decay ∈ [10−6 , 10−3 ] (log scale) Stage 2 then tuned the physics-informed loss parameters on the best-performing model from Stage 1, namely the loss weight λ ∈ [0, 0.5] and the warmup epoch at which physics-informed regularization is introduced ∈ {0, 10, 50, 100, 200}. As the physics-informed loss component is currently in a prototypical stage, this two-stage strategy was adopted to isolate its influence from the core architectural search and to allow independent refinement of each component. To avoid computational waste on unpromising trials, a pruner was employed. To avoid discarding promising trials too early, the pruner had two grace periods. First, the initial five trials were always allowed to run to completion, giving the sampler enough data to make informed pruning decisions. Subsequently, each new trial was granted a 50-step warmup period during which no pruning could occur, ensuring that intermediate results were sufficiently accumulated before a trial could be terminated early. The study was distributed across four parallel workers on an A40 GPU node within the Lawrencium cluster. Each worker executed 15 trials in Stage 1 (60 total), with each trial permitted a maximum of 1,000 training epochs, followed by 9 trials per worker in Stage 2 (36 total). 17
A PREPRINT - J UNE 23, 2026
Demo An interactive demonstration of SuperCond-GNN is available on Hugging Face Spaces, allowing users to specify circuit topologies and input parameters and obtain predicted nodal voltage distributions. The demo is accessible at https://huggingface.co/spaces/nmenon97/SuperCondGNN. Note that the hosted demo runs on Hugging Face’s base CPU tier and will therefore exhibit longer inference times.
References [1] M. Marchevsky, “Quench Detection and Protection for High-Temperature Superconductor Accelerator Magnets,” Instruments, vol. 5, p. 27, Sept. 2021. [2] A. Rasheed, O. San, and T. Kvamsdal, “Digital Twin: Values, Challenges and Enablers From a Modeling Perspective,” IEEE Access, vol. 8, pp. 21980–22012, 2020. [3] A. C. A. Martínez, Q. Ji, S. O. Prestemon, X. Wang, and G. H. I. Maury Cuna, “An Electric-Circuit Model on the Inter-Tape Contact Resistance and Current Sharing for REBCO Cable and Magnet Applications,” IEEE Transactions on Applied Superconductivity, vol. 30, pp. 1–5, June 2020. [4] R. Kang, J. Wang, Z. Feng, and Q. Xu, “The Current Unbalance in Stacked REBCO Tapes — Simulations Based on a Circuit Grid Model,” IEEE Transactions on Applied Superconductivity, vol. 33, pp. 1–12, Dec. 2023. [5] V. Pothavajhala, L. Graber, C. H. Kim, and S. Pamidi, “Experimental and Model Based Studies on Current Distribution in Superconducting DC Cables,” IEEE Transactions on Applied Superconductivity, vol. 24, pp. 1–5, June 2014. [6] G. P. Willering, D. C. van der Laan, H. W. Weijers, P. D. Noyes, G. E. Miller, and Y. Viouchkov, “Effect of variations in terminal contact resistances on the current distribution in high-temperature superconducting cables,” Superconductor Science and Technology, vol. 28, p. 035001, Jan. 2015. [7] A. D. Berger, “Stability of superconducting cables with twisted stacked YBCO coated conductors,” tech. rep., MIT Plasma Science and Fusion Center, Feb. 2011. [8] F. Lannutti, F. Menichelli, and M. Olivieri, “CUSPICE The revolutionary NGSPICE on CUDA Platforms,” in 12th MOS-AK Workshop at the ESSDERC/ESSCIRC Conference, (Venice, Italy), 2014. [9] R. Sakakibara, T. Mato, R. Inoue, H. Ueda, S. Kim, and S. Noguchi, “Experimental Investigation of CNN-Based Voltage Prediction for REBCO Pancake Coil Protection,” IEEE Transactions on Applied Superconductivity, vol. 36, pp. 1–5, Aug. 2026. [10] M. Khan, S. Krave, V. Marinozzi, J. Ngadiuba, S. Stoynev, and N. Tran, “A Weakly Supervised Machine Learning Procedure for Acoustic Emission Quench Diagnostics,” IEEE Transactions on Applied Superconductivity, vol. 36, no. 3, pp. 1–6, 2026. [11] M. Xiao, P. Song, Y. Liu, C. Korte, Z. Xu, J. Gao, J. Lu, H. Nie, Q. Deng, and T. Qu, “A Surrogate model for High Temperature Superconducting Magnets to Predict Current Distribution with Neural Network,” 2026. _eprint: 2509.06067. [12] R. Teyber, M. Marchevsky, A. C. A. Martinez, S. Prestemon, J. Weiss, and D. van der Laan, “Numerical investigation of current distributions around defects in high temperature superconducting CORC® cables,” Superconductor Science and Technology, vol. 35, p. 094008, Aug. 2022. [13] G. DeZoort, P. W. Battaglia, C. Biscarat, and J.-R. Vlimant, “Graph neural networks at the Large Hadron Collider,” Nature Reviews Physics, vol. 5, pp. 281–303, May 2023. [14] A. K. Khamis and M. Agamy, “Circuit topology aware GNN-based multi-variable model for DC-DC converters dynamics prediction in CCM and DCM,” Neural Computing and Applications, vol. 36, pp. 20807–20822, Nov. 2024. [15] K. Hakhamaneshi, M. Nassar, M. Phielipp, P. Abbeel, and V. Stojanović, “Pretraining Graph Neural Networks for few-shot Analog Circuit Modeling and Design,” Mar. 2022. [16] H. Vogt, “Ngspice, the open source Spice circuit simulator - Intro.” [17] H. Yu, B. Tang, S. Yang, S. Jiang, D. Jiang, and G. Kuang, “Experimental Studies on Quench Behavior Measurements of HTS Tapes With Various Heater Configurations,” IEEE Transactions on Applied Superconductivity, vol. 34, pp. 1–5, Aug. 2024. 18
A PREPRINT - J UNE 23, 2026
[18] L. Mo, G. Chen, J. Huang, X. Qing, Y. Hu, and X. He, “Graph Theory-Based Programmable Topology Derivation of Multiport DC–DC Converters With Reduced Switches,” IEEE Transactions on Industrial Electronics, vol. 69, pp. 5745–5755, June 2022. [19] T. Pfaff, M. Fortunato, A. Sanchez-Gonzalez, and P. W. Battaglia, “Learning Mesh-Based Simulation with Graph Networks,” June 2021. arXiv:2010.03409 [cs]. [20] T. Akiba, S. Sano, T. Yanase, T. Ohta, and M. Koyama, “Optuna: A Next-generation Hyperparameter Optimization Framework,” July 2019.
19