Digitalcommons Calpolymetadata only
A Study on Quantization and Hardware Cost Tradeoffs in a 5G NR LDPC Decoder on FPGA
5g, communications, ldpc, error-correction, fpga, digital circuits, signal processing, systems and communications
This document is indexed with metadata only — full text is not available in the archive for this record.
Open the official source ↗
Record · ID 332982
Conceptio Open Knowledge Archive — every document is proof-bundled with source, license, and retrieval metadata.