arXiv CSopen access

FPGN: Redefining Ultra-Fast Programmable Gate-based Neural Acceleration with Differentiable LUTs

1

FPGN: Redefining Ultra-Fast Programmable Gate-based Neural Acceleration with Differentiable LUTs

arXiv:2607.08427v1 [cs.AR] 9 Jul 2026

Jiawei Liang1 , Haotong Qin2 , Linfeng Du1 , Xingyu Liu1 , Shangkun Li1 , Hui Yu1 , Michele Magno2 , Xinyu Chen3 , Jiang Xu3 , Wei Zhang1 1 HKUST, 2 ETH Zurich, 3 HKUST (GZ)

Abstract—Achieving nanosecond-scale inference latency for deep neural networks (DNNs) has become a primary architectural concern for latency-critical applications. While FieldProgrammable Gate Arrays (FPGAs) offer a promising substrate for low-latency inference, conventional FPGA accelerators remain arithmetic-centric, using LUTs primarily as building blocks for numerical operators and peripheral logic. In contrast, recent LUT-native neural networks treat LUTs as learnable neurons, revealing promising theoretical potential to exploit their intrinsic logic expressivity. However, existing methods are largely confined to algorithmic optimizations, failing to translate this theoretical potential into high-performance FPGA accelerators. Specifically, their differentiable formulations do not faithfully match FPGA LUT primitives, their physically-unaware topologies compromise routability and timing closure, and their lack of automated optimization flow hinders systematic design space exploration (DSE) and efficient hardware implementation. In this paper, we propose FPGN, an end-to-end physicallyaware framework that closes the gap between LUT-native learning and latency-optimized FPGA implementation. FPGN addresses these challenges through (i) a hardware-aligned differentiable formulation for training FPGA-native LUT neurons, (ii) a structured LUT-native topology with a streaming hardware architecture to improve routing locality and timing closure, and (iii) a latency-driven compiler that leverages high-fidelity analytical Quality of Results models to automate DSE and hardware generation. Experiments show that FPGN achieves up to 205× latency reduction compared to representative FPGAbased BNN accelerators and up to 30× higher LUT efficiency than prior differentiable LUT-native networks, while maintaining competitive inference accuracy. Index Terms—Differentiable, FPGA, LUT-Native Networks, Hardware Co-Design.

I. I NTRODUCTION Deep Neural Networks (DNNs) have driven major advances in artificial intelligence [1], [2]. However, deploying them in domains prioritizing nanosecond-scale response requirements over other constraints remains highly challenging, such as high-energy physics triggers [3], [4], high-frequency trading [5], [6], and line-rate packet or flow classification in highspeed network data planes [7], [8]. While GPUs dominate high-throughput training, their rigid memory hierarchy and batch-oriented execution make them architecturally unsuitable for these latency-critical applications [9]. Specialized accelerators on Field-Programmable Gate Arrays (FPGAs) [10], [11] and Application-Specific Integrated Circuits (ASICs) [12], [13] have been developed to reduce inference latency. While ASICs offer peak performance, their inflexibility and high Non-Recurring Engineering (NRE) costs limit their adaptability to rapidly evolving algorithms [14].

× w

w

···

×

w

∑N (a) CNN w w K-LUT ··· K-LUT

Convolution Operation

w

XNOR ··· XNOR

w

N-Popcount (b) BNN K-LUT ··· K-LUT

N-Popcount

N/K-Popcount

(c) LUT as operator

(d) LUT as neuron

Fig. 1. Evolution of neural paradigms on FPGA. (a) MAC in CNN. (b) BNNs replace MAC with XNOR and N-input popcount. (c) The LUT-asoperator paradigm replaces XNOR with learnable k-LUTs while maintaining arithmetic-centric structures. (d) LUT-as-neuron paradigm unifies operators and weights into learnable LUTs.

Consequently, FPGAs have emerged as a compelling substrate for hardware-algorithm co-design, offering agile reconfigurability alongside deterministic ultra-low latency. At the core of this flexibility is the k-input Look-Up Table (k-LUT), a small memory that can be programmed to realize any Boolean function of k input bits. Despite inherent programmability, traditional FPGA accelerators follow an arithmetic-centric paradigm that treats LUTs as building blocks to implement predefined arithmetic and glue logic. For instance, Convolutional Neural Network (CNN) accelerators on FPGA [10], [15] utilize LUTs and Digital Signal Processing (DSP) slices to implement MultiplyAccumulate (MAC) as shown in Fig. 1(a). While parallelizable, the heavy memory access overhead and computational complexity of these models remain barriers to ultra-low latency implementation. Binary Neural Networks (BNNs) [11], [16] mitigate this issue by binarizing weights to one-bit values and replacing time-consuming MACs with efficient bit-wise XNOR and population count (popcount) operations (Fig. 1(b)). However, they ultimately confine LUTs to executing numerical functions, leaving the Boolean expressivity of LUTs largely underutilized. More promising methods make LUTs themselves learnable, following two distinct paradigms. The first treats LUTs as learnable operators, as exemplified by LUTNet [17]. It replaces XNOR gates with LUTs to increase local flexibility (Fig. 1(c)). However, this operation-level replacement still inherits the legacy BNN datapath and weights, which imposes structural constraints forcing the learned LUTs to remain functionally proximal to XNOR [17]. The second more radical paradigm [18]–[20] instead unifies operators and weights into learnable LUTs as illustrated in Fig. 1(d), thereby eliminating the weight-induced memory access overhead. While effective, these approaches typically rely on predefined function to fill

2

LUT configurations, which explore a negligible fraction of the k LUT’s massive 22 Boolean functional space. Recent algorithmic advances [21]–[23] have begun to construct logic-native neural networks directly on differentiable logic. Prior works [21], [22] pioneered the use of two-input logic gates as neurons, successfully pushing the latency of the image classification task on the CIFAR-10 [24] dataset down to the nanosecond level while maintaining accuracy competitive with representative BNNs. DWN [23] expands this idea to 6-LUTs that is most widely used in modern FPGAs to balance performance and area efficiency [25]. Orthogonal to these classic connection-centric CNN/MLP formulations, alternative activation-centric paradigms such as KANELÉ [26] have emerged to tabulate univariate splines for scientific computing. However, existing LUT-native methods remain largely confined to algorithmic optimizations. They either rely on lowinput logic elements (e.g., 2-input gates) [21], [22] that underutilize FPGA LUT primitives or lack the training scalability to support more complex networks beyond small MLPs [23]. More importantly, by permitting unstructured connectivity to enhance network performance, they neglect the routing and timing constraints of physical FPGA fabric, making it difficult to realize high-frequency, ultra-low-latency implementations. In addition, the absence of LUT-centric compiler support further hinders automated deployment of such designs. This reveals our key insight: transforming the FPGA fabric itself into a learnable LUT-native neural network unlocks the potential for ultra-low-latency neural acceleration, and realizing the potential in practical nanosecond-scale FPGA hardware requires full-stack co-optimization of differentiable LUT training, physically-aware topology, streaming architecture, and compilation. Guided by these insights, we propose FPGN, a physicallyaware differentiable LUT-native framework for Ultra-Fast Programmable Gate-based Neural accelerators. It is designed to address three core challenges: (i) the mismatch between differentiable training and discrete FPGA LUT primitives, (ii) the topology-architecture co-design problem imposed by FPGA physical constraints, and (iii) the absence of an automated optimization flow for LUT-native networks. To this end, FPGN is organized as a bottom-up co-design framework with three tightly coupled components: • Hardware-Aligned training methodology: FPGN first introduces a training methodology for LUT-native networks leveraging a differentiable relaxation for LUT neurons coupled with a progressive binarization process. This formulation enables stable convergence and efficient k optimization within the massive 22 Boolean functional space, thereby bridging continuous domain of gradientbased optimization and discrete nature of LUT-native hardware. • Physically-Aware Topology and Streaming Architecture: Building upon the trainable LUT neurons, FPGN proposes a physically-aware LUT-native topology with structured connectivity and a fully streaming FPGA architecture to realize it. By co-designing connectivity, dataflow, and adaptive pipelining, the proposed approach

ensures superior physical routability and timing closure to sustain high-frequency nanosecond-scale neural inference. • Latency-Driven Automated Compiler: To instantiate the proposed architecture into optimized streaming accelerators, FPGN integrates high-fidelity analytical Quality of Results (QoR) models into a latency-driven compiler that automatically explores the design space and generates optimized FPGA implementations. II. BACKGROUND AND M OTIVATION A. Arithmetic-Centric Paradigm Traditional FPGA-based CNN accelerators are inherently arithmetic-centric, necessitating frequent weight fetching to perform computationally intensive multi-bit MAC operations Pn−1 z = i=0 wi · ai (Fig. 1(a)). This incurs heavy memory access overhead and long computational latencies, representing fundamental barriers to ultra-low-latency hardware implementation. To reduce memory cost and inference latency, BNNs binarize both weights and activations to bit values in {0, 1}, thereby transforming the computationally expensive MAC operation into a sequence of efficient bit-wise XNOR and popcount operations:
zb = popcount XNOR(wb , ab ) (1) where wb ∈ {0, 1} and ab ∈ {0, 1} are vectors of binary values. A BNN neuron is illustrated in Fig. 1(b). When mapped onto FPGAs, such as in the AMD FINN framework [27], this arithmetic-centric paradigm treats the LUTs merely as primitives for synthesizing numerical logic operations comprising XNOR gates and adders. Even with physical optimizations incorporating LUT packing [28] (e.g., merging multiple XNOR and corresponding popcount into a single 6-LUT), a k-LUT is confined to only a tiny fraction of its total functional space. This functional underutilization forces the network to rely on increased depth or width to compensate for the limited expressiveness of individual neurons, inevitably increasing total inference latency. B. LUT-as-Operator Paradigm To better exploit FPGA logic, LUTNet [17] introduces learnable LUTs into pretrained BNNs through an interpolation-based differentiable formulation, as illustrated in Fig. 1(c). However, this paradigm is limited by a structural mismatch between the single-bit output of a physical LUT and BNNs’ arithmetic datapath. In a standard BNN, multiple XNOR results are aggregated by a popcount operation, which produces results in the non-negative integer domain. In contrast, a k-LUT is strictly constrained to a single-bit output. As a result, when a k-LUT (k > 2) is used to replace multiple XNOR operations, it is forced to compress a multi-bit aggregate into a single-bit signal before the popcount stage. This mismatch restricts the expressivity of learned LUTs and largely constrains the optimization to converge toward the original BNN patterns. Ultimately, this structural

3

mismatch prevents the paradigm from effectively exploring the vast Boolean function space inherent to the underlying LUT primitive. C. LUT-as-Neuron Paradigm A more radical paradigm treats LUTs as standalone neurons as illustrated in Fig. 1(d). Unlike the operator-level approach, these methods use LUT configuration bits to encode both neural parameters and logic operations and utilize specific network topology, enabling a more direct mapping to the FPGA’s fundamental logic fabric. LTN [21] and DLN [22] rely solely on two-input logic gates without auxiliary operators such as popcount. They enumerate all possible Boolean functions of a gate to represent a neuron as a differentiable weighted combination of these functions. Training updates these weights, after which the Boolean function with the largest weight is selected. Achieving accuracy comparable to FINN on CIFAR-10 image classification, these works lower the latency to nanosecondlevel. Another method DWN [23] designs a discrete gradient function by extending finite difference [29], marking the first time this paradigm is scaled to 6-LUT neurons that align with modern FPGAs. These advancements inspire us to transform the FPGA fabric itself into a learnable LUT-native neural network to unlock the full potential for nanosecond-scale neural acceleration. D. Challenges While recent advances reveal the potential of using FPGAs as learnable neural substrates, porting this algorithmic success to high-performance hardware still faces three fundamental challenges. Challenge 1: Training-Hardware Mismatch The fundamental obstacle to LUT-native learning lies in the mathematical discrepancy between the discrete Boolean nature of FPGA LUTs and the continuous gradient-based optimization. Drawing from established principles in BNN research [30], [31], optimizing within a continuous domain typically yields higher training stability and performance compared to direct discrete domain training. While the logic of a LUT is distinct from the bit-wise arithmetic in BNNs, a LUT also operates within the binary domain and thus follows similar principles and necessitates a method to bridge discrete and continuous representations. Existing differentiable LUT formulations do not satisfy gradient consistency while remaining scalable. LUTNet [17] employs Lagrange interpolation for relaxation but fails to align with its BNN architecture. DLN and LTN [21], [22] assign a trainable weight to every single candidate in the enumerated Boolean function space. As a k-input LUT contains 2k bits k which can represent 22 distinct Boolean functions, the parameter complexity scales double-exponentially. For the widely used 6-LUT in modern FPGAs [25], this requires searching 6 across 22 = 264 ≈ 1.8 × 1019 functional weights per LUT, which is prohibitively expensive and fundamentally unscalable. DWN [23] attempts to enhance learning by augmenting the precise discrete gradient function [29] of LUT logic with an extension term. This heuristic introduces a mismatch

between forward and backward that undermines optimization consistency. These limitations prevent LUT-native networks from scaling to complex tasks while maintaining network performance. This motivates us to develop a differentiable LUT formulation that remains gradient-consistent, scales efficiently to 6-LUTs, and recovers hardware logic at its discrete boundaries. Challenge 2: Topology-Architecture Co-Design under FPGA Physical Constraints While individual LUTs are expressive, practical deployment requires organizing them into a network topology. A fundamental gap exists between the unconstrained algorithmic topology and the rigid routing fabric of FPGA physical architectures. Existing LUT-as-neuron methods often adopt unstructured (random or learnable) inter-neuron connectivity to maximize network performance. Our analysis reveals that such unstructured topologies are physically incompatible as they lead to non-local routing, forcing signals to traverse long distances across the FPGA fabric. To quantify this, we profile an MLP-style LUT-native network based on DWN [23], the SOTA 6-LUT based work, consisting of two 6-LUT layers with 2000 neurons each. Comparing unstructured (random) and structured connections based on post-placement and routing (post-P&R) implementation results, we observe that the former produces convoluted timing paths (Fig. 2(a)) while the latter yields a much more localized routing (Fig. 2(b)). Quantitatively, the structured topology achieves a 3.5× reduction in half-perimeter wirelength (HPWL) (Fig. 2(c)). This reduction enables the structured design to reach 526MHz, whereas the unstructured topology is restricted to 298MHz. Furthermore, as the number of LUTs per layer increases, the structured topology maintains a high and relatively stable maximum clock frequency (Fmax ), while the unstructured alternative shows significant frequency degradation (Fig. 2(d)). These results indicate that unstructured connectivity can directly undermine the physical implementability of LUT-native networks. Beyond restricting connectivity, this lack of locality also stems from the neglect of well-studied neural network principles, such as the hierarchical aggregation and local receptive fields inherent to CNN-style topologies. These principles are also naturally compatible with the FPGA’s localized fabric. Moreover, a dedicated topology alone is insufficient. Even with structured local connectivity, a naive mapping of a LUTnative CNN to hardware can result in excessive combinational logic depth, inter-layer throughput mismatches, and inefficient data movement. Addressing these bottlenecks requires a tight co-design of structured topology and a streaming architecture that preserves locality, balances dataflow, and ensures highfrequency timing closure. Challenge 3: Absence of Systematic Design Space Exploration The realization of a LUT-native network fundamentally redefines the accelerator’s design space, yet there remains an absence of systematic methodologies to explore its unique performance-resource trade-off. In conventional FPGA-based CNN accelerators, DSP and memory blocks are typically the dominant bottlenecks, while LUTs are treated as inexhaustible

4

LUT

LUT

LUT

LUT

LUT

LUT

(a) unstructured

(c) Cong. Level: Max Fan-out: HPWL: Fmax:

unstructured 4 (0.81%) 18 260631 298.06MHz

structured No ≥3 6 73495 526.31MHz (d)

LUT

LUT

LUT

LUT

LUT

LUT

(b) structured

Fig. 2. Profiling of connection topologies. (a, b) Post-P&R layout of unstructured and structured designs, highlighting top 10 critical paths. (c) Quantitative P&R results. The structured topology drastically reduces wirelength and achieve higher frequency. (d) Scaling behavior of Fmax versus LUT count. Structured topology maintains high frequency while the unstructured one causes severe frequency degradation.

auxiliary glue logic [10], [32]. However, the LUT-as-neuron paradigm creates a DSP/memory-free architecture, shifting the key design bottleneck to LUT utilization coupled with pipeline depth and inter-layer throughput coordination. This fundamental shift renders conventional DSP-centric analytical QoR models [33], [34] inapplicable, while prior LUT-native works [17], [22] remain restricted to hand-crafted implementations that fail to explore the broader design landscape. This absence of systematic exploration necessitates high-fidelity LUT-centric analytical QoR model and a latencydriven compilation framework for LUT-native streaming accelerators. Such a framework should automatically explore the performance-resource trade-off and generate optimized FPGA implementations, bridging the gap from well-trained networks to hardware realizations. E. Our Solution To address the above challenges, we develop FPGN, a LUT-native framework for nanosecond-scale neural accelerators on FPGA, with jointly designed differentiable training, physically-aware topology and architecture design, as well as automated compilation. First, to enable training-hardware consistency for LUTnative networks on FPGA, we introduce a differentiable relaxation for LUTs together with a progressive binarization strategy that gradually transitions the model toward exact binary deployment. • Leveraging the trainable LUT neurons, we design a physically-aware LUT-native topology with structured connectivity and a fully streaming hardware architecture to enable high-frequency neural acceleration by efficiently truncating long combinational paths. • Finally, to bridge trained networks and actual FPGA implementations, we develop a latency-driven compiler equipped with high-fidelity LUT-centric analytical QoR models, which guides design space exploration (DSE) and automatically generates efficient RTL implementations. •

Together, they establish a unified path from algorithmic training to nanosecond-scale neural inference on FPGA. III. H ARDWARE -A LIGNED T RAINING M ETHODOLOGY We first address the training-hardware mismatch challenge by developing an training method for LUT-native networks that remains consistent with exact FPGA hardware. The key idea is to formulate LUT computation in a differentiable relaxation and progressively drive this relaxation toward discrete boundaries, which enables efficient gradient-based training of LUT-native networks built on modern 6-LUT primitives. For simplicity, we refer to LUT configuration bits as weights throughout the remainder of this section. A. Differentiable LUT Formulation The core challenge in training LUT-native networks is that the LUT primitive is fundamentally discrete, which prevents direct gradient-based optimization. To bridge this gap, we relax the discrete LUT by explicitly modeling its hardware decoding logic via discrete equality indicator and introduce differentiable equality indicator. A hardware k-LUT is defined by k input bits x ∈ {0, 1}k k and 2k configuration bits w ∈ {0, 1}2 . Its output is selected from w by the discrete address encoded by x: idx(x) =

k−1 X

xi 2 i ,

X

fk (x, w) =

i=0

widx(u) · I(x; u)

u∈{0,1}k

(2) where idx(·) converts a binary vector to an integer lookup address, and I(x; u) is a discrete equality indicator to select the specific entry in the LUT that evaluates to 1 if the input x exactly matches the specific address pattern u, and 0 otherwise. In digital logic, the selection process is implemented via an address decoder. For each bit position i, the circuit checks for a match using the Boolean product: xi if ui = 1, and x̄i if ui = 0. Therefore, within the strict binary domain x ∈ {0, 1}k , the decoder can be explicitly written as the following product: ( k−1 Y 1 if u = x ui 1−ui I(x, u) = xi (1 − xi ) = (3) 0 otherwise i=0 To make it trainable, we relax the logic selection into a continuous process by allowing input to take real values, i.e., x ∈ Rk . Differentiable Equality Indicator: For a given vector x ∈ Rk and a binary pattern u = (uk−1 , . . . , u0 ) ∈ {0, 1}k , the equality indicator is defined as: δ(x; u) =

k−1 Y

xiui (1 − xi )1−ui

(4)

i=0

This function equals 1 when x = u and smoothly decreases to 0 at the bitwise complement ū. With this, the LUT output can be relaxed to the following continuous function: fk (x, w) =

X u∈{0,1}k

widx(u)

k−1 Y i=0

xiui (1 − xi ) 1−ui

(5)

5

and (iii) binary fine-tuning for hardware alignment. Inspired by BNN works [31], [35], we map real-valued weights to soft binary values through a sigmoid function with an adjustable temperature τ :

Fig. 3. Sigmoid and its derivative for different temperatures τ , together with the bimodal Gaussian initialization centered at µ = ±1. Smaller τ yields a sharper approximation to binary thresholding and a narrower informativegradient region. The initialization at ±1 is used only at the start of training (τ = 1) and serves as an empirical compromise between weak multiplicative gradients and sigmoid saturation.

With this differentiable formulation, the output becomes a linear combination of all weights, allowing gradients to flow to every weight and input during backpropagation. When the inputs x are restricted to the binary domain {0, 1}k , the relaxed formulation reduces exactly to the discrete hardware LUT lookup, as only one δ(x; u) equals one. At these discrete boundaries, the gradient with respect to the LUT weights becomes: ( 1 if u = x ∂fk (x, w) = (6) ∂widx(u) 0 otherwise This proves that our formulation exactly recovers discrete LUT logic at binary inputs while enabling gradient-based optimization, thereby addressing the gradient mismatch problem of EFD in DWN [23]. Additionally, this formulation provides a scalable computational foundation for training high-input LUT primitives. While the formulation exhibits O(2k ) complexity per neuron, it represents the minimal parameterization required k to span the entire 22 Boolean functional space. Unlike prior logic-native works [21], [22] that suffer from doublek exponential parameter explosion (O(22 )), FPGN aligns the optimization complexity with the physical capacity of LUT primitives. For the 6-LUTs prevalent in modern FPGAs, this reduces the number of trainable parameters per neuron from 6 22 function-selection weights to 64 LUT entries, addressing the scalability problem in Challenge 1.

1 w (7) wq = σ(w) = sigmoid( ) = w τ 1 + e− τ As shown in Fig. 3, a larger τ yields a smoother relaxation, while a smaller τ makes the mapping increasingly close to hard binary thresholding, pushing more relaxed weights toward the binary extremes. We therefore adopt a progressive annealing schedule for τ so that training starts from a smooth continuous relaxation and gradually approaches discrete binarization. This continuous stage mainly serves as an optimization mechanism that makes the gradient flow more dense to improve training efficiency. After this relaxed stage, training is further continued in the binary domain based on the gradient in Eq. (6), so that the learned LUTs are ultimately aligned with the deployed Boolean form. Gradient Attenuation Analysis: While soft binarization enables continuous optimization, gradients can attenuate severely during training due to two issues. First, the repeated multiplications in the differentiable equality indicator (Eq. (4)) naturally shrink gradients as they propagate to LUT inputs. Second, the sigmoid used for soft binarization function narrows the effective gradient region as |w| increases as shown in Fig. 3. To mitigate these effects, we initialize weights via a bimodal distribution using Gaussian distributions. Since this initialization is applied only at the beginning of training, it is interpreted with respect to the τ = 1 sigmoid curve in Fig. 3. We set the centers of the bimodal distribution to ±1 empirically as a practical compromise. Weights of this scale are sufficiently separated from zero to avoid overly weak multiplicative gradients in the LUT relaxation, while still remaining outside the strongly saturated region of the sigmoid. This initialization therefore allows gradients to flow across layers while preserving informative updates during the continuous optimization stage. By combining progressive annealing with bimodal initialization, this three-stage optimization strategy maintains stable gradient propagation for efficient training, while ensuring bit-precise alignment with the final FPGA implementation. Together with the scalable differentiable formulation, the hardware-aligned training methodology provides a robust solution to the inherent training-hardware mismatch.

B. Bridging the Continuous-Discrete Gap While the differentiable formulation enables gradient-based optimization, directly training LUTs with discrete binary k weights w ∈ {0, 1}2 as DWN [23] remains highly unstable [30], [31] and inefficient due to extreme gradient sparsity. As Eq. (6) shows, only the single weight indexed by current input x receives an update in each iteration, while the gradients for the remaining 2k −1 weights vanish. This extreme gradient sparsity fundamentally hinders the effective exploration of the massive Boolean functional space. To overcome this, we adopt a three-stage optimization strategy: (i) stable training on smooth continuous relaxation, (ii) progressive binarization to bridge the quantization gap,

IV. P HYSICALLY-AWARE N ETWORK T OPOLOGY AND H ARDWARE A RCHITECTURE Building on our training foundation, we now scale individual LUT primitives into physically-aware network topology and their physical implementations on FPGAs. To bridge the gap between unconstrained algorithmic connectivity and the rigid FPGA routing fabric (Challenge 2), we propose a hierarchical co-design framework spanning three levels: microtopology, macro-topology, and streaming architecture. Our core strategy is to enforce structural regularity throughout the hierarchy and transform abstract neural connections to deterministic FPGA dataflow.

6

A. Structured LUT-Native Micro-Topology To bridge the gap between the limited fan-in of a single kLUT and the coordinated operations across high-dimensional feature spaces of neural networks, we define structured microtopologies following the well-studied functionality from traditional CNNs, i.e., parallel processing and reduction units. Parallel Processing Units: To process input streams in parallel, we design the LUT-vector as the basic computation unit. A LUT-vector with No output bits is represented as a mapping I ∈ {0, 1}k×No → O ∈ {0, 1}No , where each output bit is generated by an independent k-LUT. As illustrated in Fig. 4(c), LUT-vector can be used to construct layers analogous to fully-connected (FC) layers where a k-LUT is a neuron. Reduction Units: We distinguish two reduction types based on their output domains. Binary Reduction: To aggregate multiple input bits into a single binary activation (I ∈ {0, 1}Ni → O ∈ {0, 1}), we employ a LUT-tree. As shown in Fig. 4(d), it forms a decreasing pyramidal structure of ⌈logk Ni ⌉ cascading LUT-vectors. This logarithmic depth ensures that the combinational delay increases minimally as input width scales, sustaining high-frequency operation. Integer Reduction: For scenarios that need sufficient precision, we utilize popcount units for binary-to-integer transitions (I ∈ {0, 1}Ni → O ∈ Z). In-Order Flattening: After algorithmically designing these units, the structured interconnection between these topologies is critical for physical efficiency. In traditional arithmeticcentric neural networks, data ordering is merely a memory indexing convention. However, in our LUT-native streaming architecture, the algorithmic data order is strictly equivalent to the physical hardware interconnection and pin assignment. By in-order flattening high-dimensional data (e.g., feature maps) into bit-vectors (Fig. 4(a)), we ensure that the output bits of one stage are fed into the next stage with local routing. Locality-Aware Padding: To maintain this structured connectivity when data dimensions across adjacent layers are mismatched, we propose locality-aware padding that processes the data sequence through a two-stage padding mechanism. Suppose a LUT-vector comprises Ntotal LUTs while the size of input bit-vector is M < k × Ntotal . First, we allocate the unique input bits to the initial Nbase = ⌈M/k⌉ LUT units. If the Nbase -th LUT lacks sufficient inputs, we perform a local padding to get M̂ = Nbase × k bits that vacant inputs are filled by sequentially repeating the available bits within the same LUT. Second, for the remaining (Ntotal − Nbase ) LUTs, we replicate the M̂ bits in order until all LUTs are fully occupied. Algorithmically, this dual-mechanism approach increases the average information utilization per LUT by ensuring no logic gates are left idle. From a hardware perspective, the first stage guarantees local connectivity while the second stage effectively distributes the fan-out pressure across all input bits rather than overloading a single source, preventing individual signal nets from becoming timing bottlenecks and ensuring a high operating frequency (Fmax ). In essence, these structured micro-topologies are interconnected via in-order connections with locality-aware padding,

ensuring routing locality and mitigating long-distance routing wires to sustain high operating frequency. This provides the foundation that enables us to build a sophisticated global network topology capable of complex tasks.

B. Hardware-Aware Network Topology Design While micro-topologies ensure local efficiency, cascading them blindly across a deep network risks global routing congestion and precision mismatch. To preserve this local efficiency macroscopically while obtaining high algorithmic accuracy, we compose these primitives into a hierarchical, three-stage topology as shown in Fig. 4 that mirrors traditional CNN structural paradigms to sustain high representation capacity on the FPGA fabric. Aggregation Stage: To mitigate information loss and eliminate costly floating-point preprocessing, we replace conventional quantization with a learned, pixel-wise aggregation layer. It is a convolutional-style layer featuring a LUT-tree as the 1×1 convolutional kernel to aggregate a pixel’s spatial bitvector, representing different input channels into a single informative activation. By allowing multiple aggregation channels, this mechanism not only aggregates the full input information into each bit but also enables diverse feature extraction across output channels using purely LUT-native operations. Feature Extraction Stage: This stage comprises a stack of residual blocks with LUT-native convolutional (LUT-Conv) layers implemented as channel-wise parallel LUT-vectors followed by popcount units to ensure sufficient precision for the subsequent layers. By performing an inherent k-to-1 mapping within each LUT, this architecture achieves a k-fold complexity reduction to popcount units, shrinking the adder-tree depth from O(log(N )) to O(log(N/k)). To sustain high-frequency timing closure, we maintain architectural homogeneity by eliminating floating-point routing overheads. Inspired by [36], we reposition the identity addition before the BN layer, ensuring that residual additions are performed directly on low-bit integer outputs from popcounts. Consequently, BN layers can be mathematically fused into the subsequent nonlinear binarization function as a simple integer comparison during inference (Fig. 4(e)), allowing all components to be mapped onto LUTs to completely eliminate DSP usage from our design. Output Stage: The final stage comprises cascaded FClayers (Fig. 4(c)) and a task-specific unit. For classification, the task-specific unit implements a popcount-based groupsum operation to produce the final scores with high numerical precision required for robust classification performance [16], [27], as illustrated in Fig. 4(f). By connecting these macro blocks through structured connections to maintain the locality of their underlying microtopologies, we establish a hardware-aware network topology that eliminates floating-point dependencies and reduces arithmetic complexity. This deterministic, LUT-native representation provides the structural regularity required for the fully streaming dataflow.

7

0 1 2 3 4 5

(a)In-order Flatten & Locality-Aware Padding

k-LUT ··· k-LUT k-LUT ··· k-LUT popcount popcounty y ls (b) LUT-Vector channe

with Popcount

k-LUT

g

b

Aggregation Aggregation Aggregation Convolutional

· ··

k-LUT

r

k-LUT ··· k-LUT k-LUT ··· k-LUT

(c) LUT-Vector with Structured Connections

Aggregation Stage

Integer Comp.

···

k-LUT

k-LUT

k-LUT

···

0 1 2 3 4 5 6 7 8 6 7 8 LUT1 LUT2 LUT3 LUT4 0 1 2 3 4 5 6 7 8 6 7 8

⌈𝑁𝑖 /𝑘⌉ LUTs k-LUT

(d) LUT-Tree

k-LUT

Integer

Binary

BN

... Identity

TABLE I S YMBOL D EFINITIONS FOR THE A NALYTICAL Q O R M ODEL logkNi layers

6 7 8

Binarize

Connection

Description

Network Layer Parameters (Inputs) Wi , Hi , Ciin , Ciout Width, height, and channels. ki , s i Kernel size, stride. Design Parameters (Inputs) wi , hi Column-wise and row-wise unroll factors.

Convolutional Integer Comp. Full-Connections Group Sum

Symbol

(e) BN Fusing ···

···

popcount

Feature Extraction Stage

···

(f)

popcount

Output Stage

Fig. 4. FPGN’s network topology. The network consists of hardware-friendly layers built on structured micro-topology (a-d,f). (e) Mathematical fusion of BN and binarization into a simple integer comparison.

C. Fully Streaming Hardware Architecture To implement the hardware-aware topology as a physical accelerator to achieve nanosecond-scale neural acceleration, we propose a fully streaming architecture as illustrated in Fig. 5, to optimize the LUT footprint for various FPGA resource constraints while simultaneously breaking down long combinational paths into a pipelined execution flow. Flexible Intra-Layer Spatial Computation: To dynamically adjust LUT resource utilization under different resource constraints, we design the processing units of convolutionalstyle layers (the aggregation and LUT-Conv stages) to support configurable unrolling by leveraging the kernel-sharing property of convolution [33]. By scaling the unroll factor of these kernels, the architecture allows for an adaptive tradeoff between diverse hardware resource budgets and inference latency. Adaptive Intra-layer Pipelining: To ensure high-frequency timing closure, we implement an adaptive pipelining strategy within the processing units. Intra-layer processing units are based on two primitive types, LUT-vectors (Fig. 5(a, c, e)) and popcount reduction units comprising balanced adder trees (Fig. 5(d, f)). Based on the logic depth of cascaded LUTs, pipeline registers are strategically inserted to maintain consistent timing. Furthermore, since the integer adders in popcount units are implemented to utilize FPGA CarryChain primitives [37], we adaptively insert registers based on the accumulated number of Carry-Chain stages to eliminate combinational bottlenecks. LUT-Efficient Inter-Layer Streaming: To support the unrolling mechanism and sustain high-throughput streaming, we propose a stationary-window circular line buffer (Fig. 5(b)) for inter-layer decoupling. These buffers enable concurrent write and read operations, ensuring a continuous dataflow. Standard unrolling typically results in complex, multi-address access patterns, necessitating LUT-consuming and timingcritical multiplexers (MUXs) to select data from various buffer offsets based on sliding window indices. Our design mitigates this by fixing the read window and shifting the data instead, effectively replacing high-fan-in selection logic with determin-

Resource Model (Outputs & Variables) Nl,i , Nr,i Resource consumption of LUT and Reg. Bi Number of input bits to a processing unit. Latency Model (Outputs & Variables) Sti , P ti Start cycle & Processing time. Tichunk Processing time of a chunk. startup Ti The time waiting for the startup data. Iti , Di Pipeline interval and delay. Ltotal Total latency of the entire network inference.

istic structural interconnects. Specifically, the buffer performs horizontal circular shifting during row-wise streaming and vertical row-promotion upon the completion of each line. Since these shifting patterns are hard-wired post-synthesis for a given unroll factor, the fan-in for each register remains minimal and constant. This optimization strategically reduces MUX complexity, thereby minimizing the total LUT footprint, ensuring high-frequency operation and routing feasibility. Based on these dedicated LUT and timing-oriented hardware optimizations, the fully streaming hardware architecture achieves a deterministic balance between high-throughput execution and high-frequency timing closure. By organizing individual LUT neurons into structured topology and mapping it to the LUT-native hardware design, we successfully translate the algorithmic advancement of differentiable LUTs into a high-performance FPGA realization. This architecture provides a flexible hardware template and defines the design space, enabling our compiler to systematically automate spatial unrolling and performance optimization across diverse resource-constrained scenarios.

V. L ATENCY-D RIVEN AUTOMATED C OMPILER While the streaming architecture provides a highperformance template, the massive design space renders manual optimization impractical, comprising diverse unrolling factors across multiple layers. To bridge this gap, we propose a latency-driven automated compiler that systematically navigates the trade-offs between hardware concurrency and resource constraints. To achieve this, we first establish an analytical QoR model to evaluate latency and resource consumption with high-fidelity by leveraging the deterministic nature of our LUT-native architecture. Based on this mathematical foundation, the compiler employs a hybrid DSE strategy combining heuristic search with Mixed-Integer Linear Programming (MILP) solver to search for the optimal configurations. Finally, the compiler instantiates the optimized parameters into a synthesizable RTL design using a library of pre-defined hardware templates.

Quant-layer

flatten to LUT-Vectors

circular line buffers

popcount reduction

Conv-layer

residual addition

FC-layer

(f)

...

+ ...... Reg+Reg threshold Reg Reg + critical ≥ + + ... + critical balanced... path balanced path adder-tree + + isolation adder-tree Reg isolation + Reg

popcount popcount

(e)

+❹ + + +❹ Reg Reg

in-order LUT LUT LUT LUT

unroll

(d)

LUT LUT LUT LUT

circular shift

LUT LUT LUT LUT LUT LUT

read out

...

(c)

LUT

LUT-Tree with in-order connections

LUT

LUT LUT LUT

pixel bit-wise flatten

(b)

(a) LUT LUT LUT LUT

... LUT LUT LUT

8

Group sum

Fig. 5. Overview of the FPGN streaming dataflow architecture. Inter-layer circular buffers decouple adjacent layers to sustain concurrency. At the intra-layer level, pipeline registers are adaptively inserted to break long timing path.

LUT count is determined by the input bit-width (Bi ) and the output channels (Ciout ). Under the unrolling mechanism, these costs are scaled by the unroll factors (wi · hi ) to reflect the parallel instantiation of the hardware units. This relationship ensures that the LUT footprint is predictable given the degree of spatial parallelism.

TABLE II K EY E QUATIONS FOR THE A NALYTICAL Q O R M ODEL Aspect

Component

Equation

Resource Model

LUT

Reg

Total

Quant kernel + N mux Nl,i = Nl,i l,i Conv = N kernel + N arith + N mux Nl,i l,i l,i l,i P grp sum Out = ) Nl,i (⌈Bi /ki ⌉ + Nl,i

Kernel

kernel = (⌈B /k ⌉ · C out ) · w · h Nl,i i i i i i

Total

Nr,i

Chunk

chunk = (k + (w − 1) × s ) × C out × W Nr,i i i i i i

Buffer

buffer = N chunk + max(N consumer , N Nr,i r,i r,i r,i

Latency Model Processing Time Start Time

Conv/Agg

pipe

buffer (h , h = Nr,i i i+1 , ki+1 , ...) + Nr,i

producer

)

P ti = (Hi /hi − 1) · Iti + Tichunk startup Sti = Sti−1 + Ti (+Di−1 if not Agg layer)

A. High-Fidelity Analytical QoR Modeling To enable precise DSE without the need for time-consuming logic synthesis, we develop an analytical QoR model that translates algorithmic parameters into physical QoR metrics by exploiting the deterministic mapping between our hardware primitives and the FPGA fabric. The requisite symbols are defined in Table I and key analytical formulations are summarized in Table II. 1) Timing Modeling: To ensure the generated architecture meets the target clock frequency (Fmax ), the timing model quantifies combinational delays based on the specific physical implementation of two components: the logic depth of cascaded LUTs and the stages of Carry-Chain based adders [37]. By tracking these propagation delays, the compiler determines the optimal intervals for pipeline register insertion. This process truncates long combinational paths and ensures that the critical path delay remains within the system clock period. 2) Resource Utilization Modeling: Since the proposed streaming architecture is purely LUT-native, it eliminates dependencies on heterogeneous blocks such as DSPs or BRAMs. Consequently, the resource model focuses exclusively on LUTs (Nl,i ) and registers (Nr,i ), where the total consumption is defined as the analytical summation across all layers based on the deterministic structural properties of the hardware. The LUT utilization (Nl,i ) for layer i is defined by the logic required for its LUT-native units, arithmetic logic, and MUXs of circular line buffers, while registers are mainly utilized for inter-layer line buffers and pipelining. kernel LUT-native Kernels (Nl,i ): The model accounts for the direct mapping of processing units to k-LUT primitives. The

arith Arithmetic Logic (Nl,i ): The arithmetic logic includes popcount units, as well as other integer operation such as adders and comparisons within residual blocks. Since a popcount operation comprises a tree of integer adders, and both adders and comparators are implemented using CarryChain primitives, their LUT costs is modeled as a function of the operand bit-width. Specifically, the total popcount popcount cost (Nl,i ) is a function of the compressed bit-width (Bi /k), reflecting the k-fold complexity reduction introduced in Sec. IV-B. Similarly to LUT-native kernels, this cost is also scaled by layer-specific unroll factors to ensure consistency with the overall datapath parallelism. MUX ): The LUT overhead for data Buffering MUXs (Nl,i shifting is modeled based on the MUX requirements of the circular line buffers. According to the stationary read window design and the shift mechanism, the fan-in for each buffer register remains constant for a given set of unroll factors. This allows the compiler to calculate the LUT resources requirement based on the fixed number of input sources to each MUX [37].

Register Modeling (Nr,i ): Register consumption is divided buffer into inter-layer line buffer cost (Nr,i ) and pipelining cost pipe (Nr,i ) for maintaining high-throughput streaming. In our design, since each channel is physically instantiated, the line buffer supports all channels simultaneously, making its size buffer (Nr,i ) a deterministic function of the number of rows. To quantify the buffering cost, we define a chunk as the minimum set of input rows required to sustain the slidingwindow computation, whose size is determined by the rowwise unroll factor (hi ) and network configurations (kernel size ki , and stride si ). To ensure unblocked inter-layer streaming, the line buffer is designed to satisfy the requirements of both the consumer and the producer. Specifically, the buffer is sized to store at least one active chunk for the current processing task while providing additional rows to meet both the subsequent chunk requirement by the consumer layer and new data bursts requirement from the producer layer. Additionally, the pipeline pipe register count (Nr,i ) is derived from the structural timing model to break combinational logic paths for satisfying timing requirement.

9

3) Streaming Latency Modeling: The end-to-end latency (Ltotal ) is defined as the completion time of the final layer in the streaming architecture, which is determined by a layerwise model of two fundamental components: start time (Sti ) and processing time (P ti ). Processing time (P ti ): This represents the steady-state execution time to process all data. Inspired by a Roofline-analysis [10], it is constrained by (i) the latency for processing a single data chunk (Tichunk ) (compute-bound), and (ii) the pipeline interval (Iti ), the time between launching two consecutive chunks (similar to memory-bound). Start time (Sti ): The start time captures the initial starvation period before a layer begins its first processing. For the first layer, Sti is determined by the system bandwidth (BW ) required to fill the initial buffer. For subsequent layers, Sti represents the cumulative time required for the producer to generate a valid data chunk, plus the pipeline delay (Di ). By integrating these timing, resource, and latency models, we establish a comprehensive analytical QoR model that captures the complex interactions between algorithmic unrolling and physical hardware constraints, transforming the streaming hardware architecture into a mathematical foundation for the automated DSE.

TABLE III E XPERIMENTAL S ETUP

Model

Layer (Reps)

Configuration

FPGN-3

Agg (×1)

Cin = 8, Cout = (m∗ //3) · k† Stride=2, Cout = m∗ · k† 2000 LUTs per layer

Conv (×3) FC (×2) FPGN-6

Agg (×1) Conv (×3) Conv (×3) FC (×2)

FPGN-MLP

FC (×4) (CIFAR) FC (×4) (KWS) FC (×3) (JSC-OpenML) FC (×3) (JSC-CERNBox)

∗ †

Cin = 8, Cout = (m∗ //3) · k† L1, 3, 5, Stride=2, Cout = m∗ · k† L2, 4, 6, Stride=1, Cout = m∗ · k† 2000 LUTs per layer 3000 LUTs per layer 2048/1024/384/64 LUTs 1000/1000/500 LUTs 4000/3000/2000 LUTs

m is set to 16 for Agg layer and 16, 32, 64 for different Conv layers. k is set to 1, 2, 4, 8 for -S, -M, -L, and -G, separately.

B. Latency-Driven Design Space Exploration With the analytical QoR model established, the goal of DSE is to identify the optimal set of unroll factors {wi , hi } for each layer i that minimizes the total inference latency (Ltotal ) under strict FPGA resource and system bandwidth constraints. This optimization problem is inherently non-linear and non-convex, primarily due to the max-based dependencies in pipeline intervals and cascaded products of unroll factors across layers introduced by the start-time (Sti ) dependence. To solve this optimization efficiently, we decompose the exploration into a two-level hybrid strategy that combines a heuristic search with Mixed-Integer Linear Programming (MILP). Outer-Level Heuristic Search. We utilize a steepestdescent search to explore the row-wise factors {hi }. Since {hi } directly governs the line buffer capacity and the interlayer synchronization delay (Sti ), it serves as the primary source of non-linearity. By isolating {hi } in the outer loop, the remaining sub-problem can be transformed into linear formulation. Inner-Level MILP Optimization. Given a fixed set of {hi }, the optimization of column-wise factors {wi } is linearized through a candidate-selection formulation. We define a binary decision variable yi,j ∈ {0, 1}, where yi,j = 1 if the j-th configuration from a pre-profiled candidate set Pi is selected for layer i. The inner-level optimization is then formulated as an MILP: min s.t.

Ltotal = Stlast + P tlast X yi,j = 1, j∈Pi

XX i

type yi,j · Ri,j ≤ Limittype ,

type ∈ LUT, Reg

j∈Pi

(8)

Fig. 6. Training loss and accuracy trajectories. Compared to the discrete EFD rule, the proposed continuous formulation enables denser gradient updates (Epochs 1–100) and preserves forward-backward consistency during binarization (Epochs 100–200), leading to more effective convergence.

By pre-calculating the resource costs and performance contributions for each candidate j given a fixed hi , the constraints and the objective function become linear combinations of yi,j . This allows the compiler to utilize industrial solvers to find a conditionally optimal column-wise unroll factor within seconds. Combined with the heuristic search, this hybrid strategy ensures a high-quality configuration that balances spatial unrolling for lowest latency under the resource constraints, effectively mapping the LUT-native network onto the target FPGA fabric. Upon identifying the high-quality set of unroll factors, the compiler instantiates these parameters into the streaming architecture via a modular RTL-level template library. This automated process generates a fully synthesizable hardware implementation, effectively transforming the mathematical optimization results into a physical FPGA realization with minimal labor cost.

10

Fig. 7. Training loss curves of FPGN under different initialization and staging configurations. Results show that the proposed three-stage strategy with µ = 1 (green) achieves the lowest final loss and best stability.

Fig. 8. Accuracy and LUT usage of FPGN networks on CIFAR-10 dataset with different depths and scales.

VI. E VALUATION A. Experimental Setups We evaluate the proposed FPGN framework across two architectural categories: (i) CNN-style FPGN-3/6 with various widths; and (ii) MLP-style configurations (FPGN-MLP). The detailed layer configurations are summarized in Table III. These networks are trained from scratch on the CIFAR-10 [24], SVHN [38], KWS [39], and JSC (CERNBox version [40] and OpenML version [41]) datasets using PyTorch on NVIDIA A30 GPUs. We compare FPGN against three representative paradigms: binary arithmetic centric (AMD official BNN framework FINN [27]), LUT-as-operator (LUTNet [17]), and LUT-as-neuron (DWN [23], PolyLUT [18], NeuraLUT [19], AmigoLUT [42], and NeuraLUT-Assemble [20]). For FPGA implementation, Post-P&R metrics are obtained from AMD Vivado 2024.2, targeting the Versal Premium VP1902 platform (CNN-style networks) and Virtex UltraScale+ VU9P platform (MLP-style networks). The compiler is executed on an Intel i7-12700 CPU. B. Training Methodology Validation We first validate our training methodology. This ensures that the subsequent architectural and physical results are grounded in an efficient and stable training process. 1) Training Efficiency: To evaluate the proposed continuous relaxation, we conduct an ablation study by comparing it with the discrete EFD method from DWN [23], the SOTA 6-LUTbased differentiable network, using FPGN-3-S on CIFAR10. For a fair comparison, we deploy the EFD rule within

Fig. 9. Compiler-estimated latency-LUT trade-off for FPGN-6-S/M/L/G under different unroll factors. S/M/L/G scale width to invest more LUTs for higher accuracy, while unroll factors trade LUTs for lower latency.

FPGN’s topology. As illustrated in Fig. 6, the EFD baseline converges more slowly and exhibits larger fluctuations because its discrete perturbations restrict gradient updates to a single active entry out of the 2k truth-table parameters per input sample. Conversely, during the relaxed optimization phase (Epochs 1–100), our continuous relaxation allows gradients to reach all 2k LUT entries, yielding faster loss reduction and higher classification accuracy. Additionally, EFD relies on an approximate gradient heuristic, which can introduce a mismatch between the discrete forward LUT logic and the backward optimization, which can reduce optimization effectiveness. In contrast, the proposed formulation recovers the exact finite-difference result at binary points. During progressive binarization and binary fine-tuning, FPGN maintains lower loss and higher accuracy than EFD, demonstrating more effective optimization under identical topological constraints. 2) Ablation Study of Training Strategy: We then evaluate the three-stage training strategy by comparing it against two baselines: vanilla binarization (trained entirely within the binary domain from scratch) and direct fine-tuning (immediately transitioning to the binary domain at Epoch 40, skipping the progressive stage). As illustrated in Fig. 7, Vanilla Binarization suffers from the highest loss and significant instability, as direct binary optimization from scratch leads to severe gradient fluctuations. While Direct Fine-tuning benefits from floatingpoint pre-training, the abrupt transition at Epoch 40 triggers a sharp loss spike that remains irrecoverable throughout the subsequent fine-tuning phase. In contrast, our methodology achieves significantly lower loss and superior stability, confirming that the progressive transition is essential for bridging the representation gap between continuous and binary states. 3) Ablation Study of Bimodal Initialization: We further analyze the sensitivity of bimodal initialization by varying the mean value (µ). Loss curves are shown in Fig. 7. For µ ≥ 2, convergence during the FP training is hindered by vanishing gradients as weights reside within sigmoid saturation regions. In contrast, while µ = 0.5 facilitates rapid initial convergence, it causes weights to concentrate near the decision boundary (zero), leading to severe fluctuations during the progressive binarization and binary fine-tuning phases. As visualized in the exponential moving average (EMA) inset, this

11

TABLE IV E ND - TO -E ND P ERFORMANCE AND H ARDWARE E FFICIENCY C OMPARISON FOR CNN-S TYLE N ETWORKS Physical Metrics Method

Plat.

Same Platform Norm. (rel. to FINN) Fmax

Acc.

LUT

FF

BRAM

Power†

Latency

FPS

FPS/LUT

kFPS/W

Latency

FPS

FPS/LUT

kFPS/W

CIFAR-10 Dataset FINN LUTNet

KU115 KU115

228MHz 80.1% 200MHz 84.8%

49.8k 106.8k

67k –

116 –

3.3 W 5.4 W

194 µs –

29.6k 10.2k

0.59 0.10

8.97 1.89

1× –

1× 0.34×

1× 0.17×

1× 0.21×

FINN FPGN

VP1902 VP1902

327MHz 205MHz

80.1% 82.9%

49.6k 2.46M

72k 924k

120 0

8.7 W 89.8 W

135 µs 658 ns

42.5k 3.21M

0.86 1.30

4.89 35.75

1× 1/205×

1× 75.53×

1× 1.51×

1× 7.31×

SVHN Dataset FINN LUTNet

KU115 KU115

228MHz 94.9% 200MHz 96.4%

49.8k 361.5k

67k –

116 –

3.3 W –

194 µs –

29.6k 10.2k

0.59 0.03

8.97 –

1× –

1× 0.34×

1× 0.05×

1× –

FINN FPGN

VP1902 VP1902

327MHz 205MHz

49.6k 2.46M

72k 924k

120 0

8.7 W 89.8 W

135 µs 658 ns

42.5k 3.21M

0.86 1.30

4.89 35.75

1× 1/205×

1× 75.53×

1× 1.51×

1× 7.31×

94.9% 95.1%

–: Metric is not reported or cannot be directly derived from the available implementation/report. †: Power follows the reported value for prior published results and Vivado-estimated on-chip power for re-implemented designs.

Fig. 10. Correlation between compiler-estimated and Vivado postimplementation resources. The strict linear trend (Pearson > 0.99) ensures the DSE algorithm correctly identifies optimal configurations.

the designed topology provides the necessary framework for high-frequency implementations. This architecture also supports different unroll factors for latency optimization by the latency-driven compiler. Fig. 9 illustrates a latency-resource trade-off under different unroll factors for FPGN-6. The four FPGN-6 variants scale model width to improve accuracy, at the cost of increased LUT usage. Since these FPGN-6 variants share the same depth and streaming schedule, they achieve the same latency under the same unroll factors, while wider variants require more LUTs. Therefore, smaller variants provide lower-resource deployment options with the expected accuracy trade-off, whereas larger variants reach higher accuracy under higher LUT budgets. D. Latency-Driven Compiler Validation

instability results in loss increase. Consequently, µ = 1 proves optimal, striking a balance between rapid initial convergence and robustness against binarization-induced perturbations.

C. Topology Design Validation We validate the CNN-style topology that serves as the structural foundation for achieving massive spatial parallelism and ultra-low latency. The architecture allows for flexible scaling across both width and depth dimensions. We evaluate this scalability by comparing the shallower FPGN-3 and the deeper FPGN-6, across four scales (S, M, L, and G). As illustrated in Fig. 8, both configurations achieve accuracy gains as the network scales in width, demonstrating the robustness of our topology under width-oriented expansion. While expanding layer width effectively enhances expressivity, our analysis reveals that depth scaling is fundamentally more resourceefficient than width-oriented expansion for LUT-native architectures. A primary observation is the comparison between FPGN-6-L and FPGN-3-G: the deeper FPGN-6-L outperforms the shallower but wider FPGN-3-G by 0.57% in accuracy while utilizing 30% fewer LUT resources. These results confirm the scalability of the proposed CNN-style topology. Combined with the structured connectivity analyzed in Sec. II,

1) Compiler Fidelity: Our compiler utilizes a LUT-centric analytical QoR model to navigate the vast design space. To validate its fidelity, we compare its estimates against Vivado postP&R results. For latency, since the FPGN architecture avoids dynamic scheduling, the predicted cycle counts are deterministic and precisely match the simulated hardware behavior. Regarding resource modeling, predicting post-P&R utilization is inherently challenging due to aggressive logic optimizations (e.g., constant folding and retiming) by EDA tools. Thus, analytical models typically yield inaccurate absolute resource counts. However, for an automated DSE solver, the relative ordering is far more critical than absolute precision [43], [44]. As demonstrated in Fig. 10, our resource estimation exhibits a near-perfect linear correlation with physical implementations, achieving Pearson correlation coefficients of 0.996 for LUTs and 0.999 for Registers. This exceptional fidelity stems from the deterministic nature of our LUT-native templates, which minimizes unpredictable mapping. By using the regression slope as a calibration factor, we systematically close the gap between analytical abstraction and physical synthesis, ensuring our MILP solver reliably converges to the true hardware optimum. 2) DSE Solver Efficiency: The proposed heuristic-MILP solver demonstrates high practical efficiency. When optimizing

12

the complex FPGN-6-G network under resource constraints, a brute-force search over the vast unroll factor space would require days to complete due to the QoR model complexity. In contrast, our solver identifies a high-quality solution in only 16 seconds. This significant speedup confirms that our compiler provides an efficient and automated path from trained networks to optimized hardware implementations, enabling rapid design iteration for various architectures across diverse FPGA fabrics. E. End-to-End Evaluation Having validated each contribution independently, we now present a comprehensive end-to-end evaluation, comparing FPGN against representative SOTA works across three distinct paradigms. To ensure a fair comparison, We re-implemented the AMD Xilinx Official FINN on the same FPGA platform with LUTNet and FPGN as a normalization reference. 1) Comparison with Arithmetic-Centric Paradigm: As motivated in Sec. I, FPGN prioritizes nanosecond-scale response over resource constraints. On CIFAR-10 datasets, FPGN-6G achieves a deterministic latency of 658 ns and a peak throughput of 3.21 M FPS (Table IV). Compared to the BNN baseline (FINN), FPGN delivers a 205× absolute latency reduction and 75.53× throughput increase. This radical performance leap is enabled by a fundamental shift from sequential time-multiplexed execution to spatial investment of 2.46M LUTs. While FINN relies on timemultiplexed processing units and could theoretically improve performance by increasing parallelism, our normalized efficiency (FPS/LUT) reveals an inherent architectural gap. As shown in Table IV, FPGN achieves 1.51× higher LUT efficiency than FINN. This implies that even if FINN utilized the same number of LUTs as FPGN, its throughput and latency would still fall significantly short of FPGN’s. By treating LUTs as neurons, FPGN fully unleashes the fabric’s Boolean expressive power. FFs in FPGN are primarily used for pipeline registers and inter-layer line buffers, while LUT utilization remains the dominant resource constraint. Since all trained parameters are embedded directly in LUT configurations, FPGN requires no BRAM for weight storage and DSP/AIE for computation. Together with its highly parallel streaming execution, this LUT-native datapath achieves 7.31× higher energy efficiency (kFPS/W) than the same-platform FINN baseline. This confirms that for ultra-low-latency regimes, the LUTas-neuron paradigm is not only faster but also more powerefficient than the traditional arithmetic-centric paradigm. 2) Comparison with LUT-as-Operator Paradigm: FPGN further demonstrates superior hardware efficiency compared to LUTNet, which also employs the 6-LUT fabric but represents the LUT-as-operator paradigm. While LUTNet replaces fixed XNOR gates with differentiable LUTs to increase expressive power, it retains the BNN datapath. As shown in Table IV, although LUTNet utilizes LUT primitives, its hardware utility is severely constrained by this hybrid nature. On CIFAR10, FPGN delivers a 222× throughput speedup with 9× higher LUT efficiency (FPS/LUT) over LUTNet. Unlike FINN and FPGN which share identical configurations across tasks, LUTNet incorporates heuristic pruning, leading to a varying

TABLE V E ND - TO -E ND P ERFORMANCE AND H ARDWARE E FFICIENCY C OMPARISON FOR MLP-S TYLE N ETWORKS Dataset

Method

JSC CERNBox

PolyLUT NeuraLUT AmigoLUT NeuralLUTAssemble FPGN

Acc.

LUT

REG

Fmax

Latency

75.1% 75.0% 74.4%

236541 92357 42742

12384 4885 4717

235 MHz 368 MHz 520 MHz

21.0 ns 14.0 ns 9.6 ns

75.0%

8539

1332

352 MHz

5.7 ns

74.9%

12358

4839

669 MHz

6.0 ns

DWN NeuraLUTAssemble FPGN

76.3%

6302

4128

695 MHz

14.4 ns

76.0%

1780

540

941 MHz

2.1 ns

76.0%

3345

1703

730 MHz

5.5 ns

KWS

DWN FPGN

71.5% 72.5%

6169 3522

1686 1607

287 MHz 407 MHz

3.5 ns 2.5 ns

CIFAR-10

DWN FPGN

57.4% 58.1%

20837 15336

3167 2649

276 MHz 353 MHz

14.5 ns 5.7 ns

JSC OpenML

model size on SVHN. On this dataset, FPGN’s achieves a 30× higher LUT efficiency than LUTNet. This demonstrates that simply replacing binary operators with LUTs without rethinking the underlying topology is inherently inefficient, leaving LUTs’ intrinsic expressivity and the fabric’s LUTnative potential largely underutilized. While LUTNet exhibits a marginally higher accuracy, this advantage relies on external orthogonal algorithmic heuristics, such as residual binarization [11], which FPGN intentionally excludes in comparison to isolate and validate the intrinsic raw efficiency of its LUT-native architectural paradigm. By applying 4-bit residual binarization, FPGN-6-L achieves a LUTNet-comparable accuracy of 84.42% with a LUT budget similar to FPGN-6-G. Furthermore, similar to FINN, LUTNet suffers from the power overheads due to weight-related memory accesses. By contrast, FPGN delivers a substantial 34.8× energy efficiency improvement over LUTNet, proving that LUT-as-neuron paradigm is the more viable path for achieving nanosecond-scale neural acceleration on FPGA. 3) Comparison with LUT-as-Neuron Paradigm: We evaluate FPGN-MLP variants against SOTA micro-scale LUTas-neuron networks under identical hardware baselines. Table V summarizes the results. Compared with DWN [23], the closest 6-LUT-based differentiable baseline, FPGN achieves comparable or higher accuracy across CIFAR-10, KWS, and JSC-OpenML dataset while using fewer LUTs. Its structured connectivity also enables lower latency. On CIFAR-10, FPGN and DWN consume 3.864 W and 3.891 W, respectively, demonstrating comparable power consumption. We further compare FPGN with function-parameterized MLP-style methods. As shown in Table V, all works achieve competitive classification accuracy on two JSC versions. FPGN consumes fewer LUTs than PolyLUT, NeuraLUT, and AmigoLUT. This demonstrates that directly optimizing the global relaxation space of physical LUT entries expands the functional design space, thereby maximizing LUT expressivity. NeuraLUT-Assemble achieves higher resource efficiency on micro-scale networks. However, its reported end-to-end latency increases from 2.1 ns on JSC-OpenML to 5.7 ns on the more complex JSC-CERNBox workload. Since latency jointly

13

reflects clock frequency and pipeline depth, this increase indicates reduced end-to-end latency scalability as the model size grows. In comparison, FPGN’s structured connectivity is designed to preserve routing locality and latency scalability for larger deployments. 4) Discussion: Our primary comparisons focus on fully binary networks for ultra-low-latency inference. For broader context, a full-precision ResNet-20 achieves 91.25% accuracy on CIFAR-10 with a measured batch-1 latency of 9 ms on an NVIDIA A30 GPU. Representative INT8/INT16 FPGA implementations retain approximately 90% accuracy but operate at millisecond-scale latency [45], [46]. Hybrid BNNs that preserve partial high-precision operations achieve approximately 86%–88% accuracy with representative FPGA latency in the hundreds-of-microseconds range [47], [48]. Fully binary FPGA frameworks such as FINN operate at 80.1% accuracy with ∼ 200µs latency [27]. FPGN targets the extreme lowlatency end of this design space, achieving 82.9% accuracy with 658 ns latency. These representative results illustrate a general trend in which lower-precision paradigms trade accuracy for reduced inference latency. This study focuses on the fully binary operating regime rather than exhaustively exploring all intermediate precision and architecture configurations, which remains an important direction for future work. Additionally, while following prior LUT-native networks to evaluate FPGN on CNN- or MLP-style architectures, FPGN’s primitives (LUT-Vector/Tree) map to matrix multiplication and reduction and can be applied to linear operations within Transformer architectures (e.g., QKV projections). One future direction is to extend FPGN to more network architectures and more tasks. VII. C ONCLUSION In this work, we propose FPGN, a holistic co-design framework achieving nanosecond-scale neural acceleration via the novel LUT-as-neuron paradigm. By integrating hardwarealigned training, physically-aware topology, streaming hardware architecture, and latency-driven compilation, FPGN provides an end-to-end solution to translate algorithmic neurons to physical accelerators. Evaluations demonstrate a 205× latency reduction, alongside 30× higher LUT efficiency than SOTA LUT-as-operator methods. FPGN establishes a robust foundation for sub-microsecond neural acceleration, effectively unlocking the intrinsic logic speed of FPGA fabrics for the most demanding latency-critical applications. R EFERENCES [1] A. Vaswani, N. Shazeer, N. Parmar, J. Uszkoreit, L. Jones, A. N. Gomez, Ł. Kaiser, and I. Polosukhin, “Attention is all you need,” Advances in neural information processing systems, vol. 30, 2017. [2] K. He, X. Zhang, S. Ren, and J. Sun, “Deep residual learning for image recognition,” in Proceedings of the IEEE conference on computer vision and pattern recognition, pp. 770–778, 2016. [3] X. Guo, T. Bunarjyan, D. Liu, B. Lienhard, and M. Schulz, “Klinq: Knowledge distillation-assisted lightweight neural network for qubit readout on fpga,” in 2025 62nd ACM/IEEE Design Automation Conference (DAC), pp. 1–7, IEEE, 2025. [4] V. Le, N. Vora, D. Brahmbhatt, Y. Xu, G. Huang, and P. V. Nguyen, “Computing systems for superconducting qubits: Challenges and opportunities,” in Proceedings of the 23rd Annual International Conference on Mobile Systems, Applications and Services, pp. 771–774, 2025.

[5] H. Jia, Y. Huan, C. Ding, Y. Yan, J. Cui, J. Wang, C. Cai, L. Xu, Z. Zou, and L. Zheng, “A domain-specific accelerator for ultralow latency market data distribution system,” IEEE Transactions on Industrial Informatics, vol. 19, no. 4, pp. 5465–5475, 2022. [6] S. Yoo, H. Kim, J. Kim, S. Park, J.-Y. Kim, and J. Oh, “Lighttrader: A standalone high-frequency trading system with deep learning inference accelerators and proactive scheduler,” in 2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA), pp. 1017– 1030, IEEE, 2023. [7] T. Swamy, A. Rucker, M. Shahbaz, I. Gaur, and K. Olukotun, “Taurus: a data plane architecture for per-packet ml,” in Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 1099–1114, 2022. [8] S. U. Jafri, S. Rao, V. Shrivastav, and M. Tawarmalani, “Leo: Online {ML-based} traffic classification at {Multi-Terabit} line rate,” in 21st USENIX Symposium on Networked Systems Design and Implementation (NSDI 24), pp. 1573–1591, 2024. [9] A. Boutros, A. Arora, and V. Betz, “Field-programmable gate array architecture for deep learning: Survey and future directions,” Proceedings of the IEEE, 2025. [10] C. Zhang, P. Li, G. Sun, Y. Guan, B. Xiao, and J. Cong, “Optimizing fpga-based accelerator design for deep convolutional neural networks,” in Proceedings of the 2015 ACM/SIGDA international symposium on field-programmable gate arrays, pp. 161–170, 2015. [11] M. Ghasemzadeh, M. Samragh, and F. Koushanfar, “Rebnet: Residual binarized neural network,” in 2018 IEEE 26th annual international symposium on field-programmable custom computing machines (FCCM), pp. 57–64, IEEE, 2018. [12] A. Ramachandran, S. Kundu, and T. Krishna, “Microscopiq: Accelerating foundational models through outlier-aware microscaling quantization,” in Proceedings of the 52nd Annual International Symposium on Computer Architecture, pp. 1193–1209, 2025. [13] Y.-C. Ding, C.-Y. Chang, C.-Y. Lin, H.-Y. Tsai, H.-J. Tu, K.-F. Chang, Y.-C. Su, T.-H. Hsieh, Y.-K. Jian, W.-C. Chen, et al., “2.5 a 16nm 5.7 tops cnn processor supporting bi-directional fpn for small-object detection on high-resolution videos,” in 2025 IEEE International SolidState Circuits Conference (ISSCC), vol. 68, pp. 1–3, IEEE, 2025. [14] E. Nurvitadhi, D. Kwon, A. Jafari, A. Boutros, J. Sim, P. Tomson, H. Sumbul, G. Chen, P. Knag, R. Kumar, et al., “Why compete when you can work together: Fpga-asic integration for persistent rnns,” in 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 199–207, IEEE, 2019. [15] P. Lei, J. Liang, Z. Guan, J. Wang, and T. Zheng, “Acceleration of fpga based convolutional neural network for human activity classification using millimeter-wave radar,” IEEE Access, vol. 7, pp. 88917–88926, 2019. [16] M. Rastegari, V. Ordonez, J. Redmon, and A. Farhadi, “Xnor-net: Imagenet classification using binary convolutional neural networks,” in European conference on computer vision, pp. 525–542, Springer, 2016. [17] E. Wang, J. J. Davis, P. Y. Cheung, and G. A. Constantinides, “Lutnet: Learning fpga configurations for highly efficient neural network inference,” IEEE Transactions on Computers, vol. 69, no. 12, pp. 1795–1808, 2020. [18] M. Andronic and G. A. Constantinides, “Polylut: learning piecewise polynomials for ultra-low latency fpga lut-based inference,” in 2023 International Conference on Field Programmable Technology (ICFPT), pp. 60–68, IEEE, 2023. [19] M. Andronic and G. A. Constantinides, “Neuralut: Hiding neural network density in boolean synthesizable functions,” in 2024 34th International Conference on Field-Programmable Logic and Applications (FPL), pp. 140–148, 2024. [20] M. Andronic and G. A. Constantinides, “Neuralut-assemble: Hardwareaware assembling of sub-neural networks for efficient lut inference,” in 2025 IEEE 33rd Annual International Symposium on FieldProgrammable Custom Computing Machines (FCCM), pp. 208–216, IEEE, 2025. [21] F. Petersen, C. Borgelt, H. Kuehne, and O. Deussen, “Deep differentiable logic gate networks,” Advances in Neural Information Processing Systems, vol. 35, pp. 2006–2018, 2022. [22] F. Petersen, H. Kuehne, C. Borgelt, J. Welzel, and S. Ermon, “Convolutional differentiable logic gate networks,” Advances in Neural Information Processing Systems, vol. 37, pp. 121185–121203, 2024. [23] A. T. Bacellar, Z. Susskind, M. Breternitz Jr, E. John, L. K. John, P. Lima, and F. M. França, “Differentiable weightless neural networks,” arXiv preprint arXiv:2410.11112, 2024. [24] S. Zagoruyko, “92.45% on cifar-10 in torch.” http://torch.ch/blog/2015/ 07/30/cifar.html.

14

[25] A. Boutros and V. Betz, “Fpga architecture: Principles and progression,” IEEE Circuits and Systems Magazine, vol. 21, no. 2, pp. 4–29, 2021. [26] D. Hoang, A. Gupta, and P. C. Harris, “Kanelé: Kolmogorov–arnold networks for efficient lut-based evaluation,” in Proceedings of the 2026 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pp. 44–55, 2026. [27] Y. Umuroglu, N. J. Fraser, G. Gambardella, M. Blott, P. Leong, M. Jahre, and K. Vissers, “Finn: A framework for fast, scalable binarized neural network inference,” in Proceedings of the 2017 ACM/SIGDA international symposium on field-programmable gate arrays, pp. 65–74, 2017. [28] T. Ahmed, P. D. Kundarewich, and J. H. Anderson, “Packing techniques for virtex-5 fpgas,” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 2, no. 3, pp. 1–24, 2009. [29] J. C. Strikwerda, Finite difference schemes and partial differential equations. SIAM, 2004. [30] M. Courbariaux, Y. Bengio, and J.-P. David, “Binaryconnect: Training deep neural networks with binary weights during propagations,” Advances in neural information processing systems, vol. 28, 2015. [31] Z. Liu, B. Wu, W. Luo, X. Yang, W. Liu, and K.-T. Cheng, “Bi-real net: Enhancing the performance of 1-bit cnns with improved representational capability and advanced training algorithm,” in Proceedings of the European conference on computer vision (ECCV), pp. 722–737, 2018. [32] Z. Liu, Y. Dou, J. Jiang, J. Xu, S. Li, Y. Zhou, and Y. Xu, “Throughputoptimized fpga accelerator for deep convolutional neural networks,” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 10, no. 3, pp. 1–23, 2017. [33] Y. Ma, Y. Cao, S. Vrudhula, and J.-S. Seo, “Performance modeling for cnn inference accelerators on fpga,” IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, vol. 39, no. 4, pp. 843– 856, 2019. [34] W. Huang, H. Wu, Q. Chen, C. Luo, S. Zeng, T. Li, and Y. Huang, “Fpgabased high-throughput cnn hardware accelerator with high computing resource utilization ratio,” IEEE Transactions on Neural Networks and Learning Systems, vol. 33, no. 8, pp. 4069–4083, 2021. [35] H. Qin, R. Gong, X. Liu, M. Shen, Z. Wei, F. Yu, and J. Song, “Forward and backward information retention for accurate binary neural networks,” in Proceedings of the IEEE/CVF conference on computer vision and pattern recognition, pp. 2250–2259, 2020. [36] K. He, X. Zhang, S. Ren, and J. Sun, “Identity mappings in deep residual networks,” in European conference on computer vision, pp. 630–645, Springer, 2016. [37] Advanced Micro Devices, Inc., “7 series fpgas configurable logic block user guide (ug474).” https://docs.amd.com/r/en-US/ug474 7Series CLB, 2025. [38] Y. Netzer, T. Wang, A. Coates, A. Bissacco, B. Wu, A. Y. Ng, et al., “Reading digits in natural images with unsupervised feature learning,” in NIPS workshop on deep learning and unsupervised feature learning, vol. 2011, p. 7, Granada, 2011. [39] P. Warden, “Speech commands: A dataset for limited-vocabulary speech recognition,” arXiv preprint arXiv:1804.03209, 2018. [40] CERN Collaboration, “CERNBox LHC Jets Dataset.” https://cernbox. cern.ch/s/jvFd5MoWhGs1l5v/download, 2025. Accessed: 2024-11-01. [41] OpenML Contributors and LHC Jets HLF Curators, “hls4ml lhc jets hlf (OpenML Dataset 42468).” https://www.openml. org/d/42468, 2020. Accessed: 2024-11-01. [42] O. Weng, M. Andronic, D. Zuberi, J. Chen, C. Geniesse, G. A. Constantinides, N. Tran, N. J. Fraser, J. M. Duarte, and R. Kastner, “Greater than the sum of its luts: Scaling up lut-based neural networks with amigolut,” in Proceedings of the 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pp. 25–35, 2025. [43] L. Du, T. Liang, X. Zhou, J. Ge, S. Li, S. Sinha, J. Zhao, Z. Xie, and W. Zhang, “Fado: Floorplan-aware directive optimization based on synthesis and analytical models for high-level synthesis designs on multi-die fpgas,” ACM Transactions on Reconfigurable Technology and Systems, vol. 17, no. 3, pp. 1–33, 2024. [44] L. Guo, Y. Chi, J. Wang, J. Lau, W. Qiao, E. Ustun, Z. Zhang, and J. Cong, “Autobridge: Coupling coarse-grained floorplanning and pipelining for high-frequency hls design on multi-die fpgas,” in The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 81–92, 2021. [45] Y. Zhang, B. Sun, W. Jiang, Y. Ha, M. Hu, and W. Zhao, “Wsqaddernet: Efficient weight standardization based quantized addernet fpga accelerator design with high-density int8 dsp-lut co-packing optimization,” in Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, pp. 1–9, 2022. [46] J. Qiu, J. Wang, S. Yao, K. Guo, B. Li, E. Zhou, J. Yu, T. Tang, N. Xu, S. Song, et al., “Going deeper with embedded fpga platform for

convolutional neural network,” in Proceedings of the 2016 ACM/SIGDA international symposium on field-programmable gate arrays, pp. 26–35, 2016. [47] A. Fayyazi, M. Nazemi, A. Fayyazi, and M. Pedram, “Neuroblend: Towards low-power yet accurate neural network-based inference engine blending binary and fixed-point convolutions,” in Proceedings of the Great Lakes Symposium on VLSI 2024, pp. 730–735, 2024. [48] Y. Zhang, J. Pan, X. Liu, H. Chen, D. Chen, and Z. Zhang, “Fracbnn: Accurate and fpga-efficient binary neural networks with fractional activations,” in The 2021 ACM/SIGDA International Symposium on FieldProgrammable Gate Arrays, pp. 171–182, 2021.