CODA: Algorithm-Hardware Co-design for Edge Video Diffusion via NMP-Enabled Compute-Cache Operator Disaggregation

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CODA: Algorithm-Hardware Co-design for Edge Video Diffusion via NMP-Enabled Compute-Cache Operator Disaggregation

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arXiv CS · Papers · License: Open Access · 2026

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cloud distributedcomputing parallelcomputing

distributed computing, parallel computing, cloud

arXiv:2607.14908v1 [cs.AR] 16 Jul 2026

CODA: Algorithm-Hardware Co-design for Edge Video Diffusion via NMP-Enabled Compute-Cache Operator Disaggregation Yuanpeng Zhang

YuXuan Wu

Yitong Xiao

Peking University Beijing, China [email protected]

Chenhao Xue

Yi Ren

Cong Li

Peking University Beijing, China [email protected]

Yihan Yin

Dimin Niu

Guangyu Sun

Peking University Beijing, China [email protected]

Alibaba Group Inc. Hangzhou, China [email protected]

Peking University Beijing, China [email protected]

Abstract

Deploying Video Diffusion Models (VDMs) on edge devices is appealing for localized and privacy-preserving generation, but their iterative Transformer-based denoising remains too slow for practical local inference. Cross-Timestep Caching (CTC) has emerged as a promising direction for reducing redundant computation, reusing activations across adjacent denoising steps rather than modifying model weights, while largely preserving generation fidelity. However, on memory-constrained edge GPUs, CTC requires a massive cache footprint that quickly exceeds on-device VRAM and forces the cache into host memory. More fundamentally, cache operators remain tightly interleaved and chain-dependent with native compute operators, so naive near-memory offloading still incurs repeated PCIe exchanges for residual and fusion computations, turning cache reuse into a communication- and serializationbound execution flow. We therefore propose CODA, an algorithmhardware co-designed architecture centered on Compute-Cache Operator Disaggregation. CODA separates dense compute paths and memory-bound cache paths across the xPU and a lightweight DIMM-side near-memory engine, reorganizes fragmented cache activity into hardware-friendly coalesced segments, and exploits Classifier-Free Guidance (CFG) branch independence to overlap xPU compute with cache-side execution. Experiments show that CODA achieves up to 1.80× end-to-end speedup and 1.74× higher energy efficiency, while preserving competitive generation quality compared with a state-of-the-art caching algorithm.

Recent Video Diffusion Models (VDMs), exemplified by ByteDance Seedance 2.0 [29] and OpenAI Sora 2 [55], have substantially improved the fidelity and physical consistency of video generation, making them an important foundation for digital content creation [5, 14, 27, 69, 70]. As deployment scenarios broaden and representative models continue to mature and become open-source [27, 39, 65, 70], extending video generation from the cloud to edge devices such as GPU-equipped workstations becomes increasingly attractive for offline availability and privacy preservation [24, 33, 74, 75]. However, their iterative denoising process over heavy transformers still incurs high inference latency. Existing model compression methods, such as quantization [9, 19] and pruning [3, 37, 72], can reduce computation, but often require costly fine-tuning for recovery [12, 59, 71]. Prior studies [15, 61, 73, 78] have observed strong feature-map similarity between adjacent denoising timesteps, motivating CrossTimestep Caching (CTC) [43, 44, 67], which reuses intermediate features from previous timesteps (e.g., outputs of Attention or FFN modules) to bypass redundant computation. By exploiting crosstimestep similarity rather than perturbing model weights or activations, CTC remains orthogonal to conventional model compression and is particularly appealing for video generation. However, highfidelity reuse requires caching a massive volume of intermediate features, and the cache footprint scales with model size, video resolution, and duration. For example, generating a 4-second 720p video with Open-Sora [76] requires more than 40 GB of cache storage, far beyond the typical VRAM capacity (∼24 GB) of high-end edge GPUs. Existing software stacks therefore offload cross-timestep cache to host memory (DRAM) [35, 46, 51, 64, 73]. Since cache operators have extremely low arithmetic intensity, fetching massive cached data over PCIe quickly makes them bandwidth-bound, creating a severe performance wall, as shown in Figure 1(a) and Figure 1(b). A natural idea is to offload these bandwidth-bound cache operators to a Near-Memory Processing (NMP) subsystem [25, 28, 30, 56]. However, this naive approach overlooks the strict serial dependencies in VDM execution. In existing CTC flows, native compute

Keywords Video Diffusion Model, Near-Memory Processing

MICRO 2026, Athens, Greece 2026. ACM ISBN 978-X-XXXX-XXXX-X/XX/XX https://doi.org/XXXXXXX.XXXXXXX 1

Introduction

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(b) Cross-Timestep Caching with host-memory offloading Compute-cache  Host Mem (with DIMM-NMP) VRAM (e.g. GDDR6) disaggregation for Results Cache-2 Cache-5 Intermediate  better xPU use ❶ ❷ ❶ (Activations) NME Cache-1 Cache-4 Weights Centralized ❷ GPU Cache-0 Cache-3 ❶ Results Processor RAM

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Figure 1: Motivation and solution overview. (a) Host memory cache offloading can erase expected CTC gains on edge devices, while CODA substantially reduces end-to-end latency by hiding exposed cache-path overhead (xPU is NVIDIA RTX 4090 GPU). (b) Limited VRAM pushes overflow cache to host DRAM, making the cache path PCIe-bound and lowering xPU utilization. (c) CODA disaggregates cache operators to lightweight DIMM-NMP and overlaps cache-side execution with xPU compute. • CFG-Interleaved Pipelining: We exploit CFG branch independence to overlap xPU compute with cache-side execution, thereby hiding exposed communication and NMP latency.

operators and cache operators remain tightly interleaved, and results produced by one side are often immediately required by the other. As a result, NMP execution cannot proceed independently and must repeatedly exchange intermediates with the xPU across PCIe for residual and fusion computations. As discussed in Section 3.3, this back-and-forth communication leads to 2× PCIe traffic amplification in the worst case, largely negating the performance gain of caching. Once cache overflow occurs, the key bottleneck is therefore no longer only redundant computation, but also the communication and serialization overhead introduced by the cache. To address this bottleneck, we propose CODA, an algorithmhardware co-designed Compute-Cache Operator Disaggregation architecture. CODA keeps compute-intensive operators (compute operators) on the high-throughput xPU while offloading capacitycritical, bandwidth-bound cache operators to a specialized NMP subsystem, as reflected in Figure 1(c). On top of this physical disaggregation, CODA uses a static-dynamic hybrid hardware-aware scheduler to reorganize fragmented cache activity into coalesced segments, reducing fine-grained compute-cache interleaving and cross-PCIe communication. It further exploits the independence between the two Classifier-Free Guidance (CFG) branches to overlap xPU compute with cache-side execution, thereby reducing exposed overhead and end-to-end latency. Through this cross-stack co-design, CODA turns cross-timestep caching from nominal algorithmic reuse into real end-to-end system gains on edge platforms. In summary, this paper makes the following contributions:

Extensive experiments demonstrate that CODA achieves up to 1.80× end-to-end speedup and 1.74× higher energy efficiency, while incurring minor quality degradation over the SOTA baseline [73].

2 Background 2.1 Video Diffusion Models (VDMs) As the generation fidelity of Video Diffusion Models (VDMs) [16, 27, 29, 55] continues to improve, deploying them on edge devices for offline availability and privacy-preserving inference has become increasingly attractive [24, 33, 74, 75]. However, this high fidelity relies on Diffusion Transformers (DiTs) [49, 57, 76]. As illustrated in Figure 2 (left), mainstream DiT architectures employ alternating Spatial and Temporal Transformers to process complex 3D spatialtemporal tokens. Because it is stateless across different iterative denoising steps, the DiT must execute extremely dense GEMM operators at every single step. This extreme compute-bound characteristic leads to very long generation latency at the edge [21, 65, 76].

2.2

Cross-Timestep Caching (CTC)

To reduce redundant computation in iterative denoising, prior works have proposed Cross-Timestep Caching (CTC) [11, 15, 40, 41, 43, 44, 48, 61, 67, 73, 78]. As shown in Figure 2 (right), CTC exploits feature-map similarity between adjacent denoising timesteps by caching the outputs of selected operators from the previous timestep and reusing them. The “operator” refers to a module-level computation unit such as Attention or FFN. It includes primitive kernels such as LayerNorm, GELU, and Softmax inside the corresponding module, rather than treating these primitive kernels as separate cache operators. Importantly, cache reuse does not imply that an entire operator is completely skipped. Instead, it replaces the original compute-intensive GEMM operators with cache operators dominated by data retrieval and lightweight fusion. These operators typically fetch cache from storage, perform element-wise operations with lightweight features in the current branch (e.g.,

• Hybrid Hardware-Aware Caching Scheduler: We propose a scheduler that reorganizes fragmented cache activity into coalesced segments, reducing fine-grained compute-cache interleaving and cross-interface communication. We further introduce Dynamic Runtime Adjustment to safeguard rare volatile cases. • Lightweight DIMM-NMP Architecture: We design a lightweight DIMM-side NMP subsystem that enables compute-cache operator disaggregation by executing memory-bound cache operators near memory with minimal hardware overhead. 2

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Cross-Timestep Caching is fundamentally a space-for-time tradeoff, but its cache overhead is substantial. As analyzed in Figure 3(a), the cache volume grows with video resolution and frame count. Even generating a 480p, 2-second video can already exceed the VRAM of a typical high-end edge GPU (e.g., 24 GB on an NVIDIA RTX 4090), making it difficult to keep the full cache on device [27, 62, 64, 70]. Existing systems therefore typically place overflow cache in host DRAM. This relieves the on-device capacity constraint but shifts the CTC bottleneck to data movement and serialized cache-path execution. Figure 3(b) illustrates several serial operators within a cache-enabled timestep. CTC reuses cached outputs from the previous timestep and bypasses original computation, yet each cache operator still fetches the cache from host DRAM over PCIe and performs lightweight residual/scaling/fusion on the xPU before following operators proceed. Because these cache operators have very low arithmetic intensity, PCIe transfer latency can offset the benefit of skipping dense computation and may cause the hostoffloading performance reversal shown in Figure 1(a).

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Figure 2: DiT blocks of VDMs (left). Cross-Timestep Caching, which replaces selected operators with a cache path (right).

residual addition, scaling, or gated fusion), and then pass the updated features to subsequent serial operators. Therefore, while CTC reduces computation, it also shifts the corresponding execution toward a more memory-bandwidth-intensive pattern.

2.3

Classifier-Free Guidance (CFG)

3.2

To improve fidelity and alignment between generated outputs and text prompts, modern VDMs widely adopt the Classifier-Free Guidance (CFG) [2, 6, 20, 53, 76]. At each denoising timestep, the model executes two full branches in parallel: a conditional branch (𝜖𝑐𝑜𝑛𝑑 ) and an unconditional branch (𝜖𝑢𝑛𝑐𝑜𝑛𝑑 ). At the end of that timestep, after both branches have completed the forward execution of all Transformer blocks, the system fuses their outputs using: 𝜖 = 𝜖𝑢𝑛𝑐𝑜𝑛𝑑 + 𝑤 · (𝜖𝑐𝑜𝑛𝑑 − 𝜖𝑢𝑛𝑐𝑜𝑛𝑑 ) where 𝑤 is the guidance scale factor. The fused tensor serves as the timestep denoising result. In existing implementations, these two branches are typically packed into a batch (size = 2) and submitted together to the GPU [10, 36, 58, 60]. However, before reaching this fusion point, their computations within a timestep are data-independent from each other.

2.4

Heterogeneous Operator Cacheability

Our profiling results and prior CTC studies [61, 73, 78] commonly observe that different operator types have different sensitivity to cross-timestep reuse. For example, Cross-Attention is often more stable across adjacent denoising timesteps, whereas FFN and some Spatial/Temporal Attention operators can be more sensitive to reuse error. As a result, CTC policies that focus on algorithm-level heterogeneous cacheability typically assign different caching aggressiveness to different operator types or network locations. Although such operator-aware policies help control generationquality loss, they naturally create an interleaved execution pattern. Using the cache-enabled execution interval in Figure 3(b)(c) as an example, Cross-Attentions are turned into cache operators, while neighboring operators remain on the native xPU compute path, forming an execution chain with interleaved dependencies between the compute path and the cache path. This interleaving is common in CTC execution, but it also exposes a limitation: cache operators are still sandwiched between dependent compute operators, dividing the execution flow into fine-grained communication boundaries.

Near-Memory Processing (NMP)

Near-Memory Processing (NMP) is a promising architectural paradigm that reduces data movement by pushing computation closer to where data resides [1, 17, 22, 34, 38, 45, 56, 77]. Existing NMP architectures are broadly divided by where compute logic is physically deployed. Intra-DRAM designs (e.g., bank- or bank-group-level) integrate logic inside the DRAM die, close to sense amplifiers or bank I/O. Such designs exploit the extremely high internal bandwidth of DRAM but usually rely on customized DRAM processes and thus face stronger area and thermal constraints, as exemplified by UPMEM [18] and SK Hynix AiM [31]. Extra-DRAM designs (e.g., rankor channel-level) instead place lightweight compute logic near the module buffer/register chip or memory controller without modifying the memory die. They are less intrusive to commodity memory, preserve the capacity advantage of commodity DRAM, and still provide high aggregated bandwidth. Representative DIMM-NMP systems include Samsung AxDIMM [30] and RecNMP [25], which

3.3

The Pitfalls of Naive NMP Offloading

Cache operators are typical bandwidth-bound operators: they frequently access large cached tensors, while their local computation mainly consists of lightweight element-wise operations. Therefore, a natural and necessary solution is to introduce a lightweight NMP substrate that provides an execution space for these memory-bound cache operators close to the cache storage. This near-memory execution substrate forms the hardware foundation for compute-cache operator disaggregation, enabling the cache path to be separated from the dense xPU compute path and providing the necessary condition for independent scheduling and overlapped execution. 3

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Figure 3: Motivation and insight. (a) Cache storage quickly exceeds edge-GPU VRAM as video size grows. (b) With host-offloaded CTC, the xPU fetches cached tensors from host DRAM and performs the cache-side residual/scaling/fusion locally. (c) With naive NMP offloading, the current activation must be sent to the DIMM-NMP and the fused result must return to the xPU before downstream compute operators can continue, causing repeated PCIe transfers and stop-and-wait serialization. However, naive NMP offloading only changes where each cache operator is executed; it does not change the interleaved dependency structure described above. As shown in Figure 3(c), an offloaded cache operator is still placed between adjacent xPU compute stages. Downstream compute can continue only after the memoryside fusion finishes and returns the result to the xPU. Therefore, although NMP provides the execution substrate for cacheside execution, fine-grained serial dependencies still hinder compute-cache operator disaggregation. This fine-grained coupling also amplifies cross-interface traffic. In host-offloaded CTC, the xPU mainly fetches the cached tensor 𝐶 over PCIe. Naive NMP instead makes each cache operator send the current activation 𝐴 to the DIMM-NMP and return the fused result 𝑅. Since 𝐴, 𝑅, and 𝐶 are typically comparable in size, this round trip can offset the benefit of near-memory execution. This motivates CODA to use a coarser cache-path granularity, amortizing one activation/result round trip across multiple cache operators instead of repeating it at every operator boundary. Another implication is exposed critical-path latency. Naive NMP removes lightweight cache fusion from the xPU, but the xPU still waits at each cache-operator boundary before downstream dense computation can proceed. The added PCIe round trip and synchronization can outweigh the saved lightweight-operation time. CODA therefore needs to reorganize execution so that cache-side execution overlaps with dense xPU computation, rather than merely moving cache fusion closer to memory.

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Figure 4: CODA overview and cross-stack synergy.

while memory-bound cache operators are assigned to the Lightweight DIMM-NMP. Importantly, this near-memory subsystem is intentionally streamlined for the low-arithmetic-intensity access and fusion patterns of cache operators, providing a low-overhead execution substrate for the disaggregated cache path. Building on this separation and mapping, CFG-Interleaved Pipelining exploits the independence of the two CFG branches before final fusion, allowing the cache-side DMA/NMP execution of one branch to overlap with the xPU dense computation of the other. In this way, the remaining communication and processing costs of the cache path can be largely hidden behind the xPU compute window.

4 CODA Design 4.1 CODA Overview and Execution Flow

4.1.2 End-to-End Execution Walkthrough. Figure 5 illustrates the execution flow of CODA within a cacheenabled timestep. The top row shows the operator order in the current timestep. CODA scheduler combines operator cacheability with hardware cost to adjust the cache policy and form coalesced cache segments for cache-side execution. These segments read cached tensors produced by previous timesteps, but the segment does not cross timestep boundaries, because CFG must synchronize the two branches and perform fusion at the end of each timestep. When execution enters a coalesced cache segment, the xPU no longer offloads each cache operator separately. Instead, it sends the

4.1.1 Cross-Stack Synergy. As illustrated in Figure 4, CODA is organized around computecache operator disaggregation. It begins with the Hybrid HardwareAware Caching Scheduler, which makes the originally intertwined execution flow explicit by separating it into a compute path and a cache path, while reorganizing the latter into coarsegrained coalesced cache segments to amortize communication overhead. This separation enables a clean hardware mapping, in which compute-intensive dense operators remain on the centralized xPU, 4

CODA: Algorithm-Hardware Co-design for Edge Video Diffusion via NMP-Enabled Compute-Cache Operator Disaggregation within a

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Cacheability quantification for scheduling. For static policy, CODA profiles each model with 10 representative prompts before inference and measures each operator instance’s normalized output L1 similarity across adjacent denoising timesteps. The averaged profile is used as the offline cacheability signal because cacheability mainly reflects model-structural factors such as operator type, timestep, and network depth and is relatively stable across inputs. For rare outlier inputs, Dynamic Runtime Adjustment checks runtime feature evolution and applies a more conservative cache policy. Coalesced segmentation. Based on the cacheability signal above, the scheduler searches for a static cache policy 𝑆. A coalesced segment is a continuous sequence of cache operators within the same timestep that is packed and offloaded to the NMP as a single transaction and executed in the original dependency order. Its key benefit is to reduce fine-grained interleaving between compute operators and cache operators: instead of incurring PCIe communication for every cached operator, the system communicates mainly at the input and output boundaries of each segment. To jointly balance reuse benefit and execution overhead, the scheduler determines this static policy 𝑆 by minimizing the following objective: ∑︁ 𝐸 (𝑆) = 𝑤𝑐𝑜𝑠𝑡 · Cost(𝑆) + 𝑤 𝑓 𝑟𝑎𝑔 · Fragment(𝑆) (1)

… …

Figure 5: CODA execution walkthrough. Coalesced segments are formed within a timestep, execute cache-side operators on DIMM-NMP, and overlap with dense xPU computation on the other CFG branch before timestep-level CFG fusion.

current activation to the DIMM-NMP through PCIe at the segment boundary. The DIMM-NMP then reads the corresponding cached tensors from memory and executes the segment’s cache retrieval, residual/scale/fusion operations on the memory side. After the segment finishes, the fused result is returned to the xPU and the dependent downstream compute operators continue. In this way, activation/result transfers are consolidated at segment boundaries, amortizing PCIe communication and synchronization overhead. CODA further hides cache-side latency through CFG execution. Within a denoising timestep, the conditional and unconditional branches are independent before final CFG fusion. Thus, while one branch’s coalesced cache segment runs on the NMP, the xPU can advance dense computation on the other branch. The branches synchronize only after all operators in the timestep finish, when CFG fusion produces the final denoising output. This walkthrough sets the semantics used below: the scheduler forms coalesced segments, NMP executes them near memory, and CFG-interleaved pipelining overlaps cache-side execution with xPU dense computation.

4.2

where Cost(𝑆) captures the fidelity risk of the cached operator instances selected by 𝑆. For each cached operator, we use the profiled average cross-timestep output instability (implemented as 1 − Similarity𝐿1 ) as a proxy for the error introduced by replacing native computation with caching, and accumulate it over the operators covered by the plan. In contrast, Fragment(𝑆) penalizes both overly fragmented segments and segments whose execution latency deviates from the hardware-preferred pipeline window 𝑇𝑜𝑝𝑡𝑖𝑚𝑎𝑙 (which is further explained in Section 4.4): Fragment(𝑆) =

𝑘 ∑︁

𝐶𝑐𝑜𝑚𝑚 + 𝑤𝑑𝑒𝑣 · max(0,𝑇𝑒𝑥𝑒𝑐 (𝑆𝑖 ) − 𝑇𝑜𝑝𝑡𝑖𝑚𝑎𝑙 )

𝑖=1

(2) 𝐶𝑐𝑜𝑚𝑚 denotes the base communication overhead of a single PCIe transaction, which naturally discourages excessively fragmented segments, and 𝑇𝑒𝑥𝑒𝑐 (𝑆𝑖 ) is the estimated execution latency of segment 𝑆𝑖 on the NMP. The objective therefore jointly constrains two risks: overly aggressive caching that may harm generation quality, and overly fragmented or pipeline-misaligned segments that undermine system efficiency. These weights are tunable across models and policy preferences. By default, CODA uses 𝑤𝑐𝑜𝑠𝑡 = 3, 𝑤 𝑓 𝑟𝑎𝑔 = 0.8, and 𝑤𝑑𝑒𝑣 = 1, where 𝑤𝑐𝑜𝑠𝑡 favors lower reuse-risk operators, 𝑤 𝑓 𝑟𝑎𝑔 favors fewer and longer segments, and 𝑤𝑑𝑒𝑣 penalizes segments exceeding the CFG-overlap window. Since the search space over cache decisions and induced segment boundaries is non-convex, we use simulated annealing [63] to optimize the cache decisions and generate an offline static schedule for each model. In our implementation, the target cache ratio controlling overall caching aggressiveness is set to 25%~50% by default depending on the model. Simulated annealing uses 300K~500K proposals per model, an initial temperature of 1.0, a cooling factor of 0.995 every 1K proposals, and early stopping after 20K proposals without objective improvement. Because the search only uses profiled statistics and analytical latency estimates, it finishes in minutes as a one-time offline cost and does not affect the inference critical path.

Hybrid Hardware-Aware Caching Scheduler

CODA’s hardware-aware caching scheduler extends prior CTC cache policies from reuse selection to hardware-aware execution planning. Prior CTC methods [61, 73] choose reusable timesteps and operators for quality-preserving computation reduction. CODA uses the operator-instance similarity profile, which captures the above operator/timestep differences as well as the backbone-depth variation revealed by our profiling in Figure 6(c), and weighs it together with xPU-DIMM communication and DIMM-NMP execution/overlap costs. The scheduler therefore determines cached operator instances and the resulting coalesced segment boundaries offline, while runtime only applies lightweight corrections when an input deviates from the offline profile. 4.2.1 Static Profiling-Based Scheduling Policy. Given the profiled operator sequence of each model, CODA searches cache decisions offline, treating each operator instance as a candidate. Consecutive selected candidates within the same timestep form coalesced cache segments, and the remaining xPU operators separate these segments to define xPU-DIMM communication boundaries. This reduces fine-grained PCIe transactions while controlling generation-quality loss. 5

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efficiency of the static schedule in the common case while providing a low-overhead runtime correction for rare volatile inputs. Higher Similarity (Normed)

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CODA Architecture and NMP Subsystem

To efficiently execute the coarse-grained cache plans generated by the scheduler in the previous section, CODA requires a hardware substrate that supports both operator disaggregation and streaming data organization. This section presents the overall system architecture of CODA, the NMP microarchitecture tailored to cache operators, and the execution dataflow that remains compatible with modern memory protocols.

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4.3.1 System Architecture and Design Rationale. As shown in Figure 7(a), CODA adopts a heterogeneous execution framework based on compute-cache disaggregation. The xPU serves as the centralized compute engine and executes the compute-intensive dense operators in the DiT backbone, while the memory-bound cache operators are mapped to the DIMM-NMP subsystem, where they are executed on the memory side and interact with the xPU only at segment boundaries. CODA adopts the rank-level, center-buffer-based extra-DRAM NMP shown in Figure 7(b)(c) as a balanced design point for cachepath disaggregation. This choice reflects the cost-benefit tradeoff: providing an independent cache-side execution space without introducing complex control or intrusive DRAM-die modifications, while keeping its latency largely hidden by dense xPU computation. First, the rank-level organization better matches CODA’s tiled multi-stream fusion flow with lower integration complexity. For each tile group, the NME coordinates the incoming activation stream with multiple aligned cache streams (𝐶 1, . . . , 𝐶𝑛 ) and applies the fused operations in order. Placing this coordination at the rank-level center buffer avoids introducing fine-grained bank-local controllers, strict stream co-location constraints, or cross-bank partial movement and synchronization. It also preserves a commodityDIMM-like organization without modifying DRAM dies, reducing area, thermal, verification, and integration costs. Second, rank-level NMP is sufficient for CODA’s cache-path execution. For a coalesced segment, increasing internal DRAM bandwidth mainly shortens tiled fusion in the NME, while segmentboundary activation/result transfers and synchronization remain. In our evaluated configuration, tiled fusion is less than 20% of estimated cache-path latency for common segment lengths 𝑛 = 2/3/4, so Amdahl’s Law limits the gain from replacing the rank-level NME with near-bank NMP. Our evaluation (Section 5.4) further shows that the remaining PCIe/NMP overhead can be largely hidden behind xPU computation. Thus, near-bank PIM is an optional more aggressive design point, with limited extra end-to-end benefit relative to its hardware and control complexity.

Transformer Block ID

Figure 6: Spatial-temporal heterogeneity of cacheability: (a) Cross-timestep output stability (L1 similarity) profiling of different operators in Open-Sora [76] (Normalized across all timesteps for each op). (b) Relative operator sensitivity across diffusion timesteps: FFN>Spatial>Temporal>Cross. (c) Operators in the middle blocks are generally more sensitive than operators of the same type near either end of the network.

4.2.2 Dynamic Runtime Adjustment. Although the static policy covers the vast majority of inputs, real-world inference may still encounter a small number of prompts whose early-step feature evolution deviates noticeably from the offline profiling pattern, making the planned caching start point overly aggressive. To handle such cases, CODA introduces an asynchronous runtime safeguard on top of the static schedule to validate the planned cache-entry point before entering the caching phase. Shadow monitoring. This mechanism exploits a natural system window. During the high-noise early denoising stage, feature variation is typically too large for caching to be safely enabled, so the NMP remains idle while the xPU continues along the native execution path. We use this window to asynchronously offload the output features of timesteps 𝑡 + 2 and 𝑡 + 1 to the NMP before the scheduled caching start step 𝑡, and compute their L1 distance in the background. Because this check is decoupled from the main execution path, it introduces no exposed latency on the critical path and serves as a lightweight shadow monitor. Fixed-step fallback. If the measured distance exceeds a predefined safety threshold, the runtime interprets it as a signal that the operator remains too unstable near the current cache-entry point to safely enter the caching phase. In that case, the host runtime temporarily disables caching for that operator and falls back to native xPU execution for 𝑁 fb nearby denoising timesteps (typically 𝑡 and 𝑡 − 1). We adopt this fixed-step fallback instead of continuous online monitoring because it is sufficient to cover the common instability cases around cache entry while avoiding the additional control complexity, storage-access interference, and hardware overhead of continuous monitoring. In this way, DRA preserves the

4.3.2 NMP Microarchitecture. Based on the above architectural choice, CODA further streamlines the NME microarchitecture according to the characteristics of cache operators. As shown in Figure 8(b), these operators are fundamentally dominated by element-wise scaling and fusion, and we therefore adopt a SIMD Processing Element (PE) tailored to this execution pattern. In Figure 8(b), 𝑚 denotes the number of 6

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CODA: Algorithm-Hardware Co-design for Edge Video Diffusion via NMP-Enabled Compute-Cache Operator Disaggregation

DDR Physical Layer DIMM Interface

Figure 7: CODA architecture: (a) Compute-cache operator disaggregation between the xPU and DIMM-NMP subsystem. (b) Rank-level, buffer-chip-based DIMM-NMP organization. (c) Near-Memory Engine (NME) for cache-based diffusion operators. PEs in one NME, and we set 𝑚 = 4 according to the DSE in Section 5.7. 𝑛 denotes the number of cached tensors/operators fused within the current coalesced segment. Data entering the PE does not always follow a unified scale-and-fuse path. For gated fusion, the input first passes through a scalar multiplier, where it is multiplied by a broadcast scaling factor, and is then fused through the floating-point adder. For the more common residual-only case, all scaling multipliers are uniformly bypassed, and the input data are directly forwarded to the subsequent accumulation stage. Meanwhile, operand isolation clamps the multiplier inputs to stable constants to suppress redundant switching and reduce dynamic power. In addition to executing cache operators, this microarchitecture must also support the shadow monitoring mechanism introduced in the previous section. To this end, CODA reuses the existing datapath instead of introducing dedicated monitoring hardware. For DRA, the NME streams the two feature tiles to be compared through the PE lanes and bypasses the multiplier path. The augmented floating-point adder computes the element-wise difference and absolute value through sign-bit manipulation. The firmware then reorganizes the resulting difference vector and feeds it back to the same PE datapath, where the adder and registers perform tree-style accumulation to produce a local L1-difference scalar within each DIMM. Since the local computations are independent, the final global reduction can be directly handled by the host CPU when reading out the local scalars from all DIMMs. This scalar-level reduction scales only with DIMM count and is negligible compared with cache tensor movement. The reused datapath computation and final scalar aggregation run in the cache-entry shadow window and can be hidden by the xPU’s dense early-stage computation, adding no exposed critical-path latency. This monitoring occurs before cache is enabled, when early denoising features are unstable and unsuitable for cache reuse, so it does not run in parallel with cache operators and requires no separate NMP partition.

capacity inside the NME remains highly limited. CODA therefore adopts a tiled operator-fusion dataflow. As shown in Figure 8(a), within a coalesced segment, the runtime first performs DIMM-aligned partitioning along the spatial dimension for both the input activation and the cached tensors from the latest reusable timestep, so that they are split at the same positions and mapped to different NMPs. Each DIMM therefore processes only its assigned input partition together with the aligned cache partitions for the 𝑛 cache operators in the current coalesced segment. Within each DIMM, these local partitions are further divided into aligned tile groups. Each tile group contains multiple contiguous SIMD-width chunks, where each chunk matches the PE-array width, i.e., 𝑚 PEs × 8 lanes. The number of chunks in a tile group is selected according to the fusion depth 𝑛 and the available NME buffer capacity (64 chunks in our evaluated configuration). During execution, the xPU first writes the partitioned input activation into DRAM through standard write requests, and the NME firmware then iterates over these aligned tile groups. Within a tile group, the firmware processes data chunk by chunk. For each SIMD-width chunk, the PE array loads the current activation chunk into its lanes. It then streams the corresponding chunks from the aligned cache tiles in the original segment order. After each scaling, residual, or fusion update, the partial vector remains in the PE registers and is directly consumed by the next fused operation. Only after all 𝑛 cache operations for this chunk are completed is the final output chunk written to the Output Buffer. The firmware then advances to the next chunk in the tile group, and finally to the next tile group. After all tile groups are processed, the Output Buffer contains the final fused segment output to be returned to the xPU. CODA therefore avoids materializing full-tensor or full-tile intermediate results after every cache operator, reducing internal bandwidth overhead and unnecessary write-backs within the NME. The above tiled dataflow triggers concurrent accesses to multiple cache tiles within the inner loop. To reduce potential row/bank conflicts caused by highly regular contiguous layouts under concurrent accesses, CODA further applies conflict-aware placement during tensor layout to decorrelate the low-level address mapping of cache tensors that are accessed together. Concretely, instead of changing the logical tensor order, CODA assigns the 𝑛 DIMM-local tiled cache tensors consumed by the same coalesced segment to different base regions or allocation offsets when possible. This reduces the

4.3.3 Firmware Execution: Tiled Operator-Fusion Dataflow. Although cache operators process large amounts of data, their execution pattern remains dominated by element-wise scaling and fusion rather than high-arithmetic-intensity matrix operations. This operator structure allows CODA to partition them consistently by spatial position and execute them in a streaming manner across DIMM-NMPs. At the same time, a single cache operator can still involve hundreds of megabytes of data, while the on-chip SRAM 7

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Figure 8: (a) DIMM-aligned partitioning of the input activation and cached tensors within a coalesced segment for parallel execution across DIMM-NMPs. (b) Streamlined execution unit and PE datapath for cache-based diffusion operators. (n is the coalesced segment length, and m is the number of PEs.)

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𝑪𝒐𝒎𝟎 𝑪𝒐𝒎𝟎 𝑪𝒐𝒎𝟒 𝑪𝒐𝒎𝟒 𝑪𝒐𝒎𝟖 𝑪𝒐𝒎𝟖 𝑪𝒐𝒎𝟏𝟏𝑪𝒐𝒎𝟏𝟏 … [𝟎] [𝟏] [𝟎] [𝟏] [𝟎] [𝟏] [𝟎] [𝟏] 𝑳𝒂𝟎 𝑳𝒂𝟎 𝑳𝒂𝟒 𝑳𝒂𝟒 𝑳𝒂𝟖 𝑳𝒂𝟖 [𝟏] [𝟎] [𝟏] [𝟎] [𝟎] [𝟏] Compute/Cache Op 𝑳𝒂𝟑 [𝟎]

likelihood that their low-level bank/bank-group mappings align repeatedly under the memory-controller address mapping, while preserving the element-wise tiled execution order. This treatment is only an engineering layout strategy to support the tiled operatorfusion dataflow more robustly, rather than an independent method.

4.4

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Figure 9: CODA execution evolution: (a) Scheduler-only flow, where coalesced cache segments still stall the xPU through bandwidth-bound transfers. (b) Adding NMP offloading reduces the communication span of the coalesced cache segment, but the xPU remains idle during cache-path execution. (c) CFG-interleaved pipelining overlaps one branch with the other branch’s coalesced cache segment running on the NMP.

CFG-Interleaved Pipelining

Figure 9 illustrates the execution evolution enabled by CODA. Figure 9(a) shows the scheduler-only flow: after the Hybrid HardwareAware Caching Scheduler reorganizes fragmented cache operators into hardware-friendly coalesced segments, the cache path still executes through bandwidth-bound transfers and stalls the xPU. Figure 9(b) then maps these coalesced cache segments to the NMP. Compared with the scheduler-only flow in Figure 9(a), this naive “offload-and-wait” execution shortens the exposed communication span of cache processing, but the cache path and xPU compute still proceed in a serialized manner, leaving system-level pipeline bubbles. To remove this serialization bottleneck, CODA introduces CFG-Interleaved Pipelining, as shown in Figure 9(c). As discussed in Section 2.3, the conditional and unconditional branches of the CFG remain independent before the final fusion within each denoising timestep. CODA exploits this structure by breaking the bundled dispatch paradigm (Batch=2) used in existing frameworks and unrolling it into two asynchronous execution streams at the system level. This split introduces a small kernel launch overhead and slightly reduces the computational density of each dispatch. Figure 9(c) reflects this effect: the computation block of a single branch is slightly longer than exactly half of the two-branch consolidated block in Figure 9(a). Nevertheless, this overhead is amortized by the resulting cross-branch overlap. This also gives the runtime enough separation to turn branch independence into a practical masking window to hide cache-side latency. In execution, the xPU first starts one CFG branch (the blue blocks in Figure 9(c)). To avoid waiting for an entire monolithic operator to finish before communication begins, CODA applies explicit macrotiling to GEMM operators. For GPU instances, this macro-tiling exposes runtime-visible subGEMM boundaries. Once a subGEMM materializes its output tile in GPU memory, the runtime uses multistream asynchronous dispatch and event synchronization to launch

the corresponding DMA without waiting for the entire GEMM to finish. This creates a tile-level pipeline between xPU execution and data movement. Meanwhile, after receiving the first data tiles, the NMP can immediately start its internal tiled operator-fusion dataflow, while the xPU proceeds to the other CFG branch (the orange blocks) instead of stalling on the cache path. These activities can overlap in time: downstream DMA for the current operator (xPU → NMP), upstream DMA for the preceding cache result (NMP → xPU), dense xPU computation, and cache-side NMP execution. More importantly, Figure 9(c) shows from 𝐶𝑜𝑚 0 to 𝐶𝑜𝑚 4 that the NMP processes a continuous coalesced segment generated by the hybrid scheduler, rather than scattered cache operators triggered one by one. Accordingly, this overlap is built directly on the coarse-grained cache reorganization in Section 4.2. Ideally, by the time the xPU finishes the other CFG branch, the NMP has also completed the corresponding coalesced segment, enabling a tight handoff between the two branches. Accordingly, the orange branch provides the xPU compute window that masks the cache segment opened by the preceding blue branch. Under this view, the target 𝑇𝑜𝑝𝑡𝑖𝑚𝑎𝑙 in the cost function of Section 4.2 represents the desired NMP masking window for this overlap. Specifically, the scheduler aims to keep the end-to-end NMP latency—including both bidirectional PCIe communication and internal NMP computation—within the xPU branch compute window as much as possible. When this condition is satisfied, the exposed serial waiting time in Figure 9(b) is substantially reduced, leading to higher xPU utilization. 8

CODA: Algorithm-Hardware Co-design for Edge Video Diffusion via NMP-Enabled Compute-Cache Operator Disaggregation

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Table 1: Configuration Details of the Evaluated DIMM-NMP

5 Evaluation 5.1 Experimental Setup

NME Architecture Configuration: 4 PEs, 8 Lanes/PE, NME Buffer size: 64 KB, One NME per DIMM Area overhead: 0.029 𝑚𝑚 2 | Power overhead: 10.17 mW | @ 1 GHz DIMM Parameters DDR4-3200, 16 GB/DIMM × 8, 2 DIMMs/channel 2 ranks/DIMM, 2 bank groups/rank, 4 banks/bank group DIMM Timing Specifications tRC=74, tRCD=22, tCL=22, tRP=22, tBL=4 tCCD_S=4, tCCD_L=8, tRRD_S=4, tRRD_L=6, tFAW=26

5.1.1 CODA System. We evaluate CODA in a hardware-software co-designed environment. The centralized processor (xPU) is a single NVIDIA GeForce RTX 4090 with 24 GB GDDR6X memory. The host system uses an Intel Core i9-13900K and 128 GB DRAM. The GPU and the near-memory subsystem communicate over PCIe 4.0 x16, with an aggregate bidirectional bandwidth of approximately 64 GB/s. For evaluation, GPU end-to-end latency and kernel latency are profiled using NVIDIA Nsight Compute, while cycle-level NMP performance is modeled by extending Ramulator 2.0 [47]. We compute bidirectional PCIe transfer timing from the segment-boundary activation/result size and PCIe bandwidth. We then compose GPU, PCIe-transfer, and NMP events into a dependency timeline: dependent events are serialized, independent events may overlap, and final latency is taken from the critical path, which also determines hidden and exposed overhead. We implement the NME microarchitecture in RTL and use Synopsys Design Compiler with the TSMC 7nm technology library to estimate area and power. The 64KB onchip SRAM buffer is modeled using a commercial SRAM compiler. The evaluated DIMM-NMP configuration is summarized in Table 1. We estimate total energy as the sum of GPU, NME, memorysubsystem, and PCIe-link energy. NME dynamic and static power are obtained from RTL synthesis and the SRAM compiler, while memory and PCIe energy are estimated from memory-access statistics and link traffic. All latency, energy, and quality results are averaged over five runs for each prompt, and the reported end-toend results include runtime overheads such as DRA handling.

We evaluate CODA on a diverse set of VDMs, including Latte [49], Open-Sora [76], Open-Sora Plan [39], Wan 2.1 [65], HunyuanVideo [27], Vchitect-2.0 [14], and CogVideoX-5B [70]. For models that support multiple resolutions and video lengths, we select several representative configurations. All text prompts are sampled from VBench [21] to cover diverse generation scenarios. We report both system efficiency and generation quality. System efficiency is measured by end-to-end latency and total energy consumption. Quality is measured by VBench [21] for multidimensional video quality, PSNR and SSIM for frame-level reconstruction fidelity, and LPIPS for perceptual feature distance. Each workload uses 100 prompts, and to reduce the impact of diffusion sampling stochasticity, all quality, latency, and energy results are averaged over five independent runs for each prompt.

5.2

Figure 10 reports the normalized speedup and normalized energy efficiency under different model, resolution, and video-length settings. Overall, CODA achieves the highest performance and energyefficiency gains across all evaluated configurations, showing that it can translate the potential computation savings of cache reuse into realized end-to-end system benefits. A closer baseline comparison shows that moving cache operators to the memory side alone is insufficient. Cache-HostOffload reduces redundant GPU computation through cache reuse and improves over Vanilla-GPU, but only modestly. Cache-NaiveNMP underperforms Cache-HostOffload across all workloads and even falls below Vanilla-GPU for Open-Sora (854×480), revealing a performance reversal. This shows that algorithmic reuse does not translate into speedup when the cache path remains tightly interleaved and serially dependent on the native compute path, leaving communication and serialization overhead on the critical path. CODA makes reuse beneficial by reorganizing the cache path into hardware-friendly execution and overlapping it with GPU computation. Figure 10 also shows that CODA’s gain generally grows under heavier workloads, especially at higher resolutions. This follows from the scaling gap between attention computation and cached states. Let 𝑇 be tokens per frame, 𝐹 frames, and 𝑑 hidden dimension. Spatial attention scales as 𝐹𝑇 2𝑑, temporal attention as 𝑇 𝐹 2𝑑, while the cache footprint grows roughly linearly with 𝐹𝑇𝑑. As resolution increases, cache reuse removes proportionally more GPU computation, explaining why gain amplification is more evident at higher resolutions than from merely increasing video length. From the energy perspective, Cache-HostOffload and CacheNaiveNMP often show larger energy-efficiency gains than speedup

5.1.2 Baseline Systems. We consider four system configurations. Vanilla-GPU denotes the original execution without caching. Cache-HostOffload offloads overflow cache to host DRAM when VRAM capacity is insufficient. Cache-NaiveNMP offloads cache-related operators to the near-memory side using the same DIMM-NMP hardware configuration as CODA, but does not use our hardware-aware scheduler or CFG-interleaved pipelining. When the cache policy naturally selects adjacent cache operators, Cache-NaiveNMP dispatches these contiguous cache operators as a segment and communicates only at the input and output boundaries of that segment. CODA denotes the full system, including the lightweight DIMM-NMP, the hardwareaware caching scheduler, and CFG-interleaved pipelining. We use PAB [73] as the CTC algorithmic baseline. PAB derives its cache policy from per-model profiling of cross-timestep similarity and applies it as fixed reuse rules over selected timesteps and operator types. For system performance comparisons, CacheHostOffload and Cache-NaiveNMP adopt the default PAB caching setup (i.e., PAB-Cons in Table 2), while CODA uses its own caching policy. We therefore compare their end-to-end system gains at a similar video-quality operating point, rather than under a matched cache ratio or identical cached-operator coverage. For quality evaluation, we further report both the conservative and aggressive PAB settings to contextualize the quality-performance trade-off. 5.1.3

End-to-End Speedup and Energy Efficiency

Workloads and Metrics. 9

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Figure 10: CODA speedup and energy efficiency improvement on different models normalized to Vanilla-GPU. gains. Although they do not effectively hide waiting time from communication or near-memory execution, cache reuse still removes substantial redundant GPU computation. Because GPU computation dominates power, while PCIe transfers and lightweight NMP execution add smaller overhead, these baselines can save energy even with limited latency gains. CODA further reduces redundant GPU computation and hides exposed cache-step stalls through schedule reorganization and cross-branch pipelining, delivering the best end-to-end speedup and energy efficiency.

5.3

Video Generation Fidelity

As shown in Table 2, CODA remains close to the original models and to conservative PAB in overall quality. Across all evaluated models, its VBench scores stay close to the original results. More importantly, compared with PAB-Aggr, CODA generally preserves better quality across the reported metrics at a similar quality-performance operating point, indicating that its system-level gains do not come at the cost of more severe quality degradation. Overall, CODA achieves a more favorable quality-performance trade-off. For some models, such as Latte and Open-Sora, CODA is slightly worse than PAB-Cons in PSNR, SSIM, or LPIPS, indicating larger low-level reconstruction error. However, its VBench score is slightly higher. This suggests that low-level frame-wise distortion metrics and perceptual video quality do not always vary in exactly the same direction. Taken together, these results indicate that CODA remains close to the quality level of conservative PAB while avoiding the more noticeable degradation introduced by aggressive caching.

5.4

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Latte [49]

Original PAB-Cons PAB-Aggr CODA

0.8115 0.7873 0.7556 0.7916

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Open-Sora [76]

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Original PAB-Cons Open-Sora Plan [39] PAB-Aggr CODA

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Vchitect-2.0 [14]

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Wan 2.1 [65]

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0.7434 0.7316 0.7096 0.7277

26.3462 0.8535 21.6930 0.7397 24.3621 0.7978

0.0836 0.1986 0.1483

Original PAB-Cons HunyuanVideo [27] PAB-Aggr CODA

0.8120 0.8013 0.7853 0.7939

27.9286 0.8793 26.8234 0.8640 27.6777 0.8749

0.1082 0.1316 0.1152

Table 2: Quality evaluation. PAB-Cons and PAB-Aggr denote the conservative and aggressive configurations of PAB [73], with specific parameters varying by model. PSNR, SSIM, and LPIPS are calculated against the original model results.

Ablation Study and Latency Breakdown

While Figure 10 reports the full-stack end-to-end gain at a similar video-quality operating point, Figure 11 further reveals how CODA’s system mechanisms translate cache-side reuse into actual latency reduction. Specifically, it separates the overall gain into two consecutive stages: the reorganization gain from Figure 11(b) to (c), and the additional latency hiding from Figure 11(c) to (d). 10

CODA: Algorithm-Hardware Co-design for Edge Video Diffusion via NMP-Enabled Compute-Cache Operator Disaggregation

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Figure 12: Ablation study with same CODA caching policy: CacheCODA denotes variants that use the cache trace produced by CODA’s Hybrid Hardware-Aware Caching Scheduler.

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MICRO 2026, October 31–November 04, 2026, Athens, Greece

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Figure 11: Ablation study and latency breakdown: (a) Cache-HostOffload, (b) +Lightweight DIMM-NMP (naive), (c) +Hybrid Hardware-Aware Caching Scheduler, (d) +CFGInterleaved Pipelining (full CODA). Bars further separate exposed and hidden PCIe/NMP overhead to illustrate the effects of scheduling and overlap.

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First, adding Lightweight DIMM-NMP alone does not yield visible latency reduction and instead exposes additional NMP-side overhead, showing that near-memory execution capability alone cannot automatically convert cache reuse into end-to-end speedup. Nevertheless, Lightweight DIMM-NMP remains necessary because it lets cache operators complete independently on the memory side, establishing physical separation between the compute and cache paths for subsequent optimization. The scheduler then produces the first visible latency reduction from Figure 11(b) to (c) by reorganizing fragmented cache activity into hardware-friendly coalesced segments. This reduces exposed PCIe and NMP overhead from fine-grained, highly interleaved triggering, showing that system-level scheduling is needed to turn disaggregation into a measurable end-to-end benefit. CFG-Interleaved Pipelining provides the second stage of gain from Figure 11(c) to (d). After scheduling reorganizes the cache path, pipelining uses the GPU compute window of the other CFG branch to hide remaining PCIe/NMP overhead and shorten the critical path. This effect becomes stronger under heavier workloads because longer GPU operators can absorb more communication and nearmemory execution time. For HunyuanVideo, GPU computation already dominates the timeline, so cache-side overhead is almost entirely hidden, while the end-to-end gain remains bounded by the small non-compute portion left to optimize. To isolate the execution stack under the same CODA caching policy, we add a matched-scheduler ablation and report the largest evaluated resolution/length setting for each model. With the CODA caching policy, NaiveNMP already outperforms the matched HostOffload baseline, showing that the scheduler-generated cache trace is more amenable to NMP execution. Full CODA still achieves higher gains because CFG-interleaved pipelining overlaps the NMPenabled independent cache path with xPU computation.

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Figure 13: GPU dense-compute utilization across timesteps for CODA and Cache-NaiveNMP. Shaded regions indicate cache-step intervals for CODA and baseline (default PAB).

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Figure 13 compares CODA and Cache-NaiveNMP (NaiveNMP in the figure) using GPU dense-compute utilization across timesteps, normalized to non-cache timesteps (100%). NaiveNMP shows lower and more fluctuating utilization during cache steps, especially within the default-PAB intervals shaded red. This indicates that cache-side execution and communication remain exposed on the critical path, interrupting continuous GPU computation. In contrast, CODA keeps utilization higher and steadier by reducing cache-side interference and keeping the GPU active in dense computation. The figure also shows that heavier workloads create larger hiding windows because dominant GPU operators run longer. CODA therefore generally maintains higher normalized utilization in these settings. For some workloads, CODA also applies caching over slightly wider timestep ranges while preserving higher utilization and competitive generation quality.

5.6

Efficacy of Dynamic Runtime Adjustment

Although CODA’s static caching policy preserves generation quality well in most cases, a small number of prompts can still trigger DRA. DRA then conservatively adjusts the planned cache-entry behavior near the start of the caching phase. Across all evaluated models, the triggered fraction remains below 7%. Figure 14 shows representative cases where visible local degradation appears without DRA, while 11

MICRO 2026, October 31–November 04, 2026, Athens, Greece

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Figure 16 explores the proposed NMP buffer size and PE count. Performance improves with larger buffers but largely saturates around 64 KB, and increases up to 4 PEs before the benefit becomes limited. We therefore adopt a lightweight 64 KB buffer, 4-PE, 1 GHz configuration that captures most of CODA’s system-level benefit. We synthesize the NMP engine RTL with Synopsys Design Compiler in TSMC 7nm and obtain 64 KB SRAM parameters from a commercial SRAM compiler. A single NME occupies about 0.029 mm2 and consumes about 10.17mW. Compared with a 13W DIMM [28] and a typical 100 mm2 memory buffer chip [52], both area and power overheads are below 0.1%, showing that the lightweight NMP configuration is sufficient for CODA’s system-level gains.

Hunyuan

Related Work

Cross-timestep caching. Existing CTC methods exploit crosstimestep similarity to construct cache policies at different granularities, from fixed reuse rules over timesteps or operator types, as in FORA [61] and PAB [73], to token-wise caching [78], timestepaware estimation [15] and forecasting-based reuse [43]. These methods focus on reusing features, operators, or tokens to reduce redundant computation while controlling quality. CODA builds on this foundation but formulates cache reuse as hardware-aware planning: it uses cacheability as a scheduling signal and combines it with communication and execution costs in the cache-policy search. Video diffusion acceleration. Another line of work accelerates native VDM computation within existing operators. Sparse VideoGen [68] exploits spatial-temporal attention sparsity, while ViDA [13] and FlightVGM [42] use differential approximation, activation sparsification, hybrid precision, and accelerator dataflow. These methods usually reduce the computation or execution cost within existing dense operators. CODA is complementary: after CTC replaces selected dense operators with cache operators, CODA focuses on executing this cache path under overflow through DIMM-side execution, coalesced scheduling, and CFG-overlapped execution.

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Figure 16: Architecture DSE for NMP buffer and PE numbers.

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Figure 14: DRA restores visible local details of corner cases. Red boxes highlight the local details recovered by DRA.

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Figure 15: Latency breakdown at the triggered timestep when an operator falls back to conservative mode under DRA.

enabling DRA restores local details. Thus, DRA can mitigate visible local artifacts despite being activated only rarely. Figure 15 quantifies DRA’s cost by showing the normalized cache-step latency when one operator falls back to conservative mode, with annotations marking the incremental overhead at that timestep. The main added latency comes from replacing a cache operator with GPU compute, while shadow monitoring itself adds no exposed critical-path latency. Edge and Middle denote whether the fallback operator lies at the boundary or inside the original coarse-grained coalesced segment. An edge fallback introduces no extra PCIe latency, and the added GPU compute can still cover part of the original PCIe communication and NMP execution. A middle fallback introduces extra PCIe overhead, but GPU compute can hide part of that cost. Because such fallbacks occur only at a small number of triggered timesteps and are amortized over the denoising process, their end-to-end impact remains small. Thus, DRA provides a low-cost runtime safeguard for rare corner cases.

Discussion and Future Work

The current Hybrid Hardware-Aware Caching Scheduler is one instantiation of a broader hardware-aware scheduling paradigm, rather than a fixed policy tied to current VDMs and CTC settings. In CODA, the scheduler jointly considers model-side cacheability and system-side execution cost to decide where caching should be applied, where conservative execution should be retained, and how 12

CODA: Algorithm-Hardware Co-design for Edge Video Diffusion via NMP-Enabled Compute-Cache Operator Disaggregation

MICRO 2026, October 31–November 04, 2026, Athens, Greece

References

fragmented cache operators should be reorganized into hardwarefriendly segments. Thus, the scheduler is not bound to the current profiling metric or cache policy. As VDM architectures evolve and future CTC algorithms introduce new reuse opportunities and quality-performance tradeoffs, the framework can absorb updated stability signals, risk estimators, and cost terms while preserving the compute-cache disaggregation architecture. Another direction is to extend CODA beyond VDMs to diffusion language models (DLLMs) [4, 7, 8, 54]. Recent DLLM studies exploit temporal stability across denoising steps through KV-cache reuse and selective recomputation, suggesting that diffusion-based text generation may also exhibit interplay between newly computed and reused cached states [23, 50, 66]. This makes compute-cache disaggregation potentially useful for DLLM acceleration. However, this extension would not directly port the current CODA pipeline. Compared with VDMs, DLLMs expose different token-level dynamics, different cache objects, and may not provide the CFG-based overlap opportunity. A DLLM-oriented CODA would likely require redesigned scheduling signals and a new overlap mechanism tailored to token/KV evolution, which we leave for future work.

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Conclusion

This paper presents CODA, an algorithm-hardware co-designed architecture to address the system bottlenecks of edge video diffusion generation. We show that since cached states can easily exceed on-device VRAM and be forced into host memory, the key limitation is no longer only redundant computation, but also the PCIe communication and serialization overhead introduced by the cache path. CODA therefore centers on compute-cache operator disaggregation: dense compute remains on the xPU, while memorybound cache operators are offloaded to a lightweight DIMM-NMP subsystem. Combined with a hardware-aware caching scheduler and CFG-Interleaved Pipelining, this design transforms fragmented, blocking cache execution into a reorganized and overlapped execution flow. Experimental results show that CODA converts the potential benefit of cross-timestep caching into real end-to-end system gains, achieving up to 1.80× speedup and 1.74× higher energy efficiency with high generation quality and low hardware overhead. These results suggest that, for edge VDM deployment, the key is not merely to move cache-related work closer to memory, but to codesign operator disaggregation, scheduling, and execution overlap around the communication and serialization bottlenecks.

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Yuanpeng Zhang et al.

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