Towards Reliable AI-Assisted Analog Design: Template-Constrained LLM Agents for SAR ADC Generation Dimple Vijay Kochar
Hae-Seung Lee*
Anantha P. Chandrakasan*
Massachusetts Institute of Technology Cambridge, MA, USA
Massachusetts Institute of Technology Cambridge, MA, USA
Massachusetts Institute of Technology Cambridge, MA, USA Grounded Expert Knowledge/Plan
arXiv:2607.14165v1 [cs.SE] 15 Jul 2026
Abstract While Large Language Models (LLMs) have demonstrated significant capability in software code generation, their application to analog Electronic Design Automation (EDA) is bottlenecked. Owing to limited circuit topology understanding and data, directly prompting LLMs and multimodal models leads to hallucinations and failure to produce schematics capable of passing rigorous SPICE simulations, as we show in our work. Instead, we propose an end-to-end, multi-step LLM agentic framework ATLAS, capable of generating a functional Successive Approximation Register (SAR) Analog-toDigital Converter (ADC) that successfully passes simulation validation. To adhere to the rigid constraints of analog design, we utilize expert knowledge to ground the LLM in its planning, selection, parameterization, and iterative modification. As part of ATLAS, we introduce Template-Constrained Generation - which unlike other template-based works - builds towards a more generalized SAR ADC generation flow. We demonstrate a strong proof-of-concept of our framework by developing SAR ADCs across technology nodes and input specs. Overall, our expert-knowledge grounded multi-step agentic ATLAS establishes a pragmatic foundation for integrating LLMs into reliable analog design methodologies.
Keywords Analog-to-Digital Converter, ADC, SAR ADC, LLMs, Large Language Models, Agents, Template
1
Introduction
Continuous scaling of technology nodes and ever-increasing demand for mixed-signal Integrated Circuits (ICs) necessitate efficient, scalable design methodologies. Within these, Analog-to-Digital Converters (ADCs) - particularly Successive Approximation Register (SAR) ADCs - are critical components that bridge the physical and digital domains. However, while digital Electronic Design Automation (EDA) workflows have achieved high levels of abstraction and automation [1], analog design remains largely manual, iterative, and heavily intuition-driven [2]. This lack of scalable automated synthesis for analog circuits creates a severe bottleneck in modern System-on-Chip development. Recently, Large Language Models (LLMs) have demonstrated transformative capabilities in automated software engineering, logic synthesis, and hardware description language (HDL) generation and verification [1, 3–5]. However, its utility for analog EDA has been restrictive, owing to the rigid, continuous-domain physical constraints in analog EDA that differ fundamentally from discrete digital logic or software code. To this end, we conduct a deep qualitative study to explore the utility of existing LLMs/multimodal 1We acknowledge the utilization of Generative AI - specifically Nano Banana - for
creating illustrations and figures in our paper.
Input Specs
Stage 1: Grounding In Expert Knowledge Final Circuit
Stage 3: Netlist Sizing And Optimization
Stage 2: Netlist Generation
Figure 1: High-level workflow of our proposed multi-step LLM-based agentic framework ATLAS for creating SAR ADCs from user-defined input specifications in an end-to-end automated manner.1
models for designing analog schematics from scratch. Our study demonstrates that directly prompting LLMs in an unconstrained manner frequently results in hallucinations, producing physically unviable schematics with connectivity errors. To address these critical limitations, this work shifts the paradigm from unconstrained circuit generation to grounded, feedbackbased synthesis. Rather than forcing the LLM to generate complex analog topologies from scratch, we propose an end-to-end, multi-step LLM agentic framework ATLAS - Agentic Templateconstrained LLM-based ADC Synthesizer (illustrated in Figure 1). The core distinction of our framework lies in the grounding with expert knowledge across various components for planning, selection, stitching, re-configuration, testbench generation, etc., designed specifically for reliable analog circuit synthesis. We also introduce a generalized Template-Constrained generation that enables ATLAS to select component-wise expert templates and structurally modify them to meet the target specifications. Feedback from our rule-based verification and simulation engines allows ATLAS to self-debug and improve the circuit. Overall, by constraining the generative search space, our agentic framework prevents the LLM from diverging into physically impossible configurations while still harnessing its capacity for rapid iteration and code generation. To demonstrate the efficacy of our framework, we utilize it to synthesize a low-power 8-bit SAR ADC on Cadence GPDK-45nm technology node. Our agentic framework generated ADC successfully meets the input specs with an ENOB of 7.59. We further show ATLAS’s generalizability by generating three additional SAR ADCs:
Kochar et al.
* Double-Tail Dynamic Comparator
... * Intermediate coupling transistors M_c1 node_latchP node_preP node_tail2 VDD pmos_model W=2u L=0.18u M_c2 node_latchN node_preN node_tail2 VDD pmos_model W=2u L=0.18u ...
.SUBCKT DoubleTail INP INN VDD GND OUT CLK * First tail: Differential input stage M1 INP NODE1 VDD VDD PMOS L=0.18u W=15u M2 INN NODE1 VDD VDD PMOS L=0.18u W=15u * Second tail: Regenerative latch stage M3 NODE1 NODE2 GND GND NMOS L=0.18u W=10u M4 NODE1 NODE2 GND GND NMOS L=0.18u W=10u
... * Cross-coupled latch M3 outp outn vdd vdd PMOS L=45n W=2u M4 outn outp vdd vdd PMOS L=45n W=2u M5 outp outn 0 0 NMOS L=45n W=1u M6 outn outp 0 0 NMOS L=45n W=1u ...
* Biasing transistor for second tail (clocked) M5 NODE1 GND CLK GND NMOS L=0.18u W=5u * Output stage M6 NODE2 OUT GND GND NMOS L=0.18u W=8u .ENDS DoubleTail
(a) Prompting GPT-4o for Double-Tail Dynamic Comparator
(b) Prompting Gemini 3.1 and ChatGPT-Plus for Miyahara Comparator
Figure 2: Highlighting several limitations of directly prompting LLMs for netlist generation. On the left (a), we highlight several severe issues like shorted gates, input to drains, etc. in the GPT-4o created netlist. On the right (b), we highlight issues like missing connections and missing intermediate cross-coupling when prompting frontier LLMs. (1) the original 8-bit SAR ADC transferred to TSMC 65nm (generalization across technology nodes), (2) a 4-bit SAR ADC (generalization across input specifications), and (3) a 10-bit SAR ADC (capability of bit modification). In conclusion, our work makes the following contributions: (1) we qualitatively showcase the limitations of direct prompting of LLMs and multimodal models for analog circuit generation, (2) we propose a multi-step LLM agentic framework ATLAS to reliably ground the circuit generation, and (3) we demonstrate the efficacy of our framework by synthesizing four SAR ADCs across technology nodes and input specs. Overall, our work serves as a strong proofof-concept for reliable LLM-assisted analog design. The remainder of the paper is organized as follows. Section 2 discusses the past works in this direction. Section 3 shows various qualitative results highlighting the limitations of directly prompting LLMs for ADC netlist generation. Section 4 provides a detailed description of our proposed multi-step LLM agentic framework ATLAS. Section 5 demonstrates the efficacy of our framework to generate a low-power 8-bit SAR ADC end-to-end, while Section 6 highlights the generalizability of our work. We conclude and discuss future work in Section 7.
2
Related Works
Here, we briefly discuss various works in the domain of automating analog design and utilizing LLMs/AI in circuit design. Computer-Aided Design (CAD) for Analog Circuits. Recent research has been dedicated to automating analog circuit sizing, with methodologies spanning from analytical equation derivations to Bayesian Optimization (BO) [6, 7]. Recently, there has also been a surge of works utilizing reinforcement learning (RL) methods [8, 9]. Within the specific domain of Successive Approximation Register (SAR) ADCs, automation efforts have largely bifurcated into topology generation frameworks and algorithmic sizing. Generation frameworks frequently rely on template-based compilers [10–12] that use pre-defined topologies to automate layout assembly. Alternatively, macro-based SAR ADC generation leverages
digital standard cells [13] to create synthesizable analog building blocks. On the algorithmic sizing front, recent optimization techniques explicitly targeting SAR ADCs include multi-agent reinforcement learning [14], global-local optimization [15], and automated sizing via analytical equations [16]. Despite achieving high optimization efficiency, these approaches inherently function as sizing algorithms for a single, fixed SAR ADC, lacking the flexibility to easily generalize across varied architectural design spaces. LLMs for Circuit Design. Several works [17–19] have utilized LLMs plugged with external optimizers for analog circuits sizing. Specific to analog circuit design, several works [20, 21] have demonstrated that general-purpose LLMs can not design even simple analog circuits, as we also concur through our case study of designing simple ADC components in Section 3. AnalogXpert [22] utilizes in-context examples for topology utilizing sub-circuit connections, but demonstrates poor LLM performance. Owing to lack of strong analog principles in mainstream LLMs, works like Artisan [23] propose niche task-specific fine-tuning of LLMs to boost performance on simple and specialized circuits. In a similar direction, ChipNeMo [4] and AnalogSeeker [24] propose data curation and train foundation models for digital and analog design, respectively. In other directions, AnalogCoder [25], AmpAgent [26] and LADAC [27] develop agentic LLM frameworks for schematic design of simpler circuits like amplifiers, oscillators, etc. Majorly, most of these works have explored LLMs for simpler analog circuits, while we focus our work on designing SAR ADCs.
3
Direct LLM Prompting Limitations
In this section, we evaluate the capability of LLMs and multimodal LLMs to understand circuit specifications and create netlists for analog design when prompted directly in an end-to-end fashion. By highlighting the limitations of existing LLMs, we motivate our agentic framework in Section 4. Compared to other works [17, 18], we note that our work is not an exhaustive benchmark/evaluation of LLMs, but rather provides qualitative case studies to highlight some limitations of direct prompting.
M5 NODE1 GND CLK GND NMOS L=0.18u W=5u
outp 0 0 L=45n NMOS M4 outnM5 outp vdd outn vdd PMOS M5 outpM6 outn 0 0 outp NMOS 0 L=45n W=1 outn 0 NMOS M6 outn... outp 0 0 NMOS L=45n W=1 ...
* Output stage * Output stage M6 NODE2 OUT GND GND NMOS L=0.18u W=8u M6 NODE2 OUT GND GND NMOS L=0.18u W=8u .ENDS DoubleTail .ENDS DoubleTail
(a) Prompting GPT-4o forforDouble-Tail Dynamic Comparator (a) Prompting GPT-4o Double-Tail Dynamic Comparator Towards Reliable AI-Assisted Analog Design
(b) Prompting 3.1 (b) Prompting Gemini 3.1Gemini and ChatG for Miyahara for Miyahara ComparatorCo
* Low-offset Design Netlist M7 Vrefp N1 Vdd Vdd PMOS W=Wp7 L=Lp7
* Low-offset M8 VrefnDesign N2 Vdd Netlist Vdd PMOS W=Wp8 L=Lp8 M3 Vinp N1 Voutp Vss NMOS W=Wn3 L=Ln3
M4 N1 VinnVdd N2 Vdd VoutnPMOS Vss NMOS W=Wn4 L=Ln4 M7 Vrefp W=Wp7 L=Lp7 M5 N2 Voutp N1 Vss NMOS W=Wn5L=Lp8 L=Ln5 M8 Vrefn VddN3Vdd PMOS W=Wp8 Voutn N3 N2 Vss NMOS W=Wn6 L=Ln6 M3 VinpM6N1 Voutp Vss NMOS W=Wn3 L=Ln3 M1 N1 N3 Clk Vss NMOS W=Wn1 L=Ln1 M4 VinnM2N2 W=Wn4L=Ln2 L=Ln4 N2 Voutn N3 Clk Vss Vss NMOS NMOS W=Wn2 M5 Voutp N1 Clk VssVss NMOS L=Ln5 M9 N3 Voutp Vss W=Wn5 NMOS W=Wn9 L=Ln9 M6 Voutn N2 Vss NMOS L=Ln6 L=Ln10 M10N3 Voutn Clk Vss VssW=Wn6 NMOS W=Wn10 M11Clk Vdd Vss N3 Clk VddW=Wn1 PMOS W=Wp11 M1 N1 N3 NMOS L=Ln1 L=Lp11 ClpClk Voutp C1 W=Wn2 L=Ln2 M2 N2 N3 VssVssNMOS Cln Voutn Vss C1 M9 Voutp Clk Vss Vss NMOS W=Wn9 L=Ln9 Vclk Clk Vss PULSE(0 1 0 1n 1n 10n 20n) M10 Voutn Clk Vss Vss NMOS W=Wn10 L=Ln10 M11 Vdd N3 Clk Vdd PMOS W=Wp11 L=Lp11 Clp Voutp Vss C1 Cln Voutn Vss C1 Vclk Clk Vss PULSE(0 1 0 1n 1n 10n 20n)
Figure 3: Highlighting the limitations of utilizing multimodal LLMs for netlist generation. In red, we highlight the wrong connections and incorrectly identify transistors.
3.1
Prompting LLMs
Synthesizing a SAR ADC from scratch is a formidable challenge even for human experts, making end-to-end generation by an LLM highly impractical. Instead, as part of this case study, we prompt several LLMs to generate netlists for simpler components - specifically comparator - of the SAR ADC. We present qualitative results from the LLM outputs in Figure 2, highlighting errors and hallucinations. First, we prompt GPT-4o [28] to generate a double-tail dynamic comparator [29]. As shown in Figure 2 (a), there are multitudes of errors in the created netlist. Some of them include: (1) The gates of the input transistors are tied together at NODE1, completely negating any differential sensing capability, (2) The differential input signals (INP and INN) are incorrectly connected to the drain terminals of M1 and M2, (3) This netlist contains its OUT at the gate of a transistor, (4) The gate of the "clocked" biasing transistor (M5) is permanently tied to GND. Under standard conditions, this NMOS transistor will never turn on. Inspection of the post-generation rationale reveals a severe lack of analog design knowledge, leading to hallucinations and incorrect assumptions, in turn causing the fundamental errors above. We observe similar behaviors with samesized LLMs from DeepSeek [30] and Gemini [31].
Figure 4: Highlighting the limitations and lack of generalization of utilizing existing fine-tuned models for netlist generation. (left) Original circuit, (right) Fine-tuned model generated incorrect circuit.
Under a higher compute budget, we also survey frontier models like Gemini 3.1 and ChatGPT Plus. These models are much better at analog design fundamentals and avoid the basic mistakes made by the smaller models. However, they also exhibit various errors when asked to generate the simpler comparator from Miyahara [32], as shown in Figure 2 (b). For Gemini-Pro (top in (b)), we note that the generated netlist has nodes (node_latchP and node_latchN) that are not connected. On the other hand, ChatGPT Plus (bottom in (b)) misses creating intermediate nodes and merges them to output nodes creating incorrect circuit logic. We attribute some of these errors to failure in reasoning and reduced confidence, leading to hallucinations and incorrect connections. Overall, we note that LLMs are getting better at understanding analog circuits and can be utilized for simpler circuits; their utility through direct prompting for creating SAR ADCs remains limited.
3.2
Prompting Multimodal LLM
Recently, LLMs have improved on various image understanding tasks and reasoning tasks [33]. [34] have explored the use of multimodal models for reasoning over simpler circuit images. To this end, we conduct a small case study to study the capability of multimodal LLMs (specifically GPT-4o) to generate netlists from images of a low-offset comparator circuit from [35]. We attempted direct prompting as well as detailed step-by-step prompting to guide the generation of the netlist. We show the circuit and the best generated netlist by GPT-4o in Figure 3. Even in this best generation, the multimodal LLM makes several errors. While it correctly identifies the number of transistors, it incorrectly classifies them. It creates 3 PMOS and 8 NMOS transistors in the netlist; whereas the original circuit image has 7 PMOS and 4 NMOS transistors. Secondly, there are issues in the actual connections as well, specially for nodes M3 and M4 where the Vin+ and Vin- are connected to the gates in the original circuit; while the multimodal model connects them to the drain. Overall, the multimodal model have good image detection capabilities to identify the number of components and connections, but lack deeper recognition and reasoning capabilities to make correct circuit connections.
LLM
Curation Input Specs
Simulation
Wing 2: Template-Constrained Circuit Parameters To overcome the issues of base multimodal LLMs, [34] propose Anda Ranges
Prompting Fine-tuned models
Information Aggregation
Final 3.3 Circuit
Integration and Testbench Creation Kochar et al.
Retrieval-Augmented Generation
fine-tuning recipe comprising a large dataset of simple schematic images and netlists. They fine-tune a lightweight YOLO vision model [36] specifically to detect non-standardized analog circuit Open-source LLM-based External symbols across varying image qualities. They pass the detected Scientific Papers Summarization Optimizer components to an LLM to create the final netlist. We evaluate their fine-tuned model + direct prompting of GPT-4o on 30 different Sizerrelated LLM to SAR ADCs. Simultaneously, we test images of circuits also fine-tune a GPT-4o model on >700 datapoints from [37] and evaluate on this test set. Through our study, we conclude that both these fine-tuned models fail to generate correct netlists reliably. We demonstrate an example of a failure case when generating a circuit image from [38] Text and Metricin Figure 4, where we compare the original circuit (left) with the Based Retriever Planner LLM model-created circuit rendered into an image (right). Firstly, the generated netlist completely removes one transistor M9. Furthermore, the cross-coupled connections for M5-M6 and M2-M3 are incorrect. The connections for M7-M8 are also shorted which is not the case in the original circuit One of the major reasons we hypothesize for this poor performance is the distributional shift between the training and the testing data. These models have been trained Grounded Expert Input Specs on simpler circuits from textbooks [39, 40] with high-quality imKnowledge/Plan ages. When tested on complex circuits with varying image quality, the model fails to generalize. Largely, fine-tuned models also fail Figure 5: High-level illustration of stage 1 of our proposed to incorporate extra rounds of text-based feedback owing to their ATLAS involving information aggregation (top) from opentraining procedure; thus, it’s difficult to correct the mistakes of source scientific papers and a RAG-based Planner (bottom) these models without external models. for generating grounded plans for SAR ADC creation.
4
Proposed Methodology - ATLAS
To circumvent the limitations of open-ended unconstrained generation, we propose our multi-step LLM agentic framework ATLAS. Essentially, ATLAS enhances the reliability and reduces LLM hallucinations by breaking down the complex analog design process into three smaller stages: (1) Grounding in Expert Knowledge, (2) Netlist Generation, and (3) Netlist Sizing and Optimization. For the scope of this work, we do not consider layout, as all our experiments are schematic-based. For all the different agentic components we developed, a human expert tests them qualitatively to ensure reliability. We provide an illustration of our agentic framework in Figure 1 and provide a detailed overview below.
4.1
Grounding in Expert Knowledge
One of the major flaws and limitations of using LLMs for analog design is hallucinations. When the model is not as confident, it uses its best judgment and assumptions to fill the gaps. While this is not as big an issue for other tasks, a wrong assumption at any stage of circuit design is highly costly and can have ripple effects, rendering the entire circuit incorrect. We provided various illustrations of such hallucinations in Figure 2 and 3. In order to reduce hallucinations, we propose to ground the LLM with expert analog design knowledge - specifically, scientific papers and findings. We provide an illustrative workflow of this stage in Figure 5. The workflow for this stage comprises two main steps: (1) Information Aggregation, and (2) Retrieval-Augmented Generation (RAG). We describe each of these steps in more detail below.
4.1.1 Information Aggregation. In order to ground the LLM, we first need to aggregate information from the analog design experts that we can share with the LLM. Since we can not access and share proprietary company-specific information with LLMs, we rely on utilizing open-source data, specifically open-source scientific papers. We start with the open-source survey and database from [41], comprising a large database of papers that have created scientific artifacts in the form of ADCs. This database has information about the paper titles and links, as well as circuit-specific details like the technology node, signal-to-noise distortion ratio (SNDR), power, sampling frequency (𝑓𝑠 ), etc. Next, a human expert surveys and filters the papers and database entries related to SAR ADCs. Finally, an LLM surveys the filtered papers and creates a small summary of the major findings for the circuits developed from each paper. Overall, this aggregation of expert information serves as the main source of expert-grounded knowledge for the next steps in ATLAS. 4.1.2 Retrieval-Augmented Generation. To utilize the aggregated information from the previous step, we utilize retrieval-augmented generation (RAG) with LLMs. Specifically, based on the input description and specifications from the user, a heuristic retriever is used to match it to the best circuits from our database (based on proximity of metrics). We then select the top 𝑘 circuits and provide its summary to the Planner LLM along with the target input specs and descriptions. The Planner LLM then formulates a highlevel plan for creating the SAR ADC and its individual components, grounded in the expert knowledge of the retrieved scientific papers.
Towards Reliable AI-Assisted Analog Design
Integrator LLM
Generator LLM
Grounded Expert Knowledge/Plan
Rule-based Verification Wing 1: Grounded Zero-shot Template Curation
Fallback
Bit Modifier LLM
Testbench Creator LLM
Debugger LLM
Selector LLM
Input Specs
Simulation
Wing 2: Template-Constrained
Integration and Testbench Creation
4.2
Sizer LLM Netlist Generation
Based on the grounded expert knowledge and plan for the SAR ADC generation from stage 1, the next and most important stage is to create the netlist. At a high level, any netlist has several strongly intertwined components of the comparator, capdac, and the SAR logic - and our proposed workflow creates and combines them accordingly. Overall, we have a two-winged netlist generation workflow: (1) the first wing constructs the netlist through an iterative generation loop constrained by the expert literature from stage 1 and a rule-based verification engine, and (2) the second wing utilizes template-constrained generation, where the LLM chooses and modifies one among the different templates based on the grounded expert data. We present the high-level illustrative overview of this stage in Figure 6 and provide a detailed description below. 4.2.1 Grounded Zero-shot Netlist Generation. We highlighted some limitations of LLM-based netlist generation in Section 3. To counter some of these limitations, we ground the LLM generations through expert data and rule-based feedback mechanisms. Specifically, we prompt the Generator LLM with the grounded expert knowledge from stage 1, along with input specs, and component-specific information. Based on this contextual information, the Generator is tasked with generating a netlist for the specified component from scratch. Since LLMs lack niche analog design expertise, we create a rule-based verification engine that can study a netlist and provide feedback based on simple heuristics and rule violations. Some of these rules include parameter matching across connections and singular-node warnings. The Generator then updates the netlist based on the feedback provided from the rule-based verification engine, and the loop continues for a fixed number of iterations. This wing of netlist generation is extremely liberal, as the LLM can add custom components and write logic accordingly. At the
same time, such unconstrained generation can amplify the possibility of errors. We believe that this wing ofLLM-based netlist generation is Open-source External futuristic and will improve netlist generation as the LLMs’ inherent Scientific Papers Summarization Optimizer analog circuit-specific capabilities improve. However, to reliably generate ADCs, we create a second fallback wing, which is triggered if we detect issues in the netlist from this first wing. We describe this fallback generation method below.
Retrieval-Augmented Generation
This grounded expert knowledge/plan is passed to the next stage for the actual netlist generation. We provide an illustration of the generated grounded plan in Figure 8.
Information Aggregation
Circuit Figure Final 6: High-level illustration of stage 2 of our agentic framework ATLAS which coordinates the creation of the ADC netlist Parameters based Circuit on the initial grounded expert knowledge and the user-specified input specs. And Ranges
4.2.2 Template-constrained Netlist Generation. Unconstrained generation through LLMs can lead to hallucinations and logical errors; thus, we provide an Text alternate way to generate ADCs via templateand MetricPlanner constrained generation. ToRetriever this end, we first curate LLM a variety of Based different templates for the components of the SAR ADC, including the StrongArm latch [32], the Miyahara comparator [42], the standard binary-weighted capacitive DAC array [43, 44], and the split-capacitor DAC array [45, 46]. Currently, we populate these templates using available open-source data and human effort; however, they can be easily populated with larger proprietary data as Grounded Expert needed. For each template, apart from the netlist, Knowledge/Plan we utilize human experts / expert LLMs to curate a textual summary and the pros/cons. Next, we move to the Selector LLM. We provide the Selector with the templates for each component along with the grounded expert knowledge from Stage 1, and ask it to select the best template that would meet the input specs. The meta-information about the templates proves crucial for the selection, especially for complex circuits where it is difficult for the LLM to directly understand the code. Optionally, the LLM can also be prompted to update the netlist with minor modifications to the templates to cater to the input specs and grounded expert knowledge from stage 1. Overall, this wing can be highly effective with a wide range of templates, but only provides little flexibility to customize the circuit to user inputs/needs. 4.2.3 Integration and Testbench Creation. Once the netlists for each comparator are created (via the direct or template-constrained wings), the final step remains to combine them and generate the
Template Curation
Debugger LLM
Selector LLM
Input Specs
Simulation
Wing 2: Template-Constrained Final Circuit
Integration and Testbench Creation
Circuit Parameters And Ranges
External Optimizer Sizer LLM
Figure 7: High-level illustration of stage 3 of our agentic framework ATLAS - responsible for selecting and sizing the parameters of the final netlist.
higher-level logic. Here, we prompt the Integrator LLM with the high-level parameters and the meta-information about the input and outputs of each component, as well as the original input specs and the grounded expert knowledge. The Integrator is tasked to create the higher-level SAR ADC netlist which connects each of these components, adds additional gates/switches if needed, and provides the higher-level abstraction. This step is relatively easier than direct netlist generation, as the LLM does not have to reason about the low-level SAR logic and transistor connections. Since the templates/generated netlists can be for different number of bits relative to the input specs, the Bit-Modifier LLM updates the netlist to meet the specs. Specifically, provided with the entire netlist and the target number of bits, the Modifier LLM updates the netlist across the different components to meet the target specs. Next, we pass this netlist to the Testbench Creator LLM. The Testbench Creator reads the higher-level SAR ADC netlist and creates a testbench to simulate the ADC. Since unconstrained testbench creation can be noisy, we ground this LLM with a testbench template, which the LLM modifies based on the generated SAR ADC and the input specs. Largely, the testbench utilizes an ideal DAC to convert the digital signals back to analog, and the evaluation is measured using the reconstruction quality. Apart from this, a human expert also rectifies the testbench to validate the correctness of the reported metrics. Finally, we loop this testbench with a simulation engine to execute the created netlist. If there are any errors/warnings as part of the simulation, this is passed to the Debugger LLM for modification and correction of the netlist. This loop is run multiple times until the simulation succeeds to complete without any errors.
4.3
Netlist Sizing and Optimization
The final component after netlist generation remains sizing the different transistors and capacitors in the circuit. Various recent works [14–16, 19] have studied sizing in-depth with and without LLMs and can be readily plugged in for this component. In our work, we introduce this third stage of automated sizing using an LLM agent with an existing multi-objective optimizer, as illustrated in Figure 7. Specifically, given the final netlist from Stage 2, the Sizer LLM extracts the parameters that can be sized from the netlist based on the chosen templates. These parameters have variable sharing where similar transistors/capacitors are assigned the same parameter variable. Some set of parameters usually extracted by the Sizer include transistor-level and switch-level length, width,
Kochar et al.
ENOB
SINAD
SFDR
THD
Power
Target
7.5
45db
50db
-50db
8uW
Achieved
7.59
47.5db
55.6db
-51.5db
6uW
Table 1: Main results comparing ATLAS’s achieved specs against the target specs for the low-power 8-bit SAR ADC on the Cadence GPDK-45nm technology node.
multiplicity (𝑚), number of fingers (𝑛𝑓 ), as well as unit capacitance (𝑐𝑐) for capacitors. Based on the selected parameters, the Sizer writes a full-loop of optimization script, where it supplies these parameters and their expected ranges (from prior expert knowledge) to an external multiobjective optimizer, which is then run across a wide range of iterations. After the optimization run, the results and logs are presented to the Sizer, which then updates the parameter set along with the range of search - an updated version of a previous work LEDRO [17]. We conduct this iterative loop a few times and the final sized netlist constitutes the final SAR ADC developed by the LLM.
5
Synthesis of 8-bit SAR ADC
Here, we demonstrate the efficacy of ATLAS by developing a lowpower 8-bit SAR ADC end-to-end using our framework. First, we provide the experimental setup and some details about the implementation details. Later, we present our main simulated results of the synthesized SAR ADC from our framework.
5.1
Experimental Setup
Our major experiments are conducted on the Cadence GPDK-45nm technology node, simulated through Cadence Spectre. To be fair with our studies of limitation analysis in Section 3, we utilize GPT4o as the main LLM for our experiments. Our input specifications comprise the number of input bits (# bits), sampling frequency (𝑓𝑠 ), Effective Number of Bits (ENOB), Signal-to-Noise and Distortion (SINAD), Spurious-Free Dynamic Range (SFDR), Total Harmonic Distortion (THD), power, as well as an optional text description of the SAR ADC for human-in-the-loop guidance/steering. For power calculations, we average the DAC, comparator, and the SAR logic powers. For our retriever in stage 1, we utilize a simple k-Nearest Neighbors (k-NN) retrieval based on Euclidean distance in a min-max normalized feature space using 𝑘 = 5. This ensures that our selected papers for grounding the LLMs are similar to the target user specs. For our template-constrained netlist generation in stage 2, we create templates for three components of the SAR ADC pipeline - specifically the comparator, the SAR logic, and the capacitor DAC array (capdac). These components are populated with the opensource and human expert curated templates as detailed in Section 4.2.2. For our testbench template, we set VDD to 1 or 1.2 V depending on specification. For the optimizer in stage 3, we use multi-objective Bayesian optimization featuring Sobol-initialized designs, independent Gaussian-process surrogates (BoTorch) [47], and qParEGO-style batch expected improvement under random Chebyshev scalarizations with QMC [48].
Towards Reliable AI-Assisted Analog Design
### Grounded ###Papers Grounded Papers 1. - 'A 12nW1. Always-On Sensing andSensing Object Recognition - 'A 12nW Acoustic Always-On Acoustic and Object Recognition Microsystem using Frequency-Domain Feature Extraction SVM and SVM Microsystem using Frequency-Domain Featureand Extraction Classification’ Classification’ 2. 'A 3.2fJ/c.-s. 10b 100KS/s SAR100KS/s ADC in SAR 90nmADC CMOS’ 2. 'A0.35V 3.2fJ/c.-s. 0.35V 10b in 90nm CMOS’ ...
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### Recommended ArchitectureArchitecture and Sub-Blocks ### Recommended and Sub-Blocks 1. Overall Architecture: 1. Overall Architecture: - A synchronous SAR ADC architecture is chosen toismeet the low- A synchronous SAR ADC architecture chosen to meet the lowpower and high-speed requirements. This architecture will leveragewill a leverage a power and high-speed requirements. This architecture combination of innovativeofDAC and comparator designs to optimize combination innovative DAC and comparator designs to optimize power efficiency performance. powerand efficiency and performance. 2. Sampler:2. Sampler: - Design Choice: UseChoice: a low-leakage sample-and-hold circuit with acircuit with a - Design Use a low-leakage sample-and-hold charge pump to ensure effective sampling at sampling low voltages, inspired by inspired by charge pump to ensure effective at low voltages, the leakagethe reduction from matched papers. leakagetechniques reduction techniques from matched papers. - Responsibility: Capture andCapture hold theand input signal for conversion. - Responsibility: hold the input signal for conversion.
3. DAC: 3. DAC: - Design Choice: Implement split-capacitor DAC with a minimized - Design Choice: aImplement a split-capacitor DAC with a minimized capacitor size to reduce power consumption and improveand linearity, as linearity, as capacitor size to reduce power consumption improve seen in the re-switching and arbitraryand weight capacitor array techniques. seen in the re-switching arbitrary weight capacitor array techniques. - Responsibility: Convert theConvert digital output of theoutput SAR logic back an back to an - Responsibility: the digital of the SARtologic analog signal for comparison. analog signal for comparison.
## Comparator Selection "confidence": "high", "rationale": "The Miyahara Low-Noise Dynamic Comparator is wellsuited for the low-power, high-efficiency goals of the SAR ADC design. Its very low noise and high-speed performance align with the target SNDR and SFDR specifications. The excellent kickback isolation supports the synchronous design requirement, and its power efficiency matches the low-power constraint. Despite its complexity, the benefits in noise reduction and speed outweigh the drawbacks, making it the best fit for the design plan's goals.”
... ## Switching Logic "confidence": "high", "rationale": "The Split-Capacitor DAC Switching option aligns well with the design plan's emphasis on low-power and compact size, as it significantly reduces power consumption and die area. It also supports the synchronous design goal by enabling faster settling times, which is crucial for high-speed operation. Although it requires careful layout to mitigate parasitic effects, its benefits in power and area efficiency make it the best fit for the specified low-power synchronous SAR ADC design.” ...
Figure 9: Illustrating the choices and the underlying rationale 4. Comparator: 4. Comparator: - Design Choice: Utilize a dynamic with low-power for template selection by our Selection LLM for the genera- Design Choice: Utilizecomparator a dynamic comparator with low-power consumption, possibly incorporating redundancyredundancy to improve accuracy consumption, possibly incorporating to improve accuracy tion of the low-power 8-bit SAR ADC. and reduce and power, as suggested by the use of low-power comparators in reduce power, as suggested by the use of low-power comparators in matched designs. matched designs. - Responsibility: Compare the DAC output with output the sampled input - Responsibility: Compare the DAC with the sampled input signal and provide a decision the SAR logic. signal and providefor a decision for the SAR logic. ... ... Figure 8: Illustration of the grounded papers and the detailed plan generated by the Planner LLM for the 8-bit SAR ADC. We highlight some of the key choices it recommends.
5.2
SAR ADC Synthesis Results
For our primary demonstration, we consider developing a lowpower 8-bit SAR ADC with human-expert provided target specifications (specs), as shown in Table 1 (first row). We set the sampling frequency (𝑓𝑠 ) to 3.33 MHz and clock frequency (𝑓𝑐𝑙𝑘 ) as 20 MHz. We provide the input text description simply as “synchronous low power". We present the achieved metrics of our generated 8-bit SAR ADC against the target user specs in Table 1. As noted, the ATLAS’s generated SAR ADC meets all the user specifications comfortably. To make a deeper dive into our multi-agent framework’s decisionmaking, we study its intermediate outputs. In Figure 8, we show some of the retrieved grounded papers and part of the detailed grounded plan generated by the Planner in stage 1, highlighting some of its design choices. The grounded zero-shot netlist generation had some errors and didn’t succeed, but the fallback to template-constrained netlist succeeded. Some of the choices are well-grounded and we illustrate the Selector’s rationale in Figure 9.
6
Generalization Analysis
To demonstrate the generalizability of ATLAS to generate broader range of SAR ADCs, we conduct various additional analytical experiments - which we detail more in this section.
ENOB
SINAD
SFDR
THD
Power
Target
7.5
45dB
50dB
-50dB
8𝜇W
Achieved
7.82
48.8dB
56.5dB
-52.5dB
5.7𝜇W
Table 2: Results highlighting the generalization across technology nodes by comparing the achieved specs against the target specs for the 8-bit SAR ADC on a different technology node of TSMC-65nm.
6.1
Technology Nodes
Here, we show the generalization of ATLAS’s SAR ADC across technology nodes - specifically from GPDK-45nm to TSMC-65nm node. Owing to privacy and copyright concerns with sharing foundry’s technology node files, directly running our framework to generate the SAR ADC is unfeasible (although we believe doing so will further improve the ADC). Instead, the LLM-generated 8-bit SAR ADC was migrated from Cadence GPDK-45nm to TSMC-65nm using custom scripts developed to automatically map and substitute the technology primitives. We utilize a local optimizer for sizing instead of our LLM framework to ensure no foundry data leakage. Despite no technology node-specific optimizations, the generated SAR ADC performs well out-of-the-box with the main metrics compared with the target user specs provided in Table 2. Overall, this demonstrates the transferability and generalization of ATLAS across technology nodes.
Kochar et al.
ENOB
SINAD
SFDR
THD
Power
Target
3.7
24dB
31.5dB
-28dB
25𝜇W
Achieved
3.86
25dB
33.6dB
-29.8dB
21.1𝜇W
Table 3: Results highlighting the bit modification provided input specifications by comparing the achieved specs against the target specs for an asynchronous Vdd 4-bit SAR ADC design. M1
Target Achieved
ENOB
M2 SINAD
SFDR M3THD
9.5
58dB
68dB
M5
8.93
55.5dB
62.9dB
CLK
-65dB M4
-59.9dB
Power 7.5𝜇w 6.1𝜇W
Table 4: Results highlighting the bit modification capability Vip to modify the of our agentic frameworkVin ATLAS when asked 8-bit SAR ADC for 10 bits.
the Bit Modifier Agent of ATLAS to modify the template-based circuit (built for a specific number of bits) to match the target user specs. For this analysis, we utilize Gemini 3.1 as the LLM for the Bit Modifier. To test this, we use the same user specifications as the main synthesis experiment for the 8-bit SAR ADC, but only change the number of bits to 10 and set the sampling frequency (𝑓𝑠 ) as 2.5 MHz. Noting here that the templates were originally created specifically for 8 bits, and their performance when extrapolated to 10 bits remains unknown/sub-optimal. We report the results for the 10-bit SAR ADC created by ATLAS using the Bit Modifier’s capability in Table 4. We observe that the ADC fails to meet the target specs, but achieves close to 9 ENOB. Upon human expert inspection, we conclude that the Bit Modifier has strong pattern-matching reasoning to extrapolate the circuit, as we show an illustration of the correct extension of the capdac array in Figure 10.
7 C
C
2C
4C
8C
C
2C
4C
8C
2C
4C
8C
(16/15)C C
C
2C
4C
8C
16C
C
16C
(32/31)C
Figure 10: Illustration highlighting the bit-modification capability of our framework where ATLAS extended a 8-bit capdac array (top) to 10 bits (bottom).
6.2
In this paper, we propose a template-constrained LLM agentic framework ATLAS that successfully bridges the gap between unconstrained text generation and the rigorous physical demands of analog EDA. By grounding the LLM’s generative search space in expert-defined architectural priors, our framework serves as a proof-of-concept for the end-to-end synthesis of functional SAR ADCs across multiple specifications and technology nodes. While the current scope of this work validates the methodology on basic SAR ADC topologies, it establishes a reliable, non-hallucinating paradigm for integrating LLMs into EDA workflows. Future work can focus on expanding the granularity and diversity of the template libraries, as well as leveraging the evolving reasoning capabilities of newer LLMs, to tackle the continuous-domain optimization of much more complex mixed-signal systems. Ultimately, we believe this structured, prior-grounded approach opens a highly promising avenue for reliable AI-assisted analog circuit design.
Input Specifications
Next, we conduct experiments to evaluate the adaptability of ATLAS to build customized SAR ADCs for varying user input specifications. Specifically, we update the new user target specs and provide the metrics in Table 3 (top row). We set the sampling frequency (𝑓𝑠 ) to 20 MHz, choose asynchronous design, and the number of bits to 4. For the 4-bit SAR ADC, the Selector LLM chose simpler templates compared to the previous 8-bit design. It selected a standard bottom-plate capdac instead of a split-capacitor array, as the lower resolution does not require capacitance scaling. Additionally, it replaced the low-noise Miyahara comparator with a standard StrongArm latch, since kickback noise is far less critical at 4 bits and gives higher speed. We present the performance metrics of the ADC developed by our framework in Table 3 (bottom row). The results show how it meets the specs. In fact, ATLAS removed a transistor connected in parallel in the bootstrap switch in the template with the rationale of reducing THD and that indeed improved performance. Overall, this analysis provides a proof-of-concept for the generalizability of ATLAS across different input specifications.
6.3
Conclusion and Future Work
Bit Modification
In this analysis, we study the capability of the framework to adapt its circuit for varying number of bits. Specifically, this is a test of
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