arXiv CS open access

C2C-Explorer: An Exploration Framework for Chip-to-Chip Interconnect Architectures in LLM Cloud Computing Systems

2026 · arxiv_cs

arXiv CS · Papers · 2026

cloud distributed-computing parallel-computing

Conceptio Open Archive

Analyze & explore related research in Conceptio

Connect this record directly into your research workflow or AI agent. Explore citations across open repositories, query full text, and export structured proof bundles.

Explore in Search →Connect via MCP / API ↗

C2C-Explorer: An Exploration Framework for Chip-to-Chip Interconnect Architectures in LLM Cloud Computing Systems Jiayi Li△†⋄□ , Di Wu⋄□ , Qingxu Li⋆ , Hongxiao Zhao△† , Jiaqi Yang△† , Anjunyi Fan△† , Wenbin Zhang⋄□ , Boqiang Wu⋄□ , Shuting Liu⋄□ , Shifeng Fang⋄□ , Jianbo Dong⋆ , Dimin Niu⋄□ and Bonan Yan△†∗ △ Institute for Artificial Intelligence, Peking University, Beijing, China; † Beijing Advanced Innovation Center for Integrated Circuits,

School of Integrated Circuits, Peking University, Beijing, China; ⋄ Hupan Lab, Hangzhou, China; □ Damo Academy, Alibaba Group, Hangzhou, China; ⋆ Alibaba Cloud, Alibaba Group, Beijing, China bonanyan@pku.edu.cn

59%

63%

,1 ) ,4 ) 4

ETH-X, SUE, UALink SoC AXI C2C Ether- PHY net • Other Commercial Solutions: Nvidia NVLink, Huawei UB

scale out (100k XPUs, hundreds of GB/s)

6 5

2 1

XPU 6 0 1 2 3 4 5 6 0

5 5 U 4 XP 3 2 1

sw sw sw sw scale up (8-512 XPUs, TB/s)

LLM Workload on >100k XPUs?

Challenge 1: LLM Traffic generation LLM Megatron NCCL Task Deepspeed xCCL traffic input Challenge 2: Multi-XPU HW simulation Booksim OMNeT++ CN-sim Intercondie XPU XPU ... XPU nect w/o switch die Interface super node Circuits: R PE simulated perf. update parameters Challenge 3: Chip interface DSE virtual channel scheduler frame size credit ... data center

(4 XPU 0 0 1 2 3 4 5 6

...

(d)

92%

93%

77%

12%

49%

Normalized Latency

91%

... XPU

arXiv:2608.08611v1 [cs.DC] 9 Aug 2026

XPU

This paper has been accepted for publication at the 63rd ACM/IEEE Design Automation Conference (DAC ’26), July 26–29, 2026, Long Beach, CA, USA.

leaf

(TP, PP)

... ...

XPU 2 0 1 2 3 4 5 6

With the exponential growth in parameter size of large language models (LLMs), deployment strategies have transitioned from single-accelerator setups to coordinated multinode, multi-accelerator systems that form super-nodes for enhanced resource coordination [1]. This shift has revealed that inter-chip communication increasingly dominates computation in large-scale LLM workloads. Specifically, recent studies demonstrate that under typical parallel affinity configurations, communication accounts for over 90% of itera-

spine

(b)

1 Introduction

5M 3B 7B 7B 3B 4B 12 1. 2. 6. 1 18. LLM Model Size

1 5 U 4 XP 3 2 1

Keywords: chip-to-chip communication, supernode, scale out, LLM simulator, scale up, large language model, cloud computing system

computation

The scaling-up of large language models (LLMs) necessitates computing systems to have multi-processor-chip architectures, elevating the importance of chip-to-chip (C2C) communication. However, designing efficient C2C hardware architectures for LLM workloads faces three key challenges: generating realistic LLM-specific C2C traffic, accurately simulating hardware-level communication at scale, and efficiently exploring the exponentially large C2C design space. We propose C2C-Explorer, an adaptive Bayesian DSE framework that integrates a LLM-workload-driven traffic generator, a scalable interconnect simulator (switch/fullmesh, up to 512 chips), and a metric-guided evaluator into a workload-to-hardware optimization pipeline, enabling systematic C2C architectural co-design under realistic LLM workloads. Validated against FPGA-based C2C prototypes, the C2C simulator achieves 2.46–8.23% end-to-end timing error across diverse traffic patterns. Its hybrid cycle & event model further accelerates large-scale simulation by up to 7.8× over a pure cycle-accurate baseline. Applied to a 32XPU DeepSeek-R1-671B inference workload, C2C-Explorer identifies configurations that improve goodput by 44.1% and reduce memory by 98.4%. C2C-Explorer is opensource and available at https://github.com/Selinaee/ C2C-Explorer.

communication

(a)

XPU 4 0 1 2 3 4 5 6

Abstract

Optimal Design

Figure 1: (a) Left: latency breakdown (communication & compute) per training iteration vs. LLM model sizes [5]. Right: latency breakdown for Llama3.1-8B inference under various parallelism settings [6]. (b) Typical interconnect architecture for multi-XPUs LLM cloud computing systems. (c) Representative C2C interconnect protocols. (d) Three challenges in C2C design for LLM computing systems.

tion time during training (Figure 1(a), left) and exceeds 50% of total latency during inference (Figure 1(a), right), emphasizing the critical demand for high-bandwidth, low-latency interconnects [2, 3, 4]. Figure 1(b) illustrates a typical interconnect architecture employed in LLM computing systems with multiple XPUs1 . To achieve optimal deployment of LLM workloads on computing systems with > 105 XPUs, it is essential to determine the optimal interconnect in the scale-up domain. However, this endeavor faces significant challenges of lacking appropriate EDA toolkits for: (a) LLM-specific traffic generation. Figure 1(d) demonstrates that various LLM parallelization strategies, such as data or tensor parallelism, produce distinct collective communication patterns in frameworks like Megatron [7] and DeepSpeed [8], with each configuration inducing specific operations (e.g., all-reduce, all-to-all) via NCCL [9] to derive GPU-to-GPU C2C traffic traces. To obtain realistic C2C flows, these traces must be de1 XPUs refer to various architectures of processing units, e.g., central processing units (CPU), graphics processing units (GPU), neural processing units (NPU), tensor processing units (TPU), and FPGAs.

composed according to the physical interconnect structure and port mapping, a process that is inherently complex and topology-dependent. (b) Multi-XPU hardware simulation. Emulation of interconnect behavior for scaled-out systems with scaled-up chips is missing because of the complicated crosslayer protocols. (c) Design space exploration for C2C interface. Various factors, such as LLM workloads, network topologies, and chip-to-chip (C2C) link configurations, interact with multiple submodels and hardware parameters, including virtual channels (VCs), schedulers, frame sizes, and credit sets, resulting in a combinatorial explosion. Consequently, evaluating and co-optimizing the endto-end performance across all possible combinations remains a formidable challenge. To fill this gap, this work presents C2C-Explorer, a joint framework for interconnect hardware design space exploration and communication simulation under LLM workloads. The major contributions include: • An LLM traffic generator under practical LLM workloads that bridges P2P (e.g. GPU-to-GPU) communication to C2C systems by producing AXI-accurate SoC-to-C2C traffic input and feeding it directly into our C2C simulator. It integrates dual-layer flow-control semantics: a combination of application-level pacing and link-level credit backpressure, enabling realistic cycle-accurate C2C timing under real LLM workloads. • An open-source, fast, and scalable interconnect simulator based on AXI and Ethernet PHY, supporting switch and full-mesh topologies with up to hundreds of XPUs and thousands of C2C links. A hybrid modeling strategy— cycle-accurate C2C port modeling combined with eventdriven switch scheduling—provides substantial speedup while preserving link-level fidelity. • An adaptive Bayesian design space exploration (AB-DSE) method that applies hardware-informed feasibility constraints (derived from our analysis of core C2C parameters) to prune the combinatorial space, and performs Bayesian optimization to efficiently identify the optimal hardware configuration [10] [11]. To validate C2C-Explorer, we employ LLM and other communication workloads, using real-world FPGA-based C2C host prototypes as a baseline for comparison. The simulator achieves consistently low end-to-end timing error (2.46–8.23%) across multiple traffic patterns. Moreover, the hybrid scheduling model accelerates simulation runtime by up to 7.8×. With verified C2C-Explorer toolkits, we systematically analyze three core C2C design parameters (packetization, scheduling, and resource-allocation) and evaluate them against standard performance metrics. This analysis reduces the valid configuration space from

INPUT Workload: LLM trace (SimAI) Topology (XPU#, SW# C2C port map Mesh/Switch) HW conﬁg candidates (see Table 1) DSE setting (budget, weights)

C2C Explorer Framework

OUTPUT

Traffic Generator: Interleaves ﬂows and generates AXI-level C2C traffic.

Pref. Report score goodput fairness buffer usage latency (P50,P99)

C2C Simulator

Evaluator

C2C model

ﬂow completion time report

Adaptive Bayesian DSE(AB-DSE): Searches optimal conﬁguration

Best hardware conﬁg

Figure 2: C2C-Explorer framework workflow.

2394 to 1152 and achieves convergence to the optimum in approximately 20 iterations under a 32-XPU LLM workload. C2C-Explorer is available at https://github.com/ Selinaee/C2C-Explorer).

2 Related Works On one hand, existing LLM-oriented simulation frameworks such as Vidur [12], SimAI [13], and vTrain [14] primarily focus on system-level performance evaluation of existing GPU infrastructures, providing valuable insights into large-scale deployment and scheduling behaviors. Among them, SimAI can, given an LLM workload and parallelization strategy, simulate collective communication algorithms and NCCL primitives to produce GPU-to-GPU flow traces, but these traces do not map to physical hardware paths and thus cannot capture chip-to-chip communication effects. In contrast, architecture-aware simulators like LLMServingSim [15], Calculon [16], and LLMCompass [17] have made important progress in modeling computation efficiency and accelerator design, yet their communication modeling generally relies on analytical or simplified abstractions. On the other hand, traditional NoC simulators such as BookSim [18] and Garnet [19] (in gem5 [20]) focus on on-chip interconnects, while CN-Sim [21] and HexaMesh [22] target chiplet-level networks. For system-level or scale-out networks, tools such as ns-3 [23], OMNeT++ [24] are commonly used. However, none of these can capture the hardwarelevel communication behavior of scaled-out systems with scaled-up chips [25, 26]. This work bridges gaps in prior studies by focusing on C2C communication within specific LLM workloads. It advances the field through a cycle-level, hardware-aware communication model, enabling detailed analysis of chip-to-chip interactions during both training and inference.

3 The C2C-Explorer Framework Figure 2 depicts the proposed C2C-Explorer framework. It consists of 4 modules (from top to bottom): a traffic generator, a C2C simulator, an evaluator, and an adaptive Bayesian search engine (AB-DSE). Inputs for C2C-Explorer include:

1 2 waterpending chunks stall & mark MAC retry buffer c_n1

remote C2C port 2 b

process request

c_1 dual ﬂowinterval Δ control mechanisms c_2 ... RTT x Nα W = c_W ... C/BW +Δ

... chunk 1

two work modes process response

List of c2c ﬂow ID pID srcpdstp size2 0a 1a 32KB 1a -1 0b 1b 32KB 1b -1 2a (1a,1b) 0a 2a 64KB 2b (1a,1b) 0b 2b 64KB release ID only after all pIDs complete size2 = size1/ c2c port#

C2C ﬂow >> chunk (sliding window + credit control)

cycle

List of p2p ﬂow (sim-ai) ID pID src dst size1 1 -1 0 1 64KB 2 1 0 2 128KB

(b)

sliding window

(a) P2P ﬂow >> C2C ﬂow

cycle

(i) LLM executing traces generated by SimAI [13], (ii) topology descriptions (XPU/switch (SW) counts, C2C port map, mesh or switched fabric), (iii) candidate hardware parameters, and (iv) exploration budget and metric weights. Outputs of C2C-Explorer are reports for system performance, including score, goodput, fairness, buffer, P50/P99 latency, and the combination of design parameters to achieve optimal performance.

chunk size n2 = w_dwidth

The operating principle of C2C-Explorer is: the traffic generator emits AXI-level C2C traffic → the C2C simulator evaluates each configuration → the evaluator extracts flow-level metrics → AB-DSE updates the search distribution. Hardware constraints (e.g., chunk_size≥ 2· MAC_frame) are applied before each step to prune infeasible designs. This loop iterates until the preset iteration budget is reached. The function and organization of each component are detailed as follows.

wlast and emits a b response to acknowledge burst completion. Receiving the b response allows the sender to retire the chunk and decrement active_chunks. This dual-mode behavior reproduces true AXI burst semantics and chunk-level timing fidelity.

3.1 Traffic Generator

3.2 C2C Simulator and C2C Model

C2C communication timing is governed by two interacting layers: (1) application-level message generation captured by SimAI, and (2) SoC-side burst pacing combined with link-level credit flow control. The traffic generator embeds sliding window + credit control to faithfully reproduce these cross-layer interactions. As shown in Figure 3, it transforms high-level LLM P2P traces into AXI-accurate C2C traffic through three tightly coupled stages: (a) P2P→C2C flow mapping, (b) C2C→chunk conversion with dual flow-control semantics, and(c) chunk→AXI command emission.

C2C simulator covers both hardware modules (virtual channels, scheduling, flow control) and network behavior (Ethernet framing and switching), combining cycle-level port modeling with event-driven Ethernet/link modeling to balance timing fidelity and scalability. It is built on SimPy and accelerated with PyPy JIT [27].

(a) P2P→C2C flow mapping. SimAI [13] provides XPU-level P2P traces containing message sizes and parent–child dependencies. Given the target C2C topology (full-mesh or switched fabric) and the number of C2C ports, the generator distributes each P2P flow across available ports. This produces multiple per-port sub-flows while preserving dependency order. (b) C2C→chunk conversion with dual flow-control semantics. Each C2C flow is segmented into fixed-size chunks (c_1, c_2, . . .), which are injected into the pipeline under a BDP-driven sliding window. A new chunk is admitted only when (active_chunks < W), where the window size is W =

⌈ BW · RT T

⌉

Nα ,

W =

⌈

⌉

RT T Nα . +∆

C BW

Symbols: BW (bandwidth), RT T (round-trip time), C (chunk size), ∆ (inter-chunk gap), N (parallel flows), α (safety factor). Simultaneously, the physical-link behavior is modeled using credit-based backpressure: when downstream MAC buffers hit their watermark, credits are exhausted and the generator stalls and retries every cycle. (c) Chunk→AXI command emission. The generator operates in two AXI-driven modes. On the sender side, each chunk is expanded into an AXI write burst: one aw request followed by n2 = C/wd_width w beats, with the final beat asserting wlast. On the receiver side, the remote C2C port detects

n1 = size2/ chunk size

Figure 3: Traffic generator workflow with dual flow control.

Figure 4(a) summarizes the simulator’s three core features: (a) Cycle-accurate execution in C2C port: Each submodule is characterized by two parameters: param_config (functional settings such as VC count or scheduling policy) and process_time (cycles per operation). (b) Packet-centric behavior characterization: The C2C simulator adopts a packet-centric abstraction that matches the natural granularity of C2C communication. Each packet only keeps the fields that affect MAC/link behavior (control_header plus header_len and payload_len), which suffice for transmission and framing calculations while omitting unnecessary intraSoC details. (c) Producer–consumer–style pipeline via FIFO decoupling: Submodules exchange packets through FIFOdecoupled queues, following a producer–consumer– style pipeline. Each stage consumes packets from its upstream queue and pushes results to its downstream FIFO every cycle, enabling a timing-synchronized multistage pipeline. Figure 4(b) shows the hardware architecture; Figure 4(c) presents its software-mapped counterpart in our simulator. In software, each C2C port is instantiated as two concurrent tasks: a TX task executing the tx path (S1→S2→S3) and an RX task executing the rx path (S5→S6→S7). The Ethernet (w/o switch) is modeled as a separate shared task corresponding to stage S4, with which all ports interact during

(a) Processor { param_conﬁg process_time}

submodule

(b)

queue Pkt N ...

Packet { control _header Pkt 0 header_len, payload_len} submodule

Sources/Destinations SoC AXI Manager AXI Subordinate AXI Subordinate S1 aw w b ar r S2

topo 1: switch

S3 TX MAC Buffer

...

aw w

S7 ar r

RX Unpack S6 RX MAC Buffer S5

S4 Ethernet(w/o switch)

switch ... switch

AXI Manager

TX Pack

–Consumer Model

topo 2: full mesh

(c)

SoC (traffic generator) aw, w, ar tx_axi_scheduler aw, w, ar tx_pack_axi axi flit tx_pack_mac mac frame tx_mac_buffer mac frame sender(tx path)

b, r rx_process_out b, r rx_unpack_axi axi flit rx_unpack_mac mac frame rx_mac_buffer

remote SoC b, r tx_axi_scheduler b, r tx_pack_axi axi flit tx_pack_mac mac frame tx_mac_buffer

Ethernet(w/o switch) receiver(tx path) receiver(rx path)

aw, w, ar rx_process_out aw, w, ar rx_unpack_axi axi flit rx_unpack_mac mac frame rx_mac_buffer mac frame sender(rx path)

Figure 4: (a) C2C simulator features. (b) Target hardware architecture used in C2C simulator. (c) Software pipeline loop. Each C2C port runs two concurrent tasks (TX and RX), while the Ethernet/switch is modeled as a shared global task, forming the end-to-end transfer loop. Table 1: Parameters in Chip-to-Chip Model Submodules Attr.

Submodule

Parameter

traffic_generator chunk_size

Value in (Sec. 6)

Cases

2KB, 4KB, 8KB

tx_axi_scheduler

AXI scheduler

tx_pack_mac

MAC_frame_size 2KB, 4KB

tx_mac_buffer

VC_pair_nums

1,2,4,8,16,32

tx_mac_buffer

VC scheduler

DQD, FCFS, RR, WRR

rx_mac_buffer

credit

4KB, 8KB, 16KB, 32KB

Scheduling

Resource-Allocation.

Legend:

Packetization

DRR, LQ, RR, SP

Notation: DRR = deficit round-robin (4 KB quantum); LQ = longest-queuefirst; RR = round-robin; SP = strict priority (DA 0→31); DQD = DA-queuedepth; FCFS = first-come first-served; WRR = weighted round-robin (uniform). Our simulator exposes many tunable C2C parameters; Table 1 lists the core ones used in this study.

transmission. Together, they form the full end-to-end transfer loop between C2C ports. The simulator follows this path through a 7-stage pipeline (S1–S7) across multiple C2C ports, with each stage aligned to one or more evaluation axes–Packetization (S2, S6), Scheduling (S1, S3), and Resource-Allocation (S3–S5). These mappings correspond directly to the attribute annotations in Table 1. (S1) SoC–C2C boundary scheduling [Scheduling] . AXI bursts triggered by the traffic generator entering perdestination (DA) queues. tx_axi_scheduler selects which DA to serve using configurable policies. (S2) TX Pack [Packetization]. AXI channels (aw, w, ar, r, b in Figure 4(b)&(c)) are packed into AXI flits in tx_pack_axi, and aggregated into MAC frames in tx_pack_mac. Frames close upon DA changes to avoid cross-destination interleaving. Request (aw, w, r) and response (b, ar) data paths are physically separated to avoid bidirectional head-of-line blocking, especially under all-reduce traffic. (S3): TX MAC Buffer [Scheduling + Resource-Allocation]. MAC frames are placed into per-VC buffers. In tx_mac_buffer, VC number, VC assignment, and VC scheduling determine the egress order. Credit-based flow control (CBFC) throttles transmission when downstream buffers are full. (S4) Ethernet (w/o switch) [Resource-Allocation]. For P2P links, this stage has fixed propagation delays plus per-frame serialization. When con-

figured as a switch, it models an input-queued crossbar with per-(src,dst,vc) virtual output queues (VOQs) and roundrobin arbitration. Cut-through is approximated via overlapping switch processing and link transmission. This stage captures VC utilization limits, credit availability, and multiport contention. (S5) RX MAC Buffer [Resource-Allocation]. Incoming MAC frames enter per-VC RX buffers. Upon admission, credits are returned to the sender, completing the CBFC loop. (S6) RX Unpack [Packetization]. MAC frames are decomposed into AXI flits and then into individual AXI transactions. This reverses S2 and reconstitutes packetlevel and transaction-level structure on the receiver SoC. (S7) RX process output and completion signaling. The receiver issues AXI responses (b/r) to the remote sender. A chunk completes only when the sender receives the final response, enabling accurate end-to-end timing measurement. 3.3 Evaluator The C2C simulator records each flow completion time (FCT), enabling the evaluator to derive system-level communication metrics. We assess each configuration from 5 dimensions: throughput, P50 latency, P99 latency, fairness, and buffer usage (Table 2). Here, the buffer usage NV · CB reflects relative buffer provisioning, not literal hardware size. To obtain a scalar score S that serves as the optimization objective for AB-DSE search algorithm, each metric is normalized and combined through a weighted sum, where goodput is directly rewarded and all other metrics are minimized. For the user case in Sec. 6, the weights prioritize throughput (40%) and tail latency (25%), reflecting the requirements of large-scale inference workloads. 3.4 Adaptive Bayesian Design Space Exploration With the score function defined in Section 3.3, the final step is to search the large C2C design space for optimal combinations. We develop an AB-DSE engine that tightly integrates an end-to-end workflow: couples hardware-aware constraints, cycle-accurate simulation, and metric-driven optimization. As described in Algorithm 1, AB-DSE first applies C2Cfeasibility pruning eliminates analytically dominated com-

binations (e.g., suboptimal chunk–frame ratios), restricting the search to a more efficient region of the design space [28] [29]. It then performs a diversity-oriented initialization using Latin Hypercube Sampling (LHS), where each sampled configuration is simulated in the C2C simulator and scored in the evaluator. After this seeding phase, AB-DSE enters a Bayesian refinement loop. A Gaussianprocess surrogate is trained on the accumulated history, and Expected Improvement (EI) selects the next candidate expected to improve goodput, latency, fairness, or buffer usage. The surrogate is updated iteratively. When the exploration budget is exhausted, AB-DSE outputs the highestscoring configuration, representing the best achievable balance across all three C2C axes for the given LLM traffic and topology [30] [31].

(a)

(b)

(d)

(c)

host 1 switch

host 2 host 3 host 4

(e)

(f)

(g)

Figure 5: (a) Baseline system (1× 400Gbps switch and 4× FPGAbased C2C host prototypes) [32, 33] to verify C2C simulator. (b– d) Accuracy evaluation. (e–f) Simulation time vs number of XPUs and number of flows for pure cycle model and hybrid models (optimization). (g) Point-to-point simulation throughput for CPython and PyPy JIT [27, 34].

Algorithm 1 AB-DSE: C2C-Aware Adaptive Bayesian Search Require: Design space X , budget B , ratio α, traffic T Ensure: Best configuration x⋆ 1: X ← {x ∈ X | hw_constraints(x)}, H ← ∅, Binit ← ⌊αB⌋ ▷ Init: LHS diversification 2: for i = 1 to Binit do 3: xi ∼ LHS(X ); mi ← SimulateC2C(xi , T ); Si ← Evaluate(mi ) 4: H ← H ∪ {(xi , Si )} 5: end for ▷ BO: C2C-guided refinement 6: for i = Binit + 1 to B do 7: Fit GP surrogate g on H 8: xi ← arg maxx∈X EI(x; g, H) 9: mi ← SimulateC2C(xi , T ); Si ← Evaluate(mi ) 10: H ← H ∪ {(xi , Si )} 11: end for 12: return x⋆ ← arg max(x,S)∈H S

4 Experimental Validation For C2C Simulator The proposed C2C simulator achieves high emulation accuracy with reduced simulation time. The validation experiments and results are detailed as follows.

Table 2: Evaluation metrics in C2C-Explorer Metric

Formula ∑

Unit

Goal wm

Description

GBps

↑

0.40 System throughput

Q0.5 ({Fi }) cycles

↓

0.15 Median FCT

P99 Lat. Q0.99 ({Fi }) cycles

↓

0.25 99th-percentile FCT

Fairness

σF /µF

–

↓

0.05 Coeff. of variation

Buffer

N V · CB

↓

0.15 Buffer per port

Goodput P50 Lat.

Bi /Tmax

Score: S =

1−x

∑

wm · ϕm (Norm(m)), where ϕGoodput (x) = x, others

Notation: Bi = data size of flow i (bytes); Tmax : max flow completion time (FCT, cycles); Fi : FCT of flow i; Qp : p-quantile; σF , µF : std. dev. and mean of all flows FCT; NV : #VCs; CB : credit size; Norm(m) = (m − mmin )/(mmax − mmin ).

4.1 Accuracy Evaluation To the best of our knowledge, no existing simulator supports scale-up communication modeling. Following the ETH-X white-paper report, we configure our simulator using the same bandwidth link (400Gbps), switch forwarding delay (467 ns), and port processing latency (245 ns) to model the data link described in public technical reports [33]. To validate accuracy, we further built a real 400 Gbps system prototype consisting of 1 switch and 4 FPGA-based hosts (Figure 5(a)). This platform exposes the same datapath behavior as ETH-X [32]. Figure 5(b-d) evaluates a 4-XPU system under three representative patterns: (One→All), (All→One), and (All↔All). The x-axis represents the message size (KB) being transmitted, and the y-axis represents the all flow completion time (cycle). Each scenario is swept across a range of message sizes (1 KB–32 KB for (b) and (c), and 1 KB– 448 KB for (d)), resulting in multiple evaluation points per communication pattern. Across these scenarios, the mean error of all swept points relative to the ETH-X measurements is tolerably 4.39%, 2.46%, and 8.23%, respectively. 4.2 Performance and Scalability Hybrid modeling (combining switch-event scheduling with C2C-port cycle scheduling) in C2C-Explorer can expedite large-scale simulation. Figures 5(e)–(f) evaluate this against a purely cycle-accurate baseline both on 2×Intel Xeon Platinum 8358 (1TB main memory). In Figure 5(e), the x-axis is the number of concurrently communicating XPUs, while Figure 5(f) uses the number of serialized flows. Both report end-to-end simulation time on the y-axis. For 128 KB messages in Figure 5(e), the hybrid scheduler achieves 1.1×–7.8× speedups as parallelism scales from 4 to 512 XPUs (All↔All communication). For 1 MB messages, the corresponding speedups range from 0.98×–6.9×. In Figure 5(f), for 128 KB messages across 4–128 serialized flows, the hybrid scheduler achieves 0.77×–4.8× speedups. For 1 MB messages, the range is 0.72×–5.0×. Figure 5(g) reports P2P performance as message size increases on a 13th

(a)

Packetization Param.

(c)

Resource–allocation Param.

2 x MAC frame L-H / L

Scheduling Param.

(b)

1.99x 1.82x 1.91x 1

1.12x Green is better!

Figure 6: (a) Packetization parameters: effect of MAC frame size and chunk size on goodput. (b) Comparison of AXI transmit–side schedulers: DRR/DRR* (deficit round-robin with 2 KB/8 KB quantum). (c) Resource–allocation parameters: VC-pair count under three traffic imbalance levels (R=1, 4, 64), where R = max/min message size. Green indicates a higher normalized score.

Gen Intel Core i7-1355U CPU (16GB main memory); the yaxis shows delivered data per unit simulation time. The PyPy JIT runtime provides an additional acceleration up to 1.78×@data size≤16 MB. We expect the speedup ratio to increase as data sizes grow beyond 16MB based on the trend in Figure 5(g).

5.2 Scheduling Parameters Figure 6(b) compares five AXI transmit–side schedulers in an 8-XPU (All↔All) experiment with 64 KB messages. The x-axis lists the scheduling policies, and the y-axis reports latency (P50/P95/P99 FCT; lower is better) and normalized goodput (higher is better), enabling a joint comparison of throughput and latency under different scheduling strategies. We evaluate: RR (equal round-robin), WRR (weighted RR; per-destination-address (DA) weights 8:4:2:1:1:1:1:1), SP (strict priority over DAs; priority order 0→7), and DRR (deficit round-robin). In DRR, the quantum (2 KB or 8 KB) sets the maximum bytes each DA can transmit per service round; smaller quanta enforce fairness, while larger quanta permit longer bursts at the cost of higher HoL-blocking sensitivity. Relative to RR, both WRR and SP improve goodput (1.12× and 1.82×), while DRR–2KB achieves the highest gain (1.99×). RR offers low unfairness but performs poorly because its frequent destination switching prevents MAC-frame aggregation, increasing per-frame overhead. In contrast, DRR transmits multiple packets to the same destination within one quantum, enabling larger MAC frames and higher link efficiency. However, enlarging the quantum from 2 KB to 8 KB slightly hurts performance (DRR–8KB reduces goodput by 4.06%), as coarse-grained service lets one destination dominate a scheduling window and exacerbates head-of-line blocking (HoL blocking). 5.3 Resource–Allocation Parameters

5 C2C Interconnect Design Space Exploration Based on the verified C2C simulator, we use C2C-Explorer to analyze the impact of Packetization, Scheduling, and Resource-Allocation on C2C interconnect performance under LLM workloads. 5.1 Packetization Parameters In Figure 6(a), the left sub-figure x-axis sweeps the MAC frame size(KB), the right sub-figure x-axis varies the chunk size (with MAC frame size fixed at 1 KB). The y-axis both reports the measured goodput (GB/s) under P2P (no-switch) transmission. The three curves correspond to total message sizes of 128 KB, 256 KB, and 512 KB. The goodput increases sharply as the MAC frame grows from 1 KB to 8 KB and then saturates, following the MAC efficiency (L − H)/L, where L is the MAC-frame length and H is the fixed per-frame protocol overhead. Increasing L amortizes H, improving effective throughput. Goodput improves with chunk size and plateaus once the chunk length reaches roughly twice the MAC-frame size. Each chunk triggers a standalone AXI write burst with its own address, control, and response phases; for small chunks, this per-transaction overhead dominates and depresses throughput. As chunk size increases, the overhead is amortized across more payload; goodput approaches saturation once both the AXI pipeline and the link are fully utilized.

Figure 6(c) quantifies how VC number impacts C2C performance across three communication patterns (All↔All, All→One, One→All) in an 8-XPU system. Each heatmap cell shows the normalized score (green = higher), with VC pairs on the horizontal axis and evaluation metrics (Goodput, P50/P95/P99, Avg. FCT) on the vertical axis. We sweep three flow-size imbalance levels (R = max/min): balanced(64 KB, R = 1), light imbalance(32/64/128 KB, R = 4), and heavy imbalance (8/64/512 KB, R = 64). The results reveal a clear trend: balanced traffic is nearly VC-insensitive; light imbalance benefits from 4–8 VC pairs; heavy imbalance collapses unless NV approaches the concurrent flow count. This behavior follows from the effective imbalance per VC. With global concurrency C and NV VC pairs, each VC carV )−1 . ries ≈ C/NV flows, yielding Reff ≈ 1 + (R − 1) (C/N C−1 As NV increases, Reff → 1, reducing HoL blocking and restoring throughput. When NV is small, Reff ≈ R, and imbalance

Table 3: Performance improvements of the optimal configurations from AB-DSE over the worst feasible designs. Task dispatch combine LLaMA3.1 Qwen3

Goodput +14.7% +44.1% +51.7% +50.5%

P50 Lat. –12.6% –30.4% –68.7% –64.3%

P99 Lat. Fairness1 Buffer2 –12.6% + 0.001 –75% –30.4% –98.4% –68.7% -0.087 –75% –64.3% -0.034 –96.9%

Notation: Metric definitions are summarized in Table 2. 1 Lower is better. Buffer Usage.

(a)

(b)

Figure 7: User case, we evaluate C2C-Explorer using four representative flow groups, including the all-to-all expert exchange in DeepSeek-R1-671B inference (dispatch and combine), the all-reduce synchronization in LLaMA3.1-405B inference, and the gradient all-reduce in Qwen3-30B training. (Left) Normalized score vs iteration for four tasks. (Right) Sensitivity of six design parameters with mean norm. scores and 95% confidence intervals. Table 4: Comparison with representative simulators. Feat. LLM1 FCT2 TME3 AXI4 MP5 CBFC6 SW7

This Work

bookSim [18]

garnet [19]

cnsim [21]

ns-3 [23] OMNeT++ [24]

hybrid

cycle

partial event

partial

partial event

Legend: supported; not supported. 1 LLM = support for real LLM communication traces. 2 FCT = support for flow completion time analysis. 3 TME = cycle/event/hybrid timing model. 4 AXI = support for AXI-level transaction modeling. 5 MP = MAC-layer packetization and dynamic frame construction; bookSim/garnet/cnsim use fixed flits only, while ns3/OMNeT++ use pre-constructed MAC packets. 6 CBFC = credit-based flow control. 7 SW = switch-based topology.

dominates—especially in All→One, All↔All patterns.

6 User Case Study We evaluate C2C-Explorer on a 32-XPU system using three representative communication workloads that capture the dominant communication patterns in modern large-scale LLMs: the all-to-all expert exchange in DeepSeek-R1-671B inference [35], the all-reduce synchronization in LLaMA3.1-405B inference [36], and the gradient all-reduce operations in Qwen3-30B training [37], with all flow traces derived from SimAI profiling. The exploration covers 6 design parameters (Sec. 3.2), spanning packetization (MAC frame size, chunk size), scheduling (AXI-level scheduler, MAC-level scheduler), and resourceallocation (VC pair numbers, credit). Figure 7(a) shows the normalized score (y-axis) over exploration iterations (xaxis). The score weights follow Table 2. Each blue dot corresponds to the score of an evaluated configuration, while the blue solid line tracks the best score achieved so far. All tasks converge within 20 evaluations. The packetization rule (chunk_size ≥ 2× MAC_frame), used for all tasks except DeepSeek-R1 combine, shrinks the feasible space from 2394 to 1152 configurations, removing low-quality points and accelerating convergence. The resulting optimal designs deliver the improvements summarized in Table 3. Fig-

ure 7(b) isolates per-parameter sensitivity. The x-axis enumerates that parameter’s candidate values, while the y-axis shows the mean normalized score with 95% confidence intervals, and shorter bars reflect greater stability. Parameter sensitivity reveals no monotonic trends, underscoring the need for joint optimization. Packetization is most influential, but larger frame size is not universally optimal across tasks. AXI-side scheduling has a greater impact than MACside arbitration. VC=1 often scores well due to minimal buffer cost, yet all workloads prefer multi-VC designs for balanced throughput and latency. Overall, optimal settings are strongly workload-dependent.

7 Conclusion This work introduces C2C-Explorer, a framework for hardware-aware design exploration of C2C interconnects in large-scale LLM workloads. It comprises a traffic generator, a C2C simulator, and an AB-DSE optimization engine, enabling simulation and optimization of configurations for multi-XPU interconnects. Experimental results validate C2C-Explorer’s expedited execution speed and high accuracy (<9%) and demonstrate its potential for exploring communication designs in scale-up and scale-out LLM computing systems.

References [1] Jinwoo Kim, Gauthaman Murali, Heechun Park, Eric Qin, Hyoukjun Kwon, Venkata Chaitanya, Krishna Chekuri, Nihar Dasari, Arvind Singh, Minah Lee, Hakki Mert Torun, Kallol Roy, Madhavan Swaminathan, Saibal Mukhopadhyay, Tushar Krishna, and Sung Kyu Lim. Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse. In Proceedings of the 56th Annual Design Automation Conference, DAC 2019, pages Article 178, 6 pages, 2019. doi: 10.1145/3316781.3317775. [2] Heng Liao, Bingyang Liu, Xianping Chen, Zhigang Guo, Chuanning Cheng, Jianbing Wang, Xiangyu Chen, Peng Dong, Rui Meng, Wenjie Liu, et al. Ub-mesh: a hierarchically localized nd-fullmesh datacenter network

architecture. arXiv preprint arXiv:2503.20377, 2025. [3] Jiachen Mao, Qing Yang, Ang Li, Hai Helen Li, and Yiran Chen. MobiEye: An Efficient Cloud-based Video Detection System for Real-time Mobile Applications. In Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019, page 102. ACM, 2019. doi: 10.1145/3316781.3317865. [4] Burhan Ahmad Mudassar, Jong Hwan Ko, and Saibal Mukhopadhyay. Edge-cloud collaborative processing for intelligent internet of things: a case study on smart surveillance. In Proceedings of the 55th Annual Design Automation Conference, DAC 2018, pages 146:1– 146:6. ACM, 2018. doi: 10.1145/3195970.3196036. [5] Scott Cheng, Jun-Liang Lin, Murali Emani, Siddhisanket Raskar, Sam Foreman, Zhen Xie, Venkatram Vishwanath, and Mahmut Taylan Kandemir. Thorough characterization and analysis of large transformer model training at-scale. 8(1), February 2024. doi: 10.1145/3639034. URL https://doi.org/10.1145/ 3639034. [6] Lang Xu, Kaushik Kandadi Suresh, Quentin Anthony, Nawras Alnaasan, and Dhabaleswar K. Panda. Characterizing communication patterns in distributed large language model inference, 2025. URL https://arxiv. org/abs/2507.14392. [7] Mohammad Shoeybi, Mostofa Patwary, Raul Puri, Patrick LeGresley, Jared Casper, and Bryan Catanzaro. Megatron-lm: Training multi-billion parameter language models using model parallelism, 2020. URL https://arxiv.org/abs/1909.08053. [8] Jeff Rasley, Samyam Rajbhandari, Olatunji Ruwase, and Yuxiong He. Deepspeed: System optimizations enable training deep learning models with over 100 billion parameters. In Proceedings of the 26th ACM SIGKDD International Conference on Knowledge Discovery & Data Minin, KDD 2020, page 3505–3506. Association for Computing Machinery, 2020. ISBN 9781450379984. doi: 10.1145/3394486.3406703. URL https://doi.org/10.1145/3394486.3406703. [9] NVIDIA Corporation. Nccl: Nvidia collective communications library. https://developer.nvidia.com/ nccl, 2025. Accessed: 2025-11-18. [10] Mohamad Baker Alawieh, Fa Wang, and Xin Li. Efficient Hierarchical Performance Modeling for Integrated Circuits via Bayesian Co-Learning. In Proceedings of the 54th Annual Design Automation Conference, DAC 2017, pages 9:1–9:6. ACM, 2017. doi: 10.1145/3061639.3062235. [11] Mengshuo Wang, Fan Yang, Changhao Yan, Xuan Zeng, and Xiangdong Hu. Efficient Bayesian Yield Optimization Approach for Analog and SRAM Circuits. In

Proceedings of the 54th Annual Design Automation Conference, DAC 2017, pages 11:1–11:6. ACM, 2017. doi: 10.1145/3061639.3062234. [12] Amey Agrawal, Nitin Kedia, Jayashree Mohan, Ashish Panwar, Nipun Kwatra, Bhargav S Gulavani, Ramachandran Ramjee, and Alexey Tumanov. Vidur: A large-scale simulation framework for llm inference. In Proceedings of Machine Learning and Systems, 2024, 6:351–366. [13] Xizheng Wang, Qingxu Li, Yichi Xu, Gang Lu, Dan Li, Li Chen, Heyang Zhou, Linkang Zheng, Sen Zhang, Yikai Zhu, Yang Liu, Pengcheng Zhang, Kun Qian, Kunling He, Jiaqi Gao, Ennan Zhai, Dennis Cai, and Binzhang Fu. SimAI: Unifying architecture design and performance tuning for Large-Scale large language model training with scalability and precision. In 22nd USENIX Symposium on Networked Systems Design and Implementation, NSDI 2025), pages 541–558. USENIX Association, April 2025. ISBN 978-1-93913346-5. URL https://www.usenix.org/conference/ nsdi25/presentation/wang-xizheng-simai. [14] Jehyeon Bang, Yujeong Choi, Myeongwoo Kim, Yongdeok Kim, and Minsoo Rhu. vtrain: A simulation framework for evaluating cost-effective and computeoptimal large language model training. In 2024 57th IEEE/ACM International Symposium on Microarchitecture, MICRO 2024, pages 153–167. IEEE, 2024. doi: 10.1109/MICRO61859.2024.00021. [15] Jaehong Cho, Minsu Kim, Hyunmin Choi, Guseul Heo, and Jongse Park. Llmservingsim: A hw/sw co-simulation infrastructure for llm inference serving at scale. In 2024 IEEE International Symposium on Workload Characterization, IISWC 2024, page 15–29. IEEE, September 2024. doi: 10.1109/iiswc63097. 2024.00012. URL http://dx.doi.org/10.1109/ IISWC63097.2024.00012. [16] Mikhail Isaev, Nic Mcdonald, Larry Dennison, and Richard Vuduc. Calculon: a methodology and tool for high-level co-design of systems and large language models. In Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, SC 2023. Association for Computing Machinery, 2023. ISBN 9798400701092. URL https://doi.org/10.1145/3581784.3607102. [17] Hengrui Zhang, August Ning, Rohan Prabhakar, and David Wentzlaff. A hardware evaluation framework for large language model inference, 2023. URL https: //arxiv.org/abs/2312.03134. [18] Nan Jiang, Daniel U. Becker, George Michelogiannakis, James Balfour, Brian Towles, D. E. Shaw, John Kim, and William J. Dally. A detailed and flexible cycle-accurate network-on-chip simulator. In 2013

IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2013, pages 86– 96. IEEE, 2013. doi: 10.1109/ISPASS.2013.6557149. [19] Srikant Bharadwaj, Jieming Yin, Bradford Beckmann, and Tushar Krishna. Kite: A family of heterogeneous interposer topologies enabled via accurate interconnect modeling. In 2020 57th ACM/IEEE Design Automation Conference, DAC 2020, pages 1–6. ACM, 2020. doi: 10.1109/DAC18072.2020.9218539. [20] Nathan Binkert, Bradford Beckmann, Gabriel Black, Steven K. Reinhardt, Ali Saidi, Arkaprava Basu, Joel Hestness, Derek R. Hower, Tushar Krishna, Somayeh Sardashti, Rathijit Sen, Korey Sewell, Muhammad Shoaib, Nilay Vaish, Mark D. Hill, and David A. Wood. The gem5 simulator. SIGARCH Comput. Archit. News, 39(2):1–7, August 2011. ISSN 0163-5964. doi: 10. 1145/2024716.2024718. URL https://doi.org/10. 1145/2024716.2024718. [21] Yinxiao Feng, Yuchen Wei, Dong Xiang, and Kaisheng Ma. Evaluating chiplet-based Large-Scale interconnection networks via Cycle-Accurate Packet-Parallel simulation. In 2024 USENIX Annual Technical Conference, USENIX ATC 2024), pages 731–747. USENIX Association, July 2024. ISBN 978-1-93913341-0. URL https://www.usenix.org/conference/ atc24/presentation/feng-yinxiao. [22] Patrick Iff, Maciej Besta, Matheus Cavalcante, Tim Fischer, Luca Benini, and Torsten Hoefler. Hexamesh: Scaling to hundreds of chiplets with an optimized chiplet arrangement. In Proceedings of the 60th ACM/IEEE Design Automation Conference, DAC 2023, pages 1–6, 2023. doi: 10.1109/DAC56929. 2023.10248006. [23] T. R. Henderson, M. Lacage, et al. ns-3: A discreteevent network simulator for internet systems. In Proceedings of the ACM SIGCOMM 2008 Conference on Data Communication, 2008. [24] András Varga and Rudolf Hornig. An overview of the omnet++ simulation environment. In Proceedings of the 1st International Conference on Simulation Tools and Techniques for Communications, Networks and Systems & Workshops, Simutools ’08. ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering), 2008. ISBN 9789639799202. [25] Alexander Graening, Saptadeep Pal, and Puneet Gupta. Chiplets: How Small is Too Small? In Proceedings of the 60th ACM/IEEE Design Automation Conference, DAC 2023, pages 1–6, 2023. doi: 10.1109/DAC56929. 2023.10247947.

[26] Yinxiao Feng and Kaisheng Ma. Chiplet Actuary: A Quantitative Cost Model and Multi-Chiplet Architecture Exploration. In Proceedings of the 59th ACM/IEEE Design Automation Conference, DAC 2022, pages 121–126. ACM, 2022. doi: 10.1145/3489517. 3530428. [27] Carl Friedrich Bolz, Antonio Cuni, Maciej Fijalkowski, and Armin Rigo. Tracing the meta-level: Pypy’s tracing jit compiler. ICOOOLPS 2009, page 18–25. Association for Computing Machinery, 2009. ISBN 9781605585413. doi: 10.1145/1565824.1565827. URL https://doi.org/10.1145/1565824.1565827. [28] Shuhan Zhang, Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng, and Xiangdong Hu. An Efficient Multi-fidelity Bayesian Optimization Approach for Analog Circuit Synthesis. In Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019, page 64. ACM, 2019. doi: 10.1145/3316781. 3317765. [29] Hanbin Hu, Peng Li, and Jianhua Z. Huang. Enabling High-Dimensional Bayesian Optimization for Efficient Failure Detection of Analog and Mixed-Signal Circuits. In Proceedings of the 56th Annual Design Automation Conference, DAC 2019, page 17. ACM. doi: 10.1145/ 3316781.3317818. [30] Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, and Xuan Zeng. Multi-objective Bayesian optimization for analog/RF circuit synthesis. In Proceedings of the 55th Annual Design Automation Conference, DAC 2018, pages 11:1–11:6. ACM, 2018. doi: 10.1145/ 3195970.3196078. [31] Jinyuan Zhai, Changhao Yan, Sheng-Guo Wang, and Dian Zhou. An efficient Bayesian yield estimation method for high dimensional and high sigma SRAM circuits. In Proceedings of the 55th Annual Design Automation Conference, DAC 2018, pages 132:1–132:6. ACM, 2018. doi: 10.1145/3195970.3195987. [32] Open Data Center Committee (ODCC). Eth-x scale up interconnect protocol white paper, version 1.0. Technical Report ODCC-2025-03002, Open Data Center Committee (ODCC), September 2025. In Chinese. [33] Open Data Center Committee (ODCC). Eth-x scale up interconnect protocol test report. Technical Report ODCC-2025-03005, Open Data Center Committee (ODCC), September 2025. In Chinese. [34] Håkan Ardö, Carl Friedrich Bolz, and Maciej FijaBkowski. Loop-aware optimizations in pypy’s tracing jit. 48(2):63–72, October 2012. ISSN 0362-1340. doi: 10.1145/2480360.2384586. [35] Daya Guo, Dejian Yang, Haowei Zhang, Junxiao Song, Peiyi Wang, Qihao Zhu, Runxin Xu, Ruoyu Zhang, Shirong Ma, Xiao Bi, Xiaokang Zhang, Xingkai Yu, Yu Wu,

Z. F. Wu, Zhibin Gou, Zhihong Shao, Zhuoshu Li, Ziyi Gao, Aixin Liu, Bing Xue, Bingxuan Wang, Bochao Wu, Bei Feng, Chengda Lu, Chenggang Zhao, Chengqi Deng, Chong Ruan, Damai Dai, Deli Chen, Dongjie Ji, Erhang Li, Fangyun Lin, Fucong Dai, Fuli Luo, Guangbo Hao, Guanting Chen, Guowei Li, H. Zhang, Hanwei Xu, Honghui Ding, Huazuo Gao, Hui Qu, Hui Li, Jianzhong Guo, Jiashi Li, Jingchang Chen, Jingyang Yuan, Jinhao Tu, Junjie Qiu, Junlong Li, J. L. Cai, Jiaqi Ni, Jian Liang, Jin Chen, Kai Dong, Kai Hu, Kaichao You, Kaige Gao, Kang Guan, Kexin Huang, Kuai Yu, Lean Wang, Lecong Zhang, Liang Zhao, Litong Wang, Liyue Zhang, Lei Xu, Leyi Xia, Mingchuan Zhang, Minghua Zhang, Minghui Tang, Mingxu Zhou, Meng Li, Miaojun Wang, Mingming Li, Ning Tian, Panpan Huang, Peng Zhang, Qiancheng Wang, Qinyu Chen, Qiushi Du, Ruiqi Ge, Ruisong Zhang, Ruizhe Pan, Runji Wang, R. J. Chen, R. L. Jin, Ruyi Chen, Shanghao Lu, Shangyan Zhou, Shanhuang Chen, Shengfeng Ye, Shiyu Wang, Shuiping Yu, Shunfeng Zhou, Shuting Pan, S. S. Li, Shuang Zhou, Shaoqing Wu, Tao Yun, Tian Pei, Tianyu Sun, T. Wang, Wangding Zeng, Wen Liu, Wenfeng Liang, Wenjun Gao, Wenqin Yu, Wentao Zhang, W. L. Xiao, Wei An, Xiaodong Liu, Xiaohan Wang, Xiaokang Chen, Xiaotao Nie, Xin Cheng, Xin Liu, Xin Xie, Xingchao Liu, Xinyu Yang, Xinyuan Li, Xuecheng Su, Xuheng Lin, X. Q. Li, Xiangyue Jin, Xiaojin Shen, Xiaosha Chen, Xiaowen Sun, Xiaoxiang Wang, Xinnan Song, Xinyi Zhou, Xianzu Wang, Xinxia Shan, Y. K. Li, Y. Q. Wang, Y. X. Wei, Yang Zhang, Yanhong Xu, Yao Li, Yao Zhao, Yaofeng Sun, Yaohui Wang, Yi Yu, Yichao Zhang, Yifan Shi, Yiliang Xiong, Ying He, Yishi Piao, Yisong Wang, Yixuan Tan, Yiyang Ma, Yiyuan Liu, Yongqiang Guo, Yuan Ou, Yuduan Wang, Yue Gong, Yuheng Zou, and Yujia He. Deepseek‐r1 incentivizes reasoning in llms through reinforcement learning. Nature, 645(8081): 633–638, 2025. doi: 10.1038/s41586-025-09422-z. [36] Aaron Grattafiori, Abhimanyu Dubey, Abhinav Jauhri, Abhinav Pandey, Abhishek Kadian, Ahmad Al-Dahle, Aiesha Letman, Akhil Mathur, Alan Schelten, Alex Vaughan, Amy Yang, Angela Fan, Anirudh Goyal, Anthony Hartshorn, Aobo Yang, Archi Mitra, Archie Sravankumar, Artem Korenev, Arthur Hinsvark, Arun Rao, Aston Zhang, Aurelien Rodriguez, Austen Gregerson, Ava Spataru, Baptiste Roziere, Bethany Biron, Binh Tang, Bobbie Chern, Charlotte Caucheteux, Chaya Nayak, Chloe Bi, Chris Marra, Chris McConnell, Christian Keller, Christophe Touret, Chunyang Wu, Corinne Wong, Cristian Canton Ferrer, Cyrus Nikolaidis, Damien Allonsius, Daniel Song, Danielle Pintz, Danny Livshits, Danny Wyatt, David Esiobu, Dhruv Choudhary, Dhruv Mahajan, Diego Garcia-Olano, Diego Perino, Dieuwke Hupkes, Egor Lakomkin, Ehab AlBadawy, Elina Lobanova, Emily Dinan, Eric Michael Smith, Filip Radenovic, Francisco Guzmán, Frank

Zhang, Gabriel Synnaeve, Gabrielle Lee, Georgia Lewis Anderson, Govind Thattai, Graeme Nail, Gregoire Mialon, Guan Pang, Guillem Cucurell, Hailey Nguyen, Hannah Korevaar, Hu Xu, Hugo Touvron, Iliyan Zarov, Imanol Arrieta Ibarra, Isabel Kloumann, Ishan Misra, Ivan Evtimov, Jack Zhang, Jade Copet, Jaewon Lee, Jan Geffert, Jana Vranes, Jason Park, Jay Mahadeokar, Jeet Shah, Jelmer van der Linde, Jennifer Billock, Jenny Hong, Jenya Lee, Jeremy Fu, Jianfeng Chi, Jianyu Huang, Jiawen Liu, Jie Wang, Jiecao Yu, Joanna Bitton, Joe Spisak, Jongsoo Park, Joseph Rocca, Joshua Johnstun, Joshua Saxe, Junteng Jia, Kalyan Vasuden Alwala, Karthik Prasad, Kartikeya Upasani, Kate Plawiak, Ke Li, Kenneth Heafield, Kevin Stone, Khalid El-Arini, Krithika Iyer, Kshitiz Malik, Kuenley Chiu, Kunal Bhalla, Kushal Lakhotia, Lauren Rantala-Yeary, Laurens van der Maaten, Lawrence Chen, Liang Tan, Liz Jenkins, Louis Martin, Lovish Madaan, Lubo Malo, Lukas Blecher, Lukas Landzaat, Luke de Oliveira, Madeline Muzzi, Mahesh Pasupuleti, Mannat Singh, Manohar Paluri, Marcin Kardas, Maria Tsimpoukelli, Mathew Oldham, Mathieu Rita, Maya Pavlova, Melanie Kambadur, Mike Lewis, Min Si, Mitesh Kumar Singh, Mona Hassan, Naman Goyal, Narjes Torabi, Nikolay Bashlykov, Nikolay Bogoychev, Niladri Chatterji, Ning Zhang, Olivier Duchenne, Onur Çelebi, Patrick Alrassy, Pengchuan Zhang, Pengwei Li, Petar Vasic, Peter Weng, Prajjwal Bhargava, Pratik Dubal, Praveen Krishnan, Punit Singh Koura, Puxin Xu, Qing He, Qingxiao Dong, Ragavan Srinivasan, Raj Ganapathy, Ramon Calderer, Ricardo Silveira Cabral, Robert Stojnic, Roberta Raileanu, Rohan Maheswari, Rohit Girdhar, Rohit Patel, Romain Sauvestre, Ronnie Polidoro, Roshan Sumbaly, Ross Taylor, Ruan Silva, Rui Hou, Rui Wang, Saghar Hosseini, Sahana Chennabasappa, Sanjay Singh, Sean Bell, Seohyun Sonia Kim, Sergey Edunov, Shaoliang Nie, Sharan Narang, Sharath Raparthy, Sheng Shen, Shengye Wan, Shruti Bhosale, Shun Zhang, Simon Vandenhende, Soumya Batra, Spencer Whitman, Sten Sootla, Stephane Collot, Suchin Gururangan, Sydney Borodinsky, Tamar Herman, Tara Fowler, Tarek Sheasha, Thomas Georgiou, Thomas Scialom, Tobias Speckbacher, Todor Mihaylov, Tong Xiao, Ujjwal Karn, Vedanuj Goswami, Vibhor Gupta, Vignesh Ramanathan, Viktor Kerkez, Vincent Gonguet, Virginie Do, Vish Vogeti, Vítor Albiero, Vladan Petrovic, Weiwei Chu, Wenhan Xiong, Wenyin Fu, Whitney Meers, Xavier Martinet, Xiaodong Wang, Xiaofang Wang, Xiaoqing Ellen Tan, Xide Xia, Xinfeng Xie, Xuchao Jia, Xuewei Wang, Yaelle Goldschlag, Yashesh Gaur, Yasmine Babaei, Yi Wen, Yiwen Song, Yuchen Zhang, Yue Li, Yuning Mao, Zacharie Delpierre Coudert, Zheng Yan, Zhengxing Chen, Zoe Papakipos, Aaditya Singh, Aayushi Srivastava, Abha Jain, Adam Kelsey, Adam Shajnfeld, Adithya Gangidi, Adolfo Victoria, Ahuva

Goldstand, Ajay Menon, Ajay Sharma, Alex Boesenberg, Alexei Baevski, Allie Feinstein, Amanda Kallet, Amit Sangani, Amos Teo, Anam Yunus, Andrei Lupu, Andres Alvarado, Andrew Caples, Andrew Gu, Andrew Ho, Andrew Poulton, Andrew Ryan, Ankit Ramchandani, Annie Dong, Annie Franco, Anuj Goyal, Aparajita Saraf, Arkabandhu Chowdhury, Ashley Gabriel, Ashwin Bharambe, Assaf Eisenman, Azadeh Yazdan, Beau James, Ben Maurer, Benjamin Leonhardi, Bernie Huang, Beth Loyd, Beto De Paola, Bhargavi Paranjape, Bing Liu, Bo Wu, Boyu Ni, Braden Hancock, Bram Wasti, Brandon Spence, Brani Stojkovic, Brian Gamido, Britt Montalvo, Carl Parker, Carly Burton, Catalina Mejia, Ce Liu, Changhan Wang, Changkyu Kim, Chao Zhou, Chester Hu, Ching-Hsiang Chu, Chris Cai, Chris Tindal, Christoph Feichtenhofer, Cynthia Gao, Damon Civin, Dana Beaty, Daniel Kreymer, Daniel Li, David Adkins, David Xu, Davide Testuggine, Delia David, Devi Parikh, Diana Liskovich, Didem Foss, Dingkang Wang, Duc Le, Dustin Holland, Edward Dowling, Eissa Jamil, Elaine Montgomery, Eleonora Presani, Emily Hahn, Emily Wood, Eric-Tuan Le, Erik Brinkman, Esteban Arcaute, Evan Dunbar, Evan Smothers, Fei Sun, Felix Kreuk, Feng Tian, Filippos Kokkinos, Firat Ozgenel, Francesco Caggioni, Frank Kanayet, Frank Seide, Gabriela Medina Florez, Gabriella Schwarz, Gada Badeer, Georgia Swee, Gil Halpern, Grant Herman, Grigory Sizov, Guangyi, Zhang, Guna Lakshminarayanan, Hakan Inan, Hamid Shojanazeri, Han Zou, Hannah Wang, Hanwen Zha, Haroun Habeeb, Harrison Rudolph, Helen Suk, Henry Aspegren, Hunter Goldman, Hongyuan Zhan, Ibrahim Damlaj, Igor Molybog, Igor Tufanov, Ilias Leontiadis, Irina-Elena Veliche, Itai Gat, Jake Weissman, James Geboski, James Kohli, Janice Lam, Japhet Asher, Jean-Baptiste Gaya, Jeff Marcus, Jeff Tang, Jennifer Chan, Jenny Zhen, Jeremy Reizenstein, Jeremy Teboul, Jessica Zhong, Jian Jin, Jingyi Yang, Joe Cummings, Jon Carvill, Jon Shepard, Jonathan McPhie, Jonathan Torres, Josh Ginsburg, Junjie Wang, Kai Wu, Kam Hou U, Karan Saxena, Kartikay Khandelwal, Katayoun Zand, Kathy Matosich, Kaushik Veeraraghavan, Kelly Michelena, Keqian Li, Kiran Jagadeesh, Kun Huang, Kunal Chawla, Kyle Huang, Lailin Chen, Lakshya Garg, Lavender A, Leandro Silva, Lee Bell, Lei Zhang, Liangpeng Guo, Licheng Yu, Liron Moshkovich, Luca Wehrstedt, Madian Khabsa, Manav Avalani, Manish Bhatt, Martynas Mankus, Matan Hasson, Matthew Lennie, Matthias Reso, Maxim Groshev, Maxim Naumov, Maya Lathi, Meghan Keneally, Miao Liu, Michael L. Seltzer, Michal Valko, Michelle Restrepo, Mihir Patel, Mik Vyatskov, Mikayel Samvelyan, Mike Clark, Mike Macey, Mike Wang, Miquel Jubert Hermoso, Mo Metanat, Mohammad Rastegari, Munish Bansal, Nandhini Santhanam, Natascha Parks, Natasha White, Navyata Bawa, Nayan Singhal, Nick Egebo, Nicolas Usunier, Nikhil Mehta,

Nikolay Pavlovich Laptev, Ning Dong, Norman Cheng, Oleg Chernoguz, Olivia Hart, Omkar Salpekar, Ozlem Kalinli, Parkin Kent, Parth Parekh, Paul Saab, Pavan Balaji, Pedro Rittner, Philip Bontrager, Pierre Roux, Piotr Dollar, Polina Zvyagina, Prashant Ratanchandani, Pritish Yuvraj, Qian Liang, Rachad Alao, Rachel Rodriguez, Rafi Ayub, Raghotham Murthy, Raghu Nayani, Rahul Mitra, Rangaprabhu Parthasarathy, Raymond Li, Rebekkah Hogan, Robin Battey, Rocky Wang, Russ Howes, Ruty Rinott, Sachin Mehta, Sachin Siby, Sai Jayesh Bondu, Samyak Datta, Sara Chugh, Sara Hunt, Sargun Dhillon, Sasha Sidorov, Satadru Pan, Saurabh Mahajan, Saurabh Verma, Seiji Yamamoto, Sharadh Ramaswamy, Shaun Lindsay, Shaun Lindsay, Sheng Feng, Shenghao Lin, Shengxin Cindy Zha, Shishir Patil, Shiva Shankar, Shuqiang Zhang, Shuqiang Zhang, Sinong Wang, Sneha Agarwal, Soji Sajuyigbe, Soumith Chintala, Stephanie Max, Stephen Chen, Steve Kehoe, Steve Satterfield, Sudarshan Govindaprasad, Sumit Gupta, Summer Deng, Sungmin Cho, Sunny Virk, Suraj Subramanian, Sy Choudhury, Sydney Goldman, Tal Remez, Tamar Glaser, Tamara Best, Thilo Koehler, Thomas Robinson, Tianhe Li, Tianjun Zhang, Tim Matthews, Timothy Chou, Tzook Shaked, Varun Vontimitta, Victoria Ajayi, Victoria Montanez, Vijai Mohan, Vinay Satish Kumar, Vishal Mangla, Vlad Ionescu, Vlad Poenaru, Vlad Tiberiu Mihailescu, Vladimir Ivanov, Wei Li, Wenchen Wang, Wenwen Jiang, Wes Bouaziz, Will Constable, Xiaocheng Tang, Xiaojian Wu, Xiaolan Wang, Xilun Wu, Xinbo Gao, Yaniv Kleinman, Yanjun Chen, Ye Hu, Ye Jia, Ye Qi, Yenda Li, Yilin Zhang, Ying Zhang, Yossi Adi, Youngjin Nam, Yu, Wang, Yu Zhao, Yuchen Hao, Yundi Qian, Yunlu Li, Yuzi He, Zach Rait, Zachary DeVito, Zef Rosnbrick, Zhaoduo Wen, Zhenyu Yang, Zhiwei Zhao, and Zhiyu Ma. The llama 3 herd of models, 2024. URL https: //arxiv.org/abs/2407.21783. [37] An Yang, Anfeng Li, Baosong Yang, Beichen Zhang, Binyuan Hui, Bo Zheng, Bowen Yu, Chang Gao, Chengen Huang, Chenxu Lv, Chujie Zheng, Dayiheng Liu, Fan Zhou, Fei Huang, Feng Hu, Hao Ge, Haoran Wei, Huan Lin, Jialong Tang, Jian Yang, Jianhong Tu, Jianwei Zhang, Jianxin Yang, Jiaxi Yang, Jing Zhou, Jingren Zhou, Junyang Lin, Kai Dang, Keqin Bao, Kexin Yang, Le Yu, Lianghao Deng, Mei Li, Mingfeng Xue, Mingze Li, Pei Zhang, Peng Wang, Qin Zhu, Rui Men, Ruize Gao, Shixuan Liu, Shuang Luo, Tianhao Li, Tianyi Tang, Wenbiao Yin, Xingzhang Ren, Xinyu Wang, Xinyu Zhang, Xuancheng Ren, Yang Fan, Yang Su, Yichang Zhang, Yinger Zhang, Yu Wan, Yuqiong Liu, Zekun Wang, Zeyu Cui, Zhenru Zhang, Zhipeng Zhou, and Zihan Qiu. Qwen3 technical report, 2025. URL https: //arxiv.org/abs/2505.09388.

C2C-Explorer: An Exploration Framework for Chip-to-Chip Interconnect Architectures in LLM Cloud Computing Systems

Analyze & explore related research in Conceptio

Related documents