AlphaClifford: Efficient Clifford Synthesis and Transpilation with Model-based RL

arXiv:2608.18946v1 [quant-ph] 19 Aug 2026

AlphaClifford: Efficient Clifford Synthesis and Transpilation with Model-based RL Daniele Lizzio Bosco

Jacopo Cossio

Carla Piazza

Giuseppe Serra

University of Udine Udine, Italy University of Naples “Federico II” Naples, Italy lizziobosco.daniele@spes.uniud.it

University of Udine Udine, Italy cossio.jacopo@spes.uniud.it

University of Udine Udine, Italy carla.piazza@uniud.it

University of Udine Udine, Italy giuseppe.serra@uniud.it

Abstract—Clifford circuits play a foundational role in quantum computing, particularly due to their importance in quantum error correction and fault-tolerant logical synthesis. While these circuits can be efficiently simulated and represented as symplectic matrices, standard synthesis methods—such as the AaronsonGottesman algorithm—often yield sub-optimal circuits with excessively high gate counts. In this work, we introduce AlphaClifford, a model-based Reinforcement Learning framework powered by Monte Carlo Tree Search, designed to efficiently synthesize Clifford circuits from the fundamental gate set composed of H, S, and CNOT. By modeling the state space through the algebraic properties of the symplectic group, AlphaClifford effectively explores this combinatorial space to minimize overall circuit cost. For unconstrained Clifford optimization, our approach achieves a consistent reduction in both total and two-qubit (CNOT) gate counts compared to state-of-the-art synthesis heuristics, despite operating with a strictly less expressive gate set. Furthermore, we demonstrate the broad applicability of our framework on two additional tasks: hardware-constrained Clifford transpilation, where we outperform existing RL-based compilers, and as a postsynthesis optimization component within a full Clifford+T logical synthesis pipeline. Our results underscore that model-based RL is highly effective at addressing the combinatorial complexities of quantum compilation, offering a scalable pathway to mitigate hardware constraints in both near-term and future fault-tolerant quantum devices. Index Terms—Reinforcement Learning, Clifford Circuits, Quantum Synthesis, Quantum Optimization, Circuit Compilation

I. I NTRODUCTION The field of quantum computing is rapidly approaching the era of “quantum utility” [1], marking a pivotal transition where quantum devices cease to be experimental research instruments and begin to execute practical, large-scale applications. These applications are expected to span both scientific domains, such as Quantum Chemistry [2] and High Energy Physics [3], and industrial use cases, including discrete optimization [4] and finance [5]. Despite significant recent advancements in quantum hardware capabilities—most notably in error rate reduction and © 2026 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

coherence time improvements [6], [7]—the execution of quantum algorithms remains fundamentally constrained by circuit depth and the total number of physical gates. To mitigate these hardware limitations, quantum circuit optimization plays a critical role. As equivalent unitary transformations can be realized by different sequences of quantum gates, the objective of quantum circuit synthesis [8]–[12] is to find a sequence of gates that implements a target circuit (or its mathematical representation) while minimizing a specific cost metric, such as overall circuit depth or the number of two-qubit entangling gates. A closely related challenge is quantum circuit transpilation [13], [14], which involves mapping a logical circuit onto a specific physical architecture. This requires decomposing the target circuit into a native gate set and respecting strict hardware constraints, such as the limited connectivity map of the physical qubits [15]. The problems of quantum circuit synthesis and transpilation have been extensively explored in the literature, utilizing a wide array of heuristic, algebraic, and search-based techniques [9], [16]–[18]. Recently, Reinforcement Learning (RL) has emerged as a highly effective paradigm for tackling these computationally hard optimization problems [19]–[27]. By learning complex patterns rather than relying on heuristic rules, RL-based approaches have demonstrated the ability to discover novel, non-intuitive gate sequences that rule-based compilers might otherwise miss. In this work, we propose a RL-based technique to address both the synthesis and transpilation tasks specifically for the set of Clifford circuits. Generated strictly by the Hadamard (H), Phase (S), and Controlled-NOT (CNOT) gates, Clifford circuits are one of the most studied gate sets, and play a central role in the logical synthesis pipeline, particularly within the context of Clifford+T decomposition [21]. A key advantage of Clifford gates is that they admit an efficient classical representation via symplectic matrices [28]. We exploit this compact representation to develop a RL framework designed to learn highly efficient syntheses and transpilation strategies for Clifford circuits. Inspired by recent successes on similar tasks from AlphaTensor [19] and AlphaCNOT [27], our method formulates

a) Training

b) Inference

c) Applications Clifford Optimization

Ctar

Symplectic Generation

H(1), H(2), S(3), CNOT(1,2), S(3), H(1), CNOT(2,3)

X Flip

Ctar

Csyn

Target Clifford

Optimized Circuit

Symplectic Matrix

Target Clifford

Clifford Transpilation

+

Ctar

Output Sequence

Z Flip

C .

Initial Node

X H(2), CNOT(3,2), S(1), S(2), H(1)

H

Target Clifford

Connectivity Map

Hardware-Compliant

Logical Synthesis

H

Output Sequence Target Node

H

Z

S

T

S

U

U

Initial Circuit

Precompiled

T

T

Pauli Adjustment State Tree

T

T

Final Circuit

Clifford+T

T Optimization

Fig. 1: a) We train our model to reproduce a target symplectic matrix. Each symplectic matrix is modelled as the node of a tree, where nodes are connected if the corresponding matrices can be reached with an operation from H, S, and CNOT. We train a MCTS-based model as a pair of value network (for nodes, e.g. lighter blue corresponds to a higher value) and policy network (for edges, e.g. wider arrows corresponds to higher probabilities). b) Given a target Clifford circuit Ctar , we utilize our model to synthesize a circuit C with the same symplectic matrix, i.e. P · C ≡ Ctar for a suitable Pauli P . We then compute the P from initial circuit, and we apply the corresponding gates to the obtained circuit. c) AlphaClifford can be applied to a variety of tasks, including general Clifford circuits optimization, Clifford transpilation to ensure compatibility with a given hardware connectivity map, and as a component in a pipeline for logical synthesis, from a general initial circuit, to the final approximated version in Clifford+T.

the circuit compilation problem as a tree-based search over the space of symplectic matrices, with the aim of finding the shortest path from an initial matrix to the identity, allowing for a compact reconstruction of the corresponding Clifford circuit from the set gate {H, S, CNOT}. To demonstrate the broad applicability of our proposed method, we evaluate it on three different tasks: unconstrained Clifford optimization, Clifford transpilation to a target hardware connectivity map, and as a refinement step in a full logical synthesis pipeline. We show that our model achieves comparable or higher performance with respect to a variety of different techniques, including up to 56% total gate reduction compared to the Aaronson-Gottesman algorithm [28] for the general Clifford optimization task, and up to 20% compared to the RL-based Clifford transpiler from [26] on the task of transpilation. Our results suggest that AlphaClifford can be applied efficiently in different settings. The paper is organized as follows. In Section II we provide a brief introduction to the symplectic representation of Clifford circuits. In Section III we discuss related works. In Section IV we present our method. Experimental design and results are discussed in Section V. Finally, in Section VI we provide some final considerations and suggest possible directions for further works.

II. S YMPLECTIC R EPRESENTATION OF C LIFFORD C IRCUITS A. Stabilizer Formalism and Tableau Representation The n-qubit Pauli group Pn consists of all n-fold tensor products of the Pauli matrices {I, X, Y, Z} together with the multiplicative phase factors {±1, ±i}. The Clifford group Cn is defined as the normalizer of the Pauli group within the unitary group U (2n ). Specifically, for any Clifford operator C ∈ Cn and any Pauli operator P ∈ Pn , the conjugation CP C † yields another operator in Pn . The group Cn is finitely generated by the Hadamard (H), Phase (S), and ControlledNOT (CNOT) gates. By the Gottesman-Knill theorem [29], Clifford circuits can be efficiently simulated on classical hardware. The standard data structure for this is the tableau representation introduced by Aaronson and Gottesman [28]. The state of an n-qubit Clifford circuit is completely characterized by tracing the evolution of n destabilizer generators and n stabilizer generators. In this formalism, the circuit is represented as a 2n × (2n + 1) binary matrix T over the Galois field F2 : T =



X

Z

r



,

(1)

where X and Z are 2n × n Boolean matrices denoting the presence of X and Z Pauli operators, respectively. The 2ndimensional column vector r contains Boolean phase bits indicating whether the overall sign of each respective generator is +1 (ri = 0) or −1 (ri = 1).

As a simple example, consider a single-qubit system. The initial tableau corresponding to the identity circuit is   1 0 0 TI = , 0 1 0

P can be computed efficiently in O(n2 ) time. Therefore, mapping the RL state space to Sp(2n, F2 ) rather than the full Clifford group Cn reduces the search space by a factor of 22n , simplifying the learning process.

where the first row represents the destabilizer generator X and the second row represents the stabilizer generator Z. Applying a Hadamard gate H exchanges X and Z, resulting in the tableau   0 1 0 . TH = 1 0 0

III. R ELATED W ORK

This illustrates how Clifford operations act linearly on the (X , Z) components of the tableau by transforming Pauli generators. If we further apply an X gate, the Pauli structure remains unchanged, but the phase of the Z generator is flipped:   0 1 0 . TXH = 1 0 1 Thus, while the matrices X and Z encode the Pauli action of the circuit, the vector r captures the accumulated phase information. B. Symplectic Matrix Representation While the phase vector r is required to track the exact quantum state (including Pauli phases), the fundamental entangling structure and basis transformations induced by a Clifford circuit are entirely captured by the 2n × 2n binary matrix M = [X Z]. To preserve the commutation relations of the Pauli group, the matrix M must satisfy the symplectic condition over F2 : M ΩM T = Ω

(mod 2),

where Ω is the 2n × 2n block matrix defined as:   0 In Ω= , In 0

(2)

(3)

and In is the n × n identity matrix. Consequently, M is an element of the symplectic group Sp(2n, F2 ). Crucially, there exists a surjective group homomorphism ϕ : Cn → Sp(2n, F2 ) that maps a Clifford unitary to its corresponding symplectic matrix. The kernel of this homomorphism is precisely the Pauli group Pn (ignoring global phases). C. Implications for Circuit Synthesis In our context of synthesizing Clifford circuits, the homomorphism ϕ provides a powerful mathematical abstraction. If an RL agent restricts its objective to finding a sequence of {H, S, CNOT} gates that yields a symplectic matrix Msyn matching a target symplectic matrix Mtarget , the synthesized circuit Csyn and the target circuit Ctarget are guaranteed to belong to the same coset of the Pauli group. Mathematically, this establishes an equivalence up to a Pauli layer: Ctarget ≡ P · Csyn ,

(4)

where P ∈ Pn . By tracking the evolution of the phase vector r alongside the synthesis process, the residual Pauli correction

The problem of quantum circuit synthesis and compilation is extremely important for mitigating hardware limitations of current devices, and the literature addressing this challenge is extensive [30]. Within the context of Clifford circuits, the historical baseline is the well-known Aaronson-Gottesman algorithm [28], which demonstrated that this class of circuits can be efficiently simulated and synthesized in polynomial time with gates from {H, S, CNOT}. However, standard approaches usually generate sub-optimal circuits with respect to the number of gates. To address this, various advanced heuristic methods have been proposed. For instance, the approaches described in [31] (such as A*, greedy algorithms, and Volanto [32]) leverage a richer generating set to reduce the gate count in the circuit. Another approach is the one proposed in [33], where Clifford-specific template matching is combined with symbolic peephole optimization, obtaining relevant reductions in CNOT count. It is also worth noting that the literature offers solutions for the optimal and exact syntheses of Clifford circuits [34], [35]. However, finding the absolute minimum sequence of gates generally requires exponential time, drastically limiting the scalability of these methods to a very small number of qubits and rendering them unsuitable for practical, large-scale applications. Recently, many Reinforcement Learning (RL) based solutions have been proposed to address tasks related to circuit synthesis, optimization, and compilation, including state preparation [24], quantum architecture search [36], and “precompilation” in logical synthesis pipelines in Q-P RE S YN [37]. The synthesis of Clifford circuits is particularly well-suited for RL applications: the algebraic properties of these circuits provide a compact and highly efficient state representation, usually as a matrix of polynomial size. Initially, many works were based on model-free algorithms, such as Proximal Policy Optimization [38] (PPO), which learn directly by interacting with the environment without building an internal model of the dynamics. Notable among these is the recent work [26], which leverages RL for the routing and synthesis of Clifford circuits, yielding transpilers capable of significantly outperforming traditional heuristics like SABRE [39]. Another impactful model-free application is provided in [22] in the context of quantum circuit discovery for fault-tolerant logical state preparation, where RL was used to discover entirely new protocols that surpass the efficiency of manually designed circuits. Additionally, in [25] the authors propose a PPO-based approach to optimize CNOT count in linear reversible circuits. Despite the significant successes of model-free methods, recent developments demonstrate that when the mathematical

structure of the problem allows it, model-based algorithms, usually based on Monte Carlo Tree Search [40] (MCTS), offer vastly superior capabilities for exploring complex combinatorial spaces. In this regard, AlphaTensor-Quantum [19] paved the way by demonstrating how the CNOT+T component of a circuit can be optimized using search techniques originally designed for board games [41]. Similarly, AlphaCNOT [27] provided a model to address the problems of CNOT optimization in both unconstrained and constrained (i.e., depending on a connectivity map) settings. Finally, another relevant contribution is QuSynth [42], in which the task of stabilizer state preparation is reformulated by using graph-state representations, and addressed by combining RL with MCTS for structured look-ahead. Our work, AlphaClifford, builds on these developments by bringing the strengths of search-informed reinforcement learning to the synthesis of general Clifford circuits. In particular, we draw inspiration from the AlphaTensor and AlphaCNOT frameworks, adapting their core ideas to exploit the algebraic structure of Clifford operations and further advance the state of the art in this domain. IV. A LPHAC LIFFORD A popular class of Reinforcement Learning (RL) approaches is classified as model-free, i.e., they learn directly from interactions with the environment and do not leverage an explicit model of its dynamics. Model-free approaches, such as Proximal Policy Optimization [38] (PPO), rely on sequences of state–action–reward transitions to iteratively update the policy via gradient-based optimization. Conversely, model-based RL algorithms construct a representation of the environment to simulate future outcomes [43]. Within complex combinatorial spaces, such as the set of symplectic matrices, their capacity for structured and efficient exploration enables them to obtain improved performance over both classical heuristics and model-free algorithms. Following the latter principle, and inspired by recent applications such as AlphaTensor [19] and AlphaCNOT [27], we propose AlphaClifford, a novel model-based approach for exploring the combinatorial space of symplectic matrices associated with Clifford circuits. Our method, illustrated in Fig. 1, is organized into the following steps: First, we model the space of symplectic matrices as a search tree (Fig. 1a), where each node represents a specific symplectic matrix and directed edges correspond to the application of Clifford gates. In this representation, two nodes are connected if the corresponding matrices can be reached through a Clifford gate operation. • Second, we train a model to learn the structure of this space by predicting sequences of gate operations that transform the initial symplectic matrix into the target one. The training procedure, structured after the Monte Carlo Tree Search pattern [40], is detailed in Section IV-C. •

•

Third, once trained, the model is used to synthesize Clifford circuits (Fig. 1b) by generating a new sequence of gates from a target circuit. The generated sequence of Clifford gates will have the same symplectic matrix as the one associated to the target circuit.

A. Modeling the problem of symplectic matrices The search space of our problem, represented by the set of symplectic matrices, is explored through a tree-based approach. For a given problem dimension n (corresponding to the number of qubits), given a target Clifford circuit C represented by its symplectic matrix MC ∈ Sp(2n, F2 ), and possibly a connectivity map M, our aim is to determine a sequence of Clifford gates equivalent to C. To this end, we construct a search tree as follows: • The root node represents the identity matrix I2n , corresponding to the empty circuit; • Each node N is labeled by a symplectic matrix M and has one child for each admissible Clifford operation g ∈ {Hi , Si , CNOTij : i, j ∈ {1, . . . , n}} (subject to M). The child node is labeled by the matrix obtained by applying g to M , i.e., by the product of M with the matrix corresponding to g; • The terminal nodes (i.e., the leaves) are labeled by the target symplectic matrix MC . In the unconstrained setting, each node has Θ(n2 ) children due to the possible CNOT operations between pairs of qubits, along with single-qubit gates. In the case of limited connectivity constraints, only a subset of 2-qubit operations is allowed. B. Inverting the representation: from the target to the identity Training an RL agent with the forward representation described in Section IV-A would require providing, at each step k, both the current symplectic matrix Mk (encoding the partial circuit g1 , . . . , gk ) and the fixed target matrix MC . This increases the input dimensionality and, moreover, the target matrix contributes little information during an episode, as it remains constant. To avoid this, we adopt an inverted formulation that embeds the target directly into the state representation. At step k, the observation is defined as MC Mk−1 , where Mk−1 is the inverse of the current symplectic matrix over F2 , corresponding to the inverse circuit. Under this representation, synthesizing the target Clifford circuit is equivalent to reaching the identity: MC MC−1 = I2n . Hence, each episode begins in the state MC , and the agent’s task is to reach the identity matrix. This turns the problem into a goal-reaching task with a fixed terminal state and allows us to provide a single observation matrix to the model, rather than a pair (Mk , MC ).

a) Selection

b) Expansion

c) Simulation

d) Backpropagation

H(1)

S(2)

H(2)

CNOT(1,2)

H(3)

H(2), CNOT(3,2), S(1), . . ., H(1) Reward Computation

Fig. 2: Overview of the Monte Carlo Tree Search (MCTS) phases for Clifford circuit synthesis. The search space is explored by iteratively executing four distinct stages: (a) Selection: The tree is traversed from the root (representing the target symplectic matrix C) to a leaf node. Actions, corresponding to Clifford gates H, S, and CNOT, are chosen by balancing exploration and exploitation using the UCT formula. (b) Expansion: When reaching a leaf node, the tree is expanded by the addition of one or more child nodes, each representing the state resulting from a possible Clifford operation. (c) Simulation: A rollout is performed from the newly expanded node based on the policy network. A sequence of gates is sampled until a terminal state is reached, at which point the evaluation of the value network is computed based on the proximity to the identity matrix. (d) Backpropagation: The reward obtained during simulation is propagated upward to the root, updating the value estimates and visit counts for all nodes along the selected path to refine future selection steps.

When a gate gt is applied in the forward construction of the circuit, the corresponding update in the inverted representation must use the adjoint action. Since Mt = Mgt Mt−1

=⇒

−1 Mt−1 = Mt−1 Mg † , t

the state transition in the inverted formulation becomes   −1 −1 MC Mt−1 −→ MC Mt−1 Mg † . t

Thus, although the agent selects forward Clifford operations, the evolution of the internal representation proceeds by rightmultiplication with the corresponding symplectic matrices, consistently reflecting the reversed dynamics. C. Monte Carlo Tree Search Framework We adopt a Monte Carlo Tree Search [40] (MCTS) strategy to efficiently explore the space of symplectic matrices associated with Clifford circuits (see Fig. 2). The procedure is structured into four main phases: 1) Selection: Starting from the root node corresponding to the target symplectic matrix MC , the tree is traversed by iteratively selecting actions (i.e., Clifford gates in {H, S, CNOT}) according to a tree policy. In particular, we adopt the Upper Confidence Bound for Trees (UCT) criterion [43], which selects the action a maximizing s log N (s) , (5) UCT(a) = Q(s, a) + c N (s, a) where Q(s, a) is the estimated value of taking action a in state s, N (s) is the visit count of node s, N (s, a) is the number of times action a has been selected from s,

and c is an exploration constant. This criterion balances exploration of less-visited actions and exploitation of high-value ones; 2) Expansion: When a non-terminal node with unexplored actions is reached, the tree is expanded by applying a new admissible Clifford operation, thus generating a new child node. A node is terminal if it corresponds to the identity matrix or if other stopping criteria are met (e.g., maximum depth). In the presence of connectivity constraints, only allowed CNOT operations are considered; 3) Simulation: From the expanded node, a rollout is performed by sampling a sequence of Clifford gates according to the policy network until a terminal node is reached. The resulting trajectory is then processed by the value function to estimate the quality of the new node; 4) Backpropagation: The outcome of the simulation is propagated back along the selected path, updating visit counts and value estimates for each node involved in the traversal. D. Training Details The training consists of constructing a different random target matrix for each episode, and asking the model to “reach” the identity matrix starting from the inverse of the target with the fewest amount of moves. Each “move”, corresponding to a step in the environment, represents the application of a feasible gate to the current circuit. Feasible gates are H, S, and CNOTs, possibly with constraints based on topology connectivity. An episode finishes after reaching the identity,

or when the agent perform nmax moves without reaching the identity. We adopt a naive reward function √ to guide the learning process. At each step a penalty of −1/ n is applied to limit long sequences and a terminal reward of +n is assigned when reaching the identity matrix. This “non-informed” strategy is fundamental in our approach: without relying on problemspecific heuristics, the model itself naturally learns to find shorter decompositions. In particular, the training objective implicitly minimizes the total number of applied gates, which also implies a reduction of CNOTs. Note that different rewards could be used to minimize different target functions: for example, we can select a higher penalty to reduce the CNOT count. We employ a linear curriculum learning strategy [44] based on the (expected) difficulty of the instances. In practice, we generate each target symplectic matrix by selecting random k Clifford gates, where k is parameter we can tune during training. More in detail, we divide our training in tranches. Starting from k = 1, we train our model on a tranche of difficulty k. At the end of the tranche, we increase k if the model reached a solving rate of at least 95%, i.e., the model is able to correctly reproduce most matrices. We stop the training after the max difficulty of kmax = 4n2 is reached. E. Inference Once the model has been trained to synthesize symplectic matrices of size 2n × 2n, optionally subject to hardware connectivity constraints, it can be deployed for inference. Specifically, given a target Clifford circuit Ctar characterized by a symplectic matrix Mtar , our model generates a sequence of gates forming a synthetic circuit Csyn that yields the identical symplectic matrix. Consequently, Mtar = Msyn , which establishes that the target and synthetic circuits are equivalent up to a Pauli operator (i.e., Ctar ≡ P Csyn for a pauli P ). The complete inference procedure for a given target circuit proceeds as follows: (i) efficiently compute its target symplectic matrix Mtar ; (ii) query the trained model to synthesize a gate sequence corresponding to this matrix; (iii) efficiently compute the phase discrepancy—namely, the signs of the stabilizers and destabilizers—between the target and synthetic circuits; and (iv) apply the appropriate X and Z gates to correct the phase, yielding a fully equivalent circuit. A visual overview of this pipeline is provided in Fig. 1b. F. Applications We identify three primary applications where our model can be efficiently deployed: Clifford optimization (Fig. 1c, top), Clifford transpilation (Fig. 1c, middle), and as a subroutine within a standard logical synthesis pipeline (Fig. 1c, bottom). These settings are described below and are experimentally demonstrated in Sections V-A, V-B, and V-C, respectively. 1) Optimization: A direct application of our framework is Clifford circuit optimization. Given a target Clifford circuit, the objective is to find an equivalent representation

that minimizes the total number of two-qubit gates. More broadly, the model can be tailored during training to minimize alternative target metrics, such as overall circuit depth. Beyond full-circuit synthesis, AlphaClifford can also be employed as a peephole optimizer [45] for Clifford circuits involving a larger number of qubits. Starting, for example, from a circuit synthesized using the Aaronson–Gottesman algorithm, one can extract contiguous subcircuits whose support contains at most n qubits, resynthesize each block using the corresponding n-qubit AlphaClifford model, and replace the original block whenever the selected cost is reduced. By iteratively applying this procedure, models trained on relatively small problem sizes can be used to optimize substantially larger circuits, although the resulting improvements are local and do not imply global optimality. 2) Transpilation: We further evaluate our approach on the task of quantum circuit transpilation. Given n qubits and a hardware connectivity map—represented as a graph where nodes correspond to physical qubits and edges denote allowable direct interactions—the goal of transpilation is to transform a logical circuit into an equivalent physical circuit that strictly adheres to these connectivity constraints. This is usually achieved by mapping logical qubits to physical qubits and inserting additional gates (e.g., SWAP routing) to ensure all two-qubit operations occur between adjacent nodes. Addressing this task is critical for near-term quantum execution, as many hardware platforms (such as superconducting architectures [46]) only permit multi-qubit operations between physically coupled qubits. Similar to circuit optimization, the objective is to find a valid transpilation that minimizes a specific cost function, typically the two-qubit gate count or the overall circuit depth. Furthermore, for realistic hardware deployments, the cost function can be expanded to incorporate device-specific characteristics, such as penalizing the use of qubits or couplers with high error rates. To accomplish this within our framework, the model’s action space during training is constrained to the specific connectivity map of the target hardware connectivity map. 3) Optimizing Logical Synthesis Pipeline: A crucial task in fault-tolerant quantum computing is logical synthesis, which involves approximating a target unitary using a discrete, universal gate set such as Clifford+T [8]. Unlike pure Clifford synthesis, optimal exact synthesis over universal gate sets is a notoriously difficult problem, with worst-case computational complexity scaling exponentially with respect to the number of qubits [47], [48]. To address this limitation, compilers typically employ a “peephole” synthesis strategy, decomposing the target circuit into much smaller, tractable sub-blocks (typically acting on two or three qubits) [33]. A standard logical synthesis pipeline generally operates in successive stages. First, a pre-processing step can applied to the logical circuit. This may involve decomposing large multi-qubit gates into smaller two- or three-qubit instances (e.g., via recursive Cartan decomposition [49], [50]) or performing structural pre-synthesis edits to make the circuit more amenable to compilation [37]. Next, a local synthesis

algorithm compiles each of these individual sub-blocks into a Clifford+T representation. Our framework can be integrated into the final stage of this pipeline as a post-synthesis optimizer. Once the full circuit has been compiled into Clifford+T, we can extract the largest contiguous blocks of purely Clifford gates. Our model can then be applied directly to these extracted Clifford sub-circuits to find equivalent representations that minimize the total gate count, effectively compressing the circuit without altering the expensive T-gate layout. While our experimental evaluation in Section V-C demonstrates this capability on the relatively small Clifford blocks generated by standard peephole synthesis, our approach can be applied more in general in any kind of compilation task involving large blocks of consecutive Clifford gates. V. E XPERIMENTAL R ESULTS In the following, we describe the experimental evaluations and the obtained results for the tasks of Clifford Optimization (Section V-A), Clifford Transpilation (Section V-B), and optimization in the logical synthesis pipeline (Section V-C). Both policy and value networks share the same architecture, i.e., a 12-layer fully connected network with 256 hidden units per layer. We structured the net using 4 residual blocks with skip connections every three layers. We trained a different model for each number of qubits n, and for each selected connectivity map for the transpilation task. The training was executed in tranches of different complexity (computed as the number of generating gates) as described in Section IV-D, and increasing once the solving threshold of 95% is achieved for the tranche, up to a complexity of 4n2 . A. Clifford Optimization As a first task, we evaluate the ability of our model to efficiently synthesize sufficiently complex Clifford circuits. This problem can be reformulated as a Clifford optimization task: we start from a random Clifford circuit generated by qiskit [51], and we synthesize an equivalent circuit with gates from {H, S, CNOT}. For n qubits with n ∈ {3, 4, 5, 6, 7}, we evaluate our model on 100 Clifford circuits involving up to 4n2 gates. These experiments evaluate full synthesis, in which the complete target circuit is provided to a single model. Note that, as discussed in Section IV-F, the same models can be applied as local peephole optimizers to blocks of larger Clifford circuits. To evaluate our approach, we consider both the average total number of gates, and the number of two-qubit gates (in our case, CNOTs) required to synthesize a circuit. We evaluate our model both one shot, and after 10 repetitions, i.e. we sample our model 10 times, and select the circuit with lowest amount of gates. We denote the latter as AlphaClifford10 . Our results are reported in Table I. As comparison, we consider first the well-known AaronsonGottesman algorithm [28], as implemented in qiskit [51]), and then three different heuristic models (A∗ , greedy, and Volanto [32]), as provided in [31]. These three methods

provide a decomposition in a block of SWAP gates, followed by a block of one and two qubit transvection gates [52]. Given a n-qubit Pauli operator P , the corresponding transvection can be defined as   iπ (In − P ) . (6) TP := exp 4 Note that by allowing a richer gate set provides an unfair comparison versus our approach that is constrained to the less expressive set {H, S, CNOT}. Nevertheless, we include this evaluation, where the SWAP layer is first decomposed in three CNOTs. For completeness, we also consider the CNOT count obtained by the same three methods when the obtained circuits are decomposed in {H, S, CNOT} by the default transpiler provided by qiskit. Finally, we report the same metrics obtained by the qiskit greedy method, and by the well-known stim software for stabilizer simulation [53].

Problem Size (n) Approach

3

4

5

6

7

Total Gates Aaronson-Gottesman Qiskit greedy Stim

19.99 13.57 21.27

25.89 23.03 36.28

38.05 34.75 54.70

51.37 47.77 72.82

65.61 62.18 96.39

A* (with transv.) Greedy (with transv.) Volanto (with transv.)

12.97 13.03 12.95

19.56 19.40 19.93

26.54 27.42 28.65

35.04 36.08 38.12

43.15 45.61 48.14

A* (H, S, CNOT) Greedy (H, S, CNOT) Volanto (H, S, CNOT)

19.49 19.17 20.26

33.47 33.21 37.30

49.90 51.44 59.25

68.33 72.16 87.19

89.47 98.29 117.57

AlphaClifford AlphaClifford10

8.85 8.78

13.90 13.39

20.66 19.49

29.56 27.11

40.05 36.75

2-Qubit Gates Aaronson-Gottesman Qiskit greedy Stim

3.65 4.35 7.29

10.41 8.01 13.20

16.17 13.01 20.32

22.43 18.79 29.49

28.59 24.95 40.35

A* (with transv.) Greedy (with transv.) Volanto (with transv.)

6.34 6.28 6.38

10.63 10.60 11.16

15.72 16.55 17.36

21.39 22.71 24.38

27.32 29.86 32.62

A* (H, S, CNOT) Greedy (H, S, CNOT) Volanto (H, S, CNOT)

8.84 8.78 9.19

15.38 15.39 17.04

23.10 24.39 27.37

31.89 34.19 39.85

41.59 46.28 54.23

AlphaClifford AlphaClifford10

4.25 4.06

7.50 6.96

11.85 10.98

17.47 15.82

25.53 23.06

TABLE I: Average number of total and 2-Qubit gates for different optimization methods over varying problem sizes. Best results for each n are highlighted in bold. We observe that our model achieves the lowest amount of total gates, and two qubit gates, in most cases. Note that all methods were able to synthesize correctly each instance, with the exception of Greedy method that was not able to synthesize a few instances of larger dimensions (in this case, the average reported in Table I is considered only on the solved instances). We stress that the advantage compared to the methods in [31] is obtained with a less expressive gate. We expect our

method to obtain even better performance when allowing more expressive gate sets. B. Transpilation To evaluate our model, for each number of qubits and connectivity map, we generate a random Clifford circuit without connectivity constraints. We then use a model trained on the specific connectivity map to generate an equivalent circuit by using the gate set {H, S, CNOT}, where a CNOT can be selected only between pairs of qubits allowed by the connectivity map. Following the procedure in [26], we select 6 connectivity maps from 3 to 6 qubits (see Fig. 3 for additional information). As before, we provide total gate count, and CNOT count. As a comparison, we evaluate the RL-based Clifford transpiler by qiskit, available at [54]. Both methods are sampled once and 10 times, to take into account the stochasticity or RLbased approaches. Results are provided in Table II. We observe that in general, our model provides consistently a lower total gate counts than the other approach. However, it also obtains a slightly higher number of CNOTs, suggesting that a reward function tailored on the number of two-qubit gates instead of total gates could be beneficial in this specific setting. 2

0

0 1

1 1

VI. C ONCLUSION 2

2 0

2

3

3

(a) 3L

4

(b) 4L

(c) 5L 4

3 1

5 4

3

1

1 0

(d) 4T

2

0

(e) 5T

Then, we decompose each single qubit unitary in up to three Rz (θ) rotations (with additional X and H gates). Each rotation is then decomposed in {H, S, T } with the GRIDSYNTH algorithm [55] with a tolerance of ε = 0.01; • Finally, we search for blocks of adjacent Clifford circuits. For each block of at least 2 qubits, we use AlphaClifford to synthesize an optimized version. In addition, we evaluate the same pipeline with the use of Q-P RE S YN [37] to optimize the number of T gates with a sequence of 2 qubit merges. In particular, we apply a greedy optimizer to evaluate the largest sequence of gates that can be merged together, with the aim of reducing the number of resulting T gates after applying the KAK decomposition followed by GRIDSYNTH. In Table III we present the Clifford gate reduction, with the default qiskit transpiler as a comparison. Note that in this specific setting, due to the particular structure of the Clifford circuits (that are already optimal in the number of CNOT gates), the algorithms Aaronson-Gottesman and the ones from [31] did not obtain any reduction in total number of gates. Finally, note that the considered pipeline applied to random circuits leads to mostly 2 and 3 qubit Clifford blocks, therefore allowing for a small reduction of gates. We expect different choices of logical synthesis algorithms and different circuit families to provide higher reductions. •

2

3

0

(f) 6T

Fig. 3: Hardware connectivity maps utilized for benchmarking: Line graphs (a-c) and T-shape graphs (d-f). Vertices represent physical qubits and edges represent available coupling map connections. C. Full Logical synthesis pipeline Finally, we evaluate our proposed method as a component of a logical synthesis pipeline. To do so, we first generate 10 random circuits for each number of qubits n ∈ {5, 10, 15, 20, 25}. Following the approach in [37], we consider the pipeline: • Starting from the representation of the initial circuit, we decompose each 2 qubit gates in a block of CNOTs and single qubit gates with the KAK decomposition [49];

In this work, we introduced AlphaClifford, a novel modelbased reinforcement learning framework designed to address the complex combinatorial challenges of Clifford circuit synthesis and transpilation. By formulating the compilation process as a Monte Carlo Tree Search over the algebraic space of symplectic matrices, AlphaClifford consistently discovers highly optimized gate sequences. Our experimental evaluations demonstrate that AlphaClifford achieves superior or comparable results to state-of-theart methods across a variety of settings. For unconstrained optimization, it successfully minimizes both total and twoqubit gate counts compared to standard heuristics, even when restricted to a less expressive gate set. Furthermore, we showed its adaptability to hardware-constrained transpilation and its practical utility as a post-synthesis optimizer within a logical synthesis pipeline. Notably, these results were obtained using a single base architecture and a naive reward function, underscoring the generality and robustness of our technique. Ultimately, these results highlight the potential of modelbased RL to transcend the limitations of traditional heuristicdriven compilers, advancing the trajectory established by frameworks like AlphaTensor [19] and AlphaCNOT [27]. As quantum hardware continues to scale toward the era of quantum utility, computationally intelligent approaches like AlphaClifford will be critical for bridging the gap between high-level logical algorithms and the strict physical constraints of near-term and future fault-tolerant quantum devices. We highlight several promising directions for future work. First, extending the action space to include more expres-

L Maps 3L

T Maps

4L

5L

4T

5T

6T

Approach

Tot.

CNOT

Tot.

CNOT

Tot.

CNOT

Tot.

CNOT

Tot.

CNOT

Tot.

CNOT

RL-Qiskit1 RL-Qiskit10

14.52 12.19

4.91 4.60

26.80 22.90

10.51 9.54

36.95 33.31

16.78 16.08

26.38 21.58

9.60 8.43

33.63 30.92

15.15 14.29

50.85 46.11

24.41 22.74

AlphaClifford1 AlphaClifford10

9.83 9.81

5.15 4.99

17.49 17.08

10.66 10.08

29.07 27.58

18.45 17.31

16.16 15.76

9.51 8.96

26.27 25.04

16.82 15.56

42.35 38.84

27.49 25.10

TABLE II: Performance of RL-Qiskit [54] and AlphaClifford for the transpilation task. Results report average total (Tot.) and CNOT gate counts for L and T connectivity maps. Best values for metric are reported in bold. Initial Compiled

Qiskit Transpile

n

Clifford (k)

T-count (k)

5 10 15 20 25

1.24 5.17 10.27 20.26 29.59

0.76 3.14 6.23 12.28 17.92

5 10 15 20 25

1.09 4.90 9.98 19.77 29.18

0.66 2.97 6.06 11.98 17.66

Clifford (k)

%red

AlphaClifford Clifford (k)

%red

0.36 0.13 0.09 0.14 0.14

1.21 5.05 10.01 19.76 28.88

2.44 2.39 2.53 2.50 2.43

0.35 0.17 0.15 0.12 0.20

1.06 4.78 9.72 19.28 28.45

2.75 2.46 2.57 2.50 2.49

Without Pre-compilation 1.23 5.16 10.26 20.24 29.55 With Pre-compilation 1.08 4.90 9.97 19.75 29.12

TABLE III: Clifford synthesis performance: comparison of Clifford gate counts (in thousands) and reduction percentages relative to the original synthesized circuit. Results are grouped by whether pre-synthesis [37] was applied.

sive operations, such as transvections, could further enhance compilation efficiency. Second, while our generalized reward function successfully minimized total gate counts, designing tailored reward structures—such as heavily penalizing twoqubit gates to improve specific transpilation connectivity maps or incorporating error-aware routing—could yield even better hardware-specific solutions. Finally, a further direction is to investigate systematic block-selection and iterative peephole strategies for applying the models developed here to largescale Clifford circuits. VII. ACKNOWLEDGEMENTS DLB thanks Gianluca Macrı̀ for his support in preparing the figures and diagrams of this work. JC is supported by FSE/FVG PhD Grant on “Computer Science and Artificial Intelligence” (CUP G23C25000620008). This work has been partially supported by INdAM-GNCS project Algebra lineare quantistica, state preparation e compilazione di circuiti quantistici (CUP E53C25002010001) and by the regional project QUASAR-FVG Calcolo e simulazione quantistica: sviluppo, applicazioni e ricerca in Friuli Venezia Giulia (CUP G23C25001510002). R EFERENCES [1] Y. Kim, A. Eddins, S. Anand, K. X. Wei, E. Van Den Berg, S. Rosenblatt, H. Nayfeh, Y. Wu, M. Zaletel, K. Temme, and A. Kandala, “Evidence for the utility of quantum computing before fault tolerance,” Nature, vol. 618, no. 7965, pp. 500–505, Jun. 2023.

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