ABSTRACT
Abstract
Methods, apparatus, systems, and articles of manufacture are disclosed for hardware-aware machine learning model training. An example apparatus includes a configuration determiner to determine a hardware configuration of a target hardware platform on which the machine learning model is to be executed, a layer generator to assign sparsity configurations to layers of the machine learning model based on the hardware configuration, and a deployment controller to deploy the machine learning model to the target hardware platform in response to outputs of the machine learning model satisfying respective thresholds, the outputs including a quantity of clock cycles to execute the machine learning model with the layers having the assigned sparsity configurations.
Description
CROSS-REFERENCE TO RELATED APPLICATION
This application is a continuation of (and claims the benefit of priority to) U.S. patent application Ser. No. 17/013,258, filed Sep. 4, 2020, titled, âMETHODS AND APPARATUS FOR HARDWARE-AWARE MACHINE LEARNING MODEL TRAINING,â which is incorporated by reference in its entirety for all purposes.
FIELD OF THE DISCLOSURE
This disclosure relates generally to artificial intelligence and, more particularly, to methods and apparatus for hardware-aware machine learning model training.
BACKGROUND
Machine learning models, such as neural networks, are useful tools that have demonstrated their value solving complex problems regarding pattern recognition, natural language processing, automatic speech recognition, etc. Neural networks operate, for example, using artificial neurons arranged into layers that process data from an input layer to an output layer, applying weighting values to the data during the processing of the data. Such weighting values are determined during a training process.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic illustration of an example computing system including an example model training controller.
FIG. 2 is a block diagram of an example implementation of the example model training controller of FIG. 1 .
FIG. 3 is a block diagram of the example model training controller of FIGS. 1 and/or 2 to train a machine learning model.
FIG. 4 is another block diagram of the example model training controller of FIGS. 1 and/or 2 to train a machine learning model.
FIG. 5 is yet another block diagram of the example model training controller of FIGS. 1 and/or 2 to train a machine learning model.
FIG. 6 A depicts a first table of first example output data from a first example machine learning model trained by the example model training controller of FIGS. 1 and/or 2 .
FIG. 6 B depicts a second table of second example output data from the first example machine learning model not trained by the example model training controller of FIGS. 1 and/or 2 .
FIG. 7 A depicts a third table of third example output data from a second example machine learning model trained by the example model training controller of FIGS. 1 and/or 2 .
FIG. 7 B depicts a fourth table of fourth example output data from the second example machine learning model not trained by the example model training controller of FIGS. 1 and/or 2 .
FIG. 8 A depicts a fifth table of fifth example output data from a third example machine learning model trained by the example model training controller of FIGS. 1 and/or 2 .
FIG. 8 B depicts a sixth table of sixth example output data from the third example machine learning model not trained by the example model training controller of FIGS. 1 and/or 2 .
FIG. 9 A is a first example graph based on the first example output data of FIG. 6 A and the second example output data of FIG. 6 B .
FIG. 9 B is a second example graph based on the third example output data of FIG. 7 A and the fourth example output data of FIG. 7 B .
FIG. 9 C is a third example graph based on the fifth example output data of FIG. 8 A and the sixth example output data of FIG. 8 B .
FIG. 10 A is a first graph of example activation sparsity percentages with respect to example layer indices.
FIG. 10 B is a second graph of example sparsity percentages with respect to example layer indices for an example machine learning model trained by the example model training controller of FIGS. 1 and/or 2 .
FIG. 10 C is a third graph of example sparsity percentages with respect to example layer indices for an example machine learning model not trained by the example model training controller of FIGS. 1 and/or 2 .
FIG. 11 depicts an example hardware configuration that may be used by the example model training controller of FIGS. 1 and/or 2 to train an example machine learning model.
FIG. 12 is a flowchart representative of example machine readable instructions that may be executed to implement the example model training controller of FIGS. 1 and/or 2 to train a machine learning model based on a configuration of a target hardware platform.
FIG. 13 is another flowchart representative of example machine readable instructions that may be executed to implement the example model training controller of FIGS. 1 and/or 2 to train a machine learning model based on a configuration of a target hardware platform.
FIG. 14 is a block diagram of an example processing platform structured to execute the example machine readable instructions of FIGS. 12 and/or 13 to implement the example model training controller of FIGS. 1 and/or 2 .
FIG. 15 is a block diagram of an example software distribution platform to distribute software (e.g., software corresponding to the example machine readable instructions of FIGS. 12 and/or 13 ) to client devices such as consumers (e.g., for license, sale and/or use), retailers (e.g., for sale, re-sale, license, and/or sub-license), and/or original equipment manufacturers (OEMs) (e.g., for inclusion in products to be distributed to, for example, retailers and/or to direct buy customers).
DETAILED DESCRIPTION
The figures are not to scale. In general, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts.
Unless specifically stated otherwise, descriptors such as âfirst,â âsecond,â âthird,â etc., are used herein without imputing or otherwise indicating any meaning of priority, physical order, arrangement in a list, and/or ordering in any way, but are merely used as labels and/or arbitrary names to distinguish elements for ease of understanding the disclosed examples. In some examples, the descriptor âfirstâ may be used to refer to an element in the detailed description, while the same element may be referred to in a claim with a different descriptor such as âsecondâ or âthird.â In such instances, it should be understood that such descriptors are used merely for identifying those elements distinctly that might, for example, otherwise share a same name.
Artificial intelligence (AI), including machine learning (ML), deep learning (DL), and/or other artificial machine-driven logic, enables machines (e.g., computers, logic circuits, etc.) to use a model to process input data to generate an output based on patterns and/or associations previously learned by the model via a training process. For instance, the model may be trained with data to recognize patterns and/or associations and follow such patterns and/or associations when processing input data such that other input(s) result in output(s) consistent with the recognized patterns and/or associations.
Many different types of machine learning models and/or machine learning architectures exist. In examples disclosed herein, a neural network (e.g., a convolution neural network, a deep neural network, a graph neural network, etc.) model is used. In general, machine learning models/architectures that are suitable to use in the example approaches disclosed herein include convolution neural networks. However, other types of machine learning models could additionally or alternatively be used such as artificial neural networks, two-layer ( 2 -layer) radial basis neural networks (RBN), learning vector quantization (LVQ) classification neural networks, etc.
In general, implementing a ML/AI system involves at least two phases, a learning/training phase and an inference phase. In the learning/training phase, a training algorithm is used to train a model to operate in accordance with patterns and/or associations based on, for example, training data. In general, the model includes internal parameters that guide how input data is transformed into output data, such as through a series of nodes and connections within the model to transform input data into output data. Additionally, hyperparameters are used as part of the training process to control how the learning is performed (e.g., a learning rate, a number of layers to be used in the machine learning model, etc.). Hyperparameters are defined to be training parameters that are determined prior to initiating the training process.
Different types of training may be performed based on the type of ML/AI model and/or the expected output. For example, reinforcement learning includes a machine, an agent, etc., interacting with its environment, performing actions, and learning by a trial-and-error technique. In other examples, supervised training uses inputs and corresponding expected (e.g., labeled) outputs to select parameters (e.g., by iterating over combinations of select parameters) for the ML/AI model that reduce model error. As used herein, labelling refers to an expected output of the machine learning model (e.g., a classification, an expected output value, etc.) Alternatively, unsupervised training (e.g., used in deep learning, a subset of machine learning, etc.) involves inferring patterns from inputs to select parameters for the ML/AI model (e.g., without the benefit of expected (e.g., labeled) outputs).
In examples disclosed herein, ML/AI models are trained using reinforcement learning. However, any other training algorithm may additionally or alternatively be used. In some examples disclosed herein, training is performed until the level of error is no longer reducing and/or otherwise satisfies a threshold (e.g., an accuracy threshold, a training threshold, etc.). In some examples disclosed herein, training is performed until a number or quantity of cycles (e.g., clock cycles, instruction cycles, processor cycles, etc.) to execute a trained machine learning model or portion(s) thereof (e.g., one or more layers of the trained machine learning model) satisfies a threshold (e.g., a cycle threshold, a clock cycle threshold, an instruction cycle threshold, a processor cycle threshold, a training threshold, etc.). In examples disclosed herein, training can be performed locally on a computing system and/or remotely at an external computing system (e.g., a central facility, one or more servers, etc.) communicatively coupled to the computing system. Training is performed using hyperparameters that control how the learning is performed (e.g., a learning rate, a number of layers to be used in the machine learning model, etc.). In examples disclosed herein, hyperparameters that control model performance and training speed are the learning rate, a number of Epochs, a topology of the neural network, a size of the neural network, and/or regularization parameter(s). Such hyperparameters are selected by, for example, trial and error to reach an optimal model performance. In some examples re-training may be performed. Such re-training may be performed in response to override(s) by a user.
Training is performed using training data. In examples disclosed herein, the training data originates from a database (e.g., an open-source training data source, a publicly available training data source, an image database, etc.). In some examples disclosed herein, the training data is labeled when supervised training is used. Labeling is applied to the training data manually by a user or by an automated data pre-processing system. In some examples, the training data is sub-divided. For example, the training data can be sub-divided into a first portion of data for training the model and a second portion of data for validating the model. In other examples, the training data can be sub-divided into a first portion of data for training the model and a second portion of data for fine-tuning and/or otherwise adjusting the model after the model training.
Once training is complete, the model is deployed for use as an executable construct that processes an input and provides an output based on the network of nodes and connections defined in the model. The model is stored in memory of the computing system or in a database of a remote computing system. The model may then be executed by the computing system or a different computing system.
Once trained, the deployed model may be operated in an inference phase to process data. In the inference phase, data to be analyzed (e.g., live data) is input to the model, and the model executes to create an output. This inference phase can be thought of as the AI âthinkingâ to generate the output based on what it learned from the training (e.g., by executing the model to apply the learned patterns and/or associations to the live data). In some examples, input data undergoes pre-processing before being used as an input to the ma
CROSS-REFERENCE TO RELATED APPLICATION
This application is a continuation of (and claims the benefit of priority to) U.S. patent application Ser. No. 17/013,258, filed Sep. 4, 2020, titled, âMETHODS AND APPARATUS FOR HARDWARE-AWARE MACHINE LEARNING MODEL TRAINING,â which is incorporated by reference in its entirety for all purposes.
FIELD OF THE DISCLOSURE
This disclosure relates generally to artificial intelligence and, more particularly, to methods and apparatus for hardware-aware machine learning model training.
BACKGROUND
Machine learning models, such as neural networks, are useful tools that have demonstrated their value solving complex problems regarding pattern recognition, natural language processing, automatic speech recognition, etc. Neural networks operate, for example, using artificial neurons arranged into layers that process data from an input layer to an output layer, applying weighting values to the data during the processing of the data. Such weighting values are determined during a training process.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic illustration of an example computing system including an example model training controller.
FIG. 2 is a block diagram of an example implementation of the example model training controller of FIG. 1 .
FIG. 3 is a block diagram of the example model training controller of FIGS. 1 and/or 2 to train a machine learning model.
FIG. 4 is another block diagram of the example model training controller of FIGS. 1 and/or 2 to train a machine learning model.
FIG. 5 is yet another block diagram of the example model training controller of FIGS. 1 and/or 2 to train a machine learning model.
FIG. 6 A depicts a first table of first example output data from a first example machine learning model trained by the example model training controller of FIGS. 1 and/or 2 .
FIG. 6 B depicts a second table of second example output data from the first example machine learning model not trained by the example model training controller of FIGS. 1 and/or 2 .
FIG. 7 A depicts a third table of third example output data from a second example machine learning model trained by the example model training controller of FIGS. 1 and/or 2 .
FIG. 7 B depicts a fourth table of fourth example output data from the second example machine learning model not trained by the example model training controller of FIGS. 1 and/or 2 .
FIG. 8 A depicts a fifth table of fifth example output data from a third example machine learning model trained by the example model training controller of FIGS. 1 and/or 2 .
FIG. 8 B depicts a sixth table of sixth example output data from the third example machine learning model not trained by the example model training controller of FIGS. 1 and/or 2 .
FIG. 9 A is a first example graph based on the first example output data of FIG. 6 A and the second example output data of FIG. 6 B .
FIG. 9 B is a second example graph based on the third example output data of FIG. 7 A and the fourth example output data of FIG. 7 B .
FIG. 9 C is a third example graph based on the fifth example output data of FIG. 8 A and the sixth example output data of FIG. 8 B .
FIG. 10 A is a first graph of example activation sparsity percentages with respect to example layer indices.
FIG. 10 B is a second graph of example sparsity percentages with respect to example layer indices for an example machine learning model trained by the example model training controller of FIGS. 1 and/or 2 .
FIG. 10 C is a third graph of example sparsity percentages with respect to example layer indices for an example machine learning model not trained by the example model training controller of FIGS. 1 and/or 2 .
FIG. 11 depicts an example hardware configuration that may be used by the example model training controller of FIGS. 1 and/or 2 to train an example machine learning model.
FIG. 12 is a flowchart representative of example machine readable instructions that may be executed to implement the example model training controller of FIGS. 1 and/or 2 to train a machine learning model based on a configuration of a target hardware platform.
FIG. 13 is another flowchart representative of example machine readable instructions that may be executed to implement the example model training controller of FIGS. 1 and/or 2 to train a machine learning model based on a configuration of a target hardware platform.
FIG. 14 is a block diagram of an example processing platform structured to execute the example machine readable instructions of FIGS. 12 and/or 13 to implement the example model training controller of FIGS. 1 and/or 2 .
FIG. 15 is a block diagram of an example software distribution platform to distribute software (e.g., software corresponding to the example machine readable instructions of FIGS. 12 and/or 13 ) to client devices such as consumers (e.g., for license, sale and/or use), retailers (e.g., for sale, re-sale, license, and/or sub-license), and/or original equipment manufacturers (OEMs) (e.g., for inclusion in products to be distributed to, for example, retailers and/or to direct buy customers).
DETAILED DESCRIPTION
The figures are not to scale. In general, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts.
Unless specifically stated otherwise, descriptors such as âfirst,â âsecond,â âthird,â etc., are used herein without imputing or otherwise indicating any meaning of priority, physical order, arrangement in a list, and/or ordering in any way, but are merely used as labels and/or arbitrary names to distinguish elements for ease of understanding the disclosed examples. In some examples, the descriptor âfirstâ may be used to refer to an element in the detailed description, while the same element may be referred to in a claim with a different descriptor such as âsecondâ or âthird.â In such instances, it should be understood that such descriptors are used merely for identifying those elements distinctly that might, for example, otherwise share a same name.
Artificial intelligence (AI), including machine learning (ML), deep learning (DL), and/or other artificial machine-driven logic, enables machines (e.g., computers, logic circuits, etc.) to use a model to process input data to generate an output based on patterns and/or associations previously learned by the model via a training process. For instance, the model may be trained with data to recognize patterns and/or associations and follow such patterns and/or associations when processing input data such that other input(s) result in output(s) consistent with the recognized patterns and/or associations.
Many different types of machine learning models and/or machine learning architectures exist. In examples disclosed herein, a neural network (e.g., a convolution neural network, a deep neural network, a graph neural network, etc.) model is used. In general, machine learning models/architectures that are suitable to use in the example approaches disclosed herein include convolution neural networks. However, other types of machine learning models could additionally or alternatively be used such as artificial neural networks, two-layer ( 2 -layer) radial basis neural networks (RBN), learning vector quantization (LVQ) classification neural networks, etc.
In general, implementing a ML/AI system involves at least two phases, a learning/training phase and an inference phase. In the learning/training phase, a training algorithm is used to train a model to operate in accordance with patterns and/or associations based on, for example, training data. In general, the model includes internal parameters that guide how input data is transformed into output data, such as through a series of nodes and connections within the model to transform input data into output data. Additionally, hyperparameters are used as part of the training process to control how the learning is performed (e.g., a learning rate, a number of layers to be used in the machine learning model, etc.). Hyperparameters are defined to be training parameters that are determined prior to initiating the training process.
Different types of training may be performed based on the type of ML/AI model and/or the expected output. For example, reinforcement learning includes a machine, an agent, etc., interacting with its environment, performing actions, and learning by a trial-and-error technique. In other examples, supervised training uses inputs and corresponding expected (e.g., labeled) outputs to select parameters (e.g., by iterating over combinations of select parameters) for the ML/AI model that reduce model error. As used herein, labelling refers to an expected output of the machine learning model (e.g., a classification, an expected output value, etc.) Alternatively, unsupervised training (e.g., used in deep learning, a subset of machine learning, etc.) involves inferring patterns from inputs to select parameters for the ML/AI model (e.g., without the benefit of expected (e.g., labeled) outputs).
In examples disclosed herein, ML/AI models are trained using reinforcement learning. However, any other training algorithm may additionally or alternatively be used. In some examples disclosed herein, training is performed until the level of error is no longer reducing and/or otherwise satisfies a threshold (e.g., an accuracy threshold, a training threshold, etc.). In some examples disclosed herein, training is performed until a number or quantity of cycles (e.g., clock cycles, instruction cycles, processor cycles, etc.) to execute a trained machine learning model or portion(s) thereof (e.g., one or more layers of the trained machine learning model) satisfies a threshold (e.g., a cycle threshold, a clock cycle threshold, an instruction cycle threshold, a processor cycle threshold, a training threshold, etc.). In examples disclosed herein, training can be performed locally on a computing system and/or remotely at an external computing system (e.g., a central facility, one or more servers, etc.) communicatively coupled to the computing system. Training is performed using hyperparameters that control how the learning is performed (e.g., a learning rate, a number of layers to be used in the machine learning model, etc.). In examples disclosed herein, hyperparameters that control model performance and training speed are the learning rate, a number of Epochs, a topology of the neural network, a size of the neural network, and/or regularization parameter(s). Such hyperparameters are selected by, for example, trial and error to reach an optimal model performance. In some examples re-training may be performed. Such re-training may be performed in response to override(s) by a user.
Training is performed using training data. In examples disclosed herein, the training data originates from a database (e.g., an open-source training data source, a publicly available training data source, an image database, etc.). In some examples disclosed herein, the training data is labeled when supervised training is used. Labeling is applied to the training data manually by a user or by an automated data pre-processing system. In some examples, the training data is sub-divided. For example, the training data can be sub-divided into a first portion of data for training the model and a second portion of data for validating the model. In other examples, the training data can be sub-divided into a first portion of data for training the model and a second portion of data for fine-tuning and/or otherwise adjusting the model after the model training.
Once training is complete, the model is deployed for use as an executable construct that processes an input and provides an output based on the network of nodes and connections defined in the model. The model is stored in memory of the computing system or in a database of a remote computing system. The model may then be executed by the computing system or a different computing system.
Once trained, the deployed model may be operated in an inference phase to process data. In the inference phase, data to be analyzed (e.g., live data) is input to the model, and the model executes to create an output. This inference phase can be thought of as the AI âthinkingâ to generate the output based on what it learned from the training (e.g., by executing the model to apply the learned patterns and/or associations to the live data). In some examples, input data undergoes pre-processing before being used as an input to the machine learning model. Moreover, in some examples, the output data may undergo post-processing after it is generated by the AI model to transform the output into a useful result (e.g., a display of data, an instruction to be executed by a machine, etc.).
In some examples, output of the deployed model may be captured and provided as feedback. By analyzing the feedback, an accuracy of the deployed model can be determined. If the feedback indicates that the accuracy of the deployed model is less than a threshold or other criterion, training of an updated model can be triggered using the feedback and an updated training data set, hyperparameters, etc., to generate an updated, deployed model.
Embedded systems with limited computational power and memory bandwidth lack the hardware resources needed to accelerate the processing of neural networks to pursue state-of-the-art accuracy due to the increasing size of such neural networks. To reduce the size of neural networks, network compression techniques, such as sparsity techniques that exploit the concept of sparsity, may be used. Some of these network compression techniques are rule-based (e.g., rule-based network compression techniques). Such rule-based techniques cannot be generalized for all existing neural networks. For example, some rule-based techniques attempt to sparsify parameters less in early layers (e.g., layers that include useful information of the low-level features) and sparsify parameters more in later layers, or final fully connected layers (e.g., layers that include more parameters). Such rule-based techniques do not consider the dependency between the layers in the neural network and cannot easily transfer from one neural network architecture to another.
Under the current paradigm in machine learning, neural network models are trained using hardware-agnostic techniques. As a result, the building blocks (e.g., functions) and layers are not tuned to the architecture of a target hardware platform on which trained neural network models are to execute. This lack of tuning affects the performance of trained neural network models during the inference. For example, if a model was trained on a graphics processing unit (GPU), then when the model executes with non-GPU architectures (e.g., a vision processing unit (VPU)) and/or accelerators that do not necessarily optimally support GPU operators, the model will not perform at an equivalent level. In such examples, the model is not optimal on other accelerators. For example, a 7Ã7 depth-wise-separable convolution may perform acceptably on a GPU, but such an operation is typically far from optimal on most AI accelerators. In such examples, training the model without consideration of whether the model is to be executed on a target hardware platform of interest, such as a GPU or a different AI accelerator, can lead to varying degrees of accuracy and efficiency of model execution.
Further, hardware-agnostic machine learning training techniques do not take into consideration the hardware performance of a target hardware platform during sparsity generation when executing a network compression technique. Key target criteria for sparsity-based techniques include compression and speed-up. However, models generated by such sparsity-based techniques may have large overall sparsity but perform poorly (e.g., low speed-up) on a target hardware platform. For example, a neural network with large overall sparsity may have suboptimal model execution or performance on the target hardware platform due to architectural factors (e.g., processing, memory, and/or caching architecture factors).
Examples disclosed herein include hardware-aware machine learning model training of models, such as neural network models. In some disclosed examples, an example model training controller applies hardware-aware sparsity to a neural network based on an architecture (e.g., a hardware, software, and/or firmware architecture) of a target hardware platform or portion(s) thereof. In some disclosed examples, the model training controller effectuates reinforcement learning on a neural network to identify sparsity ratios for one or more layers of the neural network. In such disclosed examples, the model training controller identifies the sparsity ratios based on the architecture of the target hardware platform.
Advantageously, the example model training controller can train the neural network to achieve high performance on the target hardware platform with greater sparsity ratios relative to a baseline version of the neural network. Advantageously, the example model training controller can train different types of accelerators, such as a central processing unit (CPU), a GPU, a VPU, etc., with a subset of a training dataset to improve a speed at which to train a neural network and an efficiency of utilizing hardware resources to train the neural network.
FIG. 1 is a schematic illustration of an example computing environment 100 including an example computing system 102 including an example model training controller 104 A-E to effectuate a training and deployment of a machine learning model. The computing system 102 of the example of FIG. 1 includes an example central processing unit (CPU) 106 , a first example acceleration resource (ACCELERATION RESOURCE A) 108 , a second example acceleration resource (ACCELERATION RESOURCE B) 110 , an example general purpose processing resource 112 , an example interface resource 114 , an example bus 116 , an example power source 118 , and an example datastore 120 . The datastore 120 of the example of FIG. 1 includes example hardware configuration(s) (H/W CONFIG(S)) 122 and example machine learning model(s) (ML MODEL(S)) 124 . Further depicted in the example of FIG. 1 is an example user interface 126 , an example network 128 , and example external computing system(s) 130 .
In the illustrated example of FIG. 1 , the computing system 102 is a computing device on which the machine learning model(s) 124 is/are to be executed. In some examples, the computing system 102 is a mobile device, such as a cell or mobile phone (e.g., an Internet-enabled smartphone), a tablet computer (e.g., an Internet-enabled tablet), etc. For example, the computing system 102 can be implemented as a mobile phone having one or more processors (e.g., a CPU, a GPU, a VPU, an AI or neural-network (NN) specific processor, etc.) on a single system-on-a-chip (SoC). In some examples, the computing system 102 is a desktop computer, a laptop computer, a server, etc. For example, the computing system 102 can be implemented as a desktop computer, a laptop computer, a server, etc., having one or more processors (e.g., a CPU, a GPU, a VPU, an AI/NN specific processor, etc.) on a single SoC.
In some examples, the computing system 102 is a system-on-a-chip (SoC) representative of one or more integrated circuits (ICs) (e.g., compact ICs) that incorporate components of a computer or other electronic system in a compact format. For example, the computing system 102 may be implemented with a combination of one or more programmable processors, hardware logic, and/or hardware peripherals and/or interfaces. Additionally or alternatively, the example computing system 102 of FIG. 1 may include memory, input/output (I/O) port(s), and/or secondary storage. For example, the computing system 102 includes the model training controller 104 A-E, the CPU 106 , the first acceleration resource 108 , the second acceleration resource 110 , the general purpose processing resource 112 , the interface resource 114 , the bus 116 , the power source 118 , the datastore 120 , the memory, the I/O port(s), and/or the secondary storage all on the same substrate. In some examples, the computing system 102 includes digital, analog, mixed-signal, radio frequency (RF), or other signal processing functions.
In the illustrated example of FIG. 1 , the first acceleration resource 108 is a graphics processing unit (GPU). For example, the first acceleration resource 108 is a GPU that generates computer graphics, executes general-purpose computing, etc. In some examples, the first acceleration resource 108 processes AI tasks. In such examples, the first acceleration resource 108 can execute and/or otherwise implement a neural network, such as an artificial neural network (ANN), a convolution neural network (CNN), a deep neural network (DNN), a recurrent neural network (RNN), etc.
The second acceleration resource 110 of the example of FIG. 1 is a vision processing unit (VPU). For example, the second acceleration resource 110 can effectuate machine or computer vision computing tasks. In such examples, the second acceleration resource 110 can execute and/or otherwise implement a neural network, such as an ANN, a CNN, a DNN, an RNN, etc.
The general purpose processing resource 112 of the example of FIG. 1 is a programmable processor, such as a CPU or a GPU. In some examples, the general purpose processing resource 112 completes AI tasks. In such examples, the general purpose processing resource 112 can execute and/or otherwise implement a neural network, such as an ANN, a CNN, a DNN, an RNN, etc.
In this example, the CPU 106 , the first acceleration resource 108 , the second acceleration resource 110 , and the general purpose processing resource 112 are target hardware, or target hardware platforms. Alternatively, one or more of the first acceleration resource 108 , the second acceleration resource 110 , and/or the general purpose processing resource 112 may be a different type of hardware such as a digital signal processor (DSP), an application specific integrated circuit (ASIC), a programmable logic device (PLD), and/or a field programmable logic device (FPLD) (e.g., a field-programmable gate array (FPGA)).
In the illustrated example of FIG. 1 , the interface resource 114 is representative of one or more interfaces. For example, the interface resource 114 may be implemented by a communication device (e.g., a network interface card (NIC), a smart NIC, etc.) such as a transmitter, a receiver, a transceiver, a modem, a residential gateway, a wireless access point, and/or a network interface to facilitate exchange of data with external machines (e.g., computing devices of any kind) via the network 128 . In some examples, the communication is effectuated via an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a line-of-site wireless system, a cellular telephone system, etc. For example, the interface resource 114 may be implemented by any type of interface standard, such as a wireless fidelity (Wi-Fi) interface, an Ethernet interface, a universal serial bus (USB), a Bluetooth interface, a near field communication (NFC) interface, and/or a PCI express interface.
The computing system 102 includes the power source 118 to deliver power to resource(s) of the computing system 102 . In the example of FIG. 1 , the power source 118 is a battery. For example, the power source 118 is a limited-energy device, such as a lithium-ion battery or any other chargeable battery or power source. In such examples, the power source 118 is chargeable using a power adapter or converter (e.g., an alternating current (AC) to direct current (DC) power converter), a wall outlet (e.g., a 110V AC wall outlet, a 220V AC wall outlet, etc.), etc.
The computing system 102 of the example of FIG. 1 includes the datastore 120 to record data (e.g., the hardware configuration(s) 122 , the machine learning model(s) 124 , etc.). The datastore 120 of this example may be implemented by a volatile memory (e.g., a Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM), etc.) and/or a non-volatile memory (e.g., flash memory). The datastore 120 may additionally or alternatively be implemented by one or more double data rate (DDR) memories, such as DDR, DDR2, DDR3, DDR4, mobile DDR (mDDR), etc. The datastore 120 may additionally or alternatively be implemented by one or more mass storage devices such as hard disk drive(s), compact disk (CD) drive(s), digital versatile disk (DVD) drive(s), solid-state disk drive(s), etc. While in the illustrated example the datastore 120 is illustrated as a single database, the datastore 120 may be implemented by any number and/or type(s) of databases. Furthermore, the data stored in the datastore 120 may be in any data format such as, for example, binary data, comma delimited data, tab delimited data, structured query language (SQL) structures, etc.
In the illustrated example of FIG. 1 , the datastore 120 , and/or, more generally, the computing system 102 , stores the hardware configuration(s) 122 to be used as model input(s) for training one(s) of the machine learning model(s) 124 . In this example, the hardware configuration(s) 122 include one or more hardware configurations for respective one(s) of the resource(s) of the computing system 102 . For example, the hardware configuration(s) 122 can include a first hardware configuration associated with the CPU 106 , a second hardware configuration associated with the first acceleration resource 108 , a third hardware configuration associated with the second acceleration resource 110 , a fourth hardware configuration associated with the general purpose processing resource 112 , etc.
In the illustrated example of FIG. 1 , the datastore 120 , and/or, more generally, the computing system 102 , stores the machine learning model(s) 124 to facilitate the training, deployment, and/or execution of the machine learning model(s) 124 on the computing system 102 and/or one(s) of the external computing system(s) 130 . In this example, the machine learning model(s) 124 include one or more machine learning models. For example, the machine learning model(s) 124 can include a first neural network model, a second neural network model, etc. In such examples, the first neural network model can be a baseline neural network model, such as a neural network model that has been trained with a conventional machine learning training technique. In some such examples, the second neural network model can be a neural network model trained by the model training controller 104 A-E, which trains the neural network model based on the hardware configuration(s) 122 that corresponds to a target hardware platform (e.g., the CPU 106 , the first acceleration resource 108 , etc.) on which to execute the neural network model.
In the illustrated example of FIG. 1 , the computing system 102 is in communication with the user interface 126 . For example, the user interface 126 is a graphical user interface (GUI), an application display, etc., presented to a user on a display device in circuit with and/or otherwise in communication with the computing system 102 . In such examples, a user controls the computing system 102 , adjusts a machine learning training parameter (e.g., a learning rate, a number of layers to be used in the machine learning model, etc.) to train the machine learning model(s) 124 , etc., via the user interface 126 . Alternatively, the computing system 102 may include the user interface 126 .
In the illustrated example of FIG. 1 , the model training controller 104 A-E, the CPU 106 , the first acceleration resource 108 , the second acceleration resource 110 , the general purpose processing resource 112 , the interface resource 114 , the power source 118 , and the datastore 120 are in communication with the bus 116 . For example, the bus 116 corresponds to, is representative of, and/or otherwise includes at least one of an Inter-Integrated Circuit (I2C) bus, a Serial Peripheral Interface (SPI) bus, or a Peripheral Component Interconnect (PCI) bus.
The network 128 of the example of FIG. 1 is the Internet. However, the network 128 of this example may be implemented using any suitable wired and/or wireless network(s) including, for example, one or more data buses, one or more Local Area Networks (LANs), one or more wireless LANs, one or more cellular networks, one or more private networks, one or more public networks, etc. The network 128 enables the computing system 102 to be in communication with the external computing system(s) 130 .
In the illustrated example of FIG. 1 , the external computing systems 130 are computing devices on which the machine learning model(s) 124 is/are to be executed. In this example, the external computing systems 130 include an example desktop computer 132 , an example mobile device (e.g., a smartphone, an Internet-enabled smartphone, etc.) 134 , an example laptop computer 136 , an example tablet (e.g., a tablet computer, an Internet-enabled tablet computer, etc.) 138 , and an example server 140 . In some examples, fewer or more computing systems than depicted in FIG. 1 may be used. Additionally or alternatively, the external computing systems 130 may include, correspond to, and/or otherwise be representative of any other type of computing device.
In some examples, one or more of the external computing systems 130 execute one(s) of the machine learning model(s) 124 to process a computing workload (e.g., an AI/ML workload). For example, the mobile device 134 can be implemented as a cell or mobile phone having one or more processors (e.g., a CPU, a GPU, a VPU, an AI or neural-network (NN) specific processor, etc.) on a single system-on-a-chip (SoC) to process an AI/ML workload using one(s) of the machine learning model(s) 124 . For example, the desktop computer 132 , the laptop computer 136 , the tablet computer, and/or the server 140 can be implemented as computing device(s) having one or more processors (e.g., a CPU, a GPU, a VPU, an AI/NN specific processor, etc.) on one or more SoCs to process an AI/ML workload using one(s) of the machine learning model(s) 124 . In some examples, the server 140 includes and/or otherwise is representative of one or more servers that can implement a central or data facility, a cloud service (e.g., a public or private cloud provider, a cloud-based repository, etc.), etc., to process AI/ML workload(s) using one(s) of the machine learning model(s) 124 .
In the illustrated example of FIG. 1 , the computing system 102 includes a first model training controller 104 A (e.g., a first instance of the model training controller 104 A-E), a second model training controller 104 B (e.g., a second instance of the model training controller 104 A-E), a third model training controller 104 C (e.g., a third instance of the model training controller 104 A-E), a fourth model training controller 104 D (e.g., a fourth instance of the model training controller 104 A-E), and a fifth model training controller 104 E (e.g., a second instance of the model training controller 104 A-E) (collectively referred to herein as the model training controller 104 A-E unless specified otherwise herein). In the example of FIG. 1 , the first model training controller 104 A is implemented by hardware, software, and/or firmware. For example, the first model training controller 104 A may be implemented by one or more analog or digital circuit(s), logic circuits, programmable processor(s), programmable controller(s), GPU(s), VPU(s), DSP(s), ASIC(s), PLD(s), and/or FPLD(s).
In the illustrated example of FIG. 1 , the second model training controller 104 B is implemented by the CPU 106 , the third model training controller 104 C is implemented by the first acceleration resource 108 , the fourth model training controller 104 D is implemented by the second acceleration resource 110 , and the fifth model training controller 104 E is implemented by the general purpose processing resource 112 . Additionally or alternatively, the first model training controller 104 A, the second model training controller 104 B, the third model training controller 104 C, the fourth model training controller 104 D, the fifth model training controller 104 E, and/or portion(s) thereof, may be virtualized, such as by being implemented using one or more virtual machines, one or more containers, etc. Additionally or alternatively, the first model training controller 104 A, the second model training controller 104 B, the third model training controller 104 C, the fourth model training controller 104 D, and/or the fifth model training controller 104 E may be implemented by a different resource of the computing system 102 , such as the first acceleration resource 108 , the second acceleration resource 110 , etc. Alternatively, the computing system 102 may not include the first model training controller 104 A, the second model training controller 104 B, the third model training controller 104 C, the fourth model training controller 104 D, the fifth model training controller 104 E.
In example operation, the model training controller 104 A-E trains one(s) of the machine learning model(s) 124 based on one(s) of the hardware configuration(s) 122 . For example, the third model training controller 104 C of the first acceleration resource 108 can retrieve a first one of the machine learning model(s) 124 from the datastore 120 , the external computing system(s) 130 via the network 128 , etc. In such examples, the third model training controller 104 C can retrieve a first one of the hardware configuration(s) 122 that corresponds to the first acceleration resource 108 . For example, the first one of the hardware configuration(s) 122 can include at least one of memory configuration information, caching configuration information, or processing configuration information associated with the first acceleration resource 108 .
In example operation, the model training controller 104 A-E assigns sparsity ratios to respective layers of the machine learning model(s) 124 . For example, the third model training controller 104 C can generate a first action including assigning a first sparsity ratio of 70% to a first level, a second action including assigning a second sparsity ratio of 65% to a second level, etc., of the first one of the machine learning model(s) 124 . In such examples, the third model training controller 104 C determines a quantity of cycles (e.g., clock cycles, instruction cycles, processor cycles, etc.) to execute the respective layers using the sparsity ratio assignments.
In example operation, responsive to the sparsity ratio assignments, the model training controller 104 A-E executes the machine learning model(s) 124 using a training dataset or portion thereof. For example, the third model training controller 104 C can execute the first one of the machine learning model(s) 124 to generate an output (e.g., a model output), such as a reward. In such examples, the reward can be an accuracy of the first one of the machine learning model(s) 124 . In some such examples, the third model training controller 104 C can generate a new set of one or more actions to adjust the sparsity ratios for respective layers of the first one of the machine learning model(s) 124 based on the reward (e.g., to maximize the reward).
In some examples, the model training controller 104 A-E deploys the first one of the machine learning model(s) 124 responsive to the reward being maximized and/or otherwise satisfying a threshold, such as a reward threshold, a training threshold, etc. For example, the model training controller 104 A-E can generate and/or otherwise compile the first one of the machine learning model(s) 124 as an executable construct (e.g., an executable file, a machine readable executable, etc.) to be executed on resource(s) of the computing system 102 and/or the external computing system(s) 130 . Advantageously, the first one of the machine learning model(s) 124 has sparsity ratios that are optimized and/or otherwise increases compared to conventional network compression techniques while maintaining state-of-the-art accuracy.
FIG. 2 is a block diagram of an example implementation of the model training controller 104 A-E of FIG. 1 . In some examples, the model training controller 104 A-E trains one or more machine learning models (e.g., neural networks) based on information specific to a target hardware platform or portion(s) thereof. Many different types of machine learning models and/or machine learning architectures exist. In some examples, the model training controller 104 A-E implements reinforcement learning to train CNN models. Using reinforcement learning enables taking actions in an environment to maximize and/or otherwise improve cumulative rewards generated by the environment. Alternatively, the model training controller 104 A-E may train other types of machine learning models such as random forests, decision trees, etc., based on information specific to a target hardware platform.
In the illustrated example of FIG. 2 , the model training controller 104 A-E includes an example communication interface 210 , an example configuration determiner 220 , an example layer generator 230 , an example model training handler 240 , an example fine tuning handler 250 , an example deployment controller 260 , an example datastore 270 , and an example communication bus 280 . In this example, the datastore 270 includes and/or otherwise stores example hardware configuration(s) 272 , an example machine learning model 274 , example training data 276 , an example training output data 278 .
In the illustrated example of FIG. 2 , any of the communication interface 210 , the configuration determiner 220 , the layer generator 230 , the model training handler 240 , the fine tuning handler 250 , the deployment controller 260 , and/or the datastore 270 can communicate (e.g., communicate with each other) via the communication bus 280 . In some examples, the communication bus 280 is implemented using any suitable wired and/or wireless communication. In some examples, the communication bus 280 includes software, machine readable instructions, and/or communication protocols by which information is communicated among the communication interface 210 , the configuration determiner 220 , the layer generator 230 , the model training handler 240 , the fine tuning handler 250 , the deployment controller 260 , and/or the datastore 270 .
In the illustrated example of FIG. 2 , the model training controller 104 A-E includes the communication interface 210 to obtain a hardware configuration, such as the hardware configuration(s) 272 , associated with a target hardware platform on which a machine learning model is to be executed. For example, the communication interface 210 can obtain the hardware configuration(s) 272 from the datastore 120 of FIG. 1 , the external computing system(s) 130 via the network 128 , etc.
In some examples, the communication interface 210 obtains a machine learning model to be trained, such as the machine learning model 274 . For example, the communication interface 210 can obtain the machine learning model 274 from the datastore 120 and/or the external computing system(s) 130 . In some examples, the communication interface 210 obtains a target task (e.g., an action of an off-policy actor-critic algorithm) on which the machine learning model 274 is to operate, as well as one or more training datasets, such as the training data 276 .
In the illustrated example of FIG. 2 , the model training controller 104 A-E includes the configuration determiner 220 to determine hardware configuration information, parameters, etc., based on the hardware configuration(s) 272 . In some examples, the configuration determiner 220 identifies that the hardware configurations(s) 272 include(s) operators (e.g., functions, operations, etc.) that are conditioned for the target hardware platform, kernels that are optimized for the target hardware platform, a latency estimator that is specific to the target hardware platform, etc.
In some examples, the configuration determiner 220 determines that the hardware configuration(s) 272 include(s) at least one of memory configuration information, caching configuration information, or processing configuration information associated with the target hardware platform. For example, the configuration determiner 220 can determine that the hardware configuration(s) 272 specify memory configuration information, such as at least one of a memory type, a read memory bandwidth, a read bus width, a write memory bandwidth, a write bus width, a memory de-rate factor, or a number of memory ports associated with memory of the target hardware platform.
In some examples, the configuration determiner 220 determines that the hardware configuration(s) 272 specifies caching configuration information, such as at least one of a cache size or a cache operating frequency associated with cache memory of the target hardware platform. In some examples, the configuration determiner 220 determines that the hardware configuration(s) 124 specifies processing configuration information, such as at least one of a number of data processing units, a clock frequency, a fabric frequency, an activation precision, or a weight precision associated with one or more processors of the target hardware platform.
In some examples, the configuration determiner 220 implements means for determining a hardware configuration of a target hardware platform on which the machine learning model is to be executed. In some examples, the means for determining is implemented by executable instructions such as that implemented by at least block 1202 of FIG. 12 and/or block 1304 of FIG. 13 . In such examples, the executable instructions of block 1202 of FIG. 12 and/or block 1304 of FIG. 13 can be executed on at least one processor such as the example processor 1412 of FIG. 14 . In other examples, the means for determining is implemented by hardware logic, hardware implemented state machines, logic circuitry, and/or any other combination of hardware, software, and/or firmware.
In the illustrated example of FIG. 2 , the model training controller 104 A-E includes the layer generator 230 to generate a layer of a neural network by assigning a sparsity configuration to the layer based on the hardware configuration(s) 272 . In some examples, the layer generator 230 selects a first layer of the layers of a neural network. In such examples, the layer generator 230 determines a sparsity configuration of the first layer, such as a sparsity ratio of 30%, 50%, etc., and assigns a zero to one or more values of a matrix of the first layer based on the sparsity ratio. As used herein, the term âsparsity ratioâ refers to a ratio of (a) a number of zero-valued elements or values in a neural network layer matrix and (b) a total number of elements or values in the neural network layer matrix. For example, the layer generator 230 can generate the first layer by assigning a sparsity ratio of 30% and setting 30% of the elements of the matrix of the first layer to be zero or have zero value.
In some examples, the layer generator 230 implements means for assigning sparsity configurations to layers of the machine learning model based on a hardware configuration. For example, the means for assigning can generate one or more layers of a machine learning model based on the assignments. In some examples, the means for assigning is to select a first layer of one or more layers of a machine learning model and assign a zero to one or more values of a matrix of the first layer.
In some examples, the means for assigning is implemented by executable instructions such as that implemented by at least block 1204 of FIG. 12 and/or blocks 1306 , 1312 , 1314 of FIG. 13 . In such examples, the executable instructions of block 1204 of FIG. 12 and/or blocks 1306 , 1312 , and 1314 of FIG. 13 can be executed on at least one processor such as the example processor 1412 of FIG. 14 . In other examples, the means for assigning is implemented by hardware logic, hardware implemented state machines, logic circuitry, and/or any other combination of hardware, software, and/or firmware.
In the illustrated example of FIG. 2 , the model training controller 104 A-E includes the model training handler 240 to invoke an environment (e.g., a machine learning training environment) to generate output(s) of the machine learning model 274 . In some examples, the model training handler 240 invokes the environment to generate an embedding state for a layer so that the embedding state characterizes the layer. For example, responsive to generating an action, the model training handler 240 can invoke the environment to execute the action. In such examples, responsive to executing the action, the environment generates and/or otherwise outputs the embedding state. In some such examples, the embedding state can be an array of parameters representative of statistics of a weight tensor that corresponds to the layer. In some such e
CLAIMS
Claims ( 20 )
What is claimed is:
1 . A method for generating an executable neural network, the method comprising:
providing an embedding state to a reinforcement learning agent, the embedding state representing one or more characteristics of a layer of a neural network; generating, by the reinforcement learning agent based on the embedding state, one or more actions of reducing a number of computational cycles on a hardware device for executing the neural network; invoking an execution of the neural network by the hardware device through the reduced number of computational cycles, the neural network generating an output; determining a reward for the reinforcement learning agent by determining whether an accuracy of the output of the neural network reaches an accuracy threshold; and updating a policy of the reinforcement learning agent based on the reward.
2 . The method of claim 1 , wherein the action comprises an action of pruning weights in the layer based on a sparsity ratio determined by the reinforcement learning agent.
3 . The method of claim 1 , further comprising:
providing one or more other embedding states of one or more other layers of the neural network to the reinforcement learning agent, p 1 wherein the one or more actions are generated by the reinforcement learning agent further based on the one or more other embedding states, wherein the one or more actions comprise an action of pruning weights in the layer and one or more other actions of pruning weights in the one or more other layers.
4 . The method of claim 1 , wherein the one or more characteristics of the layer include an index, a kernel size, an input feature size, or a number of weights of the layer.
5 . The method of claim 1 , wherein the embedding state further represents an action of pruning weights in another layer of the neural network, wherein the another layer is precedent to the layer in the neural network.
6 . The method of claim 1 , wherein the reward is determined further by determining whether a target cycle reduction is reached by the one or more actions.
7 . The method of claim 6 , wherein the target cycle reduction is not reached by the one or more actions, wherein the reinforcement learning agent is to generate a new action using the updated policy, the new action comprising a reduction of computational cycles on the hardware device for executing one or more other layers in the neural network.
8 . One or more non-transitory computer-readable media storing instructions executable to perform operations for generating an executable neural network, the operations comprising:
providing an embedding state to a reinforcement learning agent, the embedding state representing one or more characteristics of a layer of a neural network; generating, by the reinforcement learning agent based on the embedding state, one or more actions of reducing a number of computational cycles on a hardware device for executing the neural network; invoking an execution of the neural network by the hardware device through the reduced number of computational cycles, the neural network generating an output; determining a reward for the reinforcement learning agent by determining whether an accuracy of the output of the neural network reaches an accuracy threshold; and updating a policy of the reinforcement learning agent based on the reward.
9 . The one or more non-transitory computer-readable media of claim 8 , wherein the action comprises an action of pruning weights in the layer based on a sparsity ratio determined by the reinforcement learning agent.
10 . The one or more non-transitory computer-readable media of claim 8 , wherein the operations further comprise:
providing one or more other embedding states of one or more other layers of the neural network to the reinforcement learning agent, wherein the one or more actions are generated by the reinforcement learning agent further based on the one or more other embedding states, wherein the one or more actions comprise an action of pruning weights in the layer and one or more other actions of pruning weights in the one or more other layers.
11 . The one or more non-transitory computer-readable media of claim 8 , wherein the one or more characteristics of the layer include an index, a kernel size, an input feature size, or a number of weights of the layer.
12 . The one or more non-transitory computer-readable media of claim 8 , wherein the embedding state further represents an action of pruning weights in another layer of the neural network, wherein the another layer is precedent to the layer in the neural network.
13 . The one or more non-transitory computer-readable media of claim 8 , wherein the reward is determined further by determining whether a target cycle reduction is reached by the one or more actions.
14 . The one or more non-transitory computer-readable media of claim 13 , wherein the target cycle reduction is not reached by the one or more actions, wherein the reinforcement learning agent is to generate a new action using the updated policy, the new action comprising a reduction of computational cycles on the hardware device for executing one or more other layers in the neural network.
15 . An apparatus for generating an executable neural network, the apparatus comprising:
a computer processor for executing computer program instructions; and a non-transitory computer-readable memory storing computer program instructions executable by the computer processor to perform operations comprising:
providing an embedding state to a reinforcement learning agent, the embedding state representing one or more characteristics of a layer of a neural network,
generating, by the reinforcement learning agent based on the embedding state, one or more actions of reducing a number of computational cycles on a hardware device for executing the neural network,
invoking an execution of the neural network by the hardware device through the reduced number of computational cycles, the neural network generating an output,
determining a reward for the reinforcement learning agent by determining whether an accuracy of the output of the neural network reaches an accuracy threshold, and
updating a policy of the reinforcement learning agent based on the reward.
16 . The apparatus of claim 15 , wherein the action comprises an action of pruning weights in the layer based on a sparsity ratio determined by the reinforcement learning agent.
17 . The apparatus of claim 15 , wherein the operations further comprise:
providing one or more other embedding states of one or more other layers of the neural network to the reinforcement learning agent, wherein the one or more actions are generated by the reinforcement learning agent further based on the one or more other embedding states, wherein the one or more actions comprise an action of pruning weights in the layer and one or more other actions of pruning weights in the one or more other layers.
18 . The apparatus of claim 15 , wherein the embedding state further represents an action of pruning weights in another layer of the neural network, wherein the another layer is precedent to the layer in the neural network.
19 . The apparatus of claim 15 , wherein the reward is determined further by determining whether a target cycle reduction is reached by the one or more actions.
20 . The apparatus of claim 15 , wherein the target cycle reduction is not reached by the one or more actions, wherein the reinforcement learning agent is to generate a new action using the updated policy, the new action comprising a reduction of computational cycles on the hardware device for executing one or more other layers in the neural network.
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æµæ±æµ·æ§åç§åéæ°æºç§æè¡ä»½æéå ¬å¸
Quick deployment-oriented large-model soft and hard all-in-one machine optimization method and device
2020
2020-09-04
US
US17/013,258
patent/US20200401891A1/en
not_active
Abandoned
2021
2021-08-03
CN
CN202110884528.XA
patent/CN114139714A/en
active
Pending
2025
2025-08-21
US
US19/306,117
patent/US20250371349A1/en
active
Pending
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Beijing Baidu Netcom Science Technology Co., Ltd.
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Red Hat, Inc.
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2020-12-24
CN114139714A
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2022-03-04
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