ABSTRACT
Abstract
A mechanism is described for facilitating on-the-fly deep learning in machine learning for autonomous machines. A method of embodiments, as described herein, includes detecting an output associated with a first deep network serving as a user-independent model associated with learning of one or more neural networks at a computing device having a processor coupled to memory. The method may further include automatically generating training data for a second deep network serving as a user-dependent model, where the training data is generated based on the output. The method may further include merging the user-independent model with the user-dependent model into a single joint model.
Description
CROSS-REFERENCE
This application is a continuation application claiming priority to U.S. application Ser. No. 18/322,218, filed May 23, 2023, which is a continuation application claiming priority to U.S. application Ser. No. 17/400,908, filed Aug. 12, 2021, now issued as U.S. Pat. No. 11,663,456, which is a continuation of U.S. application Ser. No. 16/929,976, filed Jul. 15, 2020, now issued as U.S. Pat. No. 11,120,304, which claims priority to U.S. patent application Ser. No. 16/783,451, filed Feb. 6, 2020, now issued as U.S. Pat. No. 11,354,542, which claims priority to U.S. Pat. No. 10,572,773, issued on Feb. 25, 2020, which claims the benefit of and priority to U.S. Provisional Application No. 62/502,294, entitled ON-THE-FLY DEEP LEARNING IN MACHINE LEARNING AT AUTONOMOUS MACHINES, by Yehezkel Rohekar, et al., filed May 5, 2017, which is incorporated herein by reference.
FIELD
Embodiments described herein relate generally to data processing and more particularly to facilitate on-the-fly deep learning in machine learning for autonomous machines.
BACKGROUND
Current parallel graphics data processing includes systems and methods developed to perform specific operations on graphics data such as, for example, linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors used fixed function computational units to process graphics data; however, more recently, portions of graphics processors have been made programmable, enabling such processors to support a wider variety of operations for processing vertex and fragment data.
To further increase performance, graphics processors typically implement processing techniques such as pipelining that attempt to process, in parallel, as much graphics data as possible throughout the different parts of the graphics pipeline. Parallel graphics processors with single instruction, multiple thread (SIMT) architectures are designed to maximize the amount of parallel processing in the graphics pipeline. In an SIMT architecture, groups of parallel threads attempt to execute program instructions synchronously together as often as possible to increase processing efficiency. A general overview of software and hardware for SIMT architectures can be found in Shane Cook, CUDA Programming , Chapter 3, pages 37-51 (2013) and/or Nicholas Wilt, CUDA Handbook, A Comprehensive Guide to GPU Programming , Sections 2.6.2 to 3.1.2 (June 2013).
Machine learning has been successful at solving many kinds of tasks. The computations that arise when training and using machine learning algorithms (e.g., neural networks) lend themselves naturally to efficient parallel implementations. Accordingly, parallel processors such as general-purpose graphic processing units (GPGPUs) have played a significant role in the practical implementation of deep neural networks. Parallel graphics processors with single instruction, multiple thread (SIMT) architectures are designed to maximize the amount of parallel processing in the graphics pipeline. In an SIMT architecture, groups of parallel threads attempt to execute program instructions synchronously together as often as possible to increase processing efficiency. The efficiency provided by parallel machine learning algorithm implementations allows the use of high-capacity networks and enables those networks to be trained on larger datasets.
Today, the ability of an autonomous machine and its machine learning system to learn under a varying context is limited to simple algorithms with moderate adapting flexibility. Deep learning algorithms provide state-of-the-art accuracy in many domains, e.g., facial expression recognition; however, they lack the ability to provide a context-dependent solution (e.g., facial expression of a specific person, not in the data that was used for training) along with an ability to adapt over time.
BRIEF DESCRIPTION OF THE DRAWINGS
Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements. So that the manner in which the recited features can be understood in detail, a more particular description may be had by reference to the detailed description and the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments and are therefore not to be considered limiting of its scope, for the drawings may illustrate other equally effective embodiments.
FIG. 1 is a block diagram illustrating a computer system configured to implement one or more aspects of the embodiments described herein.
FIG. 2 A- 2 D illustrate parallel processor components, according to an embodiment.
FIG. 3 A- 3 B are block diagrams of graphics multiprocessors, according to embodiments.
FIG. 4 A- 4 F illustrate an exemplary architecture in which a plurality of graphics processing units is communicatively coupled to a plurality of multi-core processors.
FIG. 5 is a conceptual diagram of a graphics processing pipeline, according to an embodiment.
FIG. 6 illustrates a computing device hosting an on-the-fly deep learning mechanism according to one embodiment.
FIG. 7 illustrates an on-the-fly deep learning mechanism according to one embodiment.
FIG. 8 A illustrates a method for on-the-fly learning according to one embodiment.
FIG. 8 B illustrates a method associated with stage one of offline learning according to one embodiment.
FIG. 8 C- 8 D illustrate methods representing stage two in on-the-fly learning according to one embodiment.
FIG. 8 E illustrates a method associated with stage three of joint tuning, training, and/or re-training according to one embodiment.
FIG. 9 A illustrates a transaction sequence of the various stages associated with on-the-fly learning according to one embodiment.
FIG. 9 B illustrates a transaction sequence associated with various stages of on-the-fly learning according to one embodiment.
FIG. 10 illustrates a machine learning software stack, according to an embodiment.
FIG. 11 illustrates a highly parallel general-purpose graphics processing unit, according to an embodiment.
FIG. 12 illustrates a multi-GPU computing system, according to an embodiment.
FIG. 13 A- 13 B illustrate layers of exemplary deep neural networks.
FIG. 14 illustrates training and deployment of a deep neural network.
FIG. 15 illustrates training and deployment of a deep neural network.
FIG. 16 is a block diagram illustrating distributed learning.
FIG. 17 illustrates an exemplary inferencing system on a chip (SOC) suitable for performing inferencing using a trained model.
FIG. 18 is a block diagram of an embodiment of a computer system with a processor having one or more processor cores and graphics processors.
FIG. 19 is a block diagram of one embodiment of a processor having one or more processor cores, an integrated memory controller, and an integrated graphics processor.
FIG. 20 is a block diagram of one embodiment of a graphics processor which may be a discreet graphics processing unit or may be graphics processor integrated with a plurality of processing cores.
FIG. 21 is a block diagram of an embodiment of a graphics processing engine for a graphics processor.
FIG. 22 is a block diagram of another embodiment of a graphics processor.
FIG. 23 is a block diagram of thread execution logic including an array of processing elements.
FIG. 24 illustrates graphics processor execution unit instruction format according to an embodiment.
FIG. 25 is a block diagram of another embodiment of a graphics processor which includes a graphics pipeline, a media pipeline, a display engine, thread execution logic, and a render output pipeline.
FIG. 26 A is a block diagram illustrating a graphics processor command format according to an embodiment.
FIG. 26 B is a block diagram illustrating a graphics processor command sequence according to an embodiment.
FIG. 27 illustrates exemplary graphics software architecture for a data processing system according to an embodiment.
FIG. 28 is a block diagram illustrating an IP core development system that may be used to manufacture an integrated circuit to perform operations according to an embodiment.
FIG. 29 is a block diagram illustrating an exemplary system on a chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment.
FIG. 30 is a block diagram illustrating an exemplary graphics processor of a system on a chip integrated circuit.
FIG. 31 is a block diagram illustrating an additional exemplary graphics processor of a system on a chip integrated circuit.
DETAILED DESCRIPTION
Embodiments provide for a novel technique for learning complex machine learning models (deep learning) with limited data collection beforehand and by wisely gathering useful data about a user of an autonomous machine, on-the-fly, during a normal operation of the machine.
Today, deep learning networks are trained offline using a large, trained dataset and thus such techniques lack the ability for on-the-fly, online learning or training, and adapting to new data. For example, a novel technique is offered for using offline training using small, labeled datasets and then constantly adapting to new incoming unlabeled data. This unlabeled data may have slightly different statistics than the labeled data.
It is contemplated that âuser understandingâ in personal computing systems, such as in RealSense® middleware tier in case of user's facial expression recognition, etc., often multiple sub-systems are used, such as: 1) calibration of user appearance (which is an interactive procedure); and 2) user-independent classifier (trained offline after gathering data from several users).
Embodiments provide for a novel technique for a real-time context-dependent deep learning to achieve a highly accurate and efficient context-dependent solution that âinterplaysâ in real-time (during scoring/interface-phase) between generic training and context-dependent training. This is done using two distinct deep learning techniques (CNN and DBN, supervised and unsupervised) and by introducing a mediating algorithm to combine these two distinct techniques.
During the first time period (e.g., minutes) of normal system operation, this novel mediating technique takes the outputs of one pre-trained deep network serving as a generic model and automatically generating training data for the second deep network serving as a context-dependent model. Further, once converged, such as a few minutes into simulation, the two networks may be fine-tuned, jointly and end-to-end, and without the mediating algorithm using any small generic labeled data. The merged network is now a context-dependent efficient classifier and achieves higher accuracy than the initial generic classifier.
It is contemplated and to be noted that several machine learning terms are used throughout this document, such as a) deep learning referring to a family of machine learning models composed of multiple layers of neural networks, having high expressive power and providing state-of-the-art accuracy, b) convolutional neural network (CNN) referring to a type of deep learning model, c) deep belief network (DBN) referring to a type of deep learning model, d) user-independent classifier/model referring to a classifier which, once trained, has a consistent accuracy over various users, and e) user-dependent classifier/model referring to a classifier which, once trained, has an accuracy level that is guaranteed only for a specific user.
It is contemplated that throughout this document âuser-independentâ and âuser-dependentâ are regarded as special cases of or synonymously referenced as âcontext-independentâ and âcontext-dependentâ, respectively; for example, recognizing facial expressions of a specific-user is provided as an example of how various embodiments may be employed or used.
It is to be noted that terms or acronyms like âconvolutional neural networkâ, âCNNâ, âneural networkâ, âNNâ, âdeep neural networkâ, âDNNâ, ârecurrent neural networkâ, âRNNâ, and/or the like may be interchangeably referenced throughout this document. Further, terms like âautonomous machineâ or simply âmachineâ, âautonomous vehicleâ or simply âvehicleâ, âautonomous agentâ or simply âagentâ, âautonomous deviceâ or âcomputing deviceâ, ârobotâ, and/or the like, may be interchangeably referenced throughout this document.
In some embodiments, a graphics processing unit (GPU) is communicatively coupled to host/processor cores to accelerate graphics operations, machine-learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor/cores over a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU may be integrated on the same package or chip as the cores and communicatively coupled to the cores over an internal processor bus/interconnect (i.e., internal to the package or chip). Regardless of the manner in which the GPU is connected, the processor cores ma
CROSS-REFERENCE
This application is a continuation application claiming priority to U.S. application Ser. No. 18/322,218, filed May 23, 2023, which is a continuation application claiming priority to U.S. application Ser. No. 17/400,908, filed Aug. 12, 2021, now issued as U.S. Pat. No. 11,663,456, which is a continuation of U.S. application Ser. No. 16/929,976, filed Jul. 15, 2020, now issued as U.S. Pat. No. 11,120,304, which claims priority to U.S. patent application Ser. No. 16/783,451, filed Feb. 6, 2020, now issued as U.S. Pat. No. 11,354,542, which claims priority to U.S. Pat. No. 10,572,773, issued on Feb. 25, 2020, which claims the benefit of and priority to U.S. Provisional Application No. 62/502,294, entitled ON-THE-FLY DEEP LEARNING IN MACHINE LEARNING AT AUTONOMOUS MACHINES, by Yehezkel Rohekar, et al., filed May 5, 2017, which is incorporated herein by reference.
FIELD
Embodiments described herein relate generally to data processing and more particularly to facilitate on-the-fly deep learning in machine learning for autonomous machines.
BACKGROUND
Current parallel graphics data processing includes systems and methods developed to perform specific operations on graphics data such as, for example, linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors used fixed function computational units to process graphics data; however, more recently, portions of graphics processors have been made programmable, enabling such processors to support a wider variety of operations for processing vertex and fragment data.
To further increase performance, graphics processors typically implement processing techniques such as pipelining that attempt to process, in parallel, as much graphics data as possible throughout the different parts of the graphics pipeline. Parallel graphics processors with single instruction, multiple thread (SIMT) architectures are designed to maximize the amount of parallel processing in the graphics pipeline. In an SIMT architecture, groups of parallel threads attempt to execute program instructions synchronously together as often as possible to increase processing efficiency. A general overview of software and hardware for SIMT architectures can be found in Shane Cook, CUDA Programming , Chapter 3, pages 37-51 (2013) and/or Nicholas Wilt, CUDA Handbook, A Comprehensive Guide to GPU Programming , Sections 2.6.2 to 3.1.2 (June 2013).
Machine learning has been successful at solving many kinds of tasks. The computations that arise when training and using machine learning algorithms (e.g., neural networks) lend themselves naturally to efficient parallel implementations. Accordingly, parallel processors such as general-purpose graphic processing units (GPGPUs) have played a significant role in the practical implementation of deep neural networks. Parallel graphics processors with single instruction, multiple thread (SIMT) architectures are designed to maximize the amount of parallel processing in the graphics pipeline. In an SIMT architecture, groups of parallel threads attempt to execute program instructions synchronously together as often as possible to increase processing efficiency. The efficiency provided by parallel machine learning algorithm implementations allows the use of high-capacity networks and enables those networks to be trained on larger datasets.
Today, the ability of an autonomous machine and its machine learning system to learn under a varying context is limited to simple algorithms with moderate adapting flexibility. Deep learning algorithms provide state-of-the-art accuracy in many domains, e.g., facial expression recognition; however, they lack the ability to provide a context-dependent solution (e.g., facial expression of a specific person, not in the data that was used for training) along with an ability to adapt over time.
BRIEF DESCRIPTION OF THE DRAWINGS
Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements. So that the manner in which the recited features can be understood in detail, a more particular description may be had by reference to the detailed description and the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments and are therefore not to be considered limiting of its scope, for the drawings may illustrate other equally effective embodiments.
FIG. 1 is a block diagram illustrating a computer system configured to implement one or more aspects of the embodiments described herein.
FIG. 2 A- 2 D illustrate parallel processor components, according to an embodiment.
FIG. 3 A- 3 B are block diagrams of graphics multiprocessors, according to embodiments.
FIG. 4 A- 4 F illustrate an exemplary architecture in which a plurality of graphics processing units is communicatively coupled to a plurality of multi-core processors.
FIG. 5 is a conceptual diagram of a graphics processing pipeline, according to an embodiment.
FIG. 6 illustrates a computing device hosting an on-the-fly deep learning mechanism according to one embodiment.
FIG. 7 illustrates an on-the-fly deep learning mechanism according to one embodiment.
FIG. 8 A illustrates a method for on-the-fly learning according to one embodiment.
FIG. 8 B illustrates a method associated with stage one of offline learning according to one embodiment.
FIG. 8 C- 8 D illustrate methods representing stage two in on-the-fly learning according to one embodiment.
FIG. 8 E illustrates a method associated with stage three of joint tuning, training, and/or re-training according to one embodiment.
FIG. 9 A illustrates a transaction sequence of the various stages associated with on-the-fly learning according to one embodiment.
FIG. 9 B illustrates a transaction sequence associated with various stages of on-the-fly learning according to one embodiment.
FIG. 10 illustrates a machine learning software stack, according to an embodiment.
FIG. 11 illustrates a highly parallel general-purpose graphics processing unit, according to an embodiment.
FIG. 12 illustrates a multi-GPU computing system, according to an embodiment.
FIG. 13 A- 13 B illustrate layers of exemplary deep neural networks.
FIG. 14 illustrates training and deployment of a deep neural network.
FIG. 15 illustrates training and deployment of a deep neural network.
FIG. 16 is a block diagram illustrating distributed learning.
FIG. 17 illustrates an exemplary inferencing system on a chip (SOC) suitable for performing inferencing using a trained model.
FIG. 18 is a block diagram of an embodiment of a computer system with a processor having one or more processor cores and graphics processors.
FIG. 19 is a block diagram of one embodiment of a processor having one or more processor cores, an integrated memory controller, and an integrated graphics processor.
FIG. 20 is a block diagram of one embodiment of a graphics processor which may be a discreet graphics processing unit or may be graphics processor integrated with a plurality of processing cores.
FIG. 21 is a block diagram of an embodiment of a graphics processing engine for a graphics processor.
FIG. 22 is a block diagram of another embodiment of a graphics processor.
FIG. 23 is a block diagram of thread execution logic including an array of processing elements.
FIG. 24 illustrates graphics processor execution unit instruction format according to an embodiment.
FIG. 25 is a block diagram of another embodiment of a graphics processor which includes a graphics pipeline, a media pipeline, a display engine, thread execution logic, and a render output pipeline.
FIG. 26 A is a block diagram illustrating a graphics processor command format according to an embodiment.
FIG. 26 B is a block diagram illustrating a graphics processor command sequence according to an embodiment.
FIG. 27 illustrates exemplary graphics software architecture for a data processing system according to an embodiment.
FIG. 28 is a block diagram illustrating an IP core development system that may be used to manufacture an integrated circuit to perform operations according to an embodiment.
FIG. 29 is a block diagram illustrating an exemplary system on a chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment.
FIG. 30 is a block diagram illustrating an exemplary graphics processor of a system on a chip integrated circuit.
FIG. 31 is a block diagram illustrating an additional exemplary graphics processor of a system on a chip integrated circuit.
DETAILED DESCRIPTION
Embodiments provide for a novel technique for learning complex machine learning models (deep learning) with limited data collection beforehand and by wisely gathering useful data about a user of an autonomous machine, on-the-fly, during a normal operation of the machine.
Today, deep learning networks are trained offline using a large, trained dataset and thus such techniques lack the ability for on-the-fly, online learning or training, and adapting to new data. For example, a novel technique is offered for using offline training using small, labeled datasets and then constantly adapting to new incoming unlabeled data. This unlabeled data may have slightly different statistics than the labeled data.
It is contemplated that âuser understandingâ in personal computing systems, such as in RealSense® middleware tier in case of user's facial expression recognition, etc., often multiple sub-systems are used, such as: 1) calibration of user appearance (which is an interactive procedure); and 2) user-independent classifier (trained offline after gathering data from several users).
Embodiments provide for a novel technique for a real-time context-dependent deep learning to achieve a highly accurate and efficient context-dependent solution that âinterplaysâ in real-time (during scoring/interface-phase) between generic training and context-dependent training. This is done using two distinct deep learning techniques (CNN and DBN, supervised and unsupervised) and by introducing a mediating algorithm to combine these two distinct techniques.
During the first time period (e.g., minutes) of normal system operation, this novel mediating technique takes the outputs of one pre-trained deep network serving as a generic model and automatically generating training data for the second deep network serving as a context-dependent model. Further, once converged, such as a few minutes into simulation, the two networks may be fine-tuned, jointly and end-to-end, and without the mediating algorithm using any small generic labeled data. The merged network is now a context-dependent efficient classifier and achieves higher accuracy than the initial generic classifier.
It is contemplated and to be noted that several machine learning terms are used throughout this document, such as a) deep learning referring to a family of machine learning models composed of multiple layers of neural networks, having high expressive power and providing state-of-the-art accuracy, b) convolutional neural network (CNN) referring to a type of deep learning model, c) deep belief network (DBN) referring to a type of deep learning model, d) user-independent classifier/model referring to a classifier which, once trained, has a consistent accuracy over various users, and e) user-dependent classifier/model referring to a classifier which, once trained, has an accuracy level that is guaranteed only for a specific user.
It is contemplated that throughout this document âuser-independentâ and âuser-dependentâ are regarded as special cases of or synonymously referenced as âcontext-independentâ and âcontext-dependentâ, respectively; for example, recognizing facial expressions of a specific-user is provided as an example of how various embodiments may be employed or used.
It is to be noted that terms or acronyms like âconvolutional neural networkâ, âCNNâ, âneural networkâ, âNNâ, âdeep neural networkâ, âDNNâ, ârecurrent neural networkâ, âRNNâ, and/or the like may be interchangeably referenced throughout this document. Further, terms like âautonomous machineâ or simply âmachineâ, âautonomous vehicleâ or simply âvehicleâ, âautonomous agentâ or simply âagentâ, âautonomous deviceâ or âcomputing deviceâ, ârobotâ, and/or the like, may be interchangeably referenced throughout this document.
In some embodiments, a graphics processing unit (GPU) is communicatively coupled to host/processor cores to accelerate graphics operations, machine-learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor/cores over a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU may be integrated on the same package or chip as the cores and communicatively coupled to the cores over an internal processor bus/interconnect (i.e., internal to the package or chip). Regardless of the manner in which the GPU is connected, the processor cores may allocate work to the GPU in the form of sequences of commands/instructions contained in a work descriptor. The GPU then uses dedicated circuitry/logic for efficiently processing these commands/instructions.
In the following description, numerous specific details are set forth. However, embodiments, as described herein, may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown in detail in order not to obscure the understanding of this description.
System Overview I
FIG. 1 is a block diagram illustrating a computing system 100 configured to implement one or more aspects of the embodiments described herein. The computing system 100 includes a processing subsystem 101 having one or more processor(s) 102 and a system memory 104 communicating via an interconnection path that may include a memory hub 105 . The memory hub 105 may be a separate component within a chipset component or may be integrated within the one or more processor(s) 102 . The memory hub 105 couples with an I/O subsystem 111 via a communication link 106 . The I/O subsystem 111 includes an I/ O hub 107 that can enable the computing system 100 to receive input from one or more input device(s) 108 . Additionally, the I/ O hub 107 can enable a display controller, which may be included in the one or more processor(s) 102 , to provide outputs to one or more display device(s) 110 A. In one embodiment, the one or more display device(s) 110 A coupled with the I/ O hub 107 can include a local, internal, or embedded display device.
In one embodiment, the processing subsystem 101 includes one or more parallel processor(s) 112 coupled to memory hub 105 via a bus or other communication link 113 . The communication link 113 may be one of any number of standards based communication link technologies or protocols, such as, but not limited to PCI Express, or may be a vendor specific communications interface or communications fabric. In one embodiment, the one or more parallel processor(s) 112 form a computationally focused parallel or vector processing system that an include a large number of processing cores and/or processing clusters, such as a many integrated core (MIC) processor. In one embodiment, the one or more parallel processor(s) 112 form a graphics processing subsystem that can output pixels to one of the one or more display device(s) 110 A coupled via the I/ O hub 107 . The one or more parallel processor(s) 112 can also include a display controller and display interface (not shown) to enable a direct connection to one or more display device(s) 110 B.
Within the I/O subsystem 111 , a system storage unit 114 can connect to the I/ O hub 107 to provide a storage mechanism for the computing system 100 . An I/ O switch 116 can be used to provide an interface mechanism to enable connections between the I/ O hub 107 and other components, such as a network adapter 118 and/or wireless network adapter 119 that may be integrated into the platform, and various other devices that can be added via one or more add-in device(s) 120 . The network adapter 118 can be an Ethernet adapter or another wired network adapter. The wireless network adapter 119 can include one or more of a Wi-Fi, Bluetooth, near field communication (NFC), or other network device that includes one or more wireless radios.
The computing system 100 can include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, and the like, may also be connected to the I/ O hub 107 . Communication paths interconnecting the various components in FIG. 1 may be implemented using any suitable protocols, such as PCI (Peripheral Component Interconnect) based protocols (e.g., PCI-Express), or any other bus or point-to-point communication interfaces and/or protocol(s), such as the NV-Link high-speed interconnect, or interconnect protocols known in the art.
In one embodiment, the one or more parallel processor(s) 112 incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitutes a graphics processing unit (GPU). In another embodiment, the one or more parallel processor(s) 112 incorporate circuitry optimized for general purpose processing, while preserving the underlying computational architecture, described in greater detail herein. In yet another embodiment, components of the computing system 100 may be integrated with one or more other system elements on a single integrated circuit. For example, the one or more parallel processor(s), 112 memory hub 105 , processor(s) 102 , and I/ O hub 107 can be integrated into a system on chip (SoC) integrated circuit. Alternatively, the components of the computing system 100 can be integrated into a single package to form a system in package (SIP) configuration. In one embodiment, at least a portion of the components of the computing system 100 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computing system.
It will be appreciated that the computing system 100 shown herein is illustrative and that variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of processor(s) 102 , and the number of parallel processor(s) 112 , may be modified as desired. For instance, in some embodiments, system memory 104 is connected to the processor(s) 102 directly rather than through a bridge, while other devices communicate with system memory 104 via the memory hub 105 and the processor(s) 102 . In other alternative topologies, the parallel processor(s) 112 are connected to the I/ O hub 107 or directly to one of the one or more processor(s) 102 , rather than to the memory hub 105 . In other embodiments, the I/ O hub 107 and memory hub 105 may be integrated into a single chip. Some embodiments may include two or more sets of processor(s) 102 attached via multiple sockets, which can couple with two or more instances of the parallel processor(s) 112 .
Some of the particular components shown herein are optional and may not be included in all implementations of the computing system 100 . For example, any number of add-in cards or peripherals may be supported, or some components may be eliminated. Furthermore, some architectures may use different terminology for components similar to those illustrated in FIG. 1 . For example, the memory hub 105 may be referred to as a Northbridge in some architectures, while the I/ O hub 107 may be referred to as a Southbridge.
FIG. 2 A illustrates a parallel processor 200 , according to an embodiment. The various components of the parallel processor 200 may be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits (ASICs), or field programmable gate arrays (FPGA). The illustrated parallel processor 200 is a variant of the one or more parallel processor(s) 112 shown in FIG. 1 , according to an embodiment.
In one embodiment, the parallel processor 200 includes a parallel processing unit 202 . The parallel processing unit includes an I/ O unit 204 that enables communication with other devices, including other instances of the parallel processing unit 202 . The I/ O unit 204 may be directly connected to other devices. In one embodiment, the I/ O unit 204 connects with other devices via the use of a hub or switch interface, such as memory hub 105 . The connections between the memory hub 105 and the I/ O unit 204 form a communication link 113 . Within the parallel processing unit 202 , the I/ O unit 204 connects with a host interface 206 and a memory crossbar 216 , where the host interface 206 receives commands directed to performing processing operations and the memory crossbar 216 receives commands directed to performing memory operations.
When the host interface 206 receives a command buffer via the I/ O unit 204 , the host interface 206 can direct work operations to perform those commands to a front end 208 . In one embodiment, the front end 208 couples with a scheduler 210 , which is configured to distribute commands or other work items to a processing cluster array 212 . In one embodiment, the scheduler 210 ensures that the processing cluster array 212 is properly configured and in a valid state before tasks are distributed to the processing clusters of the processing cluster array 212 .
The processing cluster array 212 can include up to âNâ processing clusters (e.g., cluster 214 A, cluster 214 B, through cluster 214 N). Each cluster 214 A- 214 N of the processing cluster array 212 can execute a large number of concurrent threads. The scheduler 210 can allocate work to the clusters 214 A- 214 N of the processing cluster array 212 using various scheduling and/or work distribution algorithms, which may vary depending on the workload arising for each type of program or computation. The scheduling can be handled dynamically by the scheduler 210 , or can be assisted in part by compiler logic during compilation of program logic configured for execution by the processing cluster array 212 .
In one embodiment, different clusters 214 A- 214 N of processing cluster array 212 can be allocated for processing different types of programs or for performing different types of computations.
The processing cluster array 212 can be configured to perform various types of parallel processing operations. In one embodiment, the processing cluster array 212 is configured to perform general-purpose parallel compute operations. For example, the processing cluster array 212 can include logic to execute processing tasks including filtering of video and/or audio data, performing modeling operations, including physics operations, and performing data transformations.
In one embodiment, the processing cluster array 212 is configured to perform parallel graphics processing operations. In embodiments in which the parallel processor 200 is configured to perform graphics processing operations, the processing cluster array 212 can include additional logic to support the execution of such graphics processing operations, including, but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. Additionally, the processing cluster array 212 can be configured to execute graphics processing related shader programs such as, but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. The parallel processing unit 202 can transfer data from system memory via the I/ O unit 204 for processing. During processing the transferred data can be stored to on-chip memory (e.g., parallel processor memory 222 ) during processing, then written back to system memory.
In one embodiment, when the parallel processing unit 202 is used to perform graphics processing, the scheduler 210 can be configured to divide the processing workload into approximately equal sized tasks, to better enable distribution of the graphics processing operations to multiple clusters 214 A- 214 N of the processing cluster array 212 . In some embodiments, portions of the processing cluster array 212 can be configured to perform different types of processing. For example, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations, to produce a rendered image for display. Intermediate data produced by one or more of the clusters 214 A- 214 N may be stored in buffers to allow the intermediate data to be transmitted between clusters 214 A- 214 N for further processing.
During operation, the processing cluster array 212 can receive processing tasks to be executed via the scheduler 210 , which receives commands defining processing tasks from front end 208 . For graphics processing operations, processing tasks can include indices of data to be processed, e.g., surface (patch) data, primitive data, vertex data, and/or pixel data, as well as state parameters and commands defining how the data is to be processed (e.g., what program is to be executed). The scheduler 210 may be configured to fetch the indices corresponding to the tasks or may receive the indices from the front end 208 . The front end 208 can be configured to ensure the processing cluster array 212 is configured to a valid state before the workload specified by incoming command buffers (e.g., batch-buffers, push buffers, etc.) is initiated.
Each of the one or more instances of the parallel processing unit 202 can couple with parallel processor memory 222 . The parallel processor memory 222 can be accessed via the memory crossbar 216 , which can receive memory requests from the processing cluster array 212 as well as the I/ O unit 204 . The memory crossbar 216 can access the parallel processor memory 222 via a memory interface 218 . The memory interface 218 can include multiple partition units (e.g., partition unit 220 A, partition unit 220 B, through partition unit 220 N) that can each couple to a portion (e.g., memory unit) of parallel processor memory 222 . In one implementation, the number of partition units 220 A- 220 N is configured to be equal to the number of memory units, such that a first partition unit 220 A has a corresponding first memory unit 224 A, a second partition unit 220 B has a corresponding memory unit 224 B, and an Nth partition unit 220 N has a corresponding Nth memory unit 224 N. In other embodiments, the number of partition units 220 A- 220 N may not be equal to the number of memory devices.
In various embodiments, the memory units 224 A- 224 N can include various types of memory devices, including dynamic random-access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, the memory units 224 A- 224 N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Persons skilled in the art will appreciate that the specific implementation of the memory units 224 A- 224 N can vary, and can be selected from one of various conventional designs. Render targets, such as frame buffers or texture maps may be stored across the memory units 224 A- 224 N, allowing partition units 220 A- 220 N to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory 222 . In some embodiments, a local instance of the parallel processor memory 222 may be excluded in favor of a unified memory design that utilizes system memory in conjunction with local cache memory.
In one embodiment, any one of the clusters 214 A- 214 N of the processing cluster array 212 can process data that will be written to any of the memory units 224 A- 224 N within parallel processor memory 222 . The memory crossbar 216 can be configured to transfer the output of each cluster 214 A- 214 N to any partition unit 220 A- 220 N or to another cluster 214 A- 214 N, which can perform additional processing operations on the output. Each cluster 214 A- 214 N can communicate with the memory interface 218 through the memory crossbar 216 to read from or write to various external memory devices. In one embodiment, the memory crossbar 216 has a connection to the memory interface 218 to communicate with the I/ O unit 204 , as well as a connection to a local instance of the parallel processor memory 222 , enabling the processing units within the different processing clusters 214 A- 214 N to communicate with system memory or other memory that is not local to the parallel processing unit 202 . In one embodiment, the memory crossbar 216 can use virtual channels to separate traffic streams between the clusters 214 A- 214 N and the partition units 220 A- 220 N.
While a single instance of the parallel processing unit 202 is illustrated within the parallel processor 200 , any number of instances of the parallel processing unit 202 can be included. For example, multiple instances of the parallel processing unit 202 can be provided on a single add-in card, or multiple add-in cards can be interconnected. The different instances of the parallel processing unit 202 can be configured to inter-operate even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and/or other configuration differences. For example, and in one embodiment, some instances of the parallel processing unit 202 can include higher precision floating point units relative to other instances. Systems incorporating one or more instances of the parallel processing unit 202 or the parallel processor 200 can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and/or embedded systems.
FIG. 2 B is a block diagram of a partition unit 220 , according to an embodiment. In one embodiment, the partition unit 220 is an instance of one of the partition units 220 A- 220 N of FIG. 2 A . As illustrated, the partition unit 220 includes an L2 cache <b
CLAIMS
Claims ( 20 )
What is claimed is:
1. A data processing system on a computing device, the data processing system comprising:
one or more processors including a general-purpose graphics processor; and
one or more storage devices comprising a graphics execution environment including a machine learning framework to provide machine learning primitives that are accelerated via the general-purpose graphics processor, the one or more processors to perform operations comprising:
selecting a topology for a first machine learning model for use with the machine learning framework, wherein the first machine learning model comprises a pre-trained machine learning model that was trained on a user-independent dataset to enable user-independent classification of input data; and
training, via the machine learning framework, a second machine learning model based on a dataset including user-dependent data, wherein the user-dependent data includes images and associated labels and the second machine learning model comprises an update of the first machine learning model,
wherein training the second machine learning model includes training the second machine learning model via a primitive provided by the machine learning framework and tuning parameters of the second machine learning model via the machine learning framework, the machine learning framework is a first machine learning framework that is configured to operate with a second machine learning framework, and the second machine learning framework is configured to provide a second primitive to implement a first primitive provided by the first machine learning framework.
2. The data processing system of claim 1 , wherein the first machine learning model comprises a pre-trained machine learning model for computer vision.
3. The data processing system of claim 2 , wherein training the second machine learning model includes training the second machine learning model to perform computer vision operations for image recognition.
4. The data processing system of claim 1 , wherein the first machine learning model comprises a pre-trained machine learning model for speech synthesis.
5. The data processing system of claim 1 , wherein the one or more processors are additionally configured to perform operations including receiving a selection of a topology for the first machine learning model.
6. The data processing system of claim 1 , wherein training the second machine learning model via the primitive includes training the second machine learning model via the first primitive.
7. The data processing system of claim 6 , wherein the second primitive is to cause the general-purpose graphics processor to perform an operation to train a layer of the second machine learning model.
8. The data processing system of claim 1 , wherein the graphics execution environment is a virtualized environment.
9. The data processing system of claim 1 , wherein the general-purpose graphics processor is configurable into partitions and the graphics execution environment is to execute via one or more partitions of general-purpose graphics processor.
10. The data processing system of claim 9 , wherein the general-purpose graphics processor is configured into multiple partitions and the general-purpose graphics processor is to execute multiple graphics execution environments via the multiple partitions.
11. A method comprising:
receiving selection of a topology for a first machine learning model for use with a machine learning framework, the machine learning framework to provide machine learning primitives that are accelerated via a general-purpose graphics processor, wherein the first machine learning model comprises a pre-trained machine learning model that was trained on a user-independent dataset to enable user-independent classification of input data; and
training, via the machine learning framework, a second machine learning model based on a dataset including user-dependent data, wherein the user-dependent data includes images and associated labels and the second machine learning model comprises an update of the first machine learning model, wherein training the second machine learning model includes training the second machine learning model via a primitive provided by the machine learning framework and tuning parameters of the second machine learning model via the machine learning framework, the machine learning framework is a first machine learning framework that is configured to operate with a second machine learning framework, and the second machine learning framework is configured to provide a second primitive to implement a first primitive provided by the first machine learning framework.
12. The method of claim 11 , wherein the first machine learning model comprises a pre-trained machine learning model for computer vision.
13. The method of claim 12 , wherein training the second machine learning model includes training the second machine learning model to perform computer vision operations for image recognition.
14. The method of claim 11 , wherein the first machine learning model comprises a pre-trained machine learning model for speech synthesis.
15. The method of claim 11 , wherein training the second machine learning model via the primitive includes training the second machine learning model via the first primitive.
16. A non-transitory machine-readable medium having instructions stored thereon, the instructions, when executed by one or more processors, cause the one or more processors to perform operations comprising:
selecting or receiving selection of a topology for a first machine learning model for use with a machine learning framework, the machine learning framework to provide machine learning primitives that are accelerated via a general-purpose graphics processor, wherein the first machine learning model comprises a pre-trained machine learning model trained on a user-independent dataset to enable user-independent classification of input data; and
training, via the machine learning framework, a second machine learning model based on a dataset including user-dependent data, wherein the user-dependent data includes images and associated labels and the second machine learning model comprises an update of the first machine learning model, wherein training the second machine learning model includes training the second machine learning model via a primitive provided by the machine learning framework and tuning parameters of the second machine learning model via the machine learning framework, the machine learning framework is a first machine learning framework that is configured to operate with a second machine learning framework, and the second machine learning framework is configured to provide a second primitive to implement a first primitive provided by the first machine learning framework.
17. The non-transitory machine-readable medium of claim 16 , wherein the first machine learning model comprises a pre-trained machine learning model for computer vision.
18. The non-transitory machine-readable medium of claim 17 , wherein training the second machine learning model includes training the second machine learning model to perform computer vision operations for image recognition.
19. The non-transitory machine-readable medium of claim 16 , wherein the first machine learning model comprises a pre-trained machine learning model for speech synthesis.
20. The non-transitory machine-readable medium of claim 16 , wherein training the second machine learning model via the primitive includes training the second machine learning model via the first primitive.
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