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Systems and methods for interacting with a quantum computing system — D-Wave Systems Inc. (US20210272010A1)

D-Wave Systems Inc. · Google Patents

Google Patents · Patents · License: Open Access

patent, google patents, intellectual property, US20210272010A1, D-Wave Systems Inc., Colin P. Williams, en, 2021

ABSTRACT

Abstract

Systems and methods that employ interactions between quantum computing systems and digital computing systems are described. For an iterative method, a quantum computing system may be designed, operated, and/or adapted to provide a rate of convergence that is greater than the rate of convergence of a digital supercomputer. When the digital supercomputer is iteratively used to evaluate an objective function at a cost incurred of C per iteration, the quantum computing system may be used to provide the input parameter(s) to the objective function and quickly converge on the input parameter(s) that optimize the objective function. Thus, a quantum computing system may be used to minimize the total cost incurred CT for consumption of digital supercomputer resources when a digital supercomputer is iteratively employed to evaluate an objective function.

Description

BACKGROUND

Field

The present systems and methods generally relate to interacting with quantum computing systems, and particularly relate to interactions between quantum computing systems and digital computing systems.

Quantum Computing Systems

A quantum computing system is any computing system that employs a quantum processor. A quantum processor is any computer processor that is designed to leverage at least one quantum mechanical phenomenon (such as superposition, entanglement, tunneling, etc.) in the processing of quantum information. Many different designs for quantum processor hardware exist, including but not limited to: photonic quantum processors, superconducting quantum processors, nuclear magnetic resonance quantum processors, ion-trap quantum processors, topological quantum processors, quantum dot quantum processors, etc. Regardless of the specific hardware implementation, all quantum processors encode and manipulate quantum information in quantum mechanical objects or devices called quantum bits, or âqubits;â all quantum processors employ structures or devices for communicating information between qubits; and all quantum processors employ structures or devices for reading out a state of at least one qubit. The physical form of the qubits depends on the hardware employed in the quantum processors; e.g., photonic quantum processors employ photon-based qubits, superconducting quantum processors employ superconducting qubits, and so on.

Quantum processors may be architected to operate in a variety of different ways. For example, a quantum processor may be architected as a general-purpose processor or as a special-purpose processor, and/or may be designed to perform gate/circuit-based algorithms or adiabatic/annealing-based algorithms. Exemplary systems and methods for quantum processors are described in, for example: U.S. Pat. Nos. 7,135,701, 7,418,283, 7,533,068, 7,619,437, 7,639,035, 7,898,282, 8,008,942, 8,190,548, 8,195,596, 8,283,943, and US Patent Application Publication 2011-0022820 (also see U.S. Pat. No. 8,421,053), each of which is incorporated herein by reference in its entirety.

A quantum computing system (including a quantum processor) may interact with another computing system, such as a digital computing system. Throughout this specification and the appended claims, the term âdigital computing systemâ and variants thereof are used to denote any âclassicalâ or ânon-quantumâ computing system that performs digital processing tasks. Exemplary systems and methods for interactions between a quantum computing system and a digital computing system are described in, for example: US Patent Publication 2007-0239366, U.S. Pat. Nos. 7,984,012, 8,195,726, 7,870,087, U.S. patent application Ser. No. 13/300,169 (now US Patent Application Publication 2014-0025606), and U.S. patent application Ser. No. 13/806,404 (now US Patent Application Publication 2013-0282636), each of which is incorporated herein by reference in its entirety.

Digital Supercomputer

Throughout this specification and the appended claims, the term âdigital supercomputerâ is used to describe a high-performance digital computing system that employs a large number of digital processors (e.g., on the order of 10,000, 100,000, or more digital processors) configured in either a distributed network (e.g., grid computing, cloud computing, etc.) or in a localized computer cluster. A digital supercomputer typically far exceeds the performance of a state-of-the-art personal computer in at least one metric. For example, a digital supercomputer may be able to perform a large number of floating point operations per second (FLOPS), such as on the order of TFLOPS (i.e., 10 12 FLOPS), PFLOPS (i.e., 10 15 FLOPS), or more. For example, a digital supercomputer may have more memory, input bandwidth and/or output bandwidth.

There are many computational tasks which are beyond the capabilities of typical personal computers and which require a digital supercomputer in order to be completed. Examples include applications with many variables (e.g., on the order of hundreds of variables or more) and/or involving optimization, simulation, modeling, etc. Due to their immense computational resources, digital supercomputers are relatively scarce (compared to, for example, personal computers) and can be expensive to operate. A user of a digital supercomputer is typically charged (i.e., billed) according to the amount of time for which the digital supercomputer resources are used (which may be measured in a variety of different ways, including wall-clock time, total measured FLOPs, computation time, etc.). In many cases, the cost of operating a digital supercomputer is prohibitive and a potential user who cannot afford the computational resources of a digital supercomputer is forced to simplify a computational task to an approximation that can be completed using more affordable computational resources. Thus, there is a need in the art for systems and/or methods for optimizing the use of digital supercomputer systems so that, for example, the cost of completing a computational task is reduced.

Rate of Convergence in Iterative Methods

In an iterative method, such as an iterative method of optimizing a function or otherwise solving an optimization problem, multiple candidate âsolutionsâ may be determined in series over multiple iterations. For example, a first candidate solution may be determined in a first iteration and a second candidate solution may be determined in a second iteration. In most iterative methods, successive candidate solutions are compared to the âbest known solution so farâ and a new candidate solution may replace the existing âbest known solution so farâ if it represents an improvement over the existing âbest known solution so far.â For example, a first candidate solution from a first iteration may be cast as the âbest known solution so far,â and if a second candidate solution from a second iteration is better than the first candidate solution than the second candidate solution may replace the first candidate solution as the âbest known solution so far.â Therefore, the âqualityâ of the âbest known solution so farâ (e.g., how close the best known solution so far is to the âoverall bestâ solution, or global optimum) may, on average, improve over successive iterations. In some cases, information about the existing âbest known solution so farâ may be used to influence the new candidate solutions generated in subsequent iterations. The rate of improvement in the quality of the âbest known solution so farâ may depend on many factors, but ultimately the âbest known solution so farâ may converge on the âoverall bestâ solution. Throughout this specification and the appended claims, the term ârate of convergenceâ refers to the rate at which the quality of candidate solutions provided by a system or method (e.g., the quality of the âbest known solution so farâ) converges on the quality of the overall best solution, or global optimum. Different algorithmic approaches to optimization may be characterized by their rate of convergence.

Throughout this specification and the appended claims, the term âsolutionâ is generally used to refer to a parameter for which a âgood enoughâ value is determined when an optimal value is sought. In many cases, a sub-optimal value that nevertheless satisfies some solution criterion is considered to be an acceptable solution. Similarly, the term âoptimizedâ is used throughout this specification and the appended claims to refer to a solution or function that has been through an optimization process to determine a value that satisfies at least one solution criterion. Depending on the nature of the problem or function being studied, the âsolutionâ may correspond to a specific output (e.g., an optimized value of an objective function) or a specific input or configuration of inputs (e.g., an optimized value of at least one input parameter of a function).

BRIEF SUMMARY

A method of minimizing a total cost incurred for consumption of digital supercomputer resources when a digital supercomputer is employed to optimize a function, wherein the digital supercomputer evaluates the function in response to a call from an external computing system, each call to the digital supercomputer from the external computing system having a cost incurred per call, may be summarized as including initializing communication between the digital supercomputer and the external computing system, wherein the external computing system includes a quantum computing system; optimizing the function, wherein optimizing the function comprises, for a plurality iterations: generating a candidate value for at least one input parameter by the quantum computing system, transmitting, in a respective call, the candidate value for at least one input parameter from the quantum computing system to the digital supercomputer, and evaluating the function based on the candidate value for at least one input parameter by the digital supercomputer, until a value for at least one input parameter that at least approximately optimizes the function is found, wherein the number of iterations in the plurality of iterations is dependent on a rate of convergence of the quantum computing system, and wherein the rate of convergence of the quantum computing system is greater than a rate of convergence of the digital supercomputer such that the number of iterations is minimized, and wherein the total cost incurred is minimized; and in response to finding the value for at least one input parameter that at least approximately optimizes the function: stopping the iteration, and returning the found value for at least one input parameter that at least approximately optimizes the function by the digital supercomputer.

Generating a candidate value for at least one input parameter by the quantum computing system may include performing at least one of adiabatic quantum computation and quantum annealing by the quantum computing system. Transmitting the candidate value for at least one input parameter from the quantum computing system to the digital supercomputer may include transmitting the candidate value for at least one input parameter from the quantum computing system to the digital supercomputer by at least one of: a direct electrical connection, a wireless connection, a remote connection, or an Internet connection. The number of iterations in the plurality iterations may be greater than one, and optimizing the function may further include, for at least one iteration: providing feedback to the external computing system from the digital supercomputer based on evaluating the function based on the candidate value for at least one input parameter by the digital supercomputer, wherein feedback from an current one of the iterations may influence generating a candidate value for at least one input parameter by the quantum computing system in a next one of the iterations. The number of iterations in plurality iterations may be upper bounded by a value selected from a group consisting of: 1000, 100, and 10. Generating a candidate value for at least one input parameter by the quantum computing system may include generating multiple candidate values for the at least one input parameter by the quantum computing system, and may further include, for each iteration of the plurality of iterations: selecting a candidate value for the at least one input parameter from the multiple candidate values for the at least one input parameter by the external computing system. Selecting a candidate value for the at least one input parameter from the multiple candidate values for the at least one input parameter by the external computing system may include selecting a candidate value for the at least one input parameter that occurs most frequently among the multiple candidate values for the at least one input parameter by the external computing system. Generating a candidate value for at least one input parameter by the quantum computing system may include generating respective candidate values for multiple input parameters by the quantum computing system.

A hybrid computing system that optimizes a function based on at least one input parameter may be summarized as including: a quantum computing system that generates candidate values for the at least one input parameter, wherein the quantum computing system has a first rate of convergence; and a digital supercomputer that evaluates the function based on the at least one input parameter, wherein the digital supercomputer has a second rate of convergence, and wherein for a plurality of iterations: the quantum computing system generates a candidate value for the at least one input parameter, the quantum computing system calls the digital supercomputer to transmit the candidate value for the at least one input parameter to the digital supercomputer, and the digital supercomputer evaluates the function based on the candidate value for the at least one input parameter, until a value for the at least one input parameter that at least approximately optimizes the function is found, wherein the number of calls to the digital supercomputer from the quantum computing system is dependent on the first rate of convergence of the quantum computing system, and wherein the first rate of convergence of the quantum computing system is greater than the second rate of convergence of the digital supercomputer such that the number of calls to the digital supercomputer from the quantum computing system is minimized; and in response to finding the value for the at least one input parameter that at least approximately optimizes the function: the digital supercomputer returns the found value for the at least one input parameter that at least approximately optimizes the function.

The quantum computing system may include a superconducting quantum processor, and the quantum computing system may generate candidate values for the at least one input parameter by at least one of adiabatic quantum computation and quantum annealing. The quantum computing system and the digital supercomputer may be communicatively coupleable by at least one of a direct electrical connection, a wireless connection, a remote connection, and an Internet connection.

A method of operating both a quantum computing system and a digital supercomputer to at least approximately optimize a function based on at least one input parameter may be summarized as including, for a number of iterations: generating a candidate value for at least one input parameter by the quantum computing system; programming the digital supercomputer with the candidate value for at least one input parameter; and evaluating the function based on the candidate value for at least one input parameter by the digital supercomputer, until a value for at least one input parameter that at least approximately optimizes the function is found, wherein the number of iterations is dependent on a rate of convergence of the quantum computing system, and wherein the rate of convergence of the quantum computing system is greater than a rate of convergence of the digital supercomputer; and in response to finding a value for at least one input parameter that at least approximately optimizes the function: stopping the iteration; and returning the found value for at least one input parameter that at least approximately optimizes the function by the digital supercomputer.

The method of operating both a quantum computing system and a digital supercomputer to at least approximately optimize a function based on at least one input parameter may further include, for at least one iteration: providing feedback to the quantum computing system from the digital supercomputer based on evaluating the function based on the candidate value for at least one input parameter by the digital supercomputer, wherein feedback from an i th iteration may influence generating a candidate value for at least one input parameter by the quantum computing system in an (i+1) th iteration.

BACKGROUND

Field

Quantum Computing Systems

Digital Supercomputer

Rate of Convergence in Iterative Methods

BRIEF SUMMARY

The number of iterations may be selected from a group consisting of: a number less than 1000, a number less than 100, and a number less than 10. Generating a candidate value for at least one input parameter by the quantum computing system may include generating multiple candidate values for the at least one input parameter by the quantum computing system, and may further include, for each of the number of iterations: selecting a candidate value for the at least one input parameter from the multiple candidate values for the at least one input parameter by a digital computing system. Selecting a candidate value for the at least one input parameter from the multiple candidate values for the at least one input parameter by a digital computing system may include selecting a candidate value for the at least one input parameter that occurs most frequently among the multiple candidate values for the at least one input parameter by the digital computing system. Generating a candidate value for at least one input parameter by the quantum computing system may include generating respective candidate values for multiple input parameters by the quantum computing system.

A method of iteratively operating a hybrid computing system to solve a problem, the hybrid computing system comprising a quantum computing system having a first rate of convergence and a digital computing system having a second rate of convergence, wherein the quantum computing system and the digital computing system are in communication with one another and the first rate of convergence of the quantum computing system is greater than the second rate of convergence of the digital computing system may be summarized as including, for a number of iterations: generating a candidate solution to the problem by the quantum computing system; and evaluating the candidate solution to the problem by the digital computing system, until a candidate solution to the problem that satisfies at least one solution criterion is found, wherein the number of iterations is dependent on the first rate of convergence of the quantum computing system; and in response to finding a candidate solution to the problem that satisfies at least one solution criterion: stopping the iteration; and returning the found candidate solution that satisfies at least one solution criterion by the digital computing system.

Generating a candidate solution to the problem by the quantum computing system may include performing at least one of adiabatic quantum computation and quantum annealing by the quantum computing system.

The method of iteratively operating a hybrid computing system to solve a problem may further include, for at least one iteration, providing feedback to the quantum computing system from the digital computing system based on evaluating the candidate solution to the problem by the digital computing system, wherein feedback from an i th iteration may influence generating a candidate solution to the problem by the quantum computing system in an (i+1) th iteration.

The number of iterations may be selected from a group consisting of: a number less than 1000, a number less than 100, and a number less than 10. Generating a candidate solution to the problem by the quantum computing system may include generating multiple candidate solutions to the problem by the quantum computing system, and may further include, for each of the number of iterations: selecting a candidate solution to the problem from the multiple candidate solutions to the problem by the digital computing system. Selecting a candidate solution to the problem from the multiple candidate solutions to the problem by the digital computing system may include selecting a candidate solution to the problem that occurs most frequently among the multiple candidate solutions to the problem by the digital computing system. The problem may include optimizing a function based on at least one input parameter and wherein: generating a candidate solution to the problem by the quantum computing system may include generating a candidate value for at least one input parameter by the quantum computing system; and evaluating the candidate solution to the problem by the digital computing system may include evaluating the function based on the candidate value for at least one input parameter by the digital computing system.

A hybrid computing system may be summarized as including: a cryogenic refrigeration system that provides a refrigerated environment; a superconducting quantum processor positioned within the refrigerated environment and cooled by the cryogenic refrigeration system; and a superconducting digital processor positioned within the refrigerated environment and cooled by the cryogenic refrigeration system, wherein the superconducting digital processor is superconductively coupled to the superconducting quantum processor.

The cryogenic refrigeration system may include a dilution refrigerator thermally coupled to both the superconducting quantum processor and the superconducting digital processor.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)

In the drawings, identical reference numbers identify similar elements or acts. The sizes and relative positions of elements in the drawings are not necessarily drawn to scale. For example, the shapes of various elements and angles are not drawn to scale, and some of these elements are arbitrarily enlarged and positioned to improve drawing legibility. Further, the particular shapes of the elements as drawn are not intended to convey any information regarding the actual shape of the particular elements, and have been solely selected for ease of recognition in the drawings.

FIG. 1 is a schematic diagram of a portion of an exemplary superconducting quantum processor designed for AQC (and/or quantum annealing) that may be used in the present systems and methods

FIG. 2 is an illustrative graph showing a comparison between the rate of convergence of a quantum computing system and the rate of convergence of a digital computing system in accordance with the present systems and methods.

FIG. 3 is a flow-diagram showing a method of iteratively operating a hybrid computing system to solve a problem in accordance with the present systems and methods.

FIG. 4 is a flow-diagram showing a method of operating both a quantum computing system and a digital supercomputer to at least approximately optimize a function based on at least one input parameter in accordance with the present systems and methods.

FIG. 5 is a flow-diagram showing an exemplary method of minimizing a total cost incurred C T for consumption of digital supercomputer resources when a digital supercomputer is employed to optimize a function in accordance with the present systems and methods.

FIG. 6 is a schematic diagram of a hybrid computing system in accordance with the present systems and methods.

FIG. 7 is a schematic diagram of a hybrid computing system employing both a superconducting quantum processor and a superconducting digital processor within the same refrigerated environment in accordance with the present systems and methods.

FIG. 8 illustrates an exemplary digital computing system including a digital processor that may be used to perform classical digital processing tasks described in the present systems and methods.

DETAILED DESCRIPTION

In the following description, some specific details are included to provide a thorough understanding of various disclosed embodiments. One skilled in the relevant art, however, will recognize that embodiments may be practiced without one or more of these specific details, or with other methods, components, materials, etc. In other instances, well-known structures associated with quantum processors, such as quantum devices, coupling devices, and control systems including microprocessors, drive circuitry and nontransitory computer- or processor-readable media such as nonvolatile memory for instance read only memory (ROM), electronically erasable programmable ROM (EEPROM) or FLASH memory, etc., or volatile memory for instance static or dynamic random access memory (ROM) have not been shown or described in detail to avoid unnecessarily obscuring descriptions of the embodiments of the present systems and methods. Throughout this specification and the appended claims, the words âelementâ and âelementsâ are used to encompass, but are not limited to, all such structures, systems and devices associated with quantum processors, as well as their related programmable parameters.

Unless the context requires otherwise, throughout the specification and claims which follow, the word âcompriseâ and variations thereof, such as, âcomprisesâ and âcomprisingâ are to be construed in an open, inclusive sense, that is as âincluding, but not limited to.â

Reference throughout this specification to âone embodiment,â or âan embodiment,â or âanother embodimentâ means that a particular referent feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases âin one embodiment,â or âin an embodiment,â or âanother embodimentâ in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

It should be noted that, as used in this specification and the appended claims, the singular forms âa,â âan,â and âtheâ include plural referents unless the content clearly dictates otherwise. Thus, for example, reference to a problem-solving system including âa quantum processorâ includes a single quantum processor, or two or more quantum processors, including a grid or distributed network of multiple quantum processors. It should also be noted that the term âorâ is generally employed in its sense including âand/orâ unless the content clearly dictates otherwise.

The headings provided herein are for convenience only and do not interpret the scope or meaning of the embodiments.

The various embodiments described herein provide systems and methods for interacting with quantum computing systems. For example, the present systems and methods describe optimizing the use of a digital supercomputer by interacting with the digital supercomputer by a quantum computing system.

As previously described, a quantum computing system may include a quantum processor, and quantum processors may come in many different forms. As an illustrative example, a superconducting quantum processor designed to perform adiabatic quantum computation and/or quantum annealing is used in the description that follows. However, as previously described, a person of skill in the art will appreciate that the present systems and methods may be applied to any form of quantum processor hardware (e.g., superconducting, photonic, ion-trap, quantum dot, topological) implementing any form of quantum algorithm(s) (e.g., adiabatic quantum computation, quantum annealing, gate/circuit-based quantum computing).

Adiabatic quantum computation typically involves evolving a system from a known initial Hamiltonian (the Hamiltonian being an operator whose eigenvalues are the allowed energies of the system) to a final Hamiltonian by gradually changing the Hamiltonian. A simple example of an adiabatic evolution is a linear interpolation between initial Hamiltonian and final Hamiltonian.

H e =(1â s ) H In +sH f ââ(1)

where H In is the initial Hamiltonian, H f is the final or âproblemâ Hamiltonian, H e is the evolution or instantaneous Hamiltonian, and s is the evolution coefficient which controls the rate of evolution. In general, s may vary from 0 to 1 with time t as s(t). A common approach to adiabatic quantum computation (âAQCâ), described, for example, in M.H.S. Amin, 2008 âEffect of local minima on quantum adiabatic optimizationâ, Physical Review Letters , Vol. 100, 130503, is to start with an initial Hamiltonian of the form shown in Equation 2:

â¢

(

)

where N represents the number of qubits, Ï i x is the Pauli x-matrix for the i th qubit and Î i is the single qubit tunnel splitting induced in the i th qubit. Here, the Ï i x terms are examples of âoff-diagonalâ terms. An initial Hamiltonian of this form may, for example, be evolved to a final Hamiltonian of the form:

â¡

[

â¢

]

(

)

where N represents the number of qubits, Ï i z is the Pauli z-matrix for the i th qubit, h i and J ij are dimensionless local fields coupled into each qubit and the couplings between qubits, and Îµ is some characteristic energy scale for H f . Here, the Ï i z and Ï i z Ï j z terms are examples of âdiagonalâ terms. Throughout this specification, the terms âfinal Hamiltonianâ is used but âproblem Hamiltonianâ is a suitable term since the final Hamiltonian encodes the problem of interest. Hamiltonians such as H In and H f in Equations 2 and 3, respectively, may be physically realized in a variety of different ways. A particular example is realized by an implementation of superconducting qubits.

FIG. 1 is a schematic diagram of a portion of an exemplary superconducting quantum processor 100 designed for quantum annealing and/or adiabatic quantum computing that may be used in the present systems and methods. An alternative term for superconducting quantum processor 100 is superconducting quantum processor. The portion of superconducting quantum processor 100 shown in FIG. 1 includes two superconducting qubits

101 , 102 and a tunable diagonal coupler 111 coupling information therebetween (i.e., providing pair-wise coupling between qubits 101 and 102 ). While the portion of quantum processor 100 shown in FIG. 1 includes only two qubits

101 , 102 and one coupler 111 , those of skill in the art will appreciate that quantum processor 100 may include any number of qubits and any number of coupling devices coupling information therebetween.

The portion of quantum processor 100 shown in FIG. 1 may be implemented to physically realize QA and/or AQC by initializing the system with the Hamiltonian described by Equation 2 and evolving the system to the Hamiltonian described by Equation 3 in accordance with the evolution described by Equation 1. Quantum processor 100 includes a plurality of interfaces 121 - 125 that are used to configure and control the state of quantum processor 100 . Each of interfaces 121 - 125 may be realized by a respective inductive coupling structure, as illustrated, as part of a programming subsystem and/or an evolution subsystem. Such a programming subsystem and/or evolution subsystem may be separate from quantum processor 100 , or it may be included locally (i.e., on-chip with quantum processor 100 ) as described in, for example, U.S. Pat. Nos. 7,876,248 and 8,035,540.

In the operation of quantum processor 100 , interfaces

121 and 124 may each be used to couple a flux signal into a respective compound Josephson junction

131 , 132 of qubits

101 and 102 , thereby controlling the Ai terms in the system Hamiltonian. This coupling provides the off-diagonal of terms of the Hamiltonian described by Equation 2 and these flux signals are examples of âdisordering signals.â Similarly, interfaces 122 and 123 may each be used to couple a flux signal into a respective qubit loop of qubits

101 and 102 , thereby realizing the h i terms in the system Hamiltonian. This coupling provides the diagonal Ï z terms of Equation 3. Furthermore, interface 125 may be used to couple a flux signal into coupler 111 , thereby realizing the J ij term(s) in the system Hamiltonian. This coupling provides the diagonal Ï z i Ï z i terms of Equation 3. In FIG. 1 , the contribution of each of interfaces 121 - 125 to the system Hamiltonian is indicated in boxes 121 a - 125 a , respectively. Thus, throughout this specification and the appended claims, the terms âproblem formulationâ and âconfiguration of a number of programmable parametersâ are used to refer to, for example, a specific assignment of h i and J ij terms in the system Hamiltonian of a superconducting quantum processor by, for example, interfaces 121 - 125 .

In the context of quantum processor 100 , the term âprogramming subsystemâ is used to generally describe the interfaces (e.g., âprogramming interfacesâ 122 , 123 , and 125 ) used to apply the programmable parameters (e.g., the h i and J ij terms) to the programmable elements of quantum processor 100 and other associated control circuitry and/or instructions. As previously described, the programming interfaces of the programming subsystem may communicate with other subsystems which may be separate from the quantum processor or may be included locally on the processor. Similarly, in the context of quantum processor 100 , the term âevolution subsystemâ is used to generally describe the interfaces (e.g., âevolution interfacesâ 121 and 124 ) used to evolve the programmable elements of quantum processor 100 and other associated control circuitry and/or instructions. For example, the evolution subsystem may include annealing signal lines and their corresponding interfaces ( 121 , 124 ) to the qubits ( 101 , 102 ).

Quantum processor 100 also includes readout devices

141 and 142 , where readout device 141 is configured to read out the state of qubit 101 and readout device 142 is configured to read out the state of qubit 102 . In the embodiment shown in FIG. 1 , each of readout devices

141 and 142 comprises a respective DC-SQUID that is configured to inductively couple to the corresponding qubit ( qubits

101 and 102 , respectively). In the context of quantum processor 100 , the term âreadout subsystemâ is used to generally describe the readout devices

141 , 142 used to read out the final states of the qubits (e.g., qubits 101 and 102 ) in the quantum processor to produce a bit string. The readout subsystem may also include other elements, such as routing circuitry (e.g., latching elements, a shift register, or a multiplexer circuit) and/or may be arranged in alternative configurations (e.g., an XY-addressable array, an XYZ-addressable array, etc.). Qubit readout may also be performed using alternative circuits, such as that described in PCT Patent Application Publication 2012-064974. In accordance with the present systems and methods, readout devices

141 and 142 are coupled to a âmodule for transmitting readout values to a digital supercomputerâ 150 . A module, or a program module, is a set of processor readable instructions. Module 150 may receive readout values from readout devices

141 and 142 , store these values, and transmit these values to a digital supercomputer for the purpose of using the digital supercomputer to evaluate an objective function based on the readout values (as described in much greater detail later on). Module 150 may also perform the âselecting a candidate value from a plurality of candidate valuesâ tasks described later, for example, at act 302 of method 300 from FIG. 3 , act 402 of method 400 from FIG. 4 , and/or act 503 of method 500 from FIG. 5 .

While FIG. 1 illustrates only two physical qubits

101 , 102 , one coupler 111 , and two readout devices

141 , 142 , a quantum processor (e.g., processor 100 ) may employ any number of qubits, couplers, and/or readout devices, including a larger number (e.g., hundreds, thousands or more) of qubits, couplers and/or readout devices. The application of the teachings herein to processors with a different (e.g., larger) number of computational components should be readily apparent to those of ordinary skill in the art.

At least some of the devices illustrated in FIG. 1 are simplified in order to enhance clarity. As an example, the structure of the qubits ( 101 , 102 ) and the interface to the readout devices ( 141 , 142 ) are simplified in FIG. 1 in order to reduce clutter. While the simplified circuits of quantum processor 100 may be sufficient for some applications, a quantum processor may employ qubit circuits and/or readout schemes that are considerably more complicated than those which are illustrated in FIG. 1 .

<par

CLAIMS

Claims ( 12 )

1 .- 20 . (canceled)

21 . A method of operation of a hybrid computing system to perform a computational task, the computational task which includes a digital processing component and a quantum processing component, the hybrid computing system comprising a digital processor and a quantum processor, the digital processor and the quantum processor communicatively coupled to each other by a communication channel, the hybrid computing system further comprising a cryogenic refrigeration system that provides a refrigerated environment housing the digital processor, the quantum processor, and the communication channel, the cryogenic refrigeration system operable to cool the refrigerated environment to a temperature at which the digital processor, the quantum processor, and the communication channel become superconducting, the method comprising:

causing the digital processor to perform the digital processing component of the computational task while the digital processor is superconducting; causing the quantum processor to perform the quantum processing component of the computational task while the quantum processor is superconducting; and causing a communication between the digital processor and the quantum processor via the communication channel while the digital processor, the quantum processor, and the communication channel are superconducting to reduce a latency of communication and thereby reduce an overall computation time of the computational task, wherein each of the digital processing component and the quantum processing component of the computational task include at least one of a respective determining of a candidate solution, a respective generating of a value, or a respective optimizing of a function.

22 . The method of claim 21 wherein the causing the quantum processor to perform the quantum processing component of the computational task includes causing the quantum processor to perform the quantum processing component of the computational task where the quantum processor comprises a pair of superconducting qubits, and a superconducting coupling device that provides a communicative coupling between qubits of the pair of superconducting qubits.

23 . The method of claim 21 wherein the causing the quantum processor to perform the quantum processing component of the computational task includes causing the quantum processor to perform the quantum processing component of the computational task where the quantum processor comprises a pair of superconducting qubits, and a superconducting coupling device which includes a tunable diagonal coupler and that provides a communicative coupling between qubits of the pair of superconducting qubits.

24 . The method of claim 21 wherein the causing the quantum processor to perform the quantum processing component of the computational task includes causing the quantum processor to perform the quantum processing component of the computational task by performing at least one of quantum annealing computation or adiabatic quantum computation.

25 . The method of claim 21 wherein the causing the quantum processor to perform the quantum processing component of the computational task includes:

causing a programming of qubits of the pair of superconducting qubits; and

causing a programming of the superconducting coupling device, each of the programming the qubits and the programming the superconducting coupling device being performed via a respective programming interface.

26 . The method of claim 21 wherein the causing the digital processor to perform the digital processing component of the computational task includes causing the digital processor to perform the digital processing component of the computational task on at least one of single flux quantum logic circuitry or quantum flux parametron circuitry.

27 . The method of claim 21 wherein the causing the quantum processor to perform the quantum processing component of the computational task includes causing the quantum processor to perform the quantum processing component of the computational task in parallel with the performing the digital processing component of the computational task on the digital processor.

28 . The method of claim 27 , further comprising:

causing a comparing of a respective result from each of the quantum processing component of the computational task and the digital processing component of the computational task; and causing a returning of one of the respective results, as an output of the computational task, based at least in part on the comparing a respective result from each of the quantum processing component of the computational task and the digital processing component of the computational task.

29 . The method of claim 21 wherein:

the causing the quantum processor to perform the quantum processing component of the computational task includes causing the quantum processor to perform a quantum annealing; and

the causing the digital processor to perform the digital processing component of the computational task includes causing the digital processor to perform a simulated annealing.

30 . The method of claim 21 wherein the causing a communication between the digital processor and the quantum processor via the communication channel includes:

causing a transmitting of data from the quantum processor to the digital processor, the transmitting of data which includes a transmitting of an output of the quantum processing component of the computational task; and

causing a receiving of the data from the quantum processor by the digital processor, the receiving of the data which includes a receiving of an input to the digital processing component of the computational task.

31 . The method of claim 21 wherein the causing the digital processor to perform the digital processing component of the computational task includes causing the digital processor to perform a sampling process.

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Systems and methods for interacting with a quantum computing system — D-Wave Systems Inc. (US20210272010A1)

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