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Cryptography and key management device verification — Massachusetts Institute Of Technology (US10305870B2)

Massachusetts Institute Of Technology · Google Patents

Google Patents · Patents · License: Open Access

patent, google patents, intellectual property, US10305870B2, Massachusetts Institute Of Technology, Roger I. Khazan, en, 2019

ABSTRACT

Abstract

A method for operating a secure device having a plurality of mutually exclusive circuit zones, including a first circuit zone having a first level of security and a second circuit zone having a second level of security less than the first level of security, the method including unpacking a key exchange package including receiving a key exchange package in the second circuit zone, the key exchange package including encrypted key data and processing the encrypted key data using a content key in the first circuit zone to generate decrypted key data and storing the decrypted key data in the first circuit zone without disclosing the decrypted key data into the second circuit zone.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. application Ser. No. 13/937,919 filed Jul. 9, 2013, which claims the benefit of U.S. Provisional Applications No. 61/669,171, titled âSHAMROCK: Self Contained High-Assurance Micro Crypto and Key Management Processor,â and 61/669,179, titled âMethod for Securing Data using Hardware Functional Gates,â both filed Jul. 9, 2012, the contents of which are incorporated herein by reference.

STATEMENT AS TO FEDERALLY SPONSORED RESEARCH

This invention was made with government support under Contract No. FA8721-05-C-0002 awarded by the US Air Force. The government has certain rights in the invention.

BACKGROUND

This invention relates to a device and architecture for secure cryptography and key management.

Modern cryptography offers a variety of schemes for the protection of information at-rest on devices and in-transit among devices. A cryptographic scheme typically âscramblesâ or âunscramblesâ information using a data-permutation algorithm and a short cryptographic key. The security of the scheme depends on the properties of the algorithm and the quality and secrecy of the key. Thus, cryptographic keys need to be created and managed carefully. In particular, keys need to be protected at-rest and in-transit, which itself calls for the use of various cryptographic schemes.

Hardware implementations of cryptographic functions may exist today in hardware, for example as FPGA cores. There may also be special-purpose solutions that are coupled with applications and may implement some form of specialized key management. For example, HAIPE (High Assurance Internet Protocol Encryptor) devices implement a protocol based on the Internet Protocol Security (IPSec) standard for establishing and securing Internet Protocol (IP) communication among devices.

Although many cryptographic schemes have been standardized and implemented efficiently in software and hardware, these solutions are not universally used or embedded in devices. In general, this is the case due to two main reasons:

a. The lack of generic, easy-to-deploy, and easy-to-use solutions for key management, and b. The challenge of integrating various cryptographic and key management components into a holistically secure design.

While individual cryptographic components exist and may be known to be secure, there is no known ârecipeâ for integrating different components into secure designs that guarantee security of keys and other information, at-rest and in-transit. It is in such integration that major challenges exist and vulnerabilities are often times introduced.

SUMMARY

In one general aspect, a self-contained, integrated general-purpose design and architecture for a cryptography and key-management solution can be realized as an integrated circuit core, such as, for example, a Field Programmable Gate Array (FPGA) core or an application-specific integrated circuit (ASIC) core.

The key management tasks may include operations such as creating cryptographic keys, associating keys with their purposes, protecting keys at rest in both volatile and non-volatile memory, making keys available for authorized encryptions and authorized decryptions, delivering keys securely to authorized remote devices, archiving keys, evolving keys with time, retiring keys, etc.

Some implementations attain high performance, low power, flexibility, and extensibilityâall at the same time. This is achieved by implementing certain, typically computationally demanding components, such as the standard cryptographic functions, directly in hardware (for example using VHDL), while other components, such as key management protocols, in a higher-level language, such as C, in a softcore micro-controller inside the integrated circuit. The softcore micro-controller, allows for different key management protocols and their extensions to be easily created for and deployed in the architecture, even after the integrated circuit core is manufactured and integrated into an application. The hardware implementations of the cryptographic components used by the application and by the key management components facilitate lower-power, higher-speed operations.

Embodiments of the architecture achieve assured security by separating its internals into a number of physical regions (also referred to as âzonesâ or âcircuit zonesâ in some examples), and tightly controlling which information flows from one region into another and how it does so. The separation among the different regions is enforced by hardware, through the physical layout of the regions and by their interconnections in the integrated circuit.

In some examples, a device has a dedicated region for storing and handling long-term cryptographic keys of the device (such as the ones used for authenticating the device's identity), another region for storing and handling short-term keys (such as the ones used for securing communication sessions), and yet another region for storing and handling information that does not contain exposed secrets (such as encrypted keys). The only physical paths from a region that handles cryptographic keys to the region that interfaces with the application is by going through a âscramblerâ circuit (also referred to as a âgate circuitâ or âhardware functional gateâ in some examples) such as a secure hash function or an AES encryption function. This restricted physical connectivity completely prevents a possibility of keys inadvertently leaking out due to a logical control flow problem in the design.

The hardware-enforced separations among the regions greatly simplifies the task of establishing and verifying security properties of the design and reduce the possibilities of a design bug or an attack compromising these security properties. In contrast, logical separation of regions, which uses logical âguardsâ to control and restrict the flow of information among the regions, leaves the regions physically connected and, thus, at some level, allow for a possibility that a malfunction or an attack will lead to an undesired flow of information from one region to another, and to a security problem.

Key management operations often involve coordinated processing in different regions, with information flowing among them. In some examples, the key management component allows for such coordinated processing and the necessary flow of information to occur, despite the physical separations among the regions.

The physical separation of the regions that handle keys from those that do not allows for the latter types to use memory that is external to the integrated circuit. Such external memory may be less expensive than and not be as much size-limited as the integrated circuit's internal memory. The device can protect confidentiality and integrity of the information placed in the external memory with encryption.

In some aspects, hardware functional gates include Elliptic Key Diffie-Hellman cryptography gates, true and pseudo-random number generators, signature verification gates, signing gates, Message Authentication Code (e.g., HMAC) gates, and so on.

In some aspects sensors, cameras, and other external hardware devices can be arbitrarily assigned to a security zone.

In some aspects, the general term âcryptographic processingâ relates to cryptographic operations such as encryption, decryption, digital signing, digital signature verification, secure hashing, key generation, and so on.

In another aspect, in general, a circuit for secure operation includes a number of mutually exclusive circuit zones including a first circuit zone having a first level of security and a second circuit zone having a second level of security less than the first level of security; and one or more gate circuits each providing limited transfer of data between the circuit zones, the gate circuits providing all data connectivity between the first circuit zone and the second circuit zone and statically configured to prevent unmodified transfer of data from the first circuit zone to the second circuit zone.

Aspects may include one or more of the following.

Each gate circuit may implement a function defined by its circuit to process input data and provide output data via interfaces, each of the interfaces located in a single corresponding circuit zone of the plurality of circuit zones. The function implemented by at least some of the gate circuits may include a cryptographic procedure utilizing a cryptographic key. Each of the one or more gate circuits may follow a design that enforces a security policy with the interfaces located in the corresponding circuit zones to prevent unmodified transfers of data between at least some of said circuit zones. The one or more gate circuits may include one or more of an encryption gate circuit, a controlled transfer gate circuit, a decryption gate circuit, a signing gate circuit, a secure hash function gate circuit, and a public key generation gate circuit. Each circuit zone of at least some of the circuit zones may include a memory local to that circuit zone, wherein at least some of the gate circuits include an interface for accessing memory locations in said memory.

The gate circuits may include an encryption gate circuit configured to accept a key via a first interface in the first circuit zone, to accept unencrypted data via a second interface, and to provide encrypted data via third interface in the second circuit zone. The gate circuits may include a decryption gate circuit configured to accept a key via a first interface in the first circuit zone, to accept encrypted data via a second interface in the second circuit zone, and to provide decrypted data via a third interface in the second circuit zone. The first circuit zone may include a key generation circuit for generation of a key value without disclosure of said key value to the second circuit zone. The device may be configured to use a key value provided to a gate circuit to encrypt data in at least one of the first circuit zone and the second circuit zone to provide corresponding encrypted data to the second circuit zone without disclosure of the key value into the second circuit zone.

The device may be configured to use a key value provided to a gate circuit to decrypt data in the second circuit zone to provide corresponding decrypted data to the first circuit zone without disclosure of the key value into the second circuit zone. The circuit may include a key initialization circuit comprising at least one of a non-volatile storage in the first circuit zone, a Physical Unclonable Function (PUF) in the first circuit zone, and port for passing a value from outside the device to the first circuit zone. The device may include a programmable processor located outside the first security zone, wherein the circuit is configured to validate software for controlling the processor according to key values stored in the first circuit zone. The device may include a Field Programmable Gate Array (FPGA) configured according to configuration data to implement circuit zones and gate circuits. The device may include an Application Specific Integrated Circuit (ASIC).

In another aspect, in general, data stored on a non-transitory computer readable medium includes configuration instructions for configuring a circuit having a plurality of mutually exclusive circuit zones including a first circuit zone having a first level of security and a second circuit zone having a second level of security less than the first level of security and one or more gate circuits each providing limited transfer of data between the circuit zones, the gate circuits providing all data connectivity between the first circuit zone and the second circuit zone and statically configured to prevent unmodified transfer of data from the first circuit zone to the second circuit zone.

Aspects may include one or more of the following features.

The configuration instructions may include hardware description language (HDL) instructions. The configuration instructions may include instructions for configuring a Field Programmable Gate Array (FPGA).

In another aspect, in general, a method for operating a device having a first circuit zone having a first level of security and a second circuit zone, mutually exclusive from the first circuit zone and having a second level of security less than the first level of security includes maintaining data in the first circuit zone, providing first data in the first circuit zone to an interface in the first circuit zone to a first gate circuit, the first gate circuit coupling the first circuit zone and the second circuit zone, processing the first data in a first gate circuit to produce second data, providing the second data from the first gate circuit through a second interface in the second circuit zone, wherein the first gate circuit is configured by its circuit design to process the first data to produce the second data such that disclosure of the second data does not disclose of the first data.

Aspects may include one or more of the following features.

Processing the first data in the first gate circuit to produce second data may include forming the second data according to a cryptographic procedure according to a key value in the first data. The cryptographic procedure may include at least one of an encryption procedure, a signing procedure, and a public key generation procedure. Processing the first data in the first gate circuit to produce second data may include forming the second data as a secure hash of the first data.

The method may further include maintaining third data in the second circuit zone, providing the third data in the second circuit zone to a third interface in the second circuit zone to a second gate circuit, the second gate circuit coupling the first circuit zone and the second circuit zone, processing the third data in a second gate circuit to produce fourth data, providing the fourth data from the second gate circuit through a fourth interface in the first circuit zone, wherein the second gate circuit is configured by its circuit design to process the third data to produce the fourth data such that disclosure of the fourth data does not disclose the third data.

Processing the third data in the second gate circuit to produce fourth data may include forming the fourth data according to a decryption procedure according to a key value in the first circuit zone.

In another aspect, in general, a method for operating a secure device having a plurality of mutually exclusive circuit zones, including a first circuit zone having a first level of security and a second circuit zone having a second level of security less than the first level of security, the method includes unpacking a key exchange package, the unpacking including receiving a key exchange package in the second circuit zone, the key exchange package including encrypted key data and processing the encrypted key data using a content key in the first circuit zone to generate decrypted key data and storing the decrypted key data in the first circuit zone without disclosing the decrypted key data into the second circuit zone.

Aspects may include one or more of the following features.

The key exchange package may include header data and the method further comprises processing the header data to generate the content key and storing the content key in the first circuit zone without disclosing the content key into the second circuit zone. The key exchange package may include encrypted key associated data and the method may further include processing a data item in the first circuit zone with a non-invertible function to generate a modified data item and storing the modified data item in the second circuit zone, and processing the encrypted key associated data using the modified data item to generate decrypted key associated data and storing the decrypted key associated data in the second circuit zone. The data item may include the content key.

The method may further include cryptographically processing data in the second circuit zone using the decrypted key data without disclosing the

CROSS-REFERENCE TO RELATED APPLICATIONS

STATEMENT AS TO FEDERALLY SPONSORED RESEARCH

This invention was made with government support under Contract No. FA8721-05-C-0002 awarded by the US Air Force. The government has certain rights in the invention.

BACKGROUND

This invention relates to a device and architecture for secure cryptography and key management.

SUMMARY

In some aspects sensors, cameras, and other external hardware devices can be arbitrarily assigned to a security zone.

Aspects may include one or more of the following.

Aspects may include one or more of the following features.

Processing the third data in the second gate circuit to produce fourth data may include forming the fourth data according to a decryption procedure according to a key value in the first circuit zone.

Aspects may include one or more of the following features.

The method may further include cryptographically processing data in the second circuit zone using the decrypted key data without disclosing the decrypted key data into the second circuit zone. Cryptographically processing the data may include encrypting the data into the second circuit zone using the decrypted key data. Cryptographically processing the data may include decrypting the data into the second circuit zone using the decrypted key data. The secure device may include a plurality of gate circuits providing limited transfer of data between the circuit zones, the gate circuits providing all data connectivity between the first circuit zone and the second circuit zone and preventing unmodified transfer of data from the first circuit zone to the second circuit zone. Processing the encrypted key data using the content key to generate decrypted key data may include using a decryption gate circuit to decrypt the encrypted key data using the content key.

Processing the data item to generate a modified data item may include using a secure hash gate circuit to compute a secure hash of the data item. Processing the encrypted key associated data using the modified data item may include using a decryption circuit to decrypt the encrypted key associated data using the modified data item. At least some of the plurality gate circuits providing connectivity between the first circuit zone and the second circuit zone may store data in the first circuit zone. The method may further include performing a cryptographic exchange with another secure device including using a decryption gate circuit to decrypt data received from the other device in the second circuit zone using the decrypted key data without disclosure of the decrypted key data into the second circuit zone.

The method may further include performing a cryptographic exchange with another secure device including using an encryption gate circuit to encrypt data in the second circuit zone using the decrypted key data without disclosure of the decrypted key data into the second circuit zone. The secure device may include a root circuit zone having a third level of security greater than the first level of security and the second level of security, and processing the header data in the second circuit zone to generate the content key in the first circuit zone includes using a key agreement key in the root circuit zone. Decrypted key associated data may include key metadata associated with the decrypted key data.

In another aspect, in general, a method for operating one or more secure devices, each having a plurality of mutually exclusive circuit zones, including a first circuit zone having a first level of security and a second circuit zone having a second level of security less than the first level of security, the method including processing, at a sending device, key data using a content key to generate encrypted key data and storing the encrypted key data in the second circuit zone without disclosing the key data into the second circuit zone, packaging the encrypted key data into a key exchange package, and transmitting the key exchange package to one or more receiving devices.

Aspects may include one or more of the following features.

The method may further include processing, at the sending device, a data item in the first circuit zone using a non-invertible function to generate a modified data item and storing the modified data item in the second circuit zone without disclosing the data item into the second circuit zone processing, at the sending device, key associated data using the modified data item to generate encrypted key associated data and storing the encrypted key associated data in the second circuit zone, and packaging the encrypted key associated data into the key exchange package.

The method may further include processing, at the sending device, private key data in the first circuit zone to generate header data and storing the header data in the second circuit zone, and packaging the header data into the key exchange package.

The one or more secure devices may include a plurality of gate circuits providing limited transfer of data between the circuit zones, the gate circuits providing all data connectivity between the first circuit zone and the second circuit zone and preventing unmodified transfer of data from the first circuit zone to the second circuit zone. Processing key data using a content key to generate the encrypted key data may include using an encryption gate circuit to encrypt the key data using the content key. Processing the data item to generate a modified data item may include using a secure hash gate circuit to compute a secure hash of the data item. Processing the key associated data using the modified data item may include using an encryption circuit to encrypt the key associated data using the modified data item in the second circuit zone. At least some of the plurality gate circuits providing connectivity between the first circuit zone and the second circuit zone may store data in the first circuit zone.

The method may further include receiving the key exchange package in a second circuit zone of a receiving device, the key exchange package including encrypted key data, processing, at the receiving device, the encrypted key data using a content key in the first circuit zone to generate decrypted key data and storing the decrypted key data in the first circuit zone of the receiving device without disclosing the content key into the second circuit zone of the receiving device. The key exchange package may include header data and the method may further include processing, at the receiving device, the header data to generate a content key and storing the content key in the first circuit zone of the receiving device without disclosing the content key into the second circuit zone of the receiving device.

The key exchange package may include encrypted key associated data and the method may further include processing, at the receiving device, a data item with a non-invertible function to generate a modified data item and storing the data item in the second circuit zone of the receiving device without disclosing the data item into the second circuit zone of the receiving device; and processing, at the receiving device, the encrypted key associated data using the modified data item to generate decrypted key associated data and storing the decrypted key associated data in the second circuit zone. The data item may include the content key.

In another aspect, in general, a method for establishing group key data among a plurality of secure devices, each secure device having a plurality of mutually exclusive circuit zones, including a first circuit zone having a first level of security and a second circuit zone having a second level of security less than the first level of security including receiving the key exchange package in a second circuit zone of each of the secure devices, the key exchange package including encrypted key data, establishing a shared key data in the first circuit zone of each of the secure devices including, for each of the secure devices, processing the encrypted key data using a content key to generate decrypted key data and storing the decrypted key data in the first circuit zone of each of the secure device without disclosing the content key into the second circuit zone of the secure device, securely exchanging messages between the secure devices, the messages being processed by the shared key data.

Aspects may include one or more of the following features.

The method may further include distributing the key exchange package from a secure computer server.

In another aspect, in general, a method for computer-implemented verification of security of a device includes accepting data comprising a circuit description of the device, identifying using a computer a plurality of mutually independent circuit zones from the circuit description such that no data paths pass between said circuit zones, identifying a plurality of gate circuits providing data paths between the circuit zones, the gate circuits being verified to limit unmodified transfer of data between zones by their circuitry according to a security policy, and verifying that the security device complies with the security policy according to whether all data paths between the circuit zones are via the identified gate circuits according to the security policy.

Aspects may include one or more of the following features.

The method may further include using a computer to verify that the gate circuits limit unmodified transfer of data between zones by their circuitry according to the security policy. Accepting the circuit description of the device may include accepting a specification of the circuit zones of the device. The method may further include associating a security index with each circuit zone, and wherein verifying that the security device complies with the security policy comprises verifying that the security indices of interfaces between the gate circuits and the circuit zones satisfy the security policy.

Other features and advantages of the invention are apparent from the following description, and from the claims.

DESCRIPTION OF DRAWINGS

FIG. 1 is a hardware functional gate (HFG).

FIG. 2 is first encryption HFG.

FIG. 3 is a controlled transfer HFG.

FIG. 4 is a second encryption HFG.

FIG. 5 is a decryption HFG.

FIG. 6 is a digital signing HFG.

FIG. 7 is a secure hash function HFG.

FIG. 8 is a public key generation HFG.

FIG. 9 is a device including a number of HFGs.

FIG. 10 is a secure boot procedure.

FIG. 11 is an unlock procedure.

FIG. 12 is a provisioning procedure.

FIG. 13 is a first part of a keywrap generation procedure.

FIG. 14 is a second part of a keywrap generation procedure.

FIG. 15 is a first part of a key unwrap procedure.

FIG. 16 is a second part of a key unwrap procedure.

FIG. 17 is a key fob application of a key management and cryptography device.

FIG. 18 is a secure telephony application of a key management and cryptography device.

FIG. 19 is a secure processing application of a key management and cryptography device.

FIG. 20 is an unmanned aerial vehicle (UAV) group keying application of a key management and cryptography device.

DESCRIPTION

The description below focuses on a security architecture for an integrated device that incorporates cryptographic and key management functions. In some implementations, the device is a standalone device (e.g., an integrated circuit), which may be integrated with host or peripheral devices, but it should be understood that the elements described below may be further integrated, for example, in a larger monolithic device. Also, devices that are structured according to the architecture may be implemented using a variety of technologies, including but not limited to field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs), and may include a combination of dedicated circuitry for specific functions as well programmable embedded processing cores. Although useful functionality may be achieved using a single device, multiple devices each following the architecture may interact using the integrated cryptographic and key management functions to achieve secure communication between or distributed operation (e.g., identity management) of multiple devices, and devices following the architecture may interact with other secure systems that implement consistent security policies, but that do not necessarily themselves follow the same architecture.

At a very general level, a device following the security architecture includes multiple different security âzones.â Each zone is associated with a security level, such that for at least some pairs of zones, one zone may be designated to be less secure than the other. In some examples, the security level for each zone is designated by non-negative integer index, which in this document as a matter of convention has a lower value indicating a greater degree of security (i.e., security index 0 is the most secure level), and therefore the security order of any two zones is determined by the security indices of the zones. It should be understood that in some implementations, the zones are only partially ordered according to their security levels and therefore the relative security level of certain pairs of zones is not defined.

Each security zone has associated circuitry that implements functions and transformations of data within that zone. Although circuitry implementing the functions within a circuit zones may be physically separated in the layout of a particular device, logical separation of the zones is a primary factor that permits verification of the design of a particular device as satisfying a security policy. In some examples, logical separation means that none of the circuitry related to data paths of a given security zone is connected to the circuitry related to data paths of another security zone except rigorously verified gate circuitry. Such logical separation may be verified, for example, using automated tools using a hardware description language (HDL) specification of the circuitry without necessarily making use of a layout of that circuitry on a device. Furthermore, various types of circuitry may be used to implement functions within any particular zone. For example, both dedicated logic circuitry and instruction (e.g., software) based processors may be used within any particular zone, as long as the inter-zone communication follows the security policy as discussed below.

In some implementations, circuitry implementing security zones may have further separations for security or other technical considerations. For example, different security zones may operate in different clock domains with clock signals being generated independently in some zones from other zones. Similarly, different security zones may operate in different power zones, thereby permitting power control within zones to control energy consumption, temperature etc., and potentially to control leakage of information between zones.

As an example of use of security zones, in some examples, information at a zone at security index 0 may include root cryptographic keys, which if exposed could compromise security of numerous systems or communication links. On the other hand, information at a security index 1 may include session cryptographic keys, which if exposed may compromise security of a single communication link, but may not lead to the degree of undesired access that would result from exposure of a root key.

The security architecture is based on a security policy in which exchange and use of data within a particular security level (e.g., in a particular security zone) is relatively unrestricted, but exchange of information between security levels is limited to enforce the security policy. An example of a policy related to exchange of information between security levels is that a data element at one security level may not pass to a lower security (e.g., higher security index) zone unless it is suitably hashed or encrypted with a key restricted to the higher security zone.

1 Hardware Functional Gates

In order to verify that a particular device follows the security policy, only a limited set of functional elements are permitted to have inputs and output that are in multiple different zones, and therefore can be thought of as âbridgesâ between zones or functionally âgatingâ communication and transfer of information between zones. These elements are referred to as âHardware Functional Gatesâ (HFG) or âgate circuitsâ below, without intending to limit any characteristic of such elements by this nomenclature. A set of HFG that have been verified to satisfy a desired security policy can then be used to interconnect the otherwise isolated circuits of the security zones. Verification of the HFG can use one or more of a variety of techniques including manual verification, use of formal verification procedures (e.g., proofs of correctness), and simulation or enumeration of operation of the HFG. Verification that the overall circuit satisfies the security policy is done by a static analysis of the circuitry of the device to ensure that the interconnections between zones appropriately (i.e., according to the security policies) use the HFGs, for example, using automated tools that using a hardware description language (HDL) specification of the circuitry without necessarily making use of a layout of that circuitry on a device. The HFG can be considered to be a set of âbuilding blocksâ that can be used to implement complex security procedures or protocols, such that the overall implementations can be easily verified to adhere to the security policy by virtue of appropriate use of the HFGs.

Referring to FIG. 1 , one example of an HFG is an encryption HFG 102 bridging two security zones (i.e., Zone 1 104 and Zone 2 106 ). The encryption HFG 102 has two input interfaces and one output interface. One input (K) is for a cryptographic key, and one input (D) is for a data item. In this example, both of the input interfaces are located in the same security zone (i.e., Zone 1 ). The output (E) is for an encryption of the data item using the key. In this example, the output interface is located in security Zone 2 which has a lower level of security (and a higher security index) than the security zone of the input interfaces (i.e., Zone 1 ). Furthermore, there is a control interface 109 , which may be configured to accept a signal (e.g., âgoâ) that causes the HFG to perform its function and provides a signal (e.g., âdoneâ) indicating that the function has been completed.

The HFG has an associated security policy, which dictates allowable security indexes to which the interfaces of the HFG may be coupled. If Z(K) indicates the security index of the zone to which the key (K) input is coupled, and similarly Z(D) and Z(E) indicates the zones of the data input and encryption output, respectively, then a rule for use of the HFG may be that Z(E)â¥Z(K) and Z(K)â¤Z(D). This rule can be paraphrased as the data D must be encrypted with a key (K) at the same or higher security level (same or lower security index), and the encryption of the data E may be provided by the HFG to a zone at the same of lower security level (higher security index) as the zone of the key input.

As introduced above, an overall circuit design is verified to adhere to a security policy if the circuit topology can be divided into separate zones (i.e., circuit subgraphs of possible data flow) with the only linkages for possible data flow between zones being restricted to HFGs whose interface circuits are coupled to particular zones consistent with their security policies.

In general, each security zone has distinct memory for use within the zone and for providing inputs to and storing outputs from the HFG. In some examples, the memories of the zones include an addressable memory block of volatile memory. In some examples in which an HFG is designed to use the memories in the zones it interfaces with, the control interface to the HFG accepts a command that identifies the address(es) of the inputs and outputs. For instance, for the encryption HFG discussed above, rather than the control interface simply accepting a âgoâ and providing a âdoneâ signal, the control interface may accept an input address for each of the key and data inputs, and an output address for the encrypted output. Note that these addresses are interpreted in the zones associated with the corresponding interfaces. At least conceptually each zone can be considered to have its own address space that is only accessible from circuitry within that zone or from interfaces assigned to that zone. In some cases, the control interface may accept parameters for the function (e.g., in addition to addresses). For example, a length of a data block to be encrypted may be provided to the HFG (e.g., âencrypt a block of n bytes at address addr 1 using a key at addr 2 , and save the result in a block of memory at address addr 3 â). In some examples, circuitry in a zone may be implemented using a bus-based architecture in which each of the HFG and a memory block in the zone, as well as other intra zone circuitry or processing units, are on a common zone-specific bus, which supports the read and write memory operations in the address space for that zone.

Referring to FIGS. 2-7 , an example of a non-exhaustive set of HFGS that can be used to implement a variety of devices includes a first embodiment of an encryption HFG, a controlled transfer HFG, a second embodiment of an encryption HFG, a decryption HFG, a signing HFG, a secure hash HFG, and a public key generation HFG.

1.1 First Encryption HFG

Referring to FIG. 2 , the first embodiment of the encryption HFG 202 (which is similar to the encryption HFG 102 of FIG. 1 ) is shown bridging a first security zone (i.e., Zone 1 ) 204 and a second security zone (i.e., Zone 2 ) 206 . The encryption HFG 202 is configured to encrypt a data item (D) stored in the first security zone 204 using an encryption key (K) stored in the first security zone 204 to produce an encrypted data item E K (D) which it stores in the second security zone 206 . Different instances of such an encryption HFG may implement symmetric encryption (e.g., AES) or asymmetric encryption (e.g., RSA) procedures. The encryption HFG 202 has an associated security policy. The security policy ensures that no secret information (e.g., the encryption key or plaintext D) is inadvertently transferred from the first security zone 204 to the second security zone 206 through the encryption HFG 202 . The security policy also ensures that the encryption HFG 202 does not allow data from lower security zones to be arbitrarily placed into higher security zones and later (inadvertently or maliciously) used as a key to exfiltrate other keys or data from the higher security zones into the lower security zones. As is described above, the security policy for any encryption HFG 202 is specified such that the data item D must be encrypted with a key (K) at the same or higher security level (same or lower security index), and the encryption of the data E K (D) may be provided by the HFG to a zone at the same or lower security level (higher security index) as the zone of the key input. As was noted above, this security policy can be concisely stated as: Z(E)â¥Z(K) and Z (K)â¤Z(D). The first embodiment of the encryption HFG 202 complies with the security policy since encryption of the data E is provided by the HFG to a zone (i.e, Zone 2 ) with a lower security level (higher security index) than the zone (i.e., Zone 1 ) of the key input and the data item D is encrypted with an encryption key K at a zone (i.e., Zone 1 ) having the same security level (the same security index) as the zone (i.e, Zone 1 ) associated with the data item (i.e., Z(E)>Z(K) and Z(K)=Z(D)).

To receive input data, the encryption HFG 202 includes a data item input interface 203 and an encryption key input interface 205 both located in the first security zone 204 . To provide output data, the encryption HFG 202 includes an encrypted data item output interface 207 located in the second security zone 206 . The data item input interface 203 and the encryption key input interface 205 are connected to a Zone 1 memory 212 via a Zone 1 bus 208 . The encrypted data item output interface 207 is connected to a Zone 2 memory 214 via a Zone 2 bus 210 .

In some examples, the encryption HFG 202 includes a control interface 209 which receives commands from a controller (not shown). In one exemplary operation of the encryption HFG 202 , the control interface 209 receives a command from the controller instructing the encryption HFG 202 to encrypt a data item (D) at a first address, addr 1 , in the Zone 1 memory 212 using an encryption key (K) at a second address, addr 2 , in the Zone 1 memory 212 and to store the resulting encrypted data item (E K (D)) at a third address, addr 3 , in the Zone 2 memory 214 .

The command causes the encryption HFG 202 to read the data item from addr 1 of the Zone 1 memory 212 and the encryption key from addr 2 of the Zone 1 memory 212 via the Zone 1 bus 108 . In some examples, the encryption HFG 202 reads the data item and the encryption key from the Zone 1 memory 212 in parallel. In other examples, the data item and the encryption key are sequentially read from the Zone 1 memory 212 and stored (e.g. latched) by the encryption HFG 202 . Once the encryption HFG 202 receives the data item and the encryption key at their respective input interfaces 203 , 205 , the encryption HFG 202 applies an encryption algorithm (e.g., the Advanced Encryption Standard (AES) encryption algorithm) to encrypt the data item using the encryption key. The encryption HFG 202 stores the resulting encrypted data item at addr 3 of the Zone 2 memory 214 via the Zone 2 bus 210 .

Since the encryption HFG 202 conforms to the security policy described above and includes verified hardware which does not allow lea

CLAIMS

Claims ( 14 )

What is claimed is:

1. A method for computer-implemented verification of security of a device comprising:

accepting data comprising a circuit description of the device;

identifying using a computer a plurality of mutually independent circuit zones from the circuit description such that no data paths pass directly between said circuit zones;

identifying a plurality of gate circuits providing data paths linking the circuit zones, the gate circuits being verified to limit unmodified transfer of data between zones by their circuitry according to a security policy; and

verifying that the device complies with the security policy according to whether all data paths between the circuit zones are via the identified gate circuits according to the security policy.

2. The method of claim 1 further comprising using a computer to verify that the gate circuits limit unmodified transfer of data between zones by their circuitry according to the security policy.

3. The method of claim 1 wherein accepting the circuit description of the device includes accepting a specification of the circuit zones of the device.

4. The method of claim 1 further comprising associating a security index with each circuit zone, and wherein verifying that the device complies with the security policy comprises verifying that the indices of interfaces between the gate circuits and the circuit zones satisfy the security policy.

5. The method of claim 1 wherein verifying that the device complies with the security policy includes performing a static analysis of the circuit description of the device.

6. The method of claim 1 wherein verifying that the device complies with the security policy includes determining that the plurality of gate circuits abide by the security policy.

7. The method of claim 1 wherein verifying that the device complies with the security policy includes determining that the circuitry associated with each circuit zone of plurality of mutually independent circuit zones is mutually exclusive from the circuitry associated with all other circuit zones of the plurality of mutually independent circuit zones.

8. A non-transitory machine-readable medium comprising instructions stored thereon, where the instructions when executed by a data processing system to verify security of a device, the verifying comprising:

accepting data comprising a circuit description of the device;

identifying using a computer a plurality of mutually independent circuit zones from the circuit description such that no data paths pass directly between said circuit zones;

verifying that the device complies with the security policy according to whether all data paths between the circuit zones are via the identified gate circuits according to the security policy.

9. The non-transitory machine-readable medium of claim 8 wherein the verifying further comprises using a computer to verify that the gate circuits limit unmodified transfer of data between zones by their circuitry according to the security policy.

10. The non-transitory machine-readable medium of claim 8 wherein accepting the circuit description of the device includes accepting a specification of the circuit zones of the device.

11. The non-transitory machine-readable medium of claim 8 wherein the verifying further comprises associating a security index with each circuit zone, and wherein verifying that the device complies with the security policy comprises verifying that the security indices of interfaces between the gate circuits and the circuit zones satisfy the security policy.

12. The non-transitory machine-readable medium of claim 8 wherein verifying that the device complies with the security policy includes performing a static analysis of the circuit description of the device.

13. The non-transitory machine-readable medium of claim 8 wherein verifying that the device complies with the security policy includes determining that the plurality of gate circuits abide by the security policy.

14. The non-transitory machine-readable medium of claim 8 wherein verifying that the device complies with the security policy includes determining that the circuitry associated with each circuit zone of plurality of mutually independent circuit zones is mutually exclusive from the circuitry associated with all other circuit zones of the plurality of mutually independent circuit zones.

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Ceased

2013-07-09

US13/937,884

patent/US10728231B2/en

active

Active

2013-07-09

US13/937,919

patent/US9705854B2/en

active

Active

2015

2015-06-08

US14/733,231

patent/US20150381592A1/en

not_active

Abandoned

2015-06-08

US14/733,325

patent/US10305870B2/en

active

Active

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2011-10-11

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2006-09-05

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( en )

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2006-01-05

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