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Hybrid bonding systems and methods for semiconductor wafers — Taiwan Semiconductor Manufacturing Company (US10354972B2)

Taiwan Semiconductor Manufacturing Company · Google Patents

Google Patents · Patents · License: Open Access

patent, google patents, intellectual property, US10354972B2, Taiwan Semiconductor Manufacturing Company, Ping-Yin Liu, en, 2019

ABSTRACT

Abstract

Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No. 15/689,982, filed on Aug. 29, 2017, which is a continuation of U.S. application Ser. No. 14/725,266, filed May 29, 2015, now U.S. Pat. No. 9,748,198 issued Aug. 29, 2017, which is a continuation of U.S. application Ser. No. 13/542,507, filed on Jul. 5, 2012, now U.S. Pat. No. 9,048,283 filed Jun. 2, 2015, which applications are hereby incorporated herein by reference.

This application relates to the following commonly assigned patent application: Ser. No. 13/488,745, filed on Jun. 5, 2012, entitled, âThree Dimensional Integrated Circuit Structures and Hybrid Bonding Methods for Semiconductor Wafers,â which application is hereby incorporated herein by reference.

BACKGROUND

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. Dozens or hundreds of integrated circuits are typically manufactured on a single semiconductor wafer, and individual dies on the wafer are singulated by sawing between the integrated circuits along a scribe line. The individual dies are typically packaged separately, in multi-chip modules, or in other types of packaging, for example.

The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. These smaller electronic components also require smaller packages that utilize less area than packages of the past, in some applications.

Three dimensional integrated circuits (3DICs) are a recent development in semiconductor packaging in which multiple semiconductor dies are stacked upon one another, such as package-on-package (PoP) and system-in-package (SiP) packaging techniques. 3DICs provide improved integration density and other advantages, such as faster speeds and higher bandwidth, because of the decreased length of interconnects between the stacked dies, as examples.

Hybrid bonding is one type of bonding procedure for 3DICs, wherein two semiconductor wafers are bonded together using a hybrid bonding technique. Some methods of forming 3DICs are described in patent application: Ser. No. 13/488,745, filed on Jun. 5, 2012, entitled, âThree Dimensional Integrated Circuit Structures and Hybrid Bonding Methods for Semiconductor Wafers,â which application is hereby incorporated herein by reference.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a cross-sectional view of a portion of a semiconductor wafer in accordance with an embodiment of the present disclosure;

FIGS. 2 through 5 are cross-sectional views illustrating a wafer-to-wafer hybrid bonding method in accordance with an embodiment at various stages;

FIG. 6 illustrates a single platform system for hybrid bonding semiconductor wafers together in accordance with an embodiment;

FIG. 7 illustrates additional portions of the system shown in FIG. 6 in accordance with an embodiment; and

FIG. 8 is a flow chart of a method of forming a 3DIC structure using a hybrid bonding process in accordance with an embodiment.

Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the embodiments of the present disclosure are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosure, and do not limit the scope of the disclosure.

Embodiments of the present disclosure are related to 3DIC packaging of semiconductor devices. Novel hybrid bonding systems and method for semiconductor wafers will be described herein.

Referring first to FIG. 1 , there is shown a cross-sectional view of a portion of a semiconductor wafer 100 in accordance with an embodiment of the present disclosure. Two or more semiconductor wafers such as the wafer 100 illustrated will be coupled together vertically using a novel hybrid bonding system and process in accordance with embodiments herein.

The semiconductor wafer 100 includes a workpiece 102 . The workpiece 102 includes a semiconductor substrate comprising silicon or other semiconductor materials and may be covered by an insulating layer, for example. The workpiece 102 may comprise silicon oxide over single-crystal silicon, for example. Compound semiconductors, GaAs, InP, Si/Ge, or SiC, as examples, may be used in place of silicon. The workpiece 102 may comprise a silicon-on-insulator (SOI) or a germanium-on-insulator (GOI) substrate, as examples.

The workpiece 102 may include a device region 104 formed proximate a top surface of the workpiece 102 . The device region 104 includes active components or circuits, such as conductive features, implantation regions, resistors, capacitors and other semiconductor elements, e.g., transistors, diodes, etc. The device region 104 is formed over the workpiece 102 in a front-end-of-line (FEOL) process in some embodiments, for example. The workpiece 102 may also include through-substrate vias (TSVs) 105 comprising a conductive material that provide connections from a bottom side to a top side of the workpiece 102 , as shown.

A metallization structure 106 is formed over the workpiece 102 , e.g., over the device region 104 of the workpiece 102 . The metallization structure 106 is formed over the workpiece 102 in a back-end-of-line (BEOL) process in some embodiments, for example. The metallization structure 106 includes conductive features, such as conductive lines 108 , vias 110 , and conductive pads 112 formed in an insulating material 114 . The conductive pads 112 comprise contact pads or bond pads formed on a top surface of the semiconductor wafer 100 , as examples. Some of the vias 110 couple conductive pads 112 to conductive lines 108 in the metallization structure 106 , and other vias 110 couple contact pads 112 to the device region 104 of the workpiece 102 . Vias 110 may also connect together conductive lines 108 in different metallization layers, not shown. The conductive features may comprise conductive materials typically used in BEOL processes, such as Cu, Al, W, Ti, TiN, Ta, TaN, or multiple layers or combinations thereof. In accordance with an embodiment, the conductive pads 112 disposed proximate a top surface of the metallization structure 106 comprise Cu or a copper alloy, for example. The metallization structure 106 shown is merely for illustrative purposes: the metallization structure 106 may comprise other configurations and may include one or more conductive line and via layers, for example. Some semiconductor wafers 100 may have three conductive line and via layers, or four or more conductive line and via layers, as other examples.

The semiconductor wafer 100 includes a plurality of semiconductor devices comprising portions of the workpiece 102 and the metallization layer 106 formed across the surface thereof, e.g., in a grid. The semiconductor devices comprise dies that may each be shaped in a square or rectangular pattern in a top view of the workpiece 102 , as examples.

CROSS-REFERENCE TO RELATED APPLICATIONS

BACKGROUND

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a portion of a semiconductor wafer in accordance with an embodiment of the present disclosure;

FIGS. 2 through 5 are cross-sectional views illustrating a wafer-to-wafer hybrid bonding method in accordance with an embodiment at various stages;

FIG. 6 illustrates a single platform system for hybrid bonding semiconductor wafers together in accordance with an embodiment;

FIG. 7 illustrates additional portions of the system shown in FIG. 6 in accordance with an embodiment; and

FIG. 8 is a flow chart of a method of forming a 3DIC structure using a hybrid bonding process in accordance with an embodiment.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

Embodiments of the present disclosure are related to 3DIC packaging of semiconductor devices. Novel hybrid bonding systems and method for semiconductor wafers will be described herein.

FIGS. 2 through 5 are cross-sectional views illustrating a method of hybrid bonding two semiconductor wafers 100 shown in FIG. 1 in accordance with an embodiment at various stages. FIG. 2 illustrates a more detailed view of a portion of the semiconductor wafer 100 shown in FIG. 1 that includes two conductive pads 112 disposed at the top surface of the metallization structure 106 . Some of the vias 110 are coupled to the conductive pads 112 and also the conductive lines 108 . The insulating material 114 comprises SiO 2 , and the conductive pads 112 comprise Cu, in some embodiments. Alternatively, the insulating material 114 and the conductive pads 112 may comprise other materials.

The conductive pads 112 are formed in some embodiments using a damascene process, wherein the insulating material 114 is deposited over the workpiece 102 , and the insulating material 114 is patterned using lithography. The patterned insulating material 114 is filled with a conductive material, and excess portions of the conductive material are removed from over the top surface of the insulating material 114 using a chemical mechanical polishing (CMP) process, an etch process, or combinations thereof. In other embodiments, a conductive material may be deposited and patterned using lithography, and the insulating material 114 is formed over the conductive material to form the conductive pads 112 using a subtractive etch process. The excess insulating material 114 is then removed from over the conductive pads 112 using a CMP process, an etch process, or combinations thereof.

In accordance with some embodiments of the present disclosure, after the formation of the conductive pads 112 , a CMP process is performed near an end of the fabrication process of the semiconductor wafer 100 .

After the conductive pads 112 are formed and cleaned, a protection layer 116 is formed over the top surface of the semiconductor wafer 100 , as shown in FIG. 3 . The protection layer 116 comprises an insulating material, and may comprise C, Si, H, and/or combinations thereof. In some embodiments, the protection layer 116 includes C, Si, and H. Alternatively, the protection layer 116 may comprise other materials. The protection layer 116 comprises a material that is adapted to prevent formation of or relax an oxide material on the top surfaces of the first and second semiconductor wafers, e.g., on the top surfaces of the conductive pads 112 . In some embodiments, a small portion of an oxide material 118 may be formed on top surfaces of the conductive pads 112 after the cleaning process, and the protection layer 116 relaxes the oxide material 118 , minimizing further oxidation and preventing damage to the conductive pads 112 .

The protection layer 116 is formed in some embodiments using a vapor type deposition process or a hydrophobic process having a contact angle of greater than about 60 degrees to the top surface of the semiconductor wafer 100 . Alternatively, the protection layer 116 may be formed using other methods. The protection layer 116 comprises a thickness of about 100 Angstroms or less. Alternatively, the protection layer 116 may comprise other dimensions. In some embodiments, the protection layer 116 comprises a monolayer of material.

The semiconductor wafer 100 is then stored for a period of time in some embodiments. The semiconductor wafer 100 may be placed in a fabrication facility in storage or on a shelf for a period of time after the manufacturing process is completed, for example. Advantageously, the amount of time that the semiconductor wafer 100 may be stored is increased, due to the presence of the protection layer 116 , which prevents or relaxes the formation of an oxide material on the top surfaces of the conductive pads 112 . The protection layer 116 prevents the formation of Cu oxide on top surfaces of the conductive pads 112 , in embodiments where the conductive pads 112 comprise Cu or Cu alloys, for example.

When it is time for the semiconductor wafer 100 to be packaged using a 3DIC process with another semiconductor wafer 100 , the wafer 100 is placed into a chamber 142 (not shown in FIG. 3 ; see FIG. 6 , to be described further herein.) The protection layer 116 is removed from the top surface of the wafer 100 using a removal process 119 , shown in FIGS. 3 and 4 . The removal process 119 may comprise exposure of the wafer 100 to an acid, exposure to HCOOH, exposure to HCl, thermal decomposition, thermal desorption, exposure to a plasma removal treatment, exposure to ultraviolet (UV) light, or a combination thereof, as examples. Alternatively, the removal process 119 may comprise other types of removal processes.

Before the protection layer 116 is formed, an oxide material 118 may begin forming soon after a final fabrication step on top surfaces of the conductive pads 112 , depending on the manufacturing environment, for example, because Cu oxidizes easily. The oxide material 118 may comprise copper oxide (CuO x ) for example, by exposure of the Cu conductive pads 112 to oxygen in the ambient air. The oxide material 118 may comprise other materials, depending on the type of material of the conductive pads 112 , for example. Removal of the oxide material 118 from the top surfaces of the conductive pads 112 is important to achieve a high quality hybrid bond to another semiconductor wafer 100 , to avoid high resistance connections between the wafers 100 . Advantageously, in some embodiments, a portion of or all of the oxide material 118 is removed during the removal process 119 used to remove the protection layer 116 from the top surface of the wafer 100 . The removal process 119 may also clean the top surface of the wafer 100 , in some embodiments. The removal process 119 of the protection layer 116 is performed without removing the wafer 100 from the chamber 142 , to avoid forming any additional oxide material 118 on the top surface of the conductive pads 112 .

Next, the top surface of the wafer 100 is activated using an activation process 120 , as shown in FIG. 4 . The activation process 120 comprises activating the top surfaces of the wafer 100 with plasma at a power density of less than about 1,000 Watts, for example, in some embodiments. Alternatively, other methods and power levels may be used. A surface roughness of the top surface of the wafer 100 is not substantially altered by the activation process 120 , and may comprise a root mean square (RMS) of less than about 5 Angstroms in an embodiment. The activation process 120 may also clean the top surface of the wafer 100 in some embodiments. If any oxide material 118 is left remaining on the top surface of the contact pads 112 after the removal process 119 for the protection layer 116 , a portion of or all of the remaining oxide material 118 may be removed during the activation process 120 , in some embodiments, for example. The activation process 120 is performed after the removal process 119 without removing the wafer 100 from the chamber 142 , to avoid forming any additional oxide material 118 on the top surface of the conductive pads 112 .

After the activation process 120 , the wafers 100 may be cleaned in some embodiments. The cleaning process may comprise exposure to deionized (DI) H 2 O, exposure to NH 4 OH, exposure to diluted hydrofluoric acid (DHF) (e.g., at a concentration of less than about 1% HF acid), exposure to other acids, a cleaning process with a brush, a mega-sonic procedure, a spin process, exposure to an infrared (IR) lamp, or a combination thereof, as examples, although alternatively, the cleaning process may comprise other types of cleaning processes. The cleaning process enhances a density of a hydroxy group disposed on top surfaces of the wafer 100 in some embodiments, e.g., on the top surface of the conductive pads 112 . Enhancing the density of the hydroxy group on the conductive pads 112 advantageously increases bonding strength and reduces the anneal temperature required for the hybrid bonding process, for example. The cleaning process is performed without removing the wafer 100 from the chamber 142 , again, to avoid forming any additional oxide material 118 on the top surface of the conductive pads 112 .

The removal process 119 , the activation process 120 and the cleaning process are adapted to prepare the top surface of the wafer 100 for hybrid bonding to another wafer 100 , for example, so that the top surfaces of the wafers 100 are as clean as possible so that a high quality hybrid bond is formed between two or more wafers 100 . The removal process 119 , the activation process 120 , and the cleaning process assist in the hybrid bonding of two or more wafers 100 , advantageously allowing the use of lower pressures and temperatures in a subsequent hybrid bonding process. The removal process 119 , the activation process 120 and/or the cleaning process may be used to remove a portion of or all of the oxide material 118 . A consideration of a selection of chemistries for portions of the removal process 119 , the activation process 120 and/or the cleaning process may include the following reactions, to reduce an oxide material 118 comprising CuO x , as an example:

CuO+HCOOHâCu(COOH) 2 +H2O;

Cu(HCOOH) 2 âCu+CO 2 +H 2 ; or

CuO+H 2 âCu+H 2 O.

After the cleaning process, next, without removing the wafer 100 from the chamber 142 , the wafer 100 shown in FIG. 4 is hybrid bonded to another wafer 100 . FIG. 5 illustrates two semiconductor wafers

100 a and 100 b that are bonded together using a hybrid bonding process by coupling a top surface of one semiconductor wafer 100 b to a top surface of another semiconductor wafer 100 a . The wafers comprise a first semiconductor wafer 100 a and a second semiconductor wafer 100 b that have been processed using the procedures described herein for wafer 100 shown in FIGS. 1 through 4 . The top surface of the second semiconductor wafer 100 b is coupled to the top surface of the first semiconductor wafer 100 a . The second semiconductor wafer 100 b is inverted, i.e., rotated 90 degrees, from the view shown in FIG. 4 , for example.

The bonding of the second semiconductor wafer 100 b to the first semiconductor wafer 100 a is achieved by aligning the conductive pads 112 b on the second semiconductor wafer 100 b with the conductive pads 112 a on the first semiconductor wafer 100 a , as shown in FIG. 5 . The alignment of the wafers

100 a and 100 b may be achieved using optical sensing, as an example. Top surfaces of the insulating material 114 b of the second semiconductor wafer 100 b are also aligned with top surfaces of the insulating material 114 a of the first semiconductor wafer 100 a.

After the alignment process of the wafers

100 a and 100 b , the wafers

100 a and 100 b are hybrid bonded together by applying pressure 124 and heat 126 , as shown in FIG. 5 . The pressure 124 applied may comprise a pressure of less than about 30 MPa, and the heat 126 applied may comprise an anneal process at a temperature of about 100 to 500 degrees C., as examples, although alternatively, other amounts of pressure 124 and heat 126 may be used for the hybrid bonding process. The grain size of the Cu of the conductive pads 112 may comprise about 0.1 to 5 Î¼m after the anneal process, with a bond strength larger than about 1.0 J/m 2 in an embodiment, for example. The hybrid bonding process may be performed in a N 2 environment, an Ar environment, a He environment, an (about 4 to 10% H 2 )/(about 90 to 96% inert gas or N 2 ) environment, an inert-mixing gas environment, combinations thereof, or other types of environments. The ambient environment in the chamber 142 contains a minimal amount of or no amount of O 2 , to prevent the oxidation of the conductive pads

112 a and 112 b before or during the hybrid bonding process, for example, in some embodiments.

The hybrid bonding process results in a bond 132 that is formed between the insulating materials 114 a and 114 b of the first and second semiconductor wafers

100 a and 100 b , respectively. A bond 134 is also formed between the conductive pads

112 a and 112 b of the first and second semiconductor wafers

100 a and 100 b , respectively. Bonds 132 comprise non-metal-to-non-metal bonds, and bonds 134 comprise metal-to-metal bonds. A portion of the hybrid bonding process may comprise a fusion process that forms the non-metal-to- non-metal bonds 132 , and a portion of the hybrid bonding process may comprise a copper-to-copper bonding process that formed the metal-to- metal bonds 134 , for example. The term âhybridâ refers to the

CLAIMS

Claims ( 20 )

What is claimed is:

1. A method comprising:

depositing a first protection layer on a first bonding surface of a first semiconductor wafer;

removing the first protection layer from the first bonding surface of the first semiconductor wafer to expose the first bonding surface of the first semiconductor wafer;

applying a plasma process to the first bonding surface of the first semiconductor wafer;

performing a cleaning process on the first bonding surface of the first semiconductor wafer;

coupling the first semiconductor wafer to a second semiconductor wafer; and

annealing the first semiconductor wafer and the second semiconductor wafer to bond the first bonding surface of the first semiconductor wafer to a second bonding surface of the second semiconductor wafer, wherein bonding the first bonding surface of the first semiconductor wafer to the second bonding surface of the second semiconductor wafer comprises:

forming a first bond between a first insulating layer of the first bonding surface and a second insulating layer of the second bonding surface; and

forming a second bond between a first conductive pad of the first bonding surface and a second conductive pad of the second bonding surface.

2. The method of claim 1 , wherein removing the first protection layer comprises exposing the first protection layer to an acid, HCOOH, HCl, a thermal process, a plasma removal treatment, ultraviolet (UV) light, and combinations thereof.

3. The method according to claim 1 , wherein forming the first protection layer forming a material selected from C, Si, H, or a combination thereof.

4. The method according to claim 1 , wherein removing the first protection layer performed in a first atmospheric environment, wherein the first semiconductor wafer is exposed to a second atmospheric environment between depositing the first protection layer and removing the first protection layer, and wherein the first atmospheric environment is a reduced oxygen environment compared to the second atmospheric environment.

5. The method according to claim 1 , wherein removing the first protection layer further removes a native oxide disposed at the first bonding surface.

6. The method according to claim 1 , wherein performing the cleaning process on the first bonding surface enhances a density of hydroxy groups disposed at the first bonding surface.

7. The method according to claim 1 , wherein applying the plasma process the first bonding surface does not alter a surface roughness of the first bonding surface.

8. A method comprising:

providing a first semiconductor wafer comprising a first plurality of conductive pads in a first insulating material on a top surface of the first plurality of conductive pads;

forming a first protection layer on the first plurality of conductive pads, wherein the first protective layer reduces oxidation of the first plurality of conductive pads;

removing the first protective layer to expose the first plurality of conductive pads;

after removing the first protective layer, applying a plasma process to the top surface of the first semiconductor wafer;

after applying the plasma process, aligning the first plurality of conductive pads of the first semiconductor wafer to a second plurality of conductive pads of a second semiconductor wafer; and

bonding the first semiconductor wafer to the second semiconductor wafer, wherein bonding the first semiconductor wafer to the second semiconductor wafer comprises annealing the first semiconductor wafer and the second semiconductor wafer to form:

a dielectric-to-dielectric bond between the first insulating material and a second insulating material of the second semiconductor wafer; and

a metal-to-metal bond between the first plurality of conductive pads and the second plurality of conductive pads.

9. The method of claim 8 further comprising before removing the first protection layer, placing the first semiconductor wafer and the second semiconductor wafer in a reduced oxygen environment, wherein an oxygen amount in the reduced oxygen environment is lower than an oxygen amount of an environment in which the first semiconductor wafer were stored prior to removing the first protection layer, and wherein the first semiconductor wafer and the second semiconductor wafer are not removed from the reduced oxygen environment until after bonding the first semiconductor wafer to the second semiconductor wafer.

10. The method of claim 8 further comprising after applying the plasma process, cleaning the top surface of the first semiconductor wafer.

11. The method of claim 8 , wherein the top surface of the first semiconductor wafer includes an oxide material formed thereon, and wherein removing the first protection layer or activating the top surface of the first semiconductor wafer removes at least a portion of the oxide material.

12. The method of claim 11 , wherein the first plurality of conductive pads comprises copper, and wherein removing at least the portion of the oxide material comprises removing copper oxide.

13. The method of claim 8 , further comprising:

forming a second protection layer on the second plurality of conductive pads, wherein the second protective layer reduces oxidation of the second plurality of conductive pads; and

removing the second protective layer to expose the second plurality of conductive pads.

14. The method of claim 8 , wherein the first protection layer comprises an insulating material comprising C, Si, H, or a combination thereof.

15. A method comprising:

forming a first protection layer over a first top surface of a first semiconductor wafer;

forming a second protection layer over a second top surface of a second semiconductor wafer;

removing the first protection layer from over the first top surface of the first semiconductor wafer;

removing the second protection layer from over the second top surface of the second semiconductor wafer;

after removing the first protection layer, applying a first plasma process to the first top surface of the first semiconductor wafer;

after removing the second protection layer, applying a second plasma process to the second top surface of the second semiconductor wafer;

after applying the first plasma process, applying a first cleaning process to the first top surface of the first semiconductor wafer;

after applying the second plasma process, applying a second cleaning process to the second top surface of the second semiconductor wafer; and

hybrid bonding the first semiconductor wafer to the second semiconductor wafer, wherein hybrid bonding the first semiconductor wafer to the second semiconductor wafer comprises performing an anneal at a temperature of 100Â° C. to 500Â° C.

16. The method of claim 15 , wherein the first semiconductor wafer comprises a first conductive pad disposed in a first insulating material at the first top surface, wherein the second semiconductor wafer comprising a second conductive pad disposed in a second insulating material at the second top surface.

17. The method of claim 16 , wherein removing the first protection layer removes a conductive oxide at a top surface of the first conductive pad.

18. The method of claim 16 , wherein applying the first plasma process to the first top surface removes a conductive oxide at a top surface of the first conductive pad.

19. The method of claim 15 , wherein hybrid bonding the first semiconductor wafer to the second semiconductor wafer is performed in an inert-mixing gas environment.

20. The method according to claim 15 , wherein removing the first protection layer comprises a method selected from the group consisting essentially of exposure to an acid, exposure to HCOOH, exposure to HCl, thermal decomposition, thermal desorption, exposure to a plasma removal treatment, exposure to ultraviolet (UV) light, and combinations thereof.

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Cited By (7)

* Cited by examiner, â Cited by third party

Publication number

Priority date

Publication date

Assignee

Title

WO2024253760A1

( en )

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US12176245B2

( en )

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US12406975B2

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US12431460B2

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US12550662B2

( en )

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( en )

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Families Citing this family (81)

* Cited by examiner, â Cited by third party

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Assignee

Title

EP2654074B1

( en )

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US9048283B2

( en )

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US8916448B2

( en )

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US9917069B2

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2017-01-12

Siemens Aktiengesellschaft

A method of producing a coolable electronic component and assembly comprising an electronic component and a cooling element

US9728521B2

( en )

2015-07-23

2017-08-08

Taiwan Semiconductor Manufacturing Co., Ltd.

Hybrid bond using a copper alloy for yield improvement

US9972603B2

( en )

2015-12-29

2018-05-15

Taiwan Semiconductor Manufacturing Co., Ltd.

Seal-ring structure for stacking integrated circuits

US9704820B1

( en )

2016-02-26

2017-07-11

Taiwan Semiconductor Manufacturing Company Ltd.

Semiconductor manufacturing method and associated semiconductor manufacturing system

US9666566B1

( en )

2016-04-26

2017-05-30

Taiwan Semiconductor Manufacturing Company, Ltd.

3DIC structure and method for hybrid bonding semiconductor wafers

US10672745B2

( en )

2016-10-07

2020-06-02

Xcelsis Corporation

3D processor

TWI892323B

( en )

2016-10-27

2025-08-01

ç¾åè¾å¾·äºåå°é«ç§ææéè²¬ä»»å¬å¸

Structures and methods for low temperature bonding

US10002844B1

( en )

2016-12-21

2018-06-19

Invensas Bonding Technologies, Inc.

Bonded structures

CN117878055A

( en )

2016-12-28

2024-04-12

è¾å¾·äºåå¯¼ä½æ¥åç§ææéå¬å¸

Stacking substrate processing

US10508030B2

( en )

2017-03-21

2019-12-17

Invensas Bonding Technologies, Inc.

Seal for microelectronic assembly

US10745268B2

( en )

2017-06-30

2020-08-18

Taiwan Semiconductor Manufacturing Co., Ltd.

Method of stiction prevention by patterned anti-stiction layer

US10840205B2

( en )

2017-09-24

2020-11-17

Invensas Bonding Technologies, Inc.

Chemical mechanical polishing for hybrid bonding

US10294098B2

( en )

2017-09-27

2019-05-21

Taiwan Semiconductor Manufacturing Co., Ltd.

Method for manufacturing a MEMS device by first hybrid bonding a CMOS wafer to a MEMS wafer

DE102018122261B4

( en )

2017-09-27

2024-03-28

Taiwan Semiconductor Manufacturing Co., Ltd.

INTEGRATION METHOD FOR WAFER LEVEL PACKAGING AND MICROELECTROMECHANICAL SYSTEM, MEMS, COMPONENT

US10504784B2

( en )

2017-10-25

2019-12-10

Taiwan Semiconductor Manufacturing Co., Ltd.

Inductor structure for integrated circuit

US10923408B2

( en )

2017-12-22

2021-02-16

Invensas Bonding Technologies, Inc.

Cavity packages

US11380597B2

( en )

2017-12-22

2022-07-05

Invensas Bonding Technologies, Inc.

Bonded structures

JP2019160833A

( en )

2018-03-07

2019-09-19

æ±èã¡ã¢ãªæ ªå¼ä¼ç¤¾

Semiconductor device

US11056348B2

( en )

2018-04-05

2021-07-06

Invensas Bonding Technologies, Inc.

Bonding surfaces for microelectronics

US11244916B2

( en )

2018-04-11

2022-02-08

Invensas Bonding Technologies, Inc.

Low temperature bonded structures

US10964664B2

( en )

2018-04-20

2021-03-30

Invensas Bonding Technologies, Inc.

DBI to Si bonding for simplified handle wafer

US11004757B2

( en )

2018-05-14

2021-05-11

Invensas Bonding Technologies, Inc.

Bonded structures

US11393779B2

( en )

2018-06-13

2022-07-19

Invensas Bonding Technologies, Inc.

Large metal pads over TSV

KR102878117B1

( en )

2018-06-13

2025-10-28

ìë°ì´ì ì¸ë¯¸ì»¨ëí° ë³¸ë© íí¬ëë¡ì§ì¤ ì¸ì½í¬ë ì´í°ë

TSV as a pad

CN116364659A

( en )

2018-06-29

2023-06-30

é¿æ±åå¨ç§ææéè´£ä»»å¬å¸

Semiconductor structures and methods of forming them

US10475877B1

( en )

2018-08-21

2019-11-12

Taiwan Semiconductor Manufacturing Co., Ltd.

Multi-terminal inductor for integrated circuit

US11011494B2

( en )

2018-08-31

2021-05-18

Invensas Bonding Technologies, Inc.

Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics

US11158573B2

( en )

2018-10-22

2021-10-26

Invensas Bonding Technologies, Inc.

Interconnect structures

US11244920B2

( en )

2018-12-18

2022-02-08

Invensas Bonding Technologies, Inc.

Method and structures for low temperature device bonding

KR102626314B1

( en )

2019-01-28

2024-01-17

ì¼ì±ì ìì£¼ìíì¬

Semiconductor device having bonding pads

WO2020163984A1

( en )

2019-02-11

2020-08-20

Yangtze Memory Technologies Co., Ltd.

Bonded semiconductor structures having bonding contacts made of indiffusible conductive materials and methods for forming the same

CN114530414A

( en )

2019-03-29

2022-05-24

é¿æ±åå¨ç§ææéè´£ä»»å¬å¸

Method for manufacturing semiconductor chip

US12374641B2

( en )

2019-06-12

2025-07-29

Adeia Semiconductor Bonding Technologies Inc.

Sealed bonded structures and methods for forming the same

US11315871B2

( en )

2019-06-13

2022-04-26

Nanya Technology Corporation

Integrated circuit device with bonding structure and method of forming the same

US12538781B2

( en )

2019-06-13

2026-01-27

Nanya Technology Corporation

Method of manufacturing integrated circuit device with bonding structure

US11515273B2

( en )

2019-07-26

2022-11-29

Sandisk Technologies Llc

Bonded assembly containing oxidation barriers, hybrid bonding, or air gap, and methods of forming the same

US11393780B2

( en )

2019-07-26

2022-07-19

Sandisk Technologies Llc

Bonded assembly containing oxidation barriers, hybrid bonding, or air gap, and methods of forming the same

US11139272B2

( en )

2019-07-26

2021-10-05

Sandisk Technologies Llc

Bonded assembly containing oxidation barriers and/or adhesion enhancers and methods of forming the same

US11139239B2

( en )

2019-10-01

2021-10-05

Taiwan Semiconductor Manufacturing Company, Ltd.

Recessed inductor structure to reduce step height

KR102808554B1

( en )

2019-11-07

2025-05-16

ì¼ì±ì ìì£¼ìíì¬

Substrate bonding apparatus

CN112885777B

( en )

2020-01-07

2022-12-09

é¿æ±åå¨ç§ææéè´£ä»»å¬å¸

Metal-dielectric bonding method and structure

CN113257948A

( en )

2020-02-10

2021-08-13

ä¸å½ç§å¦é¢é¿æ¥åå¦ç²¾å¯æºæ¢°ä¸ç©çç ç©¶æ

Preparation method of copper interconnection visible-infrared detector

CN111243972B

( en )

2020-02-24

2022-06-10

åå°æ»¨å·¥ä¸å¤§å¦

Multi-step synergistic surface activation low-temperature mixed bonding method

US11742314B2

( en )

2020-03-31

2023-08-29

Adeia Semiconductor Bonding Technologies Inc.

Reliable hybrid bonded apparatus

US11164822B1

( en )

2020-09-28

2021-11-02

United Microelectronics Corp.

Structure of semiconductor device and method for bonding two substrates

US11264357B1

( en )

2020-10-20

2022-03-01

Invensas Corporation

Mixed exposure for large die

US20220139869A1

( en )

2020-10-29

2022-05-05

Invensas Bonding Technologies, Inc.

Direct bonding methods and structures

KR20230125309A

( en )

2020-12-28

2023-08-29

ìë°ì´ì ì¸ë¯¸ì»¨ëí° ë³¸ë© íí¬ëë¡ì§ì¤ ì¸ì½í¬ë ì´í°ë

Structures having through-substrate vias and methods for forming the same

JP2024501017A

( en )

2020-12-28

2024-01-10

Structure with through-substrate via and method for forming the same

US12211809B2

( en )

2020-12-30

2025-01-28

Adeia Semiconductor Bonding Technologies Inc.

Structure with conductive feature and method of forming same

CN117256047A

( en )

2021-03-03

2023-12-19

ç¾åè¾å¾·äºåå¯¼ä½æ¥åç§ææéå¬å¸

Contact structures for direct bonding

US20230245996A1

( en )

2021-03-29

2023-08-03

Board Of Regents, The University Of Texas System

Processes and applications for catalyst influenced chemical etching

US12550799B2

( en )

2021-03-31

2026-02-10

Adeia Semiconductor Bonding Technologies Inc.

Direct bonding methods and structures

EP4315398A4

( en )

2021-03-31

2025-03-05

Adeia Semiconductor Bonding Technologies Inc.

Direct bonding and debonding of carrier

KR102647323B1

( en )

2021-09-23

2024-03-13

ííì ë°ê¸°ê³ ì£¼ìíì¬

Bonding apparatus and controlling method thereof

KR102630226B1

( en )

2021-09-23

2024-01-29

ííì ë°ê¸°ê³ ì£¼ìíì¬

Hybrid bonding apparatus and hybrid bonding method using the same

KR102909722B1

( en )

2021-12-07

2026-01-07

ì¼ì±ì ìì£¼ìíì¬

A semiconductor device, an apparatus for manufacturing the semiconductor device, and a method for manufacturing the semiconductor device using the apparatus

CN114220783B

( en )

2021-12-21

2024-09-17

A hybrid bonding structure and preparation method thereof

US12622307B2

( en )

2021-12-23

2026-05-05

Adeia Semiconductor Bonding Technologies Inc.

Controlled grain growth for bonding and bonded structure with controlled grain growth

KR102623814B1

( en )

2021-12-27

2024-01-10

ì¸ë©ì¤ ì£¼ìíì¬

Substrate processing apparatus, substrate bonding system including same, and substrate processing method using same

TWI799053B

( en )

2022-01-03

2023-04-11

Method for manufacturing semiconductor structure

US12125818B2

( en )

2022-02-10

2024-10-22

Tokyo Electron Limited

Technologies for plasma oxidation protection during hybrid bonding of semiconductor devices

FR3134227A1

( en )

2022-04-04

2023-10-06

Commissariat A L'energie Atomique Et Aux Energies Alternatives

Method for bonding a first substrate to a surface having an elastic nanotopology

KR20240018864A

( en )

2022-08-03

2024-02-14

ì¼ì±ì ìì£¼ìíì¬

Semiconductor chip and method of manufacturing the same

US12506114B2

( en )

2022-12-29

2025-12-23

Adeia Semiconductor Bonding Technologies Inc.

Directly bonded metal structures having aluminum features and methods of preparing same

US12545010B2

( en )

2022-12-29

2026-02-10

Adeia Semiconductor Bonding Technologies Inc.

Directly bonded metal structures having oxide layers therein

US20240321855A1

( en )

2023-03-24

2024-09-26

Taiwan Semiconductor Manufacturing Company, Ltd.

Bonding techniques for stacked transistor structures

US12564015B2

( en )

2023-04-28

2026-02-24

Applied Materials Inc.

Integrated inspection for enhanced hybrid bonding yield in advanced semiconductor packaging manufacturing

US20240390950A1

( en )

2023-05-22

2024-11-28

Applied Materials, Inc.

Method and apparatus for substrate cleaning in stack-die hybrid bonding process

US20250087628A1

( en )

2023-09-12

2025-03-13

Tokyo Electron Limited

Method of surface modification for wafer bonding

KR102762483B1

( en )

2023-12-20

2025-02-03

ì¸íëíêµ ì°ííë ¥ë¨

3d stacked semiconductor devices including hybrid bonding and manufacturing methods thereof

Citations (16)

* Cited by examiner, â Cited by third party

Publication number

Priority date

Publication date

Assignee

Title

WO1999065803A1

( en )

1998-06-17

1999-12-23

Genmark Automation, Inc.

Automated opening and closing of ultra clean storage containers

US6153524A

( en )

1997-07-29

2000-11-28

Silicon Genesis Corporation

Cluster tool method using plasma immersion ion implantation

KR20010009429A

( en )

1999-07-09

2001-02-05

ì¤ì¢ì©

Method For Manufacturing Wafer Level Chip Scale Packages Using Redistribution Substrate

US6276433B1

( en )

1999-10-25

2001-08-21

General Electric Company

Liquid metal cooled directional solidification process

US20040216673A1

( en )

2003-02-14

2004-11-04

Semiconductor Energy Laboratory Co., Ltd.

Manufacturing apparatus

US6962835B2

( en )

2003-02-07

2005-11-08

Ziptronix, Inc.

Method for room temperature metal direct bonding

US20070145367A1

( en )

2005-12-27

2007-06-28

Taiwan Semiconductor Manufacturing Company, Ltd.

Three-dimensional integrated circuit structure

US20070281438A1

( en )

2006-05-31

2007-12-06

Lianjun Liu

Methods and apparatus for RF shielding in vertically-integrated semiconductor devices

US7385283B2

( en )

2006-06-27

2008-06-10

Taiwan Semiconductor Manufacturing Co., Ltd.

Three dimensional integrated circuit and method of making the same

KR20080105956A

( en )

2007-06-01

2008-12-04

ì°¸ì¤ì¨(ì£¼)

Wafer Bonding Method

US20090140404A1

( en )

2006-11-03

2009-06-04

International Business Machines Corporation

Hermetic seal and reliable bonding structures for 3d applications

US20110027945A1

( en )

2007-12-27

2011-02-03

Sanyo Electric Co., Ltd.

Substrate for mounting device and method for producing the same, semiconductor module and method for producing the same, and portable apparatus provided with the same

KR20110134139A

( en )

2010-06-08

2011-12-14

(ì£¼)ì¤ë¦¬ì½íì¼

Manufacturing method of 3D structure image sensor

US20120126425A1

( en )

2009-02-03

2012-05-24

International Business Machines Corporation

3d integrated circuits structure

US20130320556A1

( en )

2012-06-05

2013-12-05

Taiwan Semiconductor Manufacturing Company, Ltd.

Three Dimensional Integrated Circuit Structures and Hybrid Bonding Methods for Semiconductor Wafers

US9048283B2

( en )

2012-06-05

2015-06-02

Taiwan Semiconductor Manufacturing Company, Ltd.

Hybrid bonding systems and methods for semiconductor wafers

Family Cites Families (2)

* Cited by examiner, â Cited by third party

Publication number

Priority date

Publication date

Assignee

Title

US8034409B2

( en )

2006-12-20

2011-10-11

Lam Research Corporation

Methods, apparatuses, and systems for fabricating three dimensional integrated circuits

CN102237285B

( en )

2010-04-20

2016-05-18

å°æ¹¾ç§¯ä½çµè·¯å¶é è¡ä»½æéå¬å¸

Wafer Bonder

2012

2012-07-05

US13/542,507

patent/US9048283B2/en

active

Active

2012-09-25

KR1020120106403A

patent/KR101430819B1/en

active

Active

2012-10-10

CN201210382930.9A

patent/CN103531492B/en

not_active

Expired - Fee Related

2015

2015-05-29

US14/725,266

patent/US9748198B2/en

not_active

Expired - Fee Related

2017

2017-08-29

US15/689,982

patent/US10103122B2/en

active

Active

201

Hybrid bonding systems and methods for semiconductor wafers — Taiwan Semiconductor Manufacturing Company (US10354972B2)

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