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Semiconductor device and manufacturing method thereof — Taiwan Semiconductor Manufacturing Co., Ltd. (US10964801B2)

Taiwan Semiconductor Manufacturing Co., Ltd. · Google Patents

Google Patents · Patents · License: Open Access

chih ltd.taiwansemiconductormanufacturingco.

patent, google patents, intellectual property, US10964801B2, Taiwan Semiconductor Manufacturing Co., Ltd., Chih-Sheng Li, en, 2021

ABSTRACT

Abstract

A semiconductor device includes a substrate, at least one active semiconductor fin, at least one first dummy semiconductor fin, and at least one second dummy semiconductor fin. The active semiconductor fin is disposed on the substrate. The first dummy semiconductor fin is disposed on the substrate. The second dummy semiconductor fin is disposed on the substrate and between the active semiconductor fin and the first dummy semiconductor fin. A top surface of the first dummy semiconductor fin and a top surface of the second dummy semiconductor fin are curved in different directions.

Description

PRIORITY CLAIM AND CROSS-REFERENCE

This application is a continuation of U.S. application Ser. No. 16/222,019, filed Dec. 17, 2018, entitled âSemiconductor Device and Manufacturing Method Thereof,â which is a divisional application of U.S. application Ser. No. 15/665,049, filed Jul. 31, 2017, entitled âSemiconductor Device and Manufacturing Method Thereof,â which is a continuation application of U.S. application Ser. No. 14/967,176, filed Dec. 11, 2015, now U.S. Pat. No. 9,722,050, issued on Aug. 1, 2017, entitled âSemiconductor Device and Manufacturing Method Thereof,â which application claims priority to U.S. Provisional Application No. 62/214,770, filed Sep. 4, 2015, which applications are herein incorporated by reference.

BACKGROUND

Semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.

Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. For example, a three dimensional transistor, such as a fin-like field-effect transistor (FinFET), has been introduced to replace a planar transistor. The fin transistor has a channel (referred to as a fin channel) associated with a top surface and opposite sidewalls. The fin channel has a total channel width defined by the top surface and the opposite sidewalls.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIGS. 1A to 1H are cross-sectional views of a method for manufacturing a semiconductor device at various stages in accordance with some embodiments of the present disclosure.

FIG. 2 is a cross-sectional view of a semiconductor device in accordance with some embodiments of the present disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as âbeneath,â âbelow,â âlower,â âabove,â âupperâ and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Examples of devices that can be improved from one or more embodiments of the present application are semiconductor devices. Such a device, for example, is a FinFET device. The FinFET device, for example, may be a complementary metal-oxide-semiconductor (CMOS) device including at least one P-type metal-oxide-semiconductor (PMOS) FinFET device and at least one N-type metal-oxide-semiconductor (NMOS) FinFET device. The following disclosure will continue with a FinFET example to illustrate various embodiments of the present application. It is understood, however, that the application should not be limited to a particular type of device.

FIGS. 1A to 1H are cross-sectional views of a method for manufacturing a semiconductor device at various stages in accordance with some embodiments of the present disclosure. Reference is made to FIG. 1A . A substrate 110 is provided. The substrate 110 has at least one active region 102 and at least one dummy region 104 . For example, in FIG. 1A , the substrate 110 has two active regions 102 and one dummy region 104 , and the dummy region 104 is present between the two active regions 102 . In some embodiments, the substrate 110 includes silicon. Alternatively, the substrate 110 may include germanium, silicon germanium, gallium arsenide or other appropriate semiconductor materials. Also alternatively, the substrate 110 may include an epitaxial layer. For example, the substrate 110 may have an epitaxial layer overlying a bulk semiconductor. Further, the substrate 110 may be strained for performance enhancement. For example, the epitaxial layer may include a semiconductor material different from that of the bulk semiconductor, such as a layer of silicon germanium overlying bulk silicon or a layer of silicon overlying bulk silicon germanium. Such strained substrate may be formed by selective epitaxial growth (SEG). Furthermore, the substrate 110 may include a semiconductor-on-insulator (SOI) structure. Also alternatively, the substrate 110 may include a buried dielectric layer, such as a buried oxide (BOX) layer, such as that formed by separation by implantation of oxygen (SIMOX) technology, wafer bonding, SEG, or other appropriate method.

A pad layer 122 and a mask layer 124 are formed on the substrate 110 . The pad layer 122 includes a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or any other suitable dielectric material. The mask layer 124 includes a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or any other suitable dielectric material. In some embodiments, the mask layer 124 is a hard mask layer. In some embodiments, the pad layer 122 is a silicon oxide layer deposited on the substrate 110 , and the mask layer 124 is a silicon nitride layer deposited on the pad layer 122 . The pad layer 122 and the mask layer 124 can be formed by thermal oxidation, chemical oxidation, atomic layer deposition (ALD), or any other appropriate method. In some embodiments, the thickness of the pad layer 122 may be between about 100-800 Angstroms, and the thickness of the mask layer 124 may be between about 200-2000 Angstroms.

A lithography process defining semiconductor fins on the semiconductor substrate 110 is performed. In some embodiments, a tri-layer photoresist 130 may be used, including a photoresist (PR) layer 132 as the top or uppermost portion, a middle layer 134 , and a bottom layer 136 . The tri-layer photoresist 130 is disposed on the mask layer 124 . The tri-layer photoresist 130 provides the PR layer 132 , the middle layer 134 which may include anti-reflective layers or backside anti-reflective layers to aid in the exposure and focus of the PR processing, and the bottom layer 136 which may be a hard mask material; for example, a nitride. To pattern the tri-layer photoresist 130 , the PR layer 132 is patterned using a mask, exposure to radiation, such as light or an excimer laser, for example, a bake or cure operation to harden the resist, and use of a developer to remove either the exposed or unexposed portions of the resist, depending on whether a positive resist or a negative resist is used, to form the pattern from the mask in the PR layer 132 . This patterned PR layer 132 is then used to etch the underlying middle layer 134 and bottom layer 136 to form an etch mask for the target layer; here, the mask layer 124 .

Reference is made to FIG. 1B . A trench etching is performed to form patterned mask layer 124 â². The patterned PR layer 132 (see FIG. 1A ) is used as a mask during the trench etching. In the trench etching, the middle layer 134 , the bottom layer 136 , and the mask layer 124 (see FIG. 1A ) may be etched by various methods, including a dry etch, a wet etch, or a combination of dry etch and wet etch. The dry etching process may implement fluorine-containing gas (e.g., CF 4 , SF 6 , CH 2 F 2 , CHF 3 , and/or C 2 F 6 ), chlorine-containing gas (e.g., Cl 2 , CHCl 3 , CCl 4 , and/or BCl 3 ), bromine-containing gas (e.g., HBr and/or CHBr 3 ), oxygen-containing gas, iodine-containing gas, other suitable gases and/or plasmas, or combinations thereof. The etching process may include a multiple-step etching to gain etch selectivity, flexibility and desired etch profile. After the mask layer 124 is patterned, the <figure-callout id="132" label="PR

PRIORITY CLAIM AND CROSS-REFERENCE

BACKGROUND

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1H are cross-sectional views of a method for manufacturing a semiconductor device at various stages in accordance with some embodiments of the present disclosure.

FIG. 2 is a cross-sectional view of a semiconductor device in accordance with some embodiments of the present disclosure.

DETAILED DESCRIPTION

Reference is made to FIG. 1C . Using the patterned mask layer 124 â² as a mask, the pad layer 120 and the substrate 110 are etched to form a plurality of semiconductor fins by various methods, including a dry etch, a wet etch, or a combination of dry etch and wet etch. The dry etching process may implement fluorine-containing gas (e.g., CF 4 , SF 6 , CH 2 F 2 , CHF 3 , and/or C 2 F 6 ), chlorine-containing gas (e.g., Cl 2 , CHCl 3 , CCl 4 , and/or BCl 3 ), bromine-containing gas (e.g., HBr and/or CHBr 3 ), oxygen-containing gas, iodine-containing gas, other suitable gases and/or plasmas, or combinations thereof. The etching process may include a multiple-step etching to gain etch selectivity, flexibility and desired etch profile.

In FIG. 1C , the semiconductor fins includes at least one active semiconductor fin 112 , at least one first dummy semiconductor fin 114 , and at least one second dummy semiconductor fin 116 . For example, in FIG. 1C , there are six of the active semiconductor fins 112 , four of the first dummy semiconductor fin 114 , and two of the second dummy semiconductor fins 116 , and the claimed scope is not limited in this respect. The six active semiconductor fins 112 are divided into two groups and respectively disposed in the two active regions 102 . In FIG. 1C , there are three of the active semiconductor fins 112 in one of the active regions 102 . The first dummy semiconductor fins 114 and the second dummy semiconductor fins 116 are disposed in the dummy region 104 . That is, the first dummy semiconductor fins 114 and the second dummy semiconductor fins 116 are disposed between the two groups of the active semiconductor fins 112 . The first dummy semiconductor fins 114 are disposed adjacent to each other to form a group, and one of the second dummy semiconductor fins 116 is disposed between the group of the first dummy semiconductor fins 114 and one group of the active semiconductor fins 112 . Therefore, the first dummy semiconductor fins 114 can be referred to be inner dummy semiconductor fins, and the second dummy semiconductor fins 116 can be referred to be outer dummy semiconductor fins.

The first and second dummy semiconductor fins

114 and 116 have no functionality in the semiconductor device but make the device processes more uniform, more reproducible, and more manufacturable. The active semiconductor fins 112 have functionality in the semiconductor device. Having the first and second dummy semiconductor fins

114 and 116 located next to the active semiconductor fins 112 , the active semiconductor fins 112 may be formed under a fairly similar formation surrounding in all associated locations. A consistent formation surrounding enhances uniform active semiconductor fins 112 in all associated locations, in term of fin's critical dimension (CD), profile and height.

In some embodiments, the height H 1 of the active semiconductor fins 112 , the height H 2 of the first dummy semiconductor fins 114 , and the height H 3 of the second dummy semiconductor fins 116 can be about 100 nm to about 150 nm, and the claimed scope is not limited in this respect.

Reference is made to FIG. 1D . Another tri-layer photoresist 140 may be used, including a photoresist (PR) layer 142 as the top or uppermost portion, a middle layer 144 , and a bottom layer 146 . The tri-layer photoresist 140 covers the active semiconductor fins 112 , the first dummy semiconductor fins 114 , and the second dummy semiconductor fins 116 . The tri-layer photoresist 140 provides the PR layer 142 , the middle layer 144 which may include anti-reflective layers or backside anti-reflective layers to aid in the exposure and focus of the PR processing, and the bottom layer 146 which may be a hard mask material; for example, a nitride.

The PR layer 142 of the tri-layer photoresist 140 is then patterned. The patterned PR layer 142 exposes portions of the middle layer 144 disposed on the second dummy semiconductor fins 116 . Meanwhile, another portions of the middle layer 144 disposed on the active dummy semiconductor fins 112 and the first dummy semiconductor fins 114 are still covered by the PR layer 142 . To pattern the tri-layer photoresist 140 , the PR layer 142 is patterned using a mask, exposure to radiation, such as light or an excimer laser, for example, a bake or cure operation to harden the resist, and use of a developer to remove either the exposed or unexposed portions of the resist, depending on whether a positive resist or a negative resist is used, to form the pattern from the mask in the PR layer 142 . This patterned PR layer 142 is then used to etch the underlying middle layer 144 and bottom layer 146 to form an etch mask for the target features; here, the second dummy semiconductor fins 116 .

Reference is made to FIG. 1E . Using the patterned PR layer 142 (see FIG. 1D ) as a mask, the middle layer 144 and the bottom layer 146 of the tri-layer photoresist 140 (see FIG. 1D ) are etched by various methods, including a dry etch, a wet etch, or a combination of dry etch and wet etch. Also, at least portions of the second dummy semiconductor fins 116 are removed (or etched). The dry etching process may implement fluorine-containing gas (e.g., CF 4 , SF 6 , CH 2 F 2 , CHF 3 , and/or C 2 F 6 ), chlorine-containing gas (e.g., Cl 2 , CHCl 3 , CCl 4 , and/or BCl 3 ), bromine-containing gas (e.g., HBr and/or CHBr 3 ), oxygen-containing gas, iodine-containing gas, other suitable gases and/or plasmas, or combinations thereof. The etching process may include a multiple-step etching to gain etch selectivity, flexibility and desired etch profile. After the second dummy semiconductor fins 116 are partially removed, the PR layer 142 , the middle layer 144 and the bottom layer 146 of the tri-layer photoresist 140 are removed.

In FIG. 1E , the heights H 3 a and H 3 b of the remaining second dummy semiconductor fins 116 can be about 17% to about 27% the height H 1 of the active semiconductor fins 112 . That is, the heights H 3 a and H 3 b of the remaining second dummy semiconductor fins 116 are about 17 nm to about 40.5 nm. At least one of the second dummy semiconductor fins 116 has a top surface 117 a ( 117 b ). The top surface 117 a ( 117 b ) can be non-concave, such as convex or substantially flat. In some embodiments, the top surface 117 a ( 117 b ) of the second dummy semiconductor fin 116 is curved outwardly. Moreover, in some embodiments, the heights H 3 a and H 3 b of the two remaining second dummy semiconductor fins 116 are substantially the same. The term âsubstantiallyâ as used herein may be applied to modify any quantitative representation which could permissibly vary without resulting in a change in the basic function to which it is related.

Reference is made to FIG. 1F . Still another tri-layer photoresist 150 may be used, including a photoresist (PR) layer 152 as the top or uppermost portion, a middle layer 154 , and a bottom layer 156 . The tri-layer photoresist 150 covers the active semiconductor fins 112 , the first dummy semiconductor fins 114 , and the remaining second dummy semiconductor fins 116 . The tri-layer photoresist 150 provides the PR layer 152 , the middle layer 154 which may include anti-reflective layers or backside anti-reflective layers to aid in the exposure and focus of the PR processing, and the bottom layer 156 which may be a hard mask material; for example, a nitride.

The PR layer 152 of the tri-layer photoresist 150 is then patterned. The patterned PR layer 152 exposes portions of the middle layer 154 disposed on the first dummy semiconductor fins 114 . Meanwhile, another portions of the middle layer 154 disposed on the active dummy semiconductor fins 112 and the remaining second dummy semiconductor fins 116 are still covered by the PR layer 152 . To pattern the tri-layer photoresist 150 , the PR layer 152 is patterned using a mask, exposure to radiation, such as light or an excimer laser, for example, a bake or cure operation to harden the resist, and use of a developer to remove either the exposed or unexposed portions of the resist, depending on whether a positive resist or a negative resist is used, to form the pattern from the mask in the PR layer 152 . This patterned PR layer 152 is then used to etch the underlying middle layer 154 and bottom layer 156 to form an etch mask for the target features; here, the first dummy semiconductor fins 114 .

Reference is made to FIG. 1G . Using the patterned PR layer 152 (see FIG. 1F ) as a mask, the middle layer 154 and the bottom layer 156 of the tri-layer photoresist 150 (see FIG. 1F ) are etched by various methods, including a dry etch, a wet etch, or a combination of dry etch and wet etch. Also, at least portions of the first dummy semiconductor fins 114 are removed (or etched). The dry etching process may implement fluorine-containing gas (e.g., CF 4 , SF 6 , CH 2 F 2 , CHF 3 , and/or C 2 F 6 ), chlorine-containing gas (e.g., Cl 2 , CHCl 3 , CCl 4 , and/or BCl 3 ), bromine-containing gas (e.g., HBr and/or CHBr 3 ), oxygen-containing gas, iodine-containing gas, other suitable gases and/or plasmas, or combinations thereof. The etching process may include a multiple-step etching to gain etch selectivity, flexibility and desired etch profile. After the first dummy semiconductor fins 114 are partially removed, the PR layer 152 , the middle layer 154 and the bottom layer 156 of the tri-layer photoresist 150 are removed.

In FIG. 1G , the heights H 2 a , H 2 b , H 2 c , and H 2 d of the remaining first dummy semiconductor fins 114 can be about 6% to about 16% the height H 1 of the active semiconductor fins 112 . That is, the heights H 2 a , H 2 b , H 2 c , and H 2 d of the remaining first dummy semiconductor fins 114 are about 6 nm to about 24 nm. Moreover, the heights H 3 a and H 3 b of the remaining second dummy semiconductor fins 116 are greater than the heights H 2 a , H 2 b , H 2 c , and H 2 d of the remaining first dummy semiconductor fins 114 . In some embodiments, the height difference between the remaining first dummy semiconductor fins 114 and the second dummy semiconductor fins 116 (i.e., (H 3 a or H 3 b )-(H 2 a , H 2 b , H 2 c or H 2 d )) is about 3 nm to about 30 nm, or about 3% to about 17% of the height H 1 of the active semiconductor fins 112 . In some embodiments, the profile of the remaining first dummy semiconductor fins 114 is symmetric. Or, the heights H 2 a and H 2 d are substantially the same, the heights H 2 b and H 2 c are substantially the same, and the heights H 2 a and H 2 d are greater than the heights H 2 b and H 2 c , and the claimed scope is not limited in this respect. The terms âsubstantiallyâ as used herein may be applied to modify any quantitative representation which could permissibly vary without resulting in a change in the basic function to which it is related.

The first dummy semiconductor fins 114 respectively have

top surfaces

115 a , 115 b , 115 c , and 115 d . The top surfaces 115 a , 115 b , 115 c , and 115 d can be concave. That is, the

top surfaces

115 a , 115 b , 115 c , and 115 d of the remaining first dummy semiconductor fins 114 are curved inwardly. At least one of the

top surfaces

115 a , 115 b , 115 c , and 115 d of the remaining first dummy semiconductor fins 114 and at least one of the top surfaces

117 a and 117 b of the remaining second dummy semiconductor fins 116 are curved in different directions. For example, the

top surfaces

115 a , 115 b , 115 c , and 115 d of the remaining first dummy semiconductor fins 114 are concave (or curved inwardly), and the top surfaces

117 a and 117 b of the remaining second dummy semiconductor fins 116 are non-concave, such as convex (or curved outwardly) or substantially flat. Moreover, in some embodiments, the top surfaces of at least two of the first dummy semiconductor fins 114 form a concave profile C. For example, in FIG. 1G , the

top surfaces

115 a , 115 b , 115 c , and 115 d of the remaining first dummy semiconductor fins 114 form a concave profile.

According to the aforementioned embodiments, the dummy semiconductor fins (i.e., the first and the second dummy semiconductor fins) are removed (or etched or cut) using at least two removing processes (i.e., the processes of FIGS. 1E and 1G ). Furthermore, the outer dummy semiconductor fins (i.e., the second dummy semiconductor fins) are removed before the inner dummy semiconductor fins (i.e., the first dummy semiconductor fins) are removed. Such processes can prevent the active semiconductor fins from being damaged during the removing processes of the dummy semiconductor fins. In greater detail, the second dummy semiconductor fins are removed in advance, such that a space is formed between the first dummy semiconductor fins and the active semiconductor fins. During the removing process of the first dummy semiconductor fins, this space can reduce the probability of etchant from damaging the active semiconductor fins.

Reference is made to FIG. 1H . In some embodiments, at least one isolation structure 160 is formed to cover the first and the second <figure-callout id="114" label="dummy semiconductor fins" filenames="US10964801-20210330-D00000.png,US10964801-20210330-D00003.png"

CLAIMS

Claims ( 20 )

What is claimed is:

1. A semiconductor device comprising:

a substrate;

a first active semiconductor fin disposed on the substrate;

a first dummy semiconductor fin disposed on the substrate, the first dummy semiconductor fin having a first concave upper surface; and

a second dummy semiconductor fin disposed on the substrate, the second dummy semiconductor fin having a second concave upper surface, the first concave upper surface and the second concave upper surface having different curvatures, the second dummy semiconductor fin being disposed between the first active semiconductor fin and the first dummy semiconductor fin, a height of the second dummy semiconductor fin being greater than a height of the first dummy semiconductor fin.

2. The semiconductor device of claim 1 , wherein the first dummy semiconductor fin has a first sidewall and a second sidewall opposite the second sidewall, the first sidewall of the first dummy semiconductor fin having a first height, the second sidewall of the first dummy semiconductor fin having a second height, the first height being greater than the second height.

3. The semiconductor device of claim 1 , wherein the second dummy semiconductor fin has a first sidewall and a second sidewall opposite the second sidewall, the first sidewall of the second dummy semiconductor fin having a first height, the second sidewall of the second dummy semiconductor fin having a second height, the first height being greater than the second height.

4. The semiconductor device of claim 1 , further comprising a third dummy semiconductor fin disposed on the substrate, the third dummy semiconductor fin having a convex upper surface, the third dummy semiconductor fin being disposed between the first active semiconductor fin and the second dummy semiconductor fin, a height of the third dummy semiconductor fin being greater than the height of the second dummy semiconductor fin.

5. The semiconductor device of claim 4 , wherein a height of the first active semiconductor fin is greater than the height of the third dummy semiconductor fin.

6. The semiconductor device of claim 1 , further comprising an isolation region over the substrate, the isolation region covering the first dummy semiconductor fin and the second dummy semiconductor fin.

7. The semiconductor device of claim 1 , wherein the height of the first dummy semiconductor fin is from about 6% to about 16% of a height of the first active semiconductor fin.

8. A semiconductor device comprising:

a substrate;

a first active semiconductor fin disposed on the substrate;

a first dummy semiconductor fin disposed on the substrate, the first dummy semiconductor fin having a first convex upper surface; and

a second dummy semiconductor fin disposed on the substrate, the second dummy semiconductor fin having a first concave upper surface, the first dummy semiconductor fin being disposed between the first active semiconductor fin and the second dummy semiconductor fin, a height of the first dummy semiconductor fin being greater than a height of the second dummy semiconductor fin.

9. The semiconductor device of claim 8 , wherein the height of the first dummy semiconductor fin is about 17% to about 27% of a height of the first active semiconductor fin.

10. The semiconductor device of claim 8 , wherein a difference between the height of the first dummy semiconductor fin and the height of the second dummy semiconductor fin is from about 3% to about 17% of a height of the first active semiconductor fin.

11. The semiconductor device of claim 8 , wherein the height of the second dummy semiconductor fin is from about 6% to about 16% of a height of the first active semiconductor fin.

12. The semiconductor device of claim 8 , wherein a height of the first active semiconductor fin is greater than the height of the first dummy semiconductor fin.

13. The semiconductor device of claim 8 , further comprising an isolation region over the substrate, the isolation region extending along sidewalls and the first convex upper surface of the first dummy semiconductor fin and along sidewalls and the first concave upper surface of the second dummy semiconductor fin.

14. The semiconductor device of claim 8 , further comprising a third dummy semiconductor fin disposed on the substrate, the second dummy semiconductor fin being interposed between the first dummy semiconductor fin and the third dummy semiconductor fin, the third dummy semiconductor fin having a second concave upper surface, the first concave upper surface and the second concave upper surface having different curvatures, the height of the second dummy semiconductor fin being greater than a height of the third dummy semiconductor fin.

15. A method comprising:

forming a first active semiconductor fin, a first dummy semiconductor fin, and a second dummy semiconductor fin on a substrate, wherein the first dummy semiconductor fin is disposed between the first active semiconductor fin and the second dummy semiconductor fin;

etching the first dummy semiconductor fin, a remaining portion of the first dummy semiconductor fin having a first sidewall, the first sidewall having a first height; and

after etching the first dummy semiconductor fin, etching the second dummy semiconductor fin, a remaining portion of the second dummy semiconductor fin having a second sidewall and a third sidewall opposite the second sidewall, the second sidewall having a second height, the third sidewall having a third height, the first height being greater than the second height, the second height being greater than the third height.

16. The method of claim 15 , wherein the remaining portion of the first dummy semiconductor fin has a convex top surface.

17. The method of claim 15 , wherein the remaining portion of the second dummy semiconductor fin has a concave top surface.

18. The method of claim 15 , further comprising forming an isolation structure over the substrate, wherein the isolation structure completely covers the first dummy semiconductor fin and the second dummy semiconductor fin.

19. The method of claim 18 , wherein the first active semiconductor fin protrudes above a top surface of the isolation structure.

20. The method of claim 15 , further comprising forming a second active semiconductor fin on the substrate, wherein the first dummy semiconductor fin and the second dummy semiconductor fin are disposed between the first active semiconductor fin and the second active semiconductor fin.

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2019-11-05

CN106505096A

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US20190140070A1

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US20170069504A1

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2017-03-09

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2019-08-23

Semiconductor device and manufacturing method thereof — Taiwan Semiconductor Manufacturing Co., Ltd. (US10964801B2)

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