ABSTRACT
Abstract
A particle removal method includes loading a particle attracting member with a coating layer into a processing chamber of a processing apparatus. The processing chamber is configured to perform a lithography exposure process on a semiconductor wafer. The method also includes fixing the particle attracting member on a reticle holder in the processing chamber in a cleaning cycle, attracting particles in the processing chamber by the coating layer of the particle attracting member due to a potential difference between the particles and the coating layer, and loading the particle attracting member with the coating layer and the attracted particles out of the processing chamber, after the cleaning cycle. The method also includes loading the semiconductor wafer into the processing chamber, and performing the lithography exposure process on the semiconductor wafer in the processing chamber using a reticle fixed on the reticle holder after the cleaning cycle.
Description
PRIORITY CLAIM AND CROSS-REFERENCE
This application is a Continuation of U.S. application Ser. No. 17/835,152, filed on Jun. 8, 2022, which is a Divisional of U.S. application Ser. No. 16/867,762, filed on May 6, 2020, now U.S. Pat. No. 11,385,555 issued on Jul. 12, 2022, the entirety of which is incorporated by reference herein.
BACKGROUND
The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down has also increased the complexity of processing and manufacturing ICs.
For example, there is a growing need to perform higher-resolution lithography processes. One lithography technique is extreme ultraviolet lithography (EUVL). The EUVL employs scanners using light in the extreme ultraviolet (EUV) region, having a wavelength of about 1-100 nm. One type of EUV light source is laser-produced plasma (LPP). LPP technology produces EUV light by focusing a high-power laser beam onto small fuel target droplets to form highly ionized plasma that emits EUV radiation with a peak of maximum emission at 13.5 nm. The EUV light is then collected by a collector and reflected by optics towards a lithography exposure object, e.g., a wafer.
Although existing methods and devices for the lithography process have been adequate for their intended purposes, they have not been entirely satisfactory in all respects.
BRIEF DESCRIPTION OF THE DRAWINGS
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
FIG. 1 shows a diagram of a semiconductor manufacturing system according to some embodiments of the present disclosure.
FIG. 2 is an enlarged diagram of the wafer holder and a particle attracting member according to some embodiments of the present disclosure
FIG. 3 A is a schematic diagram of the particle attracting member according to some embodiments of the present disclosure.
FIG. 3 B shows a top view of the particle attracting member according to some embodiments of the present disclosure.
FIG. 4 A is a schematic diagram of the particle attracting member according to some embodiments of the present disclosure.
FIG. 4 B shows a top view of the particle attracting member according to some embodiments of the present disclosure.
FIG. 5 A to FIG. 5 C respectively show a top view of the coating layer on the particle attracting member according to other embodiments of the present disclosure.
FIG. 6 is a flowchart of a particle removal method according to some embodiments of the present disclosure.
FIG. 7 is a flowchart of a particle removal method according to some embodiments of the present disclosure.
FIG. 8 shows a schematic view of a semiconductor manufacturing system according to some embodiments of the present disclosure.
DETAILED DESCRIPTION
The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of solutions and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Furthermore, spatially relative terms, such as âbeneath,â âbelow,â âlower,â âabove,â âupperâ and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. It should be understood that additional operations can be provided before, during, and after the method, and some of the operations described can be replaced or eliminated for other embodiments of the method.
The advanced lithography process, method, and materials described in the current disclosure can be used in many applications, including fin-type field effect transistors (FinFETs). For example, the fins may be patterned to produce a relatively close spacing between features, for which the above disclosure is well suited. In addition, spacers used in forming fins of FinFETs can be processed according to the above disclosure.
The present disclosure is generally related to a semiconductor manufacturing system and particle removal methods. More particularly, it is related to system and methods for effectively removing particles from the processing chamber of the semiconductor manufacturing system. One challenge in existing semiconductor manufacturing system is low efficiency for removing particles from the processing chamber and the fact that they take too much time. Therefore, an object of the present disclosure is to minimize the time required to remove particles from the processing chamber, thereby improving the production yield of the semiconductor process. Another challenge is that particles in the processing chamber may be easily concentrated on some module or members. Accordingly, another object of the present disclosure is to enhance local cleaning capabilities of the semiconductor manufacturing system.
Please refer to FIG. 1 , which shows a diagram of a semiconductor manufacturing system 50 according to some embodiments of the present disclosure. As shown in FIG. 1 , the semiconductor manufacturing system 50 includes a semiconductor processing apparatus 60 and a monitoring device 80 . In this embodiment, the semiconductor processing apparatus 60 is a scanning electron microscope (SEM), but it is not limited thereto. For example, the semiconductor processing apparatus 60 can be a critical-dimension scanning electron microscope (CD-SEM), a review-SEM, an EUV scanner, an etching process apparatus or another applicable processing apparatus, in some other embodiments.
As shown in FIG. 1 the semiconductor processing apparatus 60 includes one or more loading ports 61 , a transferring module 63 , a vacuum device 64 , and a processing chamber 65 . It should be understood that the elements of the semiconductor processing apparatus 60 can be added or omitted in different embodiments, and the invention should not be limited by the embodiments.
One or more semiconductor wafers W are loaded into and out of the semiconductor processing apparatus 60 through the loading ports 61 . In some embodiments, the semiconductor wafer W arrives at one loading port 61 contained in a transport carrier (not shown) such as a front-opening unified pod (FOUP), a front-opening shipping box (FOSB), a standard mechanical interface (SMIF) pod, and/or another suitable container. The transport carrier is a magazine for holding one or more semiconductor wafers W and for transporting semiconductor wafers W between different manufacturing tools or working stations. The transport carrier is sealed in order to provide a microenvironment for the semiconductor wafers W contained within and to protect the semiconductor wafers W and the semiconductor processing apparatus 60 against contamination. After being processed in the processing chamber 65 (which will be described later), the semiconductor wafers W may be transferred into another transport carrier for the processed semiconductor wafers W, which will be transported to the next processing system or inspection station.
The transferring module 63 is configured to transfer the semiconductor wafers W between the loading ports 61 and the processing chamber 65 . In some embodiments, the transferring module 63 is disposed in a transferring chamber connecting to the loading ports 61 and connecting to the processing chamber 65 , as shown in FIG. 1 . This configuration allows the transferring module 63 to transfer the semiconductor wafers W between the loading ports 61 and the processing chamber 65 . In some embodiments, the transferring module 63 includes a robotic arm for holding and transferring the semiconductor wafers W.
The processing chamber 65 is configured to perform a specific process on the semiconductor wafers W. The process may include a deposition process such as physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), atomic layer deposition (ALD) or the like; an etching process including wet and dry etching and ion beam milling; a lithographic exposure process; an ion implantation process; a thermal process such as annealing and/or thermal oxidation; a cleaning process such as rinsing and/or plasma ashing; a chemical mechanical polishing or chemical mechanical planarizing (collectively âCMPâ) process; testing; any procedure involved in the processing of the substrate W; and/or any combination thereof.
The semiconductor processing apparatus 60 further includes a wafer holder 66 disposed in the processing chamber 65 , in some embodiments as shown in FIG. 1 . The <figure-callout id="66" label="wafer holder" filenames="US20240085808A1-202
PRIORITY CLAIM AND CROSS-REFERENCE
This application is a Continuation of U.S. application Ser. No. 17/835,152, filed on Jun. 8, 2022, which is a Divisional of U.S. application Ser. No. 16/867,762, filed on May 6, 2020, now U.S. Pat. No. 11,385,555 issued on Jul. 12, 2022, the entirety of which is incorporated by reference herein.
BACKGROUND
The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down has also increased the complexity of processing and manufacturing ICs.
For example, there is a growing need to perform higher-resolution lithography processes. One lithography technique is extreme ultraviolet lithography (EUVL). The EUVL employs scanners using light in the extreme ultraviolet (EUV) region, having a wavelength of about 1-100 nm. One type of EUV light source is laser-produced plasma (LPP). LPP technology produces EUV light by focusing a high-power laser beam onto small fuel target droplets to form highly ionized plasma that emits EUV radiation with a peak of maximum emission at 13.5 nm. The EUV light is then collected by a collector and reflected by optics towards a lithography exposure object, e.g., a wafer.
Although existing methods and devices for the lithography process have been adequate for their intended purposes, they have not been entirely satisfactory in all respects.
BRIEF DESCRIPTION OF THE DRAWINGS
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
FIG. 1 shows a diagram of a semiconductor manufacturing system according to some embodiments of the present disclosure.
FIG. 2 is an enlarged diagram of the wafer holder and a particle attracting member according to some embodiments of the present disclosure
FIG. 3 A is a schematic diagram of the particle attracting member according to some embodiments of the present disclosure.
FIG. 3 B shows a top view of the particle attracting member according to some embodiments of the present disclosure.
FIG. 4 A is a schematic diagram of the particle attracting member according to some embodiments of the present disclosure.
FIG. 4 B shows a top view of the particle attracting member according to some embodiments of the present disclosure.
FIG. 5 A to FIG. 5 C respectively show a top view of the coating layer on the particle attracting member according to other embodiments of the present disclosure.
FIG. 6 is a flowchart of a particle removal method according to some embodiments of the present disclosure.
FIG. 7 is a flowchart of a particle removal method according to some embodiments of the present disclosure.
FIG. 8 shows a schematic view of a semiconductor manufacturing system according to some embodiments of the present disclosure.
DETAILED DESCRIPTION
The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of solutions and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Furthermore, spatially relative terms, such as âbeneath,â âbelow,â âlower,â âabove,â âupperâ and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. It should be understood that additional operations can be provided before, during, and after the method, and some of the operations described can be replaced or eliminated for other embodiments of the method.
The advanced lithography process, method, and materials described in the current disclosure can be used in many applications, including fin-type field effect transistors (FinFETs). For example, the fins may be patterned to produce a relatively close spacing between features, for which the above disclosure is well suited. In addition, spacers used in forming fins of FinFETs can be processed according to the above disclosure.
The present disclosure is generally related to a semiconductor manufacturing system and particle removal methods. More particularly, it is related to system and methods for effectively removing particles from the processing chamber of the semiconductor manufacturing system. One challenge in existing semiconductor manufacturing system is low efficiency for removing particles from the processing chamber and the fact that they take too much time. Therefore, an object of the present disclosure is to minimize the time required to remove particles from the processing chamber, thereby improving the production yield of the semiconductor process. Another challenge is that particles in the processing chamber may be easily concentrated on some module or members. Accordingly, another object of the present disclosure is to enhance local cleaning capabilities of the semiconductor manufacturing system.
Please refer to FIG. 1 , which shows a diagram of a semiconductor manufacturing system 50 according to some embodiments of the present disclosure. As shown in FIG. 1 , the semiconductor manufacturing system 50 includes a semiconductor processing apparatus 60 and a monitoring device 80 . In this embodiment, the semiconductor processing apparatus 60 is a scanning electron microscope (SEM), but it is not limited thereto. For example, the semiconductor processing apparatus 60 can be a critical-dimension scanning electron microscope (CD-SEM), a review-SEM, an EUV scanner, an etching process apparatus or another applicable processing apparatus, in some other embodiments.
As shown in FIG. 1 the semiconductor processing apparatus 60 includes one or more loading ports 61 , a transferring module 63 , a vacuum device 64 , and a processing chamber 65 . It should be understood that the elements of the semiconductor processing apparatus 60 can be added or omitted in different embodiments, and the invention should not be limited by the embodiments.
One or more semiconductor wafers W are loaded into and out of the semiconductor processing apparatus 60 through the loading ports 61 . In some embodiments, the semiconductor wafer W arrives at one loading port 61 contained in a transport carrier (not shown) such as a front-opening unified pod (FOUP), a front-opening shipping box (FOSB), a standard mechanical interface (SMIF) pod, and/or another suitable container. The transport carrier is a magazine for holding one or more semiconductor wafers W and for transporting semiconductor wafers W between different manufacturing tools or working stations. The transport carrier is sealed in order to provide a microenvironment for the semiconductor wafers W contained within and to protect the semiconductor wafers W and the semiconductor processing apparatus 60 against contamination. After being processed in the processing chamber 65 (which will be described later), the semiconductor wafers W may be transferred into another transport carrier for the processed semiconductor wafers W, which will be transported to the next processing system or inspection station.
The transferring module 63 is configured to transfer the semiconductor wafers W between the loading ports 61 and the processing chamber 65 . In some embodiments, the transferring module 63 is disposed in a transferring chamber connecting to the loading ports 61 and connecting to the processing chamber 65 , as shown in FIG. 1 . This configuration allows the transferring module 63 to transfer the semiconductor wafers W between the loading ports 61 and the processing chamber 65 . In some embodiments, the transferring module 63 includes a robotic arm for holding and transferring the semiconductor wafers W.
The processing chamber 65 is configured to perform a specific process on the semiconductor wafers W. The process may include a deposition process such as physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), atomic layer deposition (ALD) or the like; an etching process including wet and dry etching and ion beam milling; a lithographic exposure process; an ion implantation process; a thermal process such as annealing and/or thermal oxidation; a cleaning process such as rinsing and/or plasma ashing; a chemical mechanical polishing or chemical mechanical planarizing (collectively âCMPâ) process; testing; any procedure involved in the processing of the substrate W; and/or any combination thereof.
The semiconductor processing apparatus 60 further includes a wafer holder 66 disposed in the processing chamber 65 , in some embodiments as shown in FIG. 1 . The wafer holder 66 is configured to hold the semiconductor wafer W during processing. The wafer holder 66 can be an electrostatic chuck (e-chuck) that can secure the semiconductor wafer W using electrostatic force, but it is not limited thereto. For example, the wafer holder 66 may alternatively use mechanical, vacuum, or other clamping techniques to secure the semiconductor wafer W. In some embodiments, a driving mechanism (not shown) may further be coupled to the wafer holder 66 and configured to drive the wafer holder 66 and the semiconductor wafer W thereon to rotate along a rotation axis. Accordingly, the semiconductor wafer W is rotated during processing. However, the semiconductor wafer W may be not rotated (i.e., static) during processing, in different embodiments.
The vacuum device 64 is configured to keep the processing chamber 65 in a vacuum state during processing. In some embodiments, the vacuum device 64 is an exhaust pump connecting to the processing chamber 65 . Although not shown, the semiconductor processing apparatus 60 may further include a load lock chamber disposed between the chamber of the transferring module 63 and the processing chamber 65 , in accordance with some embodiments. The load lock chamber is capable of creating an atmosphere compatible with the transferring chamber or the processing chamber 65 depending on where the loaded semiconductor wafer W is scheduled to be next. Accordingly, the atmosphere within the transferring chamber and the processing chamber 65 can be preserved, and the time required for achieving the ideal atmosphere in those chambers is reduced. The load lock chamber also includes an exhaust pump or other suitable means for adjusting the load lock chamber atmosphere.
As shown in FIG. 1 , the semiconductor processing apparatus 60 further includes an electron- beam inspection module 67 disposed in the processing chamber 65 , in accordance with some embodiments. When a semiconductor wafer W is fixed on the wafer holder 66 , the electron- beam inspection module 67 performs an inspection of the semiconductor wafer W, such as a CD-SEM inspection, controlled by a monitoring device 80 (which will be described later).
In the present embodiment, the semiconductor wafer W may be made of silicon or another semiconductor material. Alternatively or additionally, the semiconductor wafer W may include other elementary semiconductor materials such as germanium (Ge). In some embodiments, the semiconductor wafer W is made of a compound semiconductor such as silicon carbide (SiC), gallium arsenic (GaAs), indium arsenide (InAs), or indium phosphide (InP). In some embodiments, the semiconductor wafer W is made of an alloy semiconductor such as silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenic phosphide (GaAsP), or gallium indium phosphide (GaInP). In some other embodiments, the semiconductor wafer W may be a silicon-on-insulator (SOI) or a germanium-on-insulator (GOI) substrate.
In addition, the semiconductor wafer W may have various device elements. Examples of device elements that are formed in the semiconductor wafer W include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors, high-frequency transistors, p-channel and/or n-channel field-effect transistors (PFETs/NFETs), etc.), diodes, and/or other applicable elements. Various processes are performed to form the device elements, such as deposition, etching, implantation, photolithography, annealing, and/or other suitable processes.
It has been found that particles existing within the processing chamber 65 will adversely affect the yield rate of the semiconductor wafers W after processed. For example, particles may fall on the surface of the semiconductor wafer W disposed in the processing chamber 65 during processing, causing defects on the processed semiconductor wafer W. Therefore, it is desirable to effectively remove particles from the processing chamber 65 before sending the semiconductor wafer(s) W into the processing chamber 65 for processing. To this end, before the semiconductor wafer(s) W is placed into the processing chamber 65 , the semiconductor processing apparatus 60 may further utilize a particle attracting member to remove particles from the processing chamber 65 , in accordance with some embodiments as shown in FIG. 2 .
FIG. 2 is an enlarged diagram of the wafer holder 66 and a particle attracting member DW according to some embodiments of the present disclosure. It should be appreciated that the particle attracting member DW may be loaded or transferred into and out of the semiconductor processing apparatus 60 shown in FIG. 1 (as well as the processing chamber 65 ) in a similar manner to the semiconductor wafer W described above. In these embodiments as shown in FIG. 2 , the particle attracting member DW has a disc-shaped structure similar to the semiconductor wafer W. In addition, a thin film such as a coating layer CL for attracting particles (which will be described later) is formed on a surface DWS of the particle attracting member DW. The coating layer CL of the particle attracting member DW has a planar top surface CLS and a cross-sectional shape (in top view) that matches the particle attracting member DW. However, the particle attracting member DW (and the coating layer CL thereon) may have a different shape from the semiconductor wafer W in top view. For example, the particle attracting member DW (and the coating layer CL thereon) may be rectangular, square, triangular or any other suitable shape in different cases, as long as the wafer holder 66 can firmly secure the particle attracting member DW. The coating layer CL may include a Titanium dioxide (TiO2) film, an Oxide thin film or a Nitric thin film, but it is not limited thereto.
When the particle attracting member DW is transferred into the processing chamber 65 and placed on the wafer holder 66 , no processing is performed on the particle attracting member DW, as opposed to performing a specific process on the semiconductor wafers W in the processing chamber 65 described above. For example, in some embodiments as shown in FIG. 1 , when the particle attracting member DW is fixed on the wafer holder 66 , the monitoring device 80 controls the electron- beam inspection module 67 not to perform the inspection on the particle attracting member DW.
In some embodiments, to attract particles in the processing chamber 65 the particle attracting member DW is fixed on the wafer holder 66 for a period of time, such as about two seconds to about one hour (i.e., 3600 seconds), while the processing chamber 65 is in the vacuum state (e.g., caused by the vacuum device 64 ). During the period of time, as shown in FIG. 2 , some particles PT with a first potential in the processing chamber 65 are attracted by the coating layer CL with a second potential due to a potential difference between the coating layer CL and the particles PT. In some embodiments, the coating layer CL includes a Titanium dioxide (TiO2) film, an Oxide thin film or a Nitric thin film, such that the first potential is higher than the second potential, but it is not limited thereto. In some embodiments, the potential difference between the coating layer CL and the particles PT may be greater than about 0.3 electron-volts (EV), such as 0.45 EV, but it is not limited. In some embodiments, the particles PT are attracted onto the top surface CLS of the coating layer CL but do not enter the coating layer CL. That is, there is no chemical reaction between the particles PT and the coating layer CL.
After that, the particle attracting member DW with the particles PT attracted may be removed from the semiconductor processing apparatus 60 . Accordingly, the particles PT in the processing chamber 65 can be removed by the particle attracting member DW. Based on the above design of the particle attracting member DW, the processing chamber 65 can be easily cleaned by the particle attracting member DW without shutting down the semiconductor processing apparatus 60 to allow the operator to manually clean the processing chamber 65 . Consequently, the time required for removing the particles PT from the processing chamber 65 can be greatly reduced. For example, the time it takes for removing the particles PT can be reduced from about 72 hours to about 1 hour or less using the particle attracting member DW, in some embodiments. Moreover, because there are fewer human operations involving the cleaning of the semiconductor processing apparatus 60 , the maintenance costs and the possibility of defects of the semiconductor wafers W can be reduced.
In some embodiments, as shown in FIG. 1 , the semiconductor processing apparatus 60 further includes an airflow device 68 disposed in the processing chamber 65 . The airflow device 68 may be disposed at any suitable place in the processing chamber 65 in order to enhance local cleaning capabilities of the processing chamber 65 by providing airflow. For example, in some embodiments as shown in FIG. 1 , when the particle attracting member DW is fixed on the wafer holder 66 for cleaning the processing chamber 65 , the airflow device 68 can provide airflow to the electron- beam inspection module 67 , and the increased airflow loosens the particles that accumulate or adhere to the electron- beam inspection module 67 , causing them to fall on the particle attracting member DW, which will be removed from the processing chamber 65 later. As a result, the effect of cleaning the electron- beam inspection module 67 is achieved, and the cleanliness of the entire processing chamber 65 is also improved.
In some embodiments, as shown in FIG. 1 , the semiconductor manufacturing system 50 may further include a transferring device 40 and a particle detecting apparatus 70 . The transferring device 40 is configured to transfer the particle attracting member DW between the particle detecting apparatus 70 and the semiconductor processing apparatus 60 . In some embodiments, the particle attracting member DW is received in a closable container like the transport carrier for the semiconductor wafers W described above during transferring between the particle detecting apparatus 70 and the semiconductor processing apparatus 60 . The transferring device 40 may include, for example, an automatic guided vehicle (AGV), a personal guided vehicle (PGV), a rail guided vehicle (RGV), an overhead shuttle (OHS), an overhead hoist transport (OHT) or another applicable transferring device.
The particle detecting apparatus 70 is configured to detect the number of particles on the particle attracting member DW. In some embodiments, the particle detecting apparatus 70 is an optical inspection instrument including at least on loading port, a transferring module, a light detection module (including a light emitter and light receiver), and a detection platform. After the container receiving the particle attracting member DW arrives the loading port of the particle detecting apparatus 70 , the particle attracting member DW may be transferred to the detection platform via the transferring module. The loading port and the transferring module of the particle detecting apparatus 70 may be similar or the same as the loading port 61 and the transferring module 63 illustrated in FIG. 1 , and the description is not repeated herein. When the particle attracting member DW is placed on the detection platform, the light emitter of the light detection module can emit light scanning across the surface of the particle attracting member DW (e.g., the top surface CLS of the coating layer CL), and the light receiver of the light detection module can receive the reflected light. Accordingly, the number of particles on the particle attracting member DW is obtained using optical detection. However, other particle detection or counting methods known in the art can also be used.
The monitoring device 80 can determine whether to control the transferring device 40 to transfer the particle attracting member DW to the semiconductor processing apparatus 60 (for cleaning the processing chamber 65 ) again or not according the detecting result of the particle detecting apparatus 70 . A detailed description about controlling the operation of the transferring device 40 by the monitoring device 80 will be described later.
In this embodiment, the monitoring device 80 may be a computer system. In one example, the computer system includes a processor and a system memory component. In accordance with embodiments of the present disclosure, the computer system performs specific operations via a processor executing one or more sequences of one or more instructions contained in a system memory component.
The processor may include a digital signal processor (DSP), a microcontroller (MCU), and a central processing unit (CPU). The system memory component may include a random access memory (RAM) or another dynamic storage device or read only memory (ROM) or other static storage devices, for storing data and/or instructions to be executed by the processor.
Please refer to FIG. 3 A and FIG. 3 B . FIG. 3 A is a schematic diagram of the particle attracting member DW according to some embodiments of the present disclosure, and FIG. 3 B shows a top view of the particle attracting member DW in FIG. 3 A . In these embodiments, the coating layer CL has some convex structures, such as walls, and the walls intersect with each other. As shown in FIG. 3 B , when viewed in a direction perpendicular to the surface DWS of the particle attracting member DW, the convex structures form a lattice pattern.
Please refer to FIG. 4 A and FIG. 4 B . FIG. 4 A is a schematic diagram of the particle attracting member DW according to some embodiments of the present disclosure, and FIG. 4 B shows a top view of the particle attracting member DW in FIG. 4 A . In these embodiments, the coating layer CL has some convex structures, such as fins, and the fins are parallel to each other. As shown in FIG. 4 B, when viewed in a direction perpendicular to the surface DWS of the particle attracting member DW, the convex structures form a line pattern.
Please refer to FIG. 5 A to FIG. 5 C , which respectively show a top view of the coating layer CL on the particle attracting member DW according to other embodiments of the present disclosure. As shown in FIG. 5 A , the convex structures form a honeycomb pattern. As shown in FIG. 5 B , the convex structures form a rectangular pattern, and each of the convex structures may be a square pillar. As shown in FIG. 5 C , the convex structures form a circular pattern, and each of the convex structures may be a cylinder.
Please refer to FIG. 6 , which is a flowchart of a particle removal method 600 according to some embodiments of the present disclosure. The method 600 includes operation 604 in which a particle attracting member (for example, the particle attracting member DW shown in FIG. 2 , 3 A, 3 B, 4 A, 4 B, 5 A, 5 B or 5 C described above) to be loaded into a semiconductor processing apparatus 60 (see FIG. 1 ) to remove particles is provided. The particle attracting member DW may include a coating layer CL formed on a surface thereof, and the coating layer CL can be formed by Plasma Enhanced Atomic Layer Deposition (PEALD) technology, but it is not limited thereto. Other suitable deposition processes can also be used in different embodiments. The thickness of the coating layer CL may be about 140 to about 210 â«, and the deposition pressure for forming the coating layer may be about 1800 to about 2000 mTorr, but it is not limited thereto. Other thicknesses of the coating layer CL and/or other suitable deposition pressures can also be used. In some embodiments, the coating layer CL may include a Titanium dioxide (TiO2) film, an Oxide thin film or a Nitric thin film, or a combination thereof. In some embodiments, a Titanium dioxide (TiO2) film, and one of an Oxide thin film and a Nitric thin film are formed on different regions of the outer surface of the particle attracting member DW. That is, the coating layer CL in different regions of the particle attracting member DW may include different materials.
The method 600 also includes operation 606 in which the number of particles on the particle attracting member DW is detected by a particle detecting apparatus (for example, the particle detecting apparatus shown in FIG. 1 ) to obtain a first detected data, before loading the particle attracting member DW into the semiconductor processing apparatus 60 . In some embodiments, the first detected data includes a detected value A 1 and a detected value A 2 . The detected value A 1 represents the number of particles with a diameter less than about 0.3 μm, and the detected value A 2 represents the number of particles with a diameter greater than about 0.5 μm. In cases where the particle attracting member DW is used for the first time to remove particles from the processing chamber 65 of semiconductor processing apparatus 60 , both the detected value A 1 and the detected value A 2 of the first detected data are 0.
In addition, the method 600 also includes operation 608 in which the particle attracting member DW is loaded into the processing chamber 65 of the semiconductor processing apparatus 60 so as to perform a cleaning cycle in operations
610 and 612 described below. In some embodiments, after receiving the first detected data from the particle detecting apparatus 70 , the monitoring device 80 controls the transferring device 40 to transfer the particle attracting member DW from the particle detecting apparatus 70 to one loading port 61 of the semiconductor processing apparatus 60 , and then controls the transferring module 63 to transfer the particle attracting member DW onto the wafer holder 66 of the processing chamber 65 , as shown in FIG. 1 .
In operation 610 , the particle attracting member DW is fixed on the wafer holder 66 for a preset period of time, such as about two seconds to about one hour, but it is not limited thereto. In operation 612 , as shown in FIG. 2 , when the particle attracting member DW is fixed on the wafer holder 66 , some particles PT with a first potential in the chamber 65 can be attracted by the coating layer CL with a second potential due to the potential difference between the particles PT and the coating layer CL. In some embodiments, the first potential, such as about 0.5 electron-volts (EV), is higher than the second potential, such as about 0.04 EV. As such, some particles PT having the first potential in the chamber 65 are attracted on the surface of the coating layer CL having the second potential.
Moreover, when the particle attracting member DW is fixed on the wafer holder 66 , as shown in FIG. 1 and FIG. 2 , the monitoring device 80 may control the airflow device 68 to provide an airflow in the processing chamber 65 to blow some particles toward the particle attracting member DW, in some embodiments. For example, the airflow device 68 can provide airflow to the electron- beam inspection module 67 , and the increased airflow loosens the particles that accumulate or adhere to the electron- beam inspection module 67 , causing them to fall on the particle attracting member DW, which will be removed from the processing chamber 65 later. As a result, the effect of cleaning the electron- beam inspection module 67 is achieved, and the cleanliness of the entire processing chamber 65 is also improved.
<para-num
CLAIMS
Claims ( 20 )
What is claimed is:
1 . A particle removal method, comprising:
loading a particle attracting member with a coating layer into a processing chamber of a processing apparatus, wherein the processing chamber is configured to perform a lithography exposure process on a semiconductor wafer; fixing the particle attracting member on a reticle holder in the processing chamber in a cleaning cycle; attracting particles in the processing chamber by the coating layer of the particle attracting member due to a potential difference between the particles and the coating layer; loading the particle attracting member with the coating layer and the attracted particles out of the processing chamber, after the cleaning cycle; loading the semiconductor wafer into the processing chamber; and performing the lithography exposure process on the semiconductor wafer in the processing chamber using a reticle fixed on the reticle holder, wherein the lithography exposure process is performed after the cleaning cycle.
2 . The particle removal method as claimed in claim 1 , further comprising:
determining whether the processing chamber is clean enough for the lithography exposure process for the semiconductor wafer based on a number of the particles attracted to the coating layer, before loading the semiconductor wafer into the processing chamber.
3 . The particle removal method as claimed in claim 2 , wherein the determining comprises:
before loading the particle attracting member into the processing chamber, detecting the number of particles with a specific diameter on the coating layer of the particle attracting member by optical detection to obtain a first detected value; after loading the particle attracting member out of the processing chamber, detecting the number of the particles with the specific diameter on the coating layer of the particle attracting member by optical detection to obtain a second detected value; and calculating a difference between the first detected value and the second detected value.
4 . The particle removal method as claimed in claim 3 , further comprising:
loading the semiconductor wafer into the processing chamber and performing the lithography exposure process on the semiconductor wafer, when the difference between the first detected value and the second detected value is smaller than or equal to a preset value.
5 . The particle removal method as claimed in claim 4 , further comprising:
loading the particle attracting member into the processing chamber again to attract the particles in the processing chamber by the coating layer, when the difference between the first detected value and the second detected value is greater than the preset value.
6 . The particle removal method as claimed in claim 1 , wherein the coating layer includes a Titanium dioxide (TiO 2 ) film, an Oxide thin film or a Nitric thin film.
7 . The particle removal method as claimed in claim 1 , wherein the particle attracting member is fixed on the reticle holder in the processing chamber in the cleaning cycle while the processing chamber is in a vacuum state, and the processing apparatus does not shut down when loading the particle attracting member into and out of the processing chamber.
8 . A particle removal method, comprising:
providing a first particle attracting member with a first coating layer; detecting a number of particles on the first coating layer to obtain a first detected value; loading the first particle attracting member into a processing chamber of a processing apparatus, after obtaining the first detected value, wherein the processing chamber is configured to perform a lithography exposure process on a semiconductor wafer; fixing the first particle attracting member on a reticle holder in the processing chamber in a cleaning cycle; attracting particles in the processing chamber by the first coating layer of the first particle attracting member due to a potential difference between the particles and the first coating layer; loading the first particle attracting member with the first coating layer and the attracted particles out of the processing chamber, after the cleaning cycle; detecting the number of the particles on the first coating layer of the first particle attracting member to obtain a second detected value, after loading the first particle attracting member out of the processing chamber; calculating a difference between the first detected value and the second detected value; and loading the semiconductor wafer into the processing chamber and performing the lithography exposure process on the semiconductor wafer using a reticle fixed on the reticle holder, when the difference between the first detected value and the second detected value is smaller than or equal to a preset value.
9 . The particle removal method as claimed in claim 8 , further comprising:
loading a second particle attracting member with a second coating layer into the processing chamber to attract the particles in the processing chamber by the second coating layer, when the difference between the first detected value and the second detected value is greater than the preset value.
10 . The particle removal method as claimed in claim 8 , further comprising:
polishing the first coating layer of the first particle attracting member after loading the first particle attracting member out of the processing chamber; providing a second particle attracting member by forming a second coating layer on the polished first particle attracting member; and loading the second particle attracting member with the second coating layer into the processing chamber to attract the particles in the processing chamber by the second coating layer.
11 . The particle removal method as claimed in claim 8 , further comprising:
loading the first particle attracting member into the processing chamber again to attract the particles in the processing chamber by the coating layer, when the difference between the first detected value and the second detected value is greater than the preset value.
12 . The particle removal method as claimed in claim 8 , wherein the number of the particles on the first coating layer is detected by optical detection.
13 . The particle removal method as claimed in claim 8 , wherein the particles are attracted to a surface of the first coating layer.
14 . The particle removal method as claimed in claim 8 , wherein in the cleaning cycle, no semiconductor process is performed on the first particle attracting member in the processing chamber.
15 . The particle removal method as claimed in claim 8 , wherein the first coating layer has a higher potential than the particles in the processing chamber.
16 . The particle removal method as claimed in claim 8 , wherein the first coating layer in different regions of the first particle attracting member includes different materials.
17 . A particle removal method, comprising:
loading a first particle attracting member with a coating layer and a second particle attracting member into a processing chamber of a processing apparatus, wherein the processing chamber is configured to perform a lithography exposure process on a semiconductor wafer; fixing the first particle attracting member on a reticle holder and the second particle attracting member on a wafer holder in the processing chamber in a cleaning cycle; attracting particles in the processing chamber by the first coating layer of the first particle attracting member and the second coating layer of the second particle attracting member in the cleaning cycle; loading the first particle attracting member and the second particle attracting member with the attracted particles out of the processing chamber, after the cleaning cycle; loading the semiconductor wafer into the processing chamber; and performing the lithography exposure process on the semiconductor wafer in the processing chamber, wherein the lithography exposure process is performed after the cleaning cycle.
18 . The particle removal method as claimed in claim 17 , wherein the first particle attracting member is fixed on the reticle holder and the second particle attracting member is fixed on the wafer holder in the processing chamber while the processing chamber is in a vacuum state, and the processing apparatus does not shut down when loading the first and second particle attracting members into and out of the processing chamber.
19 . The particle removal method as claimed in claim 17 , wherein the particles in the processing chamber are attracted by the first coating layer of the first particle attracting member and the second coating layer of the second particle attracting member due to a potential difference between the particles and the first coating layer and a potential difference between the particles and the second coating layer.
20 . The particle removal method as claimed in claim 19 , wherein the particles are attracted to a surface of the first coating layer and a surface of the second coating layer.
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Particle removal method
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