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Backside signal interconnection — Taiwan Semiconductor Manufacturing Company, Ltd. (US12230572B2)

Taiwan Semiconductor Manufacturing Company, Ltd. · Google Patents

Google Patents · Patents · License: Open Access

ltd.taiwansemiconductormanufacturingcompany yu

patent, google patents, intellectual property, US12230572B2, Taiwan Semiconductor Manufacturing Company, Ltd., Yu-Xuan Huang, en, 2025

ABSTRACT

Abstract

A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.

Description

PRIORITY

This is a divisional application of U.S. Application Ser. No. 17/196,174, filed Mar. 9, 2021, which claims the benefits of and priority to U.S. Provisional Application No. 63/106,264, filed Oct. 27, 2020, each of which is herein incorporated by reference in its entirety.

BACKGROUND

The electronics industry has experienced an ever-increasing demand for smaller and faster electronic devices that are simultaneously able to support a greater number of increasingly complex and sophisticated functions. To meet these demands, there is a continuing trend in the integrated circuit (IC) industry to manufacture low-cost, high-performance, and low-power ICs. Thus far, these goals have been achieved in large part by reducing IC dimensions (for example, minimum IC feature size), thereby improving production efficiency and lowering associated costs. However, such scaling has also increased complexity of the IC manufacturing processes. Thus, realizing continued advances in IC devices and their performance requires similar advances in IC manufacturing processes and technology.

For example, in standard cell designs, along with the reduction in IC feature size, the size (or footprint) of standard cells (such as Inverter, AND, OR, and NOR cells) are also shrunk in order to increase the circuit density. As a result, the area for signal interconnections (such as in M0, M1, M2 layers, etc.) per standard cell has been decreasing. This has created some adverse effects, such as congested routing, increased parasitic capacitance, and so on. Therefore, although existing approaches in semiconductor fabrication have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIGS. 1 A and 1 B show a flow chart of a method of forming a semiconductor device with backside signal interconnections and backside power rails, according to various aspects of the present disclosure.

FIG. 2 A illustrates a perspective view of a portion of a semiconductor device, according to some embodiments, and FIG. 2 B illustrates a cross-sectional view of the semiconductor device in FIG. 2 A .

FIG. 2 C illustrates a top view of a portion of the semiconductor device in FIG. 2 A , and FIGS. 2 D and 2 E illustrate cross-sectional views of a portion of the semiconductor device of FIG. 2 A along the D-D line and the E-E line in FIG. 2 C , respectively, according to some embodiments.

FIGS. 3 , 4 , 5 , 6 , 7 , 8 A, 9 , 10 , 11 A, 12 , 13 , 14 , and 15 illustrate perspective views of a portion of the semiconductor device in FIG. 2 A , according to some embodiments.

FIGS. 8 B and 11 B illustrates a plan view of a portion of the semiconductor device in FIG. 2 A , according to some embodiments.

FIGS. 16 A, 16 B, 16 C, 16 D, and 16 E illustrate schematic layout views of a portion of the semiconductor device in FIG. 2 A , according to some embodiments.

FIGS. 17 A, 17 B, 17 C, 17 D, 17 E, 17 F, 17 G, 18 A, 18 B, 18 C, 18 D, 18 E, 18 F, 18 G, and 18 H illustrate perspective views of a portion of the semiconductor device in FIG. 2 A , according to some embodiments.

FIG. 19 A illustrate a schematic view of a portion of the semiconductor device in FIG. 2 A , according to some embodiments. FIGS. 19 B and 19 C illustrate layout views of the portion of the semiconductor device in FIG. 19 A , according to some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as âbeneath,â âbelow,â âlower,â âabove,â âupperâ and the like, may be used herein for case of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Still further, when a number or a range of numbers is described with âabout,â âapproximate,â and the like, the term encompasses numbers that are within certain variations (such as +/â10% or other variations) of the number described, in accordance with the knowledge of the skilled in the art in view of the specific technology disclosed herein, unless otherwise specified. For example, the term âabout 5 nmâ may encompass the dimension range from 4.5 nm to 5.5 nm, 4.0 nm to 5.0 nm, etc.

This application generally relates to semiconductor structures and fabrication processes, and more particularly to semiconductor devices with backside signal interconnections and backside power rails. As discussed above, signal interconnections (or signal routing) has become more and more congested as the device downscaling continues. An object of the present disclosure includes providing signal interconnections on a back side (or backside) of a structure containing transistors in addition to an interconnect structure on a front side (or frontside) of the structure. The transistors can include gate-all-around (GAA) transistors, FinFET transistors, and/or other types of transistors. The backside signal interconnections can be made between a source/drain feature and another source/drain feature, between a source/drain feature and a gate, and between a gate and another gate. The structure is further provided with backside power rails (or power routings) below the backside signal interconnections in addition to power rails in the frontside interconnect structure. Thus, the structure is provided with increased number of signal routing tracks and power routing tracks for directly connecting to transistors' source/drain features and gates. Using the present disclosure, building blocks (such as standard cells) of ICs can be made smaller and circuit density of ICs can be made higher. The details of the structure and fabrication methods of the present disclosure are described below in conjunction with the accompanied drawings, which illustrate a process of making a GAA device, according to some embodiments. A GAA device refers to a device having vertically-stacked horizontally-oriented multi-channel transistors, such as nanowire transistors and nanosheet transistors. GAA devices are promising candidates to take CMOS to the next stage of the roadmap due to their better gate control ability, lower leakage current, and fully FinFET device layout compatibility. The present disclosure can also be utilized to make FinFET devices having backside signal interconnections and backside power rails. For purposes of simplicity, the present disclosure uses GAA devices as an example. Those of ordinary skill in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures, such as FinFET devices, for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein.

FIGS. 1 A and 1 B are a flow chart of a method 100 for fabricating a semiconductor device according to various aspects of the present disclosure. Additional processing is contemplated by the present disclosure. Additional operations can be provided before, during, and after method 100 , and some of the operations described can be moved, replaced, or eliminated for additional embodiments of method 100 .

Method 100 is described below in conjunction with FIG. 2 A through FIG. 15 that illustrate various top, cross-sectional, and perspective views of a semiconductor device (or a semiconductor structure) 200 at various steps of fabrication according to the method 100 , in accordance with some embodiments. In some embodiments, the device 200 is a portion of an IC chip, a system on chip (SoC), or portion thereof, that includes various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), FinFET, nanosheet FETs, nanowire FETs, other types of multi-gate FETs, metal-oxide semiconductor field effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, memory devices, other suitable components, or combinations thereof. FIGS. 2 A through 15 have been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in the device 200 , and some of the features described below can be replaced, modified, or eliminated in other embodiments of the device 200 .

At operation 102 , the method 100 ( FIG. 1 A ) provides a semiconductor structure (or semiconductor device or device) 200 having a substrate 201 , a device layer 500 over the frontside of the substrate 201 , and an interconnect structure (or a multilayer interconnect) 600 over the device layer 500 . The device layer 500 includes transistors. FIG. 2 A illustrates a perspective view of the device 200 , and FIG. 2 B illustrates a cross-sectional view of the device 200 , in portion. The device 200 may include other layers or features not shown in FIG. 2 A , such as a passivation layer over the interconnect structure 600 . The substrate 201 is at a backside of the device 200 , and the interconnect structure 600 is at a frontside of device 200 . In other words, the substrate 201 , the device layer 500 , and the interconnect structure 600 are disposed one over another from the backside to the frontside of the device 200 .

The substrate 201 is a bulk silicon (Si) substrate in the present embodiment, such as a silicon wafer. In alternative embodiments, the substrate 201 includes other semiconductors such as germanium (Ge); a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP); or an alloy semiconductor, such as silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenic phosphide (GaAsP), and gallium indium phosphide (GaInP). In some embodiments, the <figure-callout

PRIORITY

BACKGROUND

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 3 , 4 , 5 , 6 , 7 , 8 A, 9 , 10 , 11 A, 12 , 13 , 14 , and 15 illustrate perspective views of a portion of the semiconductor device in FIG. 2 A , according to some embodiments.

FIGS. 8 B and 11 B illustrates a plan view of a portion of the semiconductor device in FIG. 2 A , according to some embodiments.

FIGS. 16 A, 16 B, 16 C, 16 D, and 16 E illustrate schematic layout views of a portion of the semiconductor device in FIG. 2 A , according to some embodiments.

DETAILED DESCRIPTION

The device layer 500 includes semiconductor active regions (such as semiconductor fins), and various active devices (e.g., transistors) built in or on the semiconductor active regions. The device layer 500 may also include passive devices such as capacitors, resistors, and inductors. The device layer 500 further includes local interconnects, isolation structures, and other structures.

The interconnect structure 600 is over the device layer 500 and includes conductors 666 (such as metal lines and vias) embedded in one or more dielectric layers 664 . The conductors 666 provide connectivity to the devices in the device layer 500 . The conductors 666 may also provide power rails and ground planes for the device 200 . The conductors 666 may comprise copper, aluminum, or other suitable materials, and may be formed using single damascene process, dual damascene process, or other suitable processes. The dielectric layers 664 may comprise silicon nitride, silicon oxynitride, silicon nitride with oxygen (O) or carbon (C) elements, tetraethylorthosilicate (TEOS) formed oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials.

FIG. 2 C shows a top view of a portion of the device 200 , and FIGS. 2 D and 2 E show cross-sectional views of a portion of the device 200 along the D-D line and the E-E line in FIG. 2 C , respectively. The device 200 includes gate stacks 240 oriented lengthwise along the âyâ direction and active regions (such as semiconductor fins) 204 oriented lengthwise along the âxâ direction. The example shown in FIG. 2 C includes 4 transistors 202 , each at an intersection of the gate stacks 240 and the semiconductor fins 204 . As will be discussed, each transistor 202 includes two source/drain (S/D) features 260 on opposing sides of the respective gate stack 240 and one or more channel layer 215 connecting the two S/D features and engaged by the respective gate stack 240 . FIGS. 2 C, 2 D, and 2 E illustrate further details of the device layer 500 . Particularly, the D-D line is cut along the lengthwise direction of a semiconductor fin 204 (âxâ direction) and the E-E line is cut into the source/drain regions of the transistors and is parallel to the lengthwise direction of gate stacks 240 (âyâ direction).

Referring to FIGS. 2 C- 2 E , the semiconductor device 200 includes isolation features 230 (or isolation structure 230 ) over the substrate 201 , semiconductor fins 204 extending from the substrate 201 and adjacent to the isolation features 230 , and source/drain (S/D) features 260 over the semiconductor fins 204 in the S/D regions. The semiconductor device 200 further includes one or more channel semiconductor layers (or channel layers) 215 suspended over the semiconductor fins 204 and connecting the S/D features 260 along the âxâ direction, and gate stacks 240 between the S/D features 260 and wrapping around each of the channel layers 215 . The semiconductor device 200 further includes inner spacers 255 between the S/D features 260 and the gate stack 240 , an outer gate spacer 247 over sidewalls of the gate stack 240 and over the topmost channel layer 215 , a contact etch stop layer (CESL) 269 adjacent to the gate spacer 247 and over the S/D features 260 and the isolation features 230 , an inter-layer dielectric (ILD) layer 270 over the CESL 269 , another CESL 269 â² over the ILD 270 , and another ILD 270 â² over the CESL 269 â². Over the gate stacks 240 , the semiconductor device 200 further includes a self-aligned capping layer 352 . In some implementations (like depicted in FIG. 2 D ), a glue layer 357 may be deposited over the gate stacks 240 and to improve adhesion between the gate stacks 240 and the gate vias 359 and to reduce contact resistance thereof. Over the S/D features 260 , the semiconductor device 200 further includes silicide features 273 , S/ D contacts 275 , dielectric S/ D capping layer 356 , and S/D contact via 358 . In the depicted embodiment, the dielectric S/ D capping layer 356 is disposed over some of the source/drain features 260 , and the S/D contact via 358 is disposed over other source/drain features 260 . The device 200 further includes a semiconductor layer 239 below some of the S/D features 260 . In an embodiment, the semiconductor layer 239 includes a semiconductor material that is different from the semiconductor fin 204 and serves as a placeholder for backside via formation. In an embodiment where the device 200 is a FinFET device, the channel layers 215 are merged into one channel layer (a semiconductor fin channel), and the inner spacers 255 are omitted. Further, in such FinFET embodiment, the gate stack 240 engages top and sidewalls of the semiconductor fin channel, and in the cross-sectional view of FIG. 2 D , the gate stack 240 would be on top of the semiconductor fin channel only. The various elements of the semiconductor device 200 are further described below.

In various embodiments, the semiconductor fins 204 may include silicon, silicon germanium, germanium, or other suitable semiconductor, and may be undoped, unintentionally doped, or slightly doped with n-type or p-type dopants. The fins 204 may be patterned by any suitable method. For example, the fins 204 may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers, or mandrels, may then be used as a masking element for patterning the fins 204 . For example, the masking element may be used for etching recesses into semiconductor layers over or in the substrate 201 , leaving the fins 204 on the substrate 201 . The etching process may include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes. For example, a dry etching process may implement an oxygen-containing gas, a fluorine-containing gas (e.g., CF 4 , SF 6 , CH 2 F 2 , CHF 3 , and/or C 2 F 6 ), a chlorine-containing gas (e.g., Cl 2 , CHCl 3 , CCl 4 , and/or BCl 3 ), a bromine-containing gas (e.g., HBr and/or CHBr 3 ), an iodine-containing gas, other suitable gases and/or plasmas, and/or combinations thereof. For example, a wet etching process may comprise etching in diluted hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO 3 ), and/or acetic acid (CH 3 COOH); or other suitable wet etchant. Numerous other embodiments of methods to form the fins 204 may be suitable.

The isolation features 230 may include silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation material (for example, including silicon, oxygen, nitrogen, carbon, or other suitable isolation constituent), or combinations thereof. Isolation features 230 can include different structures, such as shallow trench isolation (STI) structures and/or deep trench isolation (DTI) structures. In an embodiment, the isolation features 230 can be formed by filling the trenches between fins 204 with insulator material (for example, by using a CVD process or a spin-on glass process), performing a chemical mechanical polishing (CMP) process to remove excessive insulator material and/or planarize a top surface of the insulator material layer, and etching back the insulator material layer to form isolation features 230 . In some embodiments, isolation features 230 include a multi-layer structure, such as a silicon nitride layer disposed over a thermal oxide liner layer.

The semiconductor layer 239 may be deposited using an epitaxial growth process or by other suitable processes. In some embodiments, epitaxial growth of semiconductor layers 239 is achieved by a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process, a metalorganic chemical vapor deposition (MOCVD) process, other suitable epitaxial growth process, or combinations thereof. The semiconductor layer 239 includes a semiconductor material that is different than the semiconductor material included in the semiconductor fins 204 to achieve etching selectivity during subsequent processing. For example, semiconductor layer 239 and semiconductor fins 204 may include different materials, different constituent atomic percentages, different constituent weight percentages, and/or other characteristics to achieve desired etching selectivity during an etching process. In an embodiment, the semiconductor fins 204 includes silicon and the semiconductor layer 239 includes silicon germanium. In another embodiment, semiconductor layer 239 and semiconductor fins 204 can both include silicon germanium, but with different silicon atomic percent. The present disclosure contemplates that semiconductor layer 239 and semiconductor fins 204 include any combination of semiconductor materials that can provide desired etching selectivity, including any of the semiconductor materials disclosed herein. The semiconductor layer 239 serves as a placeholder for backside vias and/or backside isolation.

The S/D features 260 include epitaxially grown semiconductor materials such as epitaxially grown silicon, germanium, or silicon germanium. The S/D features 260 can be formed by any epitaxy processes including chemical vapor deposition (CVD) techniques, molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. The S/D features 260 may be doped with n-type dopants and/or p-type dopants. In some embodiments, for n- type transistors 202 , the S/D features 260 include silicon and can be doped with carbon, phosphorous, arsenic, other n-type dopant, or combinations thereof (for example, forming Si:C epitaxial S/D features, Si:P epitaxial S/D features, or Si:C:P epitaxial S/D features). In some embodiments, for p- type transistors 202 , the S/D features 260 include silicon germanium or germanium, and can be doped with boron, other p-type dopant, or combinations thereof (for example, forming Si:Ge:B epitaxial S/D features). The S/D features 260 may include multiple epitaxial semiconductor layers having different levels of dopant density. In some embodiments, annealing processes (e.g., rapid thermal annealing (RTA) and/or laser annealing) are performed to activate dopants in the epitaxial S/D features 260 .

In embodiments, the channel layers 215 includes a semiconductor material suitable for transistor channels, such as silicon, silicon germanium, or other semiconductor material(s). The channel layers 215 may be in the shape of rods, bars, sheets, or other shapes in various embodiments. In an embodiment, the channel layers 215 are initially part of a stack of semiconductor layers that include the channel layers 215 and other (sacrificial) semiconductor layers alternately stacked layer-by-layer. The sacrificial semiconductor layers and the channel layers 215 include different material compositions (such as different semiconductor materials, different constituent atomic percentages, and/or different constituent weight percentages) to achieve etching selectivity. During a gate replacement process to form the gate stack 240 , the sacrificial semiconductor layers are removed, leaving the channel layers 215 suspended over the semiconductor fins 204 .

In some embodiments, the inner spacer layer 255 includes a dielectric material that includes silicon, oxygen, carbon, nitrogen, other suitable material, or combinations thereof (for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or silicon oxycarbonitride). In some embodiments, the inner spacer layer 255 includes a low-k dielectric material, such as those described herein. The inner spacer layer 255 may be formed by deposition and etching processes. For example, after S/D trenches are etched and before the S/D features 260 are epitaxially grown from the S/D trenches, an etch process may be used to recess the sacrificial semiconductor layers between the adjacent channel layers 215 to form gaps vertically between the adjacent channel layers 215 . Then, one or more dielectric materials are deposited (using CVD or ALD for example) to fill the gaps. Another etching process is performed to remove the dielectric materials outside the gaps, thereby forming the inner spacer layer 255 .

In the depicted embodiment, each gate stack 240 includes a gate dielectric layer 349 and a gate electrode 350 . The gate dielectric layer 349 may include a high-k dielectric material such as HfO 2 , HfSiO, HfSiO 4 , HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO x , ZrO, ZrO 2 , ZrSiO 2 , AlO, AlSiO, Al 2 O 3 , TiO, TiO 2 , LaO, LaSiO, Ta 2 O 3 , Ta 2 O 5 , Y 2 O 3 , SrTiO 3 , BaZrO, BaTiO 3 (BTO), (Ba,Sr) TiO 3 (BST), Si 3 N 4 , hafnium dioxide-alumina (HfO 2 âAl 2 O 3 ) alloy, other suitable high-k dielectric material, or combinations thereof. High-k dielectric material generally refers to dielectric materials having a high dielectric constant, for example, greater than that of silicon oxide (kâ3.9). The gate dielectric layer 349 may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and/or other suitable methods. In some embodiments, the gate stack 240 further includes an interfacial layer between the gate dielectric layer 349 and the channel layers 215 . The interfacial layer may include silicon dioxide, silicon oxynitride, or other suitable materials. In some embodiments, the gate electrode layer 350 includes an n-type or a p-type work function layer and a metal fill layer. For example, an n-type work function layer may comprise a metal with sufficiently low effective work function such as titanium, aluminum, tantalum carbide, tantalum carbide nitride, tantalum silicon nitride, or combinations thereof. For example, a p-type work function layer may comprise a metal with a sufficiently large effective work function, such as titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or combinations thereof. For example, a metal fill layer may include aluminum, tungsten, cobalt, copper, and/or other suitable materials. The gate electrode layer 350 may be formed by CVD, PVD, plating, and/or other suitable processes. Since the gate stack 240 includes a high-k dielectric layer and metal layer(s), it is also referred to as a high-k metal gate.

In an embodiment, the gate spacer 247 includes a dielectric material such as a dielectric material including silicon, oxygen, carbon, nitrogen, other suitable material, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbide, silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbon nitride (SiOCN)). In embodiments, the gate spacer 247 may include La 2 O 3 , Al 2 O 3 , ZnO, ZrN, Zr 2 Al 3 O 9 , TiO 2 , TaO 2 , ZrO 2 , HfO 2 , Y 2 O 3 , AlON, TaCN, ZrSi, or other suitable material(s). For example, a dielectric layer including silicon and nitrogen, such as a silicon nitride layer, can be deposited over a dummy gate stack (which is subsequently replaced by the high-k metal gate stack 240 ) and subsequently etched (e.g., anisotropically etched) to form gate spacers 247 . In some embodiments, gate spacers 247 include a multi-layer structure, such as a first dielectric layer that includes silicon nitride and a second dielectric layer that includes silicon oxide. In some embodiments, more than one set of spacers, such as seal spacers, offset spacers, sacrificial spacers, dummy spacers, and/or main spacers, are formed adjacent to the gate stack 240 . In embodiments, the gate spacer 247 may have a thickness of about 1 nm to about 40 nm, for example.

In some embodiments, the SAC layer 352 includes La 2 O 3 , Al 2 O 3 , SiOCN, SiOC, SiCN, SiO 2 , SiC, ZnO, ZrN, Zr 2 Al 3 O 9 , TiO 2 , TaO 2 , ZrO 2 , HfO 2 , Si 3 N 4 , Y 2 O 3 , AlON, TaCN, ZrSi, or other suitable material(s). The SAC layer 352 protects the gate stacks 240 from etching and CMP processes that are used for etching S/D contact holes. The SAC layer 352 may be formed by recessing the gate stacks 240 and optionally recessing the gate spacers 247 , depositing one or more dielectric materials over the recessed gate stacks 240 and optionally over the recessed gate spacers 247 , and performing a CMP process to the one or more dielectric materials.

In embodiments, the CESLs

269 and 269 â² may each include La 2 O 3 , Al 2 O 3 , SiOCN, SiOC, SiCN, SiO 2 , SiC, ZnO, ZrN, Zr 2 Al 3 O 9 , TiO 2 , TaO 2 , ZrO 2 , HfO 2 , Si 3 N 4 , Y 2 O 3 , AlON, TaCN, ZrSi, or other suitable material(s); and may be formed by CVD, PVD, ALD, or other suitable methods. The ILD layers 270 and 270 â² may each comprise tetraethylorthosilicate (TEOS) formed oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fluoride-doped silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), a low-k dielectric material, other suitable dielectric material, or combinations thereof. The ILD layers 270 and 270 â² may each be formed by PECVD (plasma enhanced CVD), FCVD (flowable CVD), or other suitable methods.

In some embodiments, the silicide features 273 may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel-platinum silicide (NiPtSi), nickel-platinum-germanium silicide (NiPtGeSi), nickel-germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds.

In an embodiment, the S/ D contacts 275 may include a conductive barrier layer and a metal fill layer over the conductive barrier layer. The conductive barrier layer may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or a conductive nitride such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or combinations thereof, and may be formed by CVD. PVD. ALD, and/or other suitable processes. The metal fill layer may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), nickel (Ni), copper (Cu), or other metals, and may be formed by CVD. PVD, ALD, plating, or other suitable processes. In some embodiments, the conductive barrier layer is omitted in the S/ D contacts 275 .

In some embodiments, the capping layer 356 includes La 2 O 3 , Al 2 O 3 , SiOCN, SiOC, SiCN, SiO 2 , SiC, ZnO, ZrN, Zr 2 Al 3 O 9 , TiO 2 , TaO 2 , ZrO 2 , HfO 2 , Si 3 N 4 , Y 2 O 3 , AlON, TaCN, ZrSi, or other suitable material(s). The capping layer 356 protects the S/ D contacts 275 from etching and CMP processes and isolating the S/ D contacts 275 from the interconnect structure formed thereon. In some embodiments, the SAC layer 352 and the capping layer 356 include different materials to achieve etch selectivity, for example, during the formation of the capping layer 356 .

In an embodiment, the S/D contact vias 358 and the gate vias 359 may each include a conductive barrier

CLAIMS

Claims ( 20 )

What is claimed is:

1. A semiconductor structure, comprising:

a first transistor having a first source/drain (S/D) feature and a first gate;

a second transistor having a second S/D feature and a second gate;

a multi-layer interconnection disposed over the first and the second transistors;

a signal interconnection under the first and the second transistors; and

a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.

2. The semiconductor structure of claim 1 , further comprising:

a first via under the first transistor and electrically connected to the first S/D feature; and

a second via under the second transistor and electrically connected to the second S/D feature, wherein the first and the second vias are isolated from the power rail, and the signal interconnection directly contacts the first via and the second via.

3. The semiconductor structure of claim 2 , wherein a bottom surface of the signal interconnection is substantially flat, and a top surface of the signal interconnection has a step profile.

4. The semiconductor structure of claim 2 , wherein a first sidewall surface of the signal interconnection directly contacts the first via, and a second sidewall surface of the signal interconnection directly contacts the second via.

5. The semiconductor structure of claim 1 , wherein the signal interconnection electrically connects the first gate to the second gate.

6. The semiconductor structure of claim 5 , wherein a bottom surface of the signal interconnection is substantially flat, and a top surface of the signal interconnection has two protrusions that directly contact the first gate and the second gate.

7. The semiconductor structure of claim 1 , further comprising:

a first via under the first transistor and electrically connected to the first S/D feature, wherein the signal interconnection directly contacts the first via and the second gate.

8. The semiconductor structure of claim 7 , wherein a bottom surface of the signal interconnection is substantially flat, a sidewall surface of the signal interconnection directly contacts the first via, and a top surface of the signal interconnection directly contacts the second gate.

9. The semiconductor structure of claim 1 , wherein the signal interconnection is part of a standard logic cell and is routed within boundaries of the standard logic cell.

10. The semiconductor structure of claim 1 , wherein the first transistor further includes a third S/D feature, further comprising:

a third via under the first transistor and electrically connecting the third S/D feature to the power rail.

11. A semiconductor structure, comprising:

a first transistor having a first source/drain (S/D) feature and a first gate;

a second transistor having a second S/D feature and a second gate;

a signal interconnection under the first and the second transistors;

an isolation feature under the signal interconnection; and

a power rail under the isolation feature,

wherein the signal interconnection electrically connects the first S/D feature to the second S/D feature and the isolation feature electrically isolates the signal interconnection from the power rail.

12. The semiconductor structure of claim 11 , further comprising:

a first via vertically between the first S/D feature and the isolation feature; and

a second via vertically between the second S/D feature and the isolation feature, and the signal interconnection directly contacts the first via and the second via.

13. The semiconductor structure of claim 11 , wherein a bottom surface of the signal interconnection is substantially flat, and a top surface of the signal interconnection has a step profile.

14. The semiconductor structure of claim 11 , further comprising:

a third transistor having a third S/D feature and a third gate; and

a dielectric spacer isolating the third S/D feature from the signal interconnection,

wherein the third S/D feature is electrically connected to the power rail.

15. The semiconductor structure of claim 14 , further comprising:

a third via vertically between the third S/D feature and the power rail to electrically connect the third S/D feature to the power rail, wherein the third via directly contacts the third S/D feature and the power rail.

16. The semiconductor structure of claim 15 , further comprising:

a first via vertically between the first S/D feature and the isolation feature,

wherein a lateral portion of the isolation feature is directly between and contacting the first via and the third via, and the lateral portion isolates the first via from the third via.

17. A semiconductor structure, comprising:

a substrate;

a first transistor disposed over the substrate, the first transistor having a first source/drain (S/D) feature and a first gate;

a second transistor disposed over the substrate, the second transistor having a second S/D feature and a second gate;

a signal interconnection under the first and the substrate;

an isolation feature under the signal interconnection; and

a power rail under the isolation feature,

wherein the signal interconnection electrically connects the first gate to the second gate and the isolation feature electrically isolates the signal interconnection from the power rail.

18. The semiconductor structure of claim 17 , wherein a bottom surface of the signal interconnection is substantially flat, and a top surface of the signal interconnection has two protrusions that directly contact the first gate and the second gate.

19. The semiconductor structure of claim 17 , further comprising:

a first via vertically between the first S/D feature and the power rail to electrically connect the first S/D feature to the power rail, wherein the first via directly contacts the first S/D feature and the power rail; and

a second via vertically between the second S/D feature and the power rail to electrically connect the second S/D feature to the power rail, wherein the second via directly contacts the second S/D feature and the power rail.

20. The semiconductor structure of claim 19 , further comprising:

a dielectric spacer isolating the first and second S/D vias from the signal interconnection.

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