ABSTRACT
Abstract
A 3D integrated circuit, the circuit including: a first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; and a second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors, where the second wafer is bonded face-to-face on top of the first wafer, where the bonded includes copper to copper bonding, and where the second crystalline substrate has been thinned to a thickness of less than 5 micro-meters.
Description
CROSS-REFERENCE OF RELATED APPLICATIONS
This application is a continuation-in-part of co-pending U.S. patent application Ser. No. 15/922,913 filed Mar. 16, 2018, (now issued as U.S. Pat. No. 10,354,995 on Jul. 16, 2019), which is a continuation-in-part of U.S. patent application Ser. No. 15/409,740 filed Jan. 19, 2017, (now issued as U.S. Pat. No. 9,941,332 on Apr. 10, 2018), which is a continuation-in-part of U.S. patent application Ser. No. 15/224,929 filed Aug. 1, 2016 (now issued as U.S. Pat. No. 9,853,089 on Dec. 26, 2017), which is a continuation-in-part of U.S. patent application Ser. No. 14/514,386 filed Oct. 15, 2014 (now issued as U.S. Pat. No. 9,406,670 on Aug. 2, 2016), which is a continuation of U.S. patent application Ser. No. 13/492,382 filed Jun. 8, 2012 (now issued as U.S. Pat. No. 8,907,442 on Dec. 9, 2014), which is a continuation of U.S. patent application Ser. No. 13/246,384 filed Sep. 27, 2011 (now issued as U.S. Pat. No. 8,237,228 on Aug. 7, 2012), which is a continuation U.S. patent application Ser. No. 12/900,379 filed Oct. 7, 2010 (now issued as U.S. Pat. No. 8,395,191 on Mar. 12, 2013), which is a continuation-in-part of U.S. patent application Ser. No. 12/859,665 filed Aug. 19, 2010 (now issued as U.S. Pat. No. 8,405,420 on Mar. 26, 2013), which is a continuation-in-part of U.S. patent application Ser. No. 12/849,272 filed Aug. 3, 2010 (now issued as U.S. Pat. No. 7,986,042 on Jul. 26, 2011) and U.S. patent application Ser. No. 12/847,911 filed Jul. 30, 2010 (now issued as U.S. Pat. No. 7,960,242 on Jun. 14, 2011); U.S. patent application Ser. No. 12/847,911 is a continuation-in-part of U.S. patent application Ser. No. 12/792,673 filed Jun. 2, 2010 (now issued as U.S. Pat. No. 7,964,916 on Jun. 21, 2011), U.S. patent application Ser. No. 12/797,493 filed Jun. 9, 2010 (now issued as U.S. Pat. No. 8,115,511 on Feb. 14, 2012), and U.S. patent application Ser. No. 12/706,520 filed Feb. 16, 2010; both U.S. patent application Ser. No. 12/792,673 and U.S. patent application Ser. No. 12/797,493 are continuation-in-part applications of U.S. patent application Ser. No. 12/577,532 filed Oct. 12, 2009, the entire contents of all of the foregoing are incorporated by reference. The entire contents of U.S. application Ser. No. 13/273,712, which was filed on Oct. 14, 2011, and is now U.S. Pat. No. 8,273,610, is incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the general field of Integrated Circuit (IC) devices and fabrication methods, and more particularly to multilayer or Three Dimensional Integrated Circuit (3D IC) devices and fabrication methods.
2. Discussion of Background Art
Semiconductor manufacturing is known to improve device density in an exponential manner over time, but such improvements come with a price. The mask set cost required for each new process technology has also been increasing exponentially. While 20 years ago a mask set cost less than $20,000, it is now quite common to be charged more than $1M for today's state of the art device mask set.
These changes represent an increasing challenge primarily to custom products, which tend to target smaller volume and less diverse markets therefore making the increased cost of product development very hard to accommodate.
Over the past 40 years, there has been a dramatic increase in functionality and performance of Integrated Circuits (ICs). This has largely been due to the phenomenon of âscalingâ; i.e., component sizes such as lateral and vertical dimensions within ICs have been reduced (âscaledâ) with every successive generation of technology. There are two main classes of components in Complementary Metal Oxide Semiconductor (CMOS) ICs, namely transistors and wires. With âscalingâ, transistor performance and density typically improve and this has contributed to the previously-mentioned increases in IC performance and functionality. However, wires (interconnects) that connect together transistors degrade in performance with âscalingâ. The situation today is that wires dominate the performance, functionality and power consumption of ICs.
3D stacking of semiconductor devices or chips is one avenue to tackle the wire issues. By arranging transistors in 3 dimensions instead of 2 dimensions (as was the case in the 1990 s ), the transistors in ICs can be placed closer to each other. This reduces wire lengths and keeps wiring delay low.
There are many techniques to construct 3D stacked integrated circuits or chips including:
Through-silicon via (TSV) technology: Multiple layers of transistors (with or without wiring levels) can be constructed separately. Following this, they can be bonded to each other and connected to each other with through-silicon vias (TSVs). Monolithic 3D technology: With this approach, multiple layers of transistors and wires can be monolithically constructed. Some monolithic 3D and 3DIC approaches are described in U.S. Pat. Nos. 8,273,610, 8,298,875, 8,362,482, 8,378,715, 8,379,458, 8,450,804, 8,557,632, 8,574,929, 8,581,349, 8,642,416, 8,669,778, 8,674,470, 8,687,399, 8,742,476, 8,803,206, 8,836,073, 8,902,663, 8,994,404, 9,023,688, 9,029,173, 9,030,858, 9,117,749, 9,142,553, 9,219,005, 9,385,058, 9,509,313, 9,640,531, 9,691,760, 9,711,407, 9,721,927, 9,871,034, 9,953,870, 9,953,994, 10,014,292, 10,014, 318; and pending U.S. Patent Application Publications and application Ser. Nos. 15/173,686, 62/562,457, 62/645,794, 62/651,722; 62/681,249, 62/713,345; and PCT Applications: PCT/US2010/052093, PCT/US2011/042071, PCT/US2016/52726, PCT/US2017/052359, PCT/US2018/016759, and PCT/US2018/52332. The entire contents of the foregoing patents, publications, and applications are incorporated herein by reference. Electro-Optics: There is also work done for integrated monolithic 3D including layers of different crystals, such as U.S. Pat. Nos. 8,283,215, 8,163,581, 8,753,913, 8,823,122, 9,197,804, 9,419,031 and 9,941,319. The entire contents of the foregoing patents, publications, and applications are incorporated herein by reference.
In landmark papers at VLSI 2007 and IEDM 2007, Toshiba presented techniques to construct 3D memories which they calledâBiCS. Many of the memory vendors followed that work by variation and alternatives mostly for non-volatile memory applications, such as now being referred to as 3D-NAND. They provide an important manufacturing advantage of being able to utilize one, usually âcriticalâ, lithography step for the patterning of multiple layers. The vast majority of these 3D Memory schemes use poly-silicon for the active memory cell channel which suffers from higher cell to cell performance variations and lower drive than a cell with a monocrystalline channel In at least our U.S. Pat. Nos. 8,026,521, 8,114,757, 8,687,399, 8,379,458, and 8,902,663, incorporated herein by reference, we presented multiple 3D memory structures generally constructed by successive layer transfers using ion cut techniques. In this work we are presenting methods and structures to construct 3D memory with monocrystalline channels constructed by successive layer transfers. This structure provides the benefit of multiple layers being processed by one lithography step with many of the benefits of a monocrystalline channel, and provides overall lower construction costs.
Additionally some embodiments of the invention may provide innovative alternatives for multi layer 3D IC technology. As on-chip interconnects are becoming the limiting factor for performance and power enhancement with device scaling, 3D IC may be an important technology for future generations of ICs. Currently the only viable technology for 3D IC is to finish the IC by the use of Through-Silicon-Via (TSV). The problem with TSVs is that they are relatively large (a few microns each in area) and therefore may lead to highly limited vertical connectivity. The current invention may provide multiple alternatives for 3D IC with at least an order of magnitude improvement in vertical connectivity.
Other techniques could also be used such as employing Silicon On Insulator (SOI) technology. In U.S. Pat. Nos. 6,355,501 and 6,821,826, both assigned to IBM, a multilayer three-dimensional Complementary Metal-Oxide-Semiconductor (CMOS) Integrated Circuit is proposed. It suggests bonding an additional thin SOI wafer on top of another SOI wafer forming an integrated circuit on top of another integrated circuit and connecting them by the use of a through-silicon-via, or thru layer via (TLV). Substrate supplier Soitec SA, of Bernin, France is now offering a technology for stacking of a thin layer of a processed wafer on top of a base wafer.
Integrating top layer transistors above an insulation layer is not common in an IC because the quality and density of prior art top layer transistors are inferior to those formed in the base (or substrate) layer. The substrate may be formed of mono-crystalline silicon and may be ideal for producing high density and high quality transistors, and hence preferable. There are some applications where it has been suggested to build memory cells using such transistors as in U.S. Pat. Nos. 6,815,781, 7,446,563 and a portion of an SRAM based FPGA such as in U.S. Pat. Nos. 6,515,511 and 7,265,421.
Embodiments of the current invention seek to take advantage of the top layer transistor to provide a much higher density antifuse-based programmable logic. An additional advantage for such use will be the option to further reduce cost in high volume production by utilizing custom mask(s) to replace the antifuse function, thereby eliminating the top layer(s) anti-fuse programming logic altogether.
Additionally some embodiments of the invention may provide innovative alternatives for multi-layer 3D IC technology. As on-chip interconnects are becoming the limiting factor for performance and power enhancement with device scaling, 3D IC may be an important technology for future generations of ICs. Currently the only viable technology for 3D IC is to finish the IC by the use of Through-Silicon-Via (TSV). The problem with TSVs is that they are relatively large (a few microns each in area) and therefore may lead to highly limited vertical connectivity. The current invention may provide multiple alternatives for 3D IC with an order of magnitude improvement in vertical connectivity.
Constructing future 3D ICs will require new architectures and new ways of thinking In particular, yield and reliability of extremely complex three dimensional systems will have to be addressed, particularly given the yield and reliability difficulties encountered in building complex Application Specific Integrated Circuits (ASIC) of recent deep submicron process generations.
Additionally the 3D technology according to some embodiments of the current invention may enable some very innovative IC alternatives with reduced development costs, increased yield, and other important benefits.
SUMMARY
The invention relates to multilayer or Three Dimensional Integrated Circuit (3D IC) devices and fabrication methods.
In one aspect, a 3D semiconductor device, the device comprising: a first die, comprising a first die area and a plurality of first die top contacts; a second die, comprising a second die area and a plurality of first bottom contacts; and a third die, comprising a third die area and a plurality of second bottom contacts, wherein said first die area is greater than the sum of said second die area and said third die area, wherein said second die and said third die are both placed on top of said first die laterally with respect to each other, wherein said plurality of first bottom contacts are connected to said first die top contacts, and wherein said plurality of second bottom contacts are connected to said first die top contacts.
In another aspect, a 3D semiconductor device, the device comprising: a a first die, comprising a first die area and a plurality of first die top contacts; a second die, comprising a second die area and a plurality of first bottom contacts; a third die, comprising a third die area and a plurality of second bottom contacts; and a fourth die, comprising a fourth die area and a plurality of third bottom contacts, wherein said first die area is greater than the sum of said second die area, said third die area, and said fourth die area, wherein said second die, said third die, and said fourth die are all placed on top of said first die laterally with respect to each other, wherein said plurality of first bottom contacts are connected to said first die top contacts, wherein said plurality of second bottom contacts are connected to said first die top contacts, and wherein said plurality of third bottom contacts are connected to said first die top contacts.
In another aspect, a 3D semiconductor device, the device comprising: a first die, comprising a first die area and a plurality of first die top contacts; a second die, comprising a second die area and a plurality of first bottom contacts; and a third die, comprising a third die area and a plurality of second bottom contacts, wherein said first die area is greater than second die area, wherein said second die and said third die are both placed on top of said first die laterally with respect to each other, wherein said plurality of first bottom contacts are connected to said first die top contacts, wherein said second die comprises a plurality of second top contacts, wherein said plurality of second bottom contacts are connected to said plurality of second top contacts.
Additionally there is a growing need to reduce the impact of inter-chip interconnects. In fact, interconnects are now dominating IC performance and power. One solution to shorten interconnect may be to use a 3D IC. Currently, the only known way for general logic 3D IC is to integrate finished device one on top of the other by utilizing Through-Silicon-Vias as now called TSVs. The problem with TSVs is that their large size, usually a few microns each, may severely limit the number of connections that can be made. Some embodiments of the current invention may provide multiple alternatives to constructing a 3D IC wherein many connections may be made less than one micron in size, thus enabling the use of 3D IC technology for most device applications.
Additionally some embodiments of this invention may offer new device alternatives by utilizing the proposed 3D IC technology.
BRIEF DESCRIPTION OF THE DRAWINGS
Various embodiments of the present invention will be understood and appreciated more fully from the following detailed description, taken in conjunction with the drawings in which:
FIG. 1 is a drawing illustration of a layer transfer process flow;
FIGS. 2A, 2B are device simulations of a junction-less transistor;
FIGS. 3A-3M are drawing illustrations of the formation of a resistive memory transistor;
FIGS. 4A-4M are drawing illustrations of the formation of a resistive memory transistor;
FIGS. 5A-5J are drawing illustrations of the formation of a resistive memory transistor with periphery on top;
FIG. 6 is a drawing illustration of a metal interconnect stack prior art;
FIG. 7 is a drawing illustration of a metal interconnect stack;
FIG. 8 is an exemplary illustration of some additional embodiments and combinations of devices, circuits, paths, and connections of a 3D device;
FIG. 9 is a drawing illustration of a programmable device layers structure;
<div id="p-0033"
CROSS-REFERENCE OF RELATED APPLICATIONS
This application is a continuation-in-part of co-pending U.S. patent application Ser. No. 15/922,913 filed Mar. 16, 2018, (now issued as U.S. Pat. No. 10,354,995 on Jul. 16, 2019), which is a continuation-in-part of U.S. patent application Ser. No. 15/409,740 filed Jan. 19, 2017, (now issued as U.S. Pat. No. 9,941,332 on Apr. 10, 2018), which is a continuation-in-part of U.S. patent application Ser. No. 15/224,929 filed Aug. 1, 2016 (now issued as U.S. Pat. No. 9,853,089 on Dec. 26, 2017), which is a continuation-in-part of U.S. patent application Ser. No. 14/514,386 filed Oct. 15, 2014 (now issued as U.S. Pat. No. 9,406,670 on Aug. 2, 2016), which is a continuation of U.S. patent application Ser. No. 13/492,382 filed Jun. 8, 2012 (now issued as U.S. Pat. No. 8,907,442 on Dec. 9, 2014), which is a continuation of U.S. patent application Ser. No. 13/246,384 filed Sep. 27, 2011 (now issued as U.S. Pat. No. 8,237,228 on Aug. 7, 2012), which is a continuation U.S. patent application Ser. No. 12/900,379 filed Oct. 7, 2010 (now issued as U.S. Pat. No. 8,395,191 on Mar. 12, 2013), which is a continuation-in-part of U.S. patent application Ser. No. 12/859,665 filed Aug. 19, 2010 (now issued as U.S. Pat. No. 8,405,420 on Mar. 26, 2013), which is a continuation-in-part of U.S. patent application Ser. No. 12/849,272 filed Aug. 3, 2010 (now issued as U.S. Pat. No. 7,986,042 on Jul. 26, 2011) and U.S. patent application Ser. No. 12/847,911 filed Jul. 30, 2010 (now issued as U.S. Pat. No. 7,960,242 on Jun. 14, 2011); U.S. patent application Ser. No. 12/847,911 is a continuation-in-part of U.S. patent application Ser. No. 12/792,673 filed Jun. 2, 2010 (now issued as U.S. Pat. No. 7,964,916 on Jun. 21, 2011), U.S. patent application Ser. No. 12/797,493 filed Jun. 9, 2010 (now issued as U.S. Pat. No. 8,115,511 on Feb. 14, 2012), and U.S. patent application Ser. No. 12/706,520 filed Feb. 16, 2010; both U.S. patent application Ser. No. 12/792,673 and U.S. patent application Ser. No. 12/797,493 are continuation-in-part applications of U.S. patent application Ser. No. 12/577,532 filed Oct. 12, 2009, the entire contents of all of the foregoing are incorporated by reference. The entire contents of U.S. application Ser. No. 13/273,712, which was filed on Oct. 14, 2011, and is now U.S. Pat. No. 8,273,610, is incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the general field of Integrated Circuit (IC) devices and fabrication methods, and more particularly to multilayer or Three Dimensional Integrated Circuit (3D IC) devices and fabrication methods.
2. Discussion of Background Art
Semiconductor manufacturing is known to improve device density in an exponential manner over time, but such improvements come with a price. The mask set cost required for each new process technology has also been increasing exponentially. While 20 years ago a mask set cost less than $20,000, it is now quite common to be charged more than $1M for today's state of the art device mask set.
These changes represent an increasing challenge primarily to custom products, which tend to target smaller volume and less diverse markets therefore making the increased cost of product development very hard to accommodate.
Over the past 40 years, there has been a dramatic increase in functionality and performance of Integrated Circuits (ICs). This has largely been due to the phenomenon of âscalingâ; i.e., component sizes such as lateral and vertical dimensions within ICs have been reduced (âscaledâ) with every successive generation of technology. There are two main classes of components in Complementary Metal Oxide Semiconductor (CMOS) ICs, namely transistors and wires. With âscalingâ, transistor performance and density typically improve and this has contributed to the previously-mentioned increases in IC performance and functionality. However, wires (interconnects) that connect together transistors degrade in performance with âscalingâ. The situation today is that wires dominate the performance, functionality and power consumption of ICs.
3D stacking of semiconductor devices or chips is one avenue to tackle the wire issues. By arranging transistors in 3 dimensions instead of 2 dimensions (as was the case in the 1990 s ), the transistors in ICs can be placed closer to each other. This reduces wire lengths and keeps wiring delay low.
There are many techniques to construct 3D stacked integrated circuits or chips including:
Through-silicon via (TSV) technology: Multiple layers of transistors (with or without wiring levels) can be constructed separately. Following this, they can be bonded to each other and connected to each other with through-silicon vias (TSVs). Monolithic 3D technology: With this approach, multiple layers of transistors and wires can be monolithically constructed. Some monolithic 3D and 3DIC approaches are described in U.S. Pat. Nos. 8,273,610, 8,298,875, 8,362,482, 8,378,715, 8,379,458, 8,450,804, 8,557,632, 8,574,929, 8,581,349, 8,642,416, 8,669,778, 8,674,470, 8,687,399, 8,742,476, 8,803,206, 8,836,073, 8,902,663, 8,994,404, 9,023,688, 9,029,173, 9,030,858, 9,117,749, 9,142,553, 9,219,005, 9,385,058, 9,509,313, 9,640,531, 9,691,760, 9,711,407, 9,721,927, 9,871,034, 9,953,870, 9,953,994, 10,014,292, 10,014, 318; and pending U.S. Patent Application Publications and application Ser. Nos. 15/173,686, 62/562,457, 62/645,794, 62/651,722; 62/681,249, 62/713,345; and PCT Applications: PCT/US2010/052093, PCT/US2011/042071, PCT/US2016/52726, PCT/US2017/052359, PCT/US2018/016759, and PCT/US2018/52332. The entire contents of the foregoing patents, publications, and applications are incorporated herein by reference. Electro-Optics: There is also work done for integrated monolithic 3D including layers of different crystals, such as U.S. Pat. Nos. 8,283,215, 8,163,581, 8,753,913, 8,823,122, 9,197,804, 9,419,031 and 9,941,319. The entire contents of the foregoing patents, publications, and applications are incorporated herein by reference.
In landmark papers at VLSI 2007 and IEDM 2007, Toshiba presented techniques to construct 3D memories which they calledâBiCS. Many of the memory vendors followed that work by variation and alternatives mostly for non-volatile memory applications, such as now being referred to as 3D-NAND. They provide an important manufacturing advantage of being able to utilize one, usually âcriticalâ, lithography step for the patterning of multiple layers. The vast majority of these 3D Memory schemes use poly-silicon for the active memory cell channel which suffers from higher cell to cell performance variations and lower drive than a cell with a monocrystalline channel In at least our U.S. Pat. Nos. 8,026,521, 8,114,757, 8,687,399, 8,379,458, and 8,902,663, incorporated herein by reference, we presented multiple 3D memory structures generally constructed by successive layer transfers using ion cut techniques. In this work we are presenting methods and structures to construct 3D memory with monocrystalline channels constructed by successive layer transfers. This structure provides the benefit of multiple layers being processed by one lithography step with many of the benefits of a monocrystalline channel, and provides overall lower construction costs.
Additionally some embodiments of the invention may provide innovative alternatives for multi layer 3D IC technology. As on-chip interconnects are becoming the limiting factor for performance and power enhancement with device scaling, 3D IC may be an important technology for future generations of ICs. Currently the only viable technology for 3D IC is to finish the IC by the use of Through-Silicon-Via (TSV). The problem with TSVs is that they are relatively large (a few microns each in area) and therefore may lead to highly limited vertical connectivity. The current invention may provide multiple alternatives for 3D IC with at least an order of magnitude improvement in vertical connectivity.
Other techniques could also be used such as employing Silicon On Insulator (SOI) technology. In U.S. Pat. Nos. 6,355,501 and 6,821,826, both assigned to IBM, a multilayer three-dimensional Complementary Metal-Oxide-Semiconductor (CMOS) Integrated Circuit is proposed. It suggests bonding an additional thin SOI wafer on top of another SOI wafer forming an integrated circuit on top of another integrated circuit and connecting them by the use of a through-silicon-via, or thru layer via (TLV). Substrate supplier Soitec SA, of Bernin, France is now offering a technology for stacking of a thin layer of a processed wafer on top of a base wafer.
Integrating top layer transistors above an insulation layer is not common in an IC because the quality and density of prior art top layer transistors are inferior to those formed in the base (or substrate) layer. The substrate may be formed of mono-crystalline silicon and may be ideal for producing high density and high quality transistors, and hence preferable. There are some applications where it has been suggested to build memory cells using such transistors as in U.S. Pat. Nos. 6,815,781, 7,446,563 and a portion of an SRAM based FPGA such as in U.S. Pat. Nos. 6,515,511 and 7,265,421.
Embodiments of the current invention seek to take advantage of the top layer transistor to provide a much higher density antifuse-based programmable logic. An additional advantage for such use will be the option to further reduce cost in high volume production by utilizing custom mask(s) to replace the antifuse function, thereby eliminating the top layer(s) anti-fuse programming logic altogether.
Additionally some embodiments of the invention may provide innovative alternatives for multi-layer 3D IC technology. As on-chip interconnects are becoming the limiting factor for performance and power enhancement with device scaling, 3D IC may be an important technology for future generations of ICs. Currently the only viable technology for 3D IC is to finish the IC by the use of Through-Silicon-Via (TSV). The problem with TSVs is that they are relatively large (a few microns each in area) and therefore may lead to highly limited vertical connectivity. The current invention may provide multiple alternatives for 3D IC with an order of magnitude improvement in vertical connectivity.
Constructing future 3D ICs will require new architectures and new ways of thinking In particular, yield and reliability of extremely complex three dimensional systems will have to be addressed, particularly given the yield and reliability difficulties encountered in building complex Application Specific Integrated Circuits (ASIC) of recent deep submicron process generations.
Additionally the 3D technology according to some embodiments of the current invention may enable some very innovative IC alternatives with reduced development costs, increased yield, and other important benefits.
SUMMARY
The invention relates to multilayer or Three Dimensional Integrated Circuit (3D IC) devices and fabrication methods.
In one aspect, a 3D semiconductor device, the device comprising: a first die, comprising a first die area and a plurality of first die top contacts; a second die, comprising a second die area and a plurality of first bottom contacts; and a third die, comprising a third die area and a plurality of second bottom contacts, wherein said first die area is greater than the sum of said second die area and said third die area, wherein said second die and said third die are both placed on top of said first die laterally with respect to each other, wherein said plurality of first bottom contacts are connected to said first die top contacts, and wherein said plurality of second bottom contacts are connected to said first die top contacts.
In another aspect, a 3D semiconductor device, the device comprising: a a first die, comprising a first die area and a plurality of first die top contacts; a second die, comprising a second die area and a plurality of first bottom contacts; a third die, comprising a third die area and a plurality of second bottom contacts; and a fourth die, comprising a fourth die area and a plurality of third bottom contacts, wherein said first die area is greater than the sum of said second die area, said third die area, and said fourth die area, wherein said second die, said third die, and said fourth die are all placed on top of said first die laterally with respect to each other, wherein said plurality of first bottom contacts are connected to said first die top contacts, wherein said plurality of second bottom contacts are connected to said first die top contacts, and wherein said plurality of third bottom contacts are connected to said first die top contacts.
In another aspect, a 3D semiconductor device, the device comprising: a first die, comprising a first die area and a plurality of first die top contacts; a second die, comprising a second die area and a plurality of first bottom contacts; and a third die, comprising a third die area and a plurality of second bottom contacts, wherein said first die area is greater than second die area, wherein said second die and said third die are both placed on top of said first die laterally with respect to each other, wherein said plurality of first bottom contacts are connected to said first die top contacts, wherein said second die comprises a plurality of second top contacts, wherein said plurality of second bottom contacts are connected to said plurality of second top contacts.
Additionally there is a growing need to reduce the impact of inter-chip interconnects. In fact, interconnects are now dominating IC performance and power. One solution to shorten interconnect may be to use a 3D IC. Currently, the only known way for general logic 3D IC is to integrate finished device one on top of the other by utilizing Through-Silicon-Vias as now called TSVs. The problem with TSVs is that their large size, usually a few microns each, may severely limit the number of connections that can be made. Some embodiments of the current invention may provide multiple alternatives to constructing a 3D IC wherein many connections may be made less than one micron in size, thus enabling the use of 3D IC technology for most device applications.
Additionally some embodiments of this invention may offer new device alternatives by utilizing the proposed 3D IC technology.
BRIEF DESCRIPTION OF THE DRAWINGS
Various embodiments of the present invention will be understood and appreciated more fully from the following detailed description, taken in conjunction with the drawings in which:
FIG. 1 is a drawing illustration of a layer transfer process flow;
FIGS. 2A, 2B are device simulations of a junction-less transistor;
FIGS. 3A-3M are drawing illustrations of the formation of a resistive memory transistor;
FIGS. 4A-4M are drawing illustrations of the formation of a resistive memory transistor;
FIGS. 5A-5J are drawing illustrations of the formation of a resistive memory transistor with periphery on top;
FIG. 6 is a drawing illustration of a metal interconnect stack prior art;
FIG. 7 is a drawing illustration of a metal interconnect stack;
FIG. 8 is an exemplary illustration of some additional embodiments and combinations of devices, circuits, paths, and connections of a 3D device;
FIG. 9 is a drawing illustration of a programmable device layers structure;
FIG. 9A is a drawing illustration of a programmable device layers structure;
FIG. 9B-9I are drawing illustrations of the preprocessed wafers and layers and generalized layer transfer;
FIG. 10A through 10F are a drawing illustration of one reticle site on a wafer;
FIG. 11A through 11E are a drawing illustration of Configurable system;
FIG. 12 a drawing illustration of a flow chart for 3D logic partitioning;
FIG. 13 is a drawing illustration of a layer transfer process flow;
FIG. 14 is a drawing illustration of an underlying programming circuits;
FIG. 15 is a drawing illustration of an underlying isolation transistors circuits;
FIG. 16A is a topology drawing illustration of underlying back bias circuitry;
FIG. 16B is a drawing illustration of underlying back bias circuits;
FIG. 16C is a drawing illustration of power control circuits
FIG. 16D is a drawing illustration of probe circuits
FIG. 17 is a drawing illustration of an underlying SRAM;
FIG. 18A is a drawing illustration of an underlying I/O;
FIG. 18B is a drawing illustration of side âcutâ;
FIG. 18C is a drawing illustration of a 3D IC system;
FIG. 18D is a drawing illustration of a 3D IC processor and DRAM system;
FIG. 18E is a drawing illustration of a 3D IC processor and DRAM system;
FIG. 18F is a drawing illustration of a custom SOI wafer used to build through-silicon connections;
FIG. 18G is a drawing illustration of a prior art method to make through-silicon vias;
FIG. 18H is a drawing illustration of a process flow for making custom SOI wafers;
FIG. 18I is a drawing illustration of a processor-DRAM stack;
FIG. 18J is a drawing illustration of a process flow for making custom SOI wafers;
FIGS. 19A-19D are drawing illustrations of an advanced TSV flow; and
FIGS. 20A-20C are drawing illustrations of an advanced TSV multi-connections flow.
DETAILED DESCRIPTION
Embodiments of the present invention are now described with reference to the drawing figures. Persons of ordinary skill in the art will appreciate that the description and figures illustrate rather than limit the invention and that in general the figures are not drawn to scale for clarity of presentation. Such skilled persons will also realize that many more embodiments are possible by applying the inventive principles contained herein and that such embodiments fall within the scope of the invention which is not to be limited except by the appended claims.
Some drawing figures may describe process flows for fabricating devices. The process flows, which may be a sequence of steps for fabricating a device, may have many structures, numerals and labels that may be common between two or more successive steps. In such cases, some labels, numerals and structures used for a certain step's figure may have been described in the previous steps' figures.
A technology for creating layer stacks or overlying or underlying circuitry is to use the âSmartCutâ process. The âSmartCutâ process is a well understood technology used for fabrication of SOI wafers. The âSmartCutâ process, together with wafer bonding technology, enables a âLayer Transferâ whereby a thin layer of a single or mono-crystalline silicon wafer is transferred from one wafer to another wafer. The âLayer Transferâ could be done at less than 400° C. and the resultant transferred layer could be even less than 100 nm thick. The process with some variations and under different names is commercially available by two companies, namely, Soitec (Crolles, France) and SiGenâSilicon Genesis Corporation (San Jose, Calif.). A room temperature wafer bonding process utilizing ion-beam preparation of the wafer surfaces in a vacuum has been recently demonstrated by Mitsubishi Heavy Industries Ltd., Tokyo, Japan. This process allows room temperature layer transfer.
Alternatively, other technology may be used. For example, other technologies may be utilized for layer transfer as described in, for example, IBM's layer transfer method shown at IEDM 2005 by A. W. Topol, et. al. The IBM's layer transfer method employs a SOI technology and utilizes glass handle wafers. The donor circuit may be high-temperature processed on an SOI wafer, temporarily bonded to a borosilicate glass handle wafer, backside thinned by chemical mechanical polishing of the silicon and then the Buried Oxide (BOX) is selectively etched off. The now thinned donor wafer is subsequently aligned and low-temperature oxide-to-oxide bonded to the acceptor wafer topside. A low temperature release of the glass handle wafer from the thinned donor wafer is performed, and then thru bond via connections are made. Additionally, epitaxial liftoff (ELO) technology as shown by P. Demeester, et. al, of IMEC in Semiconductor Science Technology 1993 may be utilized for layer transfer. ELO makes use of the selective removal of a very thin sacrificial layer between the substrate and the layer structure to be transferred. The to-be-transferred layer of GaAs or silicon may be adhesively ârolledâ up on a cylinder or removed from the substrate by utilizing a flexible carrier, such as, for example, black wax, to bow up the to-be-transferred layer structure when the selective etch, such as, for example, diluted Hydrofluoric (HF) Acid, etches the exposed release layer, such as, for example, silicon oxide in SOI or AlAs. After liftoff, the transferred layer is then aligned and bonded to the desired acceptor substrate or wafer. The manufacturability of the ELO process for multilayer layer transfer use was recently improved by J. Yoon, et. al., of the University of Illinois at Urbana-Champaign as described in Nature May 20, 2010.
Canon developed a layer transfer technology called ELTRANâEpitaxial Layer TRANsfer from porous silicon. ELTRAN may be utilized. The Electrochemical Society Meeting abstract No. 438 from year 2000 and the JSAP International July 2001 paper show a seed wafer being anodized in an HF/ethanol solution to create pores in the top layer of silicon, the pores are treated with a low temperature oxidation and then high temperature hydrogen annealed to seal the pores. Epitaxial silicon may then be deposited on top of the porous silicon and then oxidized to form the SOI BOX. The seed wafer may be bonded to a handle wafer and the seed wafer may be split off by high pressure water directed at the porous silicon layer. The porous silicon may then be selectively etched off leaving a uniform silicon layer.
FIG. 1 is a drawing illustration of a layer transfer process flow. In another alternative of the invention, âLayer-Transferâ is used for construction of the underlying circuitry 814 . 102 is a wafer that was processed to construct the underlying circuitry. The wafer 102 could be of the most advanced process or more likely a few generations behind. It could comprise the programming circuits 814 and other useful structures and may be a preprocessed CMOS silicon wafer, or a partially processed CMOS, or other prepared silicon or semiconductor substrate. Wafer 102 may also be called an acceptor substrate or a target wafer. An oxide layer 112 is then deposited on top of the wafer 102 and then is polished for better planarization and surface preparation. A donor wafer 106 is then brought in to be bonded to 102 . The surfaces of both donor wafer 106 and wafer 102 may be pre-processed for low temperature bonding by various surface treatments, such as an RCA pre-clean that may comprise dilute ammonium hydroxide or hydrochloric acid, and may include plasma surface preparations to lower the bonding energy and enhance the wafer to wafer bond strength. The donor wafer 106 is pre-prepared for âSmartCutâ by an ion implant of an atomic species, such as H+ ions, at the desired depth to prepare the SmartCut line 108 . SmartCut line 108 may also be called a layer transfer demarcation plane, shown as a dashed line. The SmartCut line 108 or layer transfer demarcation plane may be formed before or after other processing on the donor wafer 106 . Donor wafer 106 may be bonded to wafer 102 by bringing the donor wafer 106 surface in physical contact with the wafer 102 surface, and then applying mechanical force and/or thermal annealing to strengthen the oxide to oxide bond. Alignment of the donor wafer 106 with the wafer 102 may be performed immediately prior to the wafer bonding. Acceptable bond strengths may be obtained with bonding thermal cycles that do not exceed approximately 400° C. After bonding the two wafers a SmartCut step is performed to cleave and remove the top portion 114 of the donor wafer 106 along the cut layer 108 . The cleaving may be accomplished by various applications of energy to the SmartCut line 108 , or layer transfer demarcation plane, such as a mechanical strike by a knife or jet of liquid or jet of air, or by local laser heating, or other suitable methods. The result is a 3D wafer 110 which comprises wafer 102 with an added layer 104 of mono-crystalline silicon, or multiple layers of materials. Layer 104 may be polished chemically and mechanically to provide a suitable surface for further processing. Layer 104 could be quite thin at the range of 50-200 nm as desired. The described flow is called âlayer transferâ. Layer transfer is commonly utilized in the fabrication of SOIâSilicon On Insulator-wafers. For SOI wafers the upper surface is oxidized so that after âlayer transferâ a buried oxideâBOXâprovides isolation between the top thin mono-crystalline silicon layer and the bulk of the wafer. The use of an implanted atomic species, such as Hydrogen or Helium or a combination, to create a cleaving plane as described above may be referred to in this document as âion-cutâ and is the preferred and illustrated layer transfer method utilized.
Persons of ordinary skill in the art will appreciate that the illustrations in FIG. 1 are exemplary only and are not drawn to scale. Such skilled persons will further appreciate that many variations are possible such as, for example, a heavily doped (greater than 1e20 atoms/cm3) boron layer or silicon germanium (SiGe) layer may be utilized as an etch stop either within the ion-cut process flow, wherein the layer transfer demarcation plane may be placed within the etch stop layer or into the substrate material below, or the etch stop layers may be utilized without a implant cleave process and the donor wafer may be preferentially etched away until the etch stop layer is reached. Such skilled persons will further appreciate that the oxide layer within an SOI or GeOI donor wafer may serve as the etch stop layer. Many other modifications within the scope of the invention will suggest themselves to such skilled persons after reading this specification. Thus the invention is to be limited only by the appended claims.
One alternative method is to have a thin layer transfer of single crystal silicon which will be used for epitaxial Ge crystal growth using the transferred layer as the seed for the germanium. Another alternative method is to use the thin layer transfer of mono-crystalline silicon for epitaxial growth of GexSi1-x. The percent Ge in Silicon of such layer would be determined by the transistor specifications of the circuitry. Prior art have presented approaches whereby the base silicon is used to crystallize the germanium on top of the oxide by using holes in the oxide to drive crystal or lattice seeding from the underlying silicon crystal. However, it is very hard to do such on top of multiple interconnection layers. By using layer transfer we can have a mono-crystalline layer of silicon crystal on top and make it relatively easy to seed and crystallize an overlying germanium layer. Amorphous germanium could be conformally deposited by CVD at 300° C. and pattern aligned to the underlying layer, such as a pre-processed wafer or layer, and then encapsulated by a low temperature oxide. A short microsecond-duration heat pulse melts the Ge layer while keeping the underlying structure below 400° C. The Ge/Si interface will start the crystal or lattice epitaxial growth to crystallize the germanium or GexSi1-x layer. Then implants are made to form Ge transistors and activated by laser pulses without damaging the underlying structure taking advantage of the low activation temperature of dopants in germanium.
Another class of devices that may be constructed partly at high temperature before layer transfer to a substrate with metal interconnects and then completed at low temperature after layer transfer is a junction-less transistor (JLT). For example, in deep sub micron processes copper metallization is utilized, so a high temperature would be above approximately 400° C., whereby a low temperature would be approximately 400° C. and below. The junction-less transistor structure avoids the sharply graded junctions needed as silicon technology scales, and provides the ability to have a thicker gate oxide for an equivalent performance when compared to a traditional MOSFET transistor. The junction-less transistor is also known as a nanowire transistor without junctions, or gated resistor, or nanowire transistor as described in a paper by Jean-Pierre Colinge, et. al., published in Nature Nanotechnology on Feb. 21, 2010. The junction-less transistors may be constructed whereby the transistor channel is a thin solid piece of evenly and heavily doped single crystal silicon. The doping concentration of the channel may be identical to that of the source and drain. The considerations may include the nanowire channel must be thin and narrow enough to allow for full depletion of the carriers when the device is turned off, and the channel doping must be high enough to allow a reasonable current to flow when the device is on. These considerations may lead to tight process variation boundaries for channel thickness, width, and doping for a reasonably obtainable gate work function and gate oxide thickness.
One of the challenges of a junction-less transistor device is turning the channel off with minimal leakage at a zero gate bias. To enhance gate control over the transistor channel, the channel may be doped unevenly; whereby the heaviest doping is closest to the gate or gates and the channel doping is lighter the farther away from the gate electrode. One example would be where the center of a 2, 3, or 4 gate sided junction-less transistor channel is more lightly doped than the edges. This may enable much lower off currents for the same gate work function and control. FIGS. 52 A and 52 B show, on logarithmic and linear scales respectively, simulated drain to source current Ids as a function of the gate voltage Vg for various junction-less transistor channel dopings where the total thickness of the n-channel is 20 nm. Two of the four curves in each figure correspond to evenly doping the 20 nm channel thickness to 1E17 and 1E18 atoms/cm3, respectively. The remaining two curves show simulation results where the 20 nm channel has two layers of 10 nm thickness each. In the legend denotations for the remaining two curves, the first number corresponds to the 10 nm portion of the channel that is the closest to the gate electrode. For example, the curve D=1E18/1E17 shows the simulated results where the 10 nm channel portion doped at 1E18 is closest to the gate electrode while the 10 nm channel portion doped at 1E17 is farthest away from the gate electrode. In FIG. 2A , curves 202 and 204 correspond to doping patterns of D=1E18/1E17 and D=1E17/1E18, respectively. According to FIG. 52A , at a Vg of 0 volts, the off current for the doping pattern of D=1E18/1E17 is approximately 50 times lower than that of the reversed doping pattern of D=1E17/1E18. Likewise, in FIG. 52B , curves
206 and 208 correspond to doping patterns of D=1E18/1E17 and D=1E17/1E18, respectively. FIG. 52B shows that at a Vg of 1 volt, the Ids of both doping patterns are within a few percent of each other.
The junction-less transistor channel may be constructed with even, graded, or discrete layers of doping. The channel may be constructed with materials other than doped mono-crystalline silicon, such as poly-crystalline silicon, or other semi-conducting, insulating, or conducting material, such as graphene or other graphitic material, and may be in combination with other layers of similar or different material. For example, the center of the channel may comprise a layer of oxide, or of lightly doped silicon, and the edges more heavily doped single crystal silicon. This may enhance the gate control effectiveness for the off state of the resistor, and may also increase the on-current due to strain effects on the other layer or layers in the channel Strain techniques may also be employed from covering and insulator material above, below, and surrounding the transistor channel and gate. Lattice modifiers may also be employed to strain the silicon, such as an embedded SiGe implantation and anneal. The cross section of the transistor channel may be rectangular, circular, or oval shaped, to enhance the gate control of the channel Alternatively, to optimize the mobility of the P-channel junction-less transistor in the 3D layer transfer method, the donor wafer may be rotated 90 degrees with respect to the acceptor wafer prior to bonding to facilitate the creation of the P-channel in the <110> silicon plane direction.
Novel monolithic 3D memory technologies utilizing material resistance changes may be constructed in a similar manner. There are many types of resistance-based memories including phase change memory, Metal Oxide memory, resistive RAM (RRAM), memristors, solid-electrolyte memory, ferroelectric RAM, MRAM, etc. Background information on these resistive-memory types is given in âOverview of candidate device technologies for storage-class memory,â IBM Journal of Research and Development , vol. 52, no. 4.5, pp. 449-464, July 2008 by Burr, G. W., et. al. The contents of this document are incorporated in this specification by reference.
The monolithic 3D integration concepts described in this patent application can lead to novel embodiments of poly-crystalline silicon based memory architectures. While the below concepts in FIGS. 3 and 4 are explained by using resistive memory architectures as an example, it will be clear to one skilled in the art that similar concepts can be applied to the NAND flash, charge trap, and DRAM memory architectures and process flows described previously in this patent application's parent (U.S. application Ser. No. 12/900,379, issued as U.S. Pat. No. 8,395,191) or other of the incorporated by reference documents.
As illustrated in FIGS. 3A to 3K , a resistance-based zero additional masking steps per memory layer 3D memory may be constructed that is suitable for 3D IC manufacturing. This 3D memory utilizes junction-less transistors and has a resistance-based memory element in series with a select or access transistor.
As illustrated in FIG. 3A , a silicon substrate with peripheral circuitry 302 may be constructed with high temperature (greater than approximately 400° C.) resistant wiring, such as, for example, Tungsten. The peripheral circuitry substrate 302 may include memory control circuits as well as circuitry for other purposes and of various types, such as, for example, analog, digital, RF, or memory. The peripheral circuitry substrate 302 may include peripheral circuits that can withstand an additional rapid-thermal-anneal (RTA) and still remain operational and retain good performance. For this purpose, the peripheral circuits may be formed such that they have had a weak RTA or no RTA for activating dopants. The top surface of the peripheral circuitry substrate 302 may be prepared for oxide wafer bonding with a deposition of a silicon oxide 304 , thus forming acceptor wafer 314 .
As illustrated in FIG. 3B , a mono-crystalline silicon donor wafer 312 may be optionally processed to include a wafer sized layer of N+ doping (not shown) which may have a different dopant concentration than the N+ substrate 306 . The N+ doping layer may be formed by ion implantation and thermal anneal. A screen oxide 308 may be grown or deposited prior to the implant to protect the silicon from implant contamination and to provide an oxide surface for later wafer to wafer bonding. A layer transfer demarcation plane 310 (shown as a dashed line) may be formed in donor wafer 312 within the N+ substrate 306 or the N+ doping layer (not shown) by hydrogen implantation or other methods as previously described. Both the donor wafer 312 and acceptor wafer 314 may be prepared for wafer bonding as previously described and then bonded at the surfaces of oxide layer 304 and oxide layer 308 , at a low temperature (less than approximately 400° C.) preferred for lowest stresses, or a moderate temperature (less than approximately 900° C.).
As illustrated in FIG. 3C , the portion of the N+ layer (not shown) and the N+ wafer substrate 306 that are above the layer transfer demarcation plane 310 may be removed by cleaving and polishing, or other processes as previously described, such as, for example, ion-cut or other methods, thus forming the remaining mono-crystalline silicon N+ layer 306 â². Remaining N+ layer 306 â² and oxide layer 308 have been layer transferred to acceptor wafer 314 . The top surface of N+ layer 306 â² may be chemically or mechanically polished smooth and flat. Now transistors or portions of transistors may be formed and aligned to the acceptor wafer 314 alignment marks (not shown). Oxide layer 320 may be deposited to prepare the surface for later oxide to oxide bonding, leading to the formation of the first Si/ SiO2 layer 323 that includes silicon oxide layer 320 , N+ silicon layer 306 â², and oxide layer 308 .
As illustrated in FIG. 3D , additional Si/SiO2 layers, such as, for example, second Si/ SiO2 layer 325 and third Si/ SiO2 layer 327 , may each be formed as described in FIGS. 3A to 3C . Oxide layer 329 may be deposited to electrically isolate the top N+ silicon layer.
As illustrated in FIG. 3E , oxide 329 , third Si/ SiO2 layer 327 , second Si/ SiO2 layer 325 and first Si/ SiO2 layer 323 may be lithographically defined and plasma/RIE etched to form a portion of the memory cell structure, which now includes regions of N+ silicon 326 and oxide 322 .
As illustrated in FIG. 3F , a gate dielectric and gate electrode material may be deposited, planarized with a chemical mechanical polish (CMP), and then lithographically defined and plasma/RIE etched to form gate dielectric regions 328 which may either be self aligned to and covered by gate electrodes 330 (shown), or cover the entire N+ silicon 326 and oxide 322 multi-layer structure. The gate stack including gate electrode 330 and gate dielectric 328 may be formed with a gate dielectric, such as, for example, thermal oxide, and a gate electrode material, such as, for example, poly-crystalline silicon. Alternatively, the gate dielectric may be an atomic layer deposited (ALD) material that is paired with a work function specific gate metal according to an industry standard of high k metal gate process schemes described previously. Moreover, the gate dielectric may be formed with a rapid thermal oxidation (RTO), a low temperature oxide deposition or low temperature microwave plasma oxidation of the silicon surfaces and then a gate electrode such as, for example, tungsten or aluminum may be deposited.
As illustrated in FIG. 3G , the entire structure may be covered with a gap fill oxide 332 , which may be planarized with chemical mechanical polishing. The oxide 332 is shown transparent in the figure for clarity, along with word-line regions (WL) 350 , coupled with and composed of gate electrodes 330 , and source-line regions (SL) 352 , composed of N+ silicon regions 326 .
As illustrated in FIG. 3H , bit-line (BL) contacts 334 may be lithographically defined, etched along with plasma/RIE through oxide 332 , the three N+ silicon regions 326 , and associated oxide vertical isolation regions to connect all memory layers vertically. BL contacts 334 may then be processed by a photoresist removal. Resistance change memory material 338 , such as, for example, hafnium oxide, may then be deposited, preferably with atomic layer deposition (ALD). The electrode for the resistance change memory element may then be deposited by ALD to form the electrode/<figure-callout id="334" label="BL contact" filenames="US10910364-20210202-D00010.png,US1091036
CLAIMS
Claims ( 20 )
We claim:
1. A 3D integrated circuit, the circuit comprising:
a first wafer comprising a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers,
wherein said first copper interconnecting layers at least interconnect said plurality of first transistors; and
a second wafer comprising a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers,
wherein said second copper interconnecting layers at least interconnect said plurality of second transistors,
wherein said second wafer is bonded face-to-face on top of said first wafer,
wherein said bonded comprises copper to copper bonding, and
wherein said second crystalline substrate has been thinned to a thickness of less than 5 micro-meters.
2. The 3D integrated circuit of claim 1 , further comprising:
a via through said second crystalline substrate,
wherein said via has a radius of less than 1 micro-meter.
3. The 3D integrated circuit of claim 1 ,
wherein said second crystalline substrate does not comprise a built-in oxide layer.
4. The 3D integrated circuit of claim 1 ,
wherein said face-to-face bonding comprises hybrid bonding.
5. The 3D integrated circuit of claim 1 ,
wherein said first wafer comprises memory control circuits and said second wafer comprises a plurality of memory cells, or said second wafer comprises memory control circuits and said first wafer comprises a plurality of memory cells.
6. The 3D integrated circuit of claim 1 , further comprising:
vias through said second crystalline substrate,
wherein at least one of said vias is used to connect said 3D integrated circuit to an external device.
7. The 3D integrated circuit of claim 1 ,
wherein said first wafer comprises a plurality of self-aligned memory levels.
8. A 3D integrated circuit, the circuit comprising:
a first wafer comprising a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers,
wherein said first copper interconnecting layers at least interconnect said plurality of first transistors;
a second wafer comprising a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers,
wherein said second copper interconnecting layers at least interconnect said plurality of second transistors,
wherein said second wafer is bonded face-to-face on top of said first wafer, and
wherein said bonded comprises copper to copper bonding; and
vias through said second crystalline substrate,
wherein said vias have a radius of less than 1 micro-meter, and
wherein at least one of said vias is used to connect said 3D integrated circuit to an external device.
9. The 3D integrated circuit of claim 8 ,
wherein said bonded comprises copper to copper bonding, and
wherein said second crystalline substrate has been thinned to a thickness of less than 5 micro-meters.
10. The 3D integrated circuit of claim 8 ,
wherein said second crystalline substrate does not comprise a built-in oxide layer.
11. The 3D integrated circuit of claim 8 ,
wherein said face-to-face bonding comprises hybrid bonding.
12. The 3D integrated circuit of claim 8 ,
wherein said first wafer comprises memory control circuits and said second wafer comprises a plurality of memory cells, or said second wafer comprises memory control circuits and said first wafer comprises a plurality of memory cells.
13. The 3D integrated circuit of claim 8 ,
wherein said first wafer comprises memory control circuits and said second wafer comprises a plurality of DRAM cells, or said second wafer comprises memory control circuits and said first wafer comprises a plurality of DRAM cells.
14. The 3D integrated circuit of claim 8 ,
wherein said first wafer comprises a plurality of self-aligned memory levels.
15. A 3D integrated circuit, the circuit comprising:
a first wafer comprising a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers,
wherein said first copper interconnecting layers at least interconnect said plurality of first transistors;
a second wafer comprising a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers,
wherein said second copper interconnecting layers at least interconnect said plurality of second transistors,
wherein said second wafer is bonded face-to-face on top of said first wafer, and
wherein said bonded comprises copper to copper bonding; and
first vias through said second crystalline substrate,
wherein at least one of said first vias is used to connect said 3D integrated circuit to an external device, and
wherein said first wafer comprises a plurality of self-aligned memory levels.
16. The 3D integrated circuit of claim 15 ,
wherein said bonded comprises hybrid bonding, and
wherein said second crystalline substrate has a thickness of less than 5 micro-meters.
17. The 3D integrated circuit of claim 15 ,
wherein said second crystalline substrate does not comprise a built-in oxide layer.
18. The 3D integrated circuit of claim 15 ,
wherein said face-to-face bonding comprises hybrid bonding.
19. The 3D integrated circuit of claim 15 , further comprising:
second vias through said first crystalline substrate.
20. The 3D integrated circuit of claim 15 ,
wherein said second wafer comprises memory control circuits and said first wafer comprises a plurality of non-volatile memory cells.
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