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Semiconductor structure and method for manufacturing the same — Taiwan Semiconductor Manufacturing Company Ltd. (US12237283B2)

ABSTRACT

Abstract

A semiconductor structure includes a first substrate, a plurality of first bonding pads disposed in the first dielectric layer, a plurality of second bonding pads disposed in the first dielectric layer, a second substrate, and a dielectric layer between the first substrate and the second substrate. The first bonding pads have a first width, and the second bonding pads have a second width greater than the first width. The second width is greater than the first width. The second bonding pads are arranged to form a frame pattern surrounding the first bonding pads. The first bonding pads and the second bonding pads are arranged to form a plurality of columns and a plurality of rows. Two of the second bonding pads are disposed at two opposite ends of each column and two opposite ends of each row.

Description

PRIORITY CLAIM AND CROSS-REFERENCE

This application is a continuation of U.S. patent application Ser. No. 17/071,895, entitled of “SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME”, which is a continuation of U.S. patent application Ser. No. 15/792,346, filed on Oct. 24, 2017, entitled of “SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME”, the entire disclosure of which is hereby incorporated by reference.

BACKGROUND

Semiconductor device are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. Many integrated circuits are typically manufactured on a single semiconductor wafer, and individual dies on the wafer are singulated by sawing between the integrated circuits along a scribe line. The individual ides are typically packaged separately, in multi-chip modules, or in other types of packaging, for example.

The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. These smaller electronic components also require smaller packages that utilize less area than packages of the past, in some applications.

Three dimension integrated circuits (3DICs) are a recent development in semiconductor packaging in which multiple semiconductor dies are stacked upon one another, such as package-on-package (PoP) an system-in-package (SiP) packaging techniques. Some 3DICs provide improved integration density and other advantages, such as faster speeds and higher bandwidth, because of the decreased length of interconnects between the stacked dies, as example. However, there are many challenges related to 3DICs.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 A and FIG. 1 B are schematic drawings illustrating a semiconductor structure according to aspects of the present disclosure in some embodiments, wherein FIG. 1 A is a plan view of the semiconductor structure and FIG. 1 B is a sectional view of the semiconductor structure.

FIGS. 2 - 3 are schematic drawings illustrating a semiconductor structure according to aspects of the present disclosure in some embodiments.

FIG. 4 is a schematic drawing illustrating a semiconductor structure according to aspects of the present disclosure in some embodiments.

FIG. 5 is a schematic drawing illustrating a semiconductor structure according to aspects of the present disclosure in some embodiments.

FIG. 6 A and FIG. 6 B are schematic drawings illustrating a semiconductor structure according to aspects of the present disclosure in some embodiments, wherein FIG. 6 A is a plan view of the semiconductor structure and FIG. 6 B is a sectional view of the semiconductor structure.

FIG. 7 A and FIG. 7 B are schematic drawings illustrating a semiconductor structure according to aspects of the present disclosure in some embodiments, wherein FIG. 7 A is a plan view of the semiconductor structure and FIG. 7 B is a sectional view of the semiconductor structure.

FIGS. 8 - 9 are schematic drawings illustrating a semiconductor structure according to aspects of the present disclosure in some embodiments.

FIG. 10 is a schematic drawing illustrating a semiconductor structure according to aspects of the present disclosure in some embodiments.

FIG. 11 A and FIG. 11 B are schematic drawings illustrating a semiconductor structure according to aspects of the present disclosure in some embodiments, wherein FIG. 11 A is a plan view of the semiconductor structure and FIG. 11 B is a sectional view of the semiconductor structure.

FIG. 12 is a schematic drawing illustrating a semiconductor structure according to aspects of the present disclosure in some embodiments.

FIG. 13 is a flow chart representing a method for manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure.

FIGS. 14 through 15 illustrate sectional views of a semiconductor structure at various fabrication stages constructed according to aspects of the present disclosure in one or more embodiments.

FIG. 16 is a flow chart representing a method for manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure.

FIGS. 17 through 18 illustrate sectional views of a semiconductor structure at various fabrication stages constructed according to aspects of the present disclosure in one or more embodiments.

FIG. 19 is a schematic drawing illustrating a semiconductor structure according to aspects of the present disclosure in some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper”, “on” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, the terms such as “first”, “second” and “third” describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another. The terms such as “first”, “second” and “third” when used herein do not imply a sequence or order unless clearly indicated by the context.

As used herein, the terms “approximately,” “substantially,” “substantial” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, w % ben used in conjunction with a numerical value, the terms can refer to a range of variation of less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, two numerical values can be deemed to be “substantially” the same or equal if a difference between the values is less than or equal to ±10% of an average of the values, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, “substantially” parallel can refer to a range of angular variation relative to 0° that is less than or equal to ±10°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. For example, “substantially” perpendicular can refer to a range of angular variation relative to 90° that is less than or equal to ±10°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.

The manufacturing of integrated circuits often involves the bonding of device dies to package substrate. In a typical bonding process, a pack-and-place tool is used to pick up, place, and stack dies onto package components one-by-one. Typically, a vacuum pick-and-place tool uses a vacuum to pick up and attach a die to a pickup head of the tool. Usually, the pickup head is provided to make contact with the majority of the surface area of the die. However, edges of the die are usually bended upwardly when placing the die onto the package substrate, and thus bonding pads near the edges of the die may be outwardly shifted. Moreover, the shifted bonding pads may not align with the corresponding pads over the package substrate. Consequently, electrical connections between the shifted bonding pads over the die and the corresponding pads over the package substrate are failed, and thus performance and reliability of the semiconductor package are adversely impacted.

One or more implementations of the present invention will now be described with reference to the attached drawings, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures are not necessarily drawn to scale. As used herein, the terms “die” and “chip” are interchangeable throughout the specification.

The terms “wafer” and “substrate” used herein include any structure having an exposed surface onto which a layer is deposited according to the present invention, for example, to form the circuit structure such as a redistribution layer (RDL). The term substrate is understood to include semiconductor wafers, but not limited thereto. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon.

FIG. 1 A and FIG. 1 B are schematic drawings illustrating a semiconductor structure 100 according to aspects of the present disclosure in some embodiments, FIG. 1 A is a plan view of the semiconductor structure 100 and FIG. 1 B is a sectional view of the semiconductor structure 100 . The semiconductor structure 100 such as a die can be vertically bonded to another semiconductor structure or a package component to form a 3DIC package. The semiconductor structure 100 can include a substrate 102 , and the substrate 102 can include silicon, silicon germanium, silicon carbon, III-V compound semiconductor material, or the like. The substrate 102 may include active components or circuits, such as conductive features, implantation regions, resistors, capacitors, and other semiconductor elements e.g., transistors, diodes, etc. Those active components or circuits can be formed over the substrate 102 in front-end-of-line (FEOL) operations in some embodiments, for example. An interconnect structure (not shown) can be formed over a first surface 104 of the substrate 102 in back-end-of-line (BEOL) operations in some embodiments, for example. The interconnect structure includes conductive features, such as conductive lines and vias formed in an insulating material. In some embodiments, the insulating material can

PRIORITY CLAIM AND CROSS-REFERENCE

This application is a continuation of U.S. patent application Ser. No. 17/071,895, entitled of “SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME”, which is a continuation of U.S. patent application Ser. No. 15/792,346, filed on Oct. 24, 2017, entitled of “SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME”, the entire disclosure of which is hereby incorporated by reference.

BACKGROUND

Semiconductor device are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. Many integrated circuits are typically manufactured on a single semiconductor wafer, and individual dies on the wafer are singulated by sawing between the integrated circuits along a scribe line. The individual ides are typically packaged separately, in multi-chip modules, or in other types of packaging, for example.

The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. These smaller electronic components also require smaller packages that utilize less area than packages of the past, in some applications.

Three dimension integrated circuits (3DICs) are a recent development in semiconductor packaging in which multiple semiconductor dies are stacked upon one another, such as package-on-package (PoP) an system-in-package (SiP) packaging techniques. Some 3DICs provide improved integration density and other advantages, such as faster speeds and higher bandwidth, because of the decreased length of interconnects between the stacked dies, as example. However, there are many challenges related to 3DICs.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 A and FIG. 1 B are schematic drawings illustrating a semiconductor structure according to aspects of the present disclosure in some embodiments, wherein FIG. 1 A is a plan view of the semiconductor structure and FIG. 1 B is a sectional view of the semiconductor structure.

FIGS. 2 - 3 are schematic drawings illustrating a semiconductor structure according to aspects of the present disclosure in some embodiments.

FIG. 4 is a schematic drawing illustrating a semiconductor structure according to aspects of the present disclosure in some embodiments.

FIG. 5 is a schematic drawing illustrating a semiconductor structure according to aspects of the present disclosure in some embodiments.

FIG. 6 A and FIG. 6 B are schematic drawings illustrating a semiconductor structure according to aspects of the present disclosure in some embodiments, wherein FIG. 6 A is a plan view of the semiconductor structure and FIG. 6 B is a sectional view of the semiconductor structure.

FIG. 7 A and FIG. 7 B are schematic drawings illustrating a semiconductor structure according to aspects of the present disclosure in some embodiments, wherein FIG. 7 A is a plan view of the semiconductor structure and FIG. 7 B is a sectional view of the semiconductor structure.

FIGS. 8 - 9 are schematic drawings illustrating a semiconductor structure according to aspects of the present disclosure in some embodiments.

FIG. 10 is a schematic drawing illustrating a semiconductor structure according to aspects of the present disclosure in some embodiments.

FIG. 11 A and FIG. 11 B are schematic drawings illustrating a semiconductor structure according to aspects of the present disclosure in some embodiments, wherein FIG. 11 A is a plan view of the semiconductor structure and FIG. 11 B is a sectional view of the semiconductor structure.

FIG. 12 is a schematic drawing illustrating a semiconductor structure according to aspects of the present disclosure in some embodiments.

FIG. 13 is a flow chart representing a method for manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure.

FIGS. 14 through 15 illustrate sectional views of a semiconductor structure at various fabrication stages constructed according to aspects of the present disclosure in one or more embodiments.

FIG. 16 is a flow chart representing a method for manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure.

FIGS. 17 through 18 illustrate sectional views of a semiconductor structure at various fabrication stages constructed according to aspects of the present disclosure in one or more embodiments.

FIG. 19 is a schematic drawing illustrating a semiconductor structure according to aspects of the present disclosure in some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper”, “on” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, the terms such as “first”, “second” and “third” describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another. The terms such as “first”, “second” and “third” when used herein do not imply a sequence or order unless clearly indicated by the context.

As used herein, the terms “approximately,” “substantially,” “substantial” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, w % ben used in conjunction with a numerical value, the terms can refer to a range of variation of less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, two numerical values can be deemed to be “substantially” the same or equal if a difference between the values is less than or equal to ±10% of an average of the values, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, “substantially” parallel can refer to a range of angular variation relative to 0° that is less than or equal to ±10°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. For example, “substantially” perpendicular can refer to a range of angular variation relative to 90° that is less than or equal to ±10°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.

The manufacturing of integrated circuits often involves the bonding of device dies to package substrate. In a typical bonding process, a pack-and-place tool is used to pick up, place, and stack dies onto package components one-by-one. Typically, a vacuum pick-and-place tool uses a vacuum to pick up and attach a die to a pickup head of the tool. Usually, the pickup head is provided to make contact with the majority of the surface area of the die. However, edges of the die are usually bended upwardly when placing the die onto the package substrate, and thus bonding pads near the edges of the die may be outwardly shifted. Moreover, the shifted bonding pads may not align with the corresponding pads over the package substrate. Consequently, electrical connections between the shifted bonding pads over the die and the corresponding pads over the package substrate are failed, and thus performance and reliability of the semiconductor package are adversely impacted.

One or more implementations of the present invention will now be described with reference to the attached drawings, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures are not necessarily drawn to scale. As used herein, the terms “die” and “chip” are interchangeable throughout the specification.

The terms “wafer” and “substrate” used herein include any structure having an exposed surface onto which a layer is deposited according to the present invention, for example, to form the circuit structure such as a redistribution layer (RDL). The term substrate is understood to include semiconductor wafers, but not limited thereto. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon.

FIG. 1 A and FIG. 1 B are schematic drawings illustrating a semiconductor structure 100 according to aspects of the present disclosure in some embodiments, FIG. 1 A is a plan view of the semiconductor structure 100 and FIG. 1 B is a sectional view of the semiconductor structure 100 . The semiconductor structure 100 such as a die can be vertically bonded to another semiconductor structure or a package component to form a 3DIC package. The semiconductor structure 100 can include a substrate 102 , and the substrate 102 can include silicon, silicon germanium, silicon carbon, III-V compound semiconductor material, or the like. The substrate 102 may include active components or circuits, such as conductive features, implantation regions, resistors, capacitors, and other semiconductor elements e.g., transistors, diodes, etc. Those active components or circuits can be formed over the substrate 102 in front-end-of-line (FEOL) operations in some embodiments, for example. An interconnect structure (not shown) can be formed over a first surface 104 of the substrate 102 in back-end-of-line (BEOL) operations in some embodiments, for example. The interconnect structure includes conductive features, such as conductive lines and vias formed in an insulating material. In some embodiments, the insulating material can include a plurality of dielectric layers.

The semiconductor structure 100 further includes a plurality of first bonding pads 110 and a plurality of second bonding pads 120 over the first surface 104 of the substrate 102 . Some of the vias electrically couple the first and second bonding pads

110 and 120 to the conductive lines in the interconnect structure, and to the circuits over the substrate 102 through the conductive lines. The vias may also couple the conductive lines in different layers. The conductive lines and the vias can include conductive materials typically used in BEOL operations, such as Cu, Al, Ti, TiN, Ta. TaN, or multiple layers or combination thereof. In some embodiments of the present disclosure, the first bonding pads 110 and the second bonding pads 120 are formed in a topmost dielectric layer 106 of the interconnection structure over the first surface 104 of the substrate 102 .

Referring to FIGS. 1 A and 1 B , in some embodiments of the present disclosure, the semiconductor structure 100 is generally a square including a length 140 and a width 142 in a plan view. The first bonding pads 110 and the second bonding pads 120 are arranged to form an array of columns and rows as shown in FIG. 1 A . For example, the first bonding pads 110 and the second bonding pads 120 are arranged to form a plurality of columns along a first direction D 1 , and also arranged to form a plurality of rows along a second direction D 2 orthogonal to the first direction D 1 . In some embodiments of the present disclosure, the first bonding pads 110 are disposed in a central region 150 while the second bonding pads 120 are disposed in an edge region 152 which surrounds the central region 150 . In other words, the second bonding pads 120 are disposed adjacent to the edges and/or corners of the substrate 102 as shown in FIG. 1 A . In some embodiments of the present disclosure, a width 144 of the edge region 152 can be equal to or less than one-tenth of the length 140 and/or the width 142 of the semiconductor structure 100 , but not limited to this.

Still referring to FIGS. 1 A and 1 B , the first bonding pads 110 and the second bonding pads 120 can include various shapes. For example but not limited to, the first bonding pads 110 and the second bonding pads 120 can in circular shape, elliptical shape, quadrilateral shape, octagonal shape or polygonal shape. The first bonding pads 110 respectively include a first width W 1 and the second bonding pads 120 respectively include a second width W 2 . In some embodiments, the first width W 1 of the first bonding pads 110 is substantially different from the second width W 2 of the second bonding pads 120 . In some embodiments of the present disclosure, the second width W 2 is substantially greater than the first width W 1 . In other words, at least one second bonding pad 120 including the second width W 2 substantially different from the first width W 1 of the first bonding pad 110 is provided. In some embodiments of the present disclosure, a difference ΔW between the first width W 1 and the second width W 2 can be related to a size and/or a thickness of the semiconductor structure 100 . For example but not limited to, the difference ΔW can be correlated positively with the size of the semiconductor structure 100 . For example but not limited to, the difference ΔW can be correlated negatively with the thickness of the semiconductor structure 100 . In some embodiments of the present disclosure, the second width W 2 of the second bonding pads 120 are less than 5 micrometers (μm), but not limited to this.

Still referring to FIGS. 1 A and 1 B , at least one of the second bonding pads 120 is adjacent to one of the first bonding pads 110 . In some embodiments of the present disclosure, two adjacent first bonding pads 110 in the same column or the same row include a distance d 1 therebetween, and the second bonding pad 120 and its adjacent first bonding pad 110 include a distance d 2 therebetween. In some embodiments, the distance d 2 is substantially less than the distance d 1 .

Referring to FIGS. 2 - 3 , which are schematic drawings illustrating a semiconductor structure according to aspects of the present disclosure in some embodiments. It should be understood that similar features in FIGS. 1 A- 1 B and 2 - 3 are identified by the same reference numerals for clarity and simplicity. Furthermore, similar elements in FIGS. 1 A- 1 B and 2 - 3 can include similar materials, and thus those details are omitted in the interest of brevity. As shown in FIGS. 2 - 3 , in some embodiments of the present disclosure, the semiconductor structure 100 can be bonded to another semiconductor structure 200 to form a semiconductor package 300 . The semiconductor structure 200 can include a semiconductor structure or a package component. In some embodiments of the present disclosure, the semiconductor structure 200 can be a package substrate strip, an interposer wafer, a packaged wafer, a device wafer, or the like.

In some embodiments of the present disclosure, the semiconductor structure 200 can include a second substrate 202 . The second substrate 202 may include active components or circuits, such as conductive features, implantation regions, resistors, capacitors, and other semiconductor elements e.g., transistors, diodes, etc. Those active components or circuits can be formed over the substrate 202 in FEOL operations in some embodiments, for example. An interconnect structure (not shown) can be formed over a second surface 204 of the second substrate 202 in BEOL operations in some embodiments, for example. As mentioned above, the interconnect structure can include conductive features, such as conductive lines and vias formed in an insulating material. In some embodiments, the insulating material can include a plurality of dielectric layers. The semiconductor structure 200 includes a plurality of third bonding pads 210 over the second surface 204 of the second substrate 202 . Some of the vias electrically couple the third bonding pads 210 to the conductive lines in the interconnect structure, and to the circuits over the second substrate 202 through the conductive lines. The vias may also couple the conductive lines in different layers. The conductive lines and the vias can include conductive materials typically used in BEOL operations. In some embodiments of the present disclosure, the third bonding pads 210 are formed in a topmost dielectric layer 206 of the interconnection structure over the second surface 204 of the second substrate 202 .

Still referring to FIGS. 2 - 3 , in some embodiments of the present disclosure, the third bonding pads 210 are arranged to form an array of columns and rows. The third bonding pads 210 can include various shapes as mentioned above, thus the details are omitted for simplicity. The third bonding pads 210 respectively include a third width W 3 as shown in FIGS. 2 - 3 . In some embodiments of the present disclosure, the third width W 3 of the third bonding pads 210 can be the same as the first width W 1 of the first bonding pads 110 . In some embodiments of the present disclosure, the third width W can be different from the first width W 1 of the first bonding pads 110 . Still in some embodiments of the present disclosure, the second width W 2 of the second bonding pads 120 is substantially greater than the third width W 3 of the third bonding pads 210 . Furthermore, in some embodiments of the present disclosure, a distance d 3 between two adjacent third bonding pads 210 can be the same as the distance d 1 between two adjacent first bonding pads 110 .

Referring to FIGS. 2 - 3 , a pick-and-place tool is used to pick, place and stack the semiconductor structure 100 onto the semiconductor structure 200 . FIG. 2 illustrates a pickup head 700 of the pick-and-place tool, and the first surface 104 of the first substrate 102 is arranged to face the second surface 204 of the second substrate 202 . The pickup head 700 is provided to make contact with the majority of the surface area of the semiconductor structure 10 , and thus edges of the semiconductor structure 10 may be upwardly bended. Consequently, the second bonding pads 120 in the edge region 152 of the semiconductor structure 100 may be outwardly shifted, and a distance d 2 ′ between the shifted second bonding pad 120 and its adjacent first bonding pad 110 is therefore made greater than the original distance d 2 , as shown in FIG. 2 .

Referring to FIG. 3 , the semiconductor structure 100 is then bonded to the semiconductor structure 200 by hybrid bonding. In the hybrid bonding, the first and second bonding pads

110 and 120 of the semiconductor structure 100 are bonded to the third bonding pads 210 of the semiconductor structure 200 , and the dielectric layer 106 of the semiconductor structure 100 is bonded to the dielectric layer 206 of the semiconductor structure 200 . As shown in FIG. 3 , the third bonding pads 210 of the semiconductor structure 200 vertically align with and contact the first bonding pads 110 in the central region 150 of the semiconductor structure 100 . More importantly, though the second bonding pads 120 may be outwardly shifted during the pick-and-place operation, the misalignment issue can be ignored because the enlarged second bonding pads 120 at least partially contact the third bonding pads 210 as shown in FIG. 3 . Accordingly, electrical connection between the semiconductor structure 1000 and the semiconductor structure 200 is constructed.

FIG. 4 is a schematic drawing illustrating another semiconductor structure 310 according to aspects of the present disclosure in some embodiments. It should be understood that similar features in FIGS. 3 and 4 are identified by the same reference numerals for clarity and simplicity. Furthermore, similar elements in FIGS. 3 and 4 can include similar materials, and thus those details are omitted in the interest of brevity. As shown in FIG. 4 , in some embodiments of the present disclosure, the semiconductor structure 100 can be bonded to another semiconductor structure 200 a to form the semiconductor package 310 . The semiconductor structure 200 a can include a semiconductor structure or a package component similar as the semiconductor structure 200 , and thus only the difference is detailed. The semiconductor structure 200 a includes a plurality of third bonding pads 210 and a plurality of fourth bonding pads 220 formed in a topmost dielectric layer 206 of the interconnection structure over the second surface 204 of the substrate 202 .

Referring to FIG. 4 , in some embodiments of the present disclosure, the third bonding pads 210 and the fourth bonding pads 220 are arranged to form an array of columns and rows. In some embodiments of the present disclosure, the fourth bonding pads 220 surround the third bonding pads 210 . The third bonding pads 210 and the fourth bonding pads 220 can include various shapes as mentioned above, thus the details are omitted for simplicity. The third bonding pads 210 respectively include a third width W 3 and the fourth bonding pads 220 respectively include a fourth width W 4 . In some embodiments, the third width W 3 of the third bonding pads 210 is substantially different from the fourth width W 4 of the fourth bonding pads 220 . In some embodiments of the present disclosure, the fourth width W 4 is substantially greater than the third width W 3 . In other words, at least one fourth bonding pad 220 including the fourth width W 4 substantially different from the third width W 3 of the third bonding pad 210 is provided. In some embodiments, the second width W 2 is substantially the same as the fourth width W 4 .

Still referring to FIG. 4 , a pick-and-place tool is used to pick, place and stack the semiconductor structure 100 onto the semiconductor structure 200 a . In some embodiments of the present disclosure, a pickup head (not shown) is provided to make contact with the majority of the surface area of the semiconductor structure 100 , and thus edges of the semiconductor structure 100 may be upwardly bended. Consequently, the first bonding pads 110 may vertically align with the third bonding pads 210 . However, the second bonding pads 120 in the edge region 152 of the semiconductor structure 100 may be outwardly shifted, and a distance d 2 ′ between the shifted second bonding pad 120 and its adjacent first bonding pad 110 is therefore made greater than the original distance d 2 .

Still referring to FIG. 4 , the semiconductor structure 100 is then bonded to the semiconductor structure 200 a to form the semiconductor package 310 by hybrid bonding. In the hybrid bonding, the first bonding pads 110 of the semiconductor structure 100 are bonded to the third bonding pads

CLAIMS

Claims ( 20 )

What is claimed is:

1. A semiconductor structure comprising:

a first semiconductor die substrate;

a plurality of first bonding pads disposed over the first semiconductor die substrate and comprising a first width, wherein each of the first bonding pads has a first surface facing the first semiconductor die substrate and a second surface opposite to the first surface;

a plurality of second bonding pads disposed over the first semiconductor die substrate and comprising a second width greater than the first width, wherein the second bonding pads are arranged to form a frame pattern surrounding the first bonding pads, and each of the second bonding pads has a first surface facing the first semiconductor die substrate and a second surface opposite to the first surface with a width substantially equal to that of the first surface, and the second surface of at least one of the second bonding pad is flush with the second surface of at least one of the first bonding pad;

a second semiconductor die substrate;

a plurality of third bonding pads disposed over the second semiconductor die substrate, wherein each of the third bonding pads has a first surface and a second surface opposite to the first surface, and each of the bonding pads has a third width;

a plurality of fourth bonding pads disposed over the second semiconductor die substrate, wherein each of the fourth bonding pads has a fourth width greater than the third width; and

a dielectric structure between the first semiconductor die substrate and the second semiconductor die substrate, wherein the dielectric structure comprises a first dielectric layer and a second dielectric layer bonded to each other,

wherein the first dielectric layer has a first surface aligned with the first surfaces of the first bonding pads and the first surfaces of the second bonding pads, and the second dielectric layer has a second surface aligned with the second surfaces of the third bonding pads,

wherein the third bonding pads are in contact with the first bonding pads, and the fourth bonding pads are in contact with the second bonding pads,

wherein a difference between the second width and the first width is positively correlated with a size of the semiconductor structure comprising the first semiconductor die substrate, the first bonding pads and the second bonding pads,

wherein a thickness of the first dielectric layer is substantially equal to thicknesses of the first bonding pads and thicknesses of the second bonding pads, and a thickness of the second dielectric layer is substantially equal to thicknesses of the third bonding pads and thicknesses of the fourth bonding pads.

2. The semiconductor structure of claim 1 , wherein the first bonding pads and the second bonding pads are embedded in the dielectric structure.

3. The semiconductor structure of claim 1 , wherein the first surface of the first dielectric layer is in contact with the first semiconductor die substrate and the second surface of the second dielectric layer is in contact with the second semiconductor die substrate.

4. The semiconductor structure of claim 1 , wherein the first dielectric layer has a third surface facing the second semiconductor die substrate, and the second surfaces of the second bonding pads are entirely flush with the third surface of the first dielectric layer.

5. The semiconductor structure of claim 1 , wherein the third width of the third bonding pad is equal to the first width of the first bonding pads.

6. The semiconductor structure of claim 1 , wherein each of the third bonding pads is in physical contact with a portion of the one of the first bonding pads.

7. The semiconductor structure of claim 1 , wherein the difference between the second width and the first width is correlated negatively with a thickness of the semiconductor structure.

8. The semiconductor structure of claim 1 , wherein the fourth width of each fourth bonding pad is equal to the second width of each second bonding pad.

9. A semiconductor structure comprising:

a first semiconductor die substrate;

a first dielectric layer disposed over the first semiconductor die substrate;

a plurality of first bonding pads disposed over the first semiconductor die substrate and in the first dielectric layer;

a plurality of second bonding pads disposed over the first semiconductor die substrate and in the first dielectric layer, wherein a width of each second bonding pad is greater than a width of each first bonding pad;

a second semiconductor die substrate;

a second dielectric layer disposed over the second semiconductor die substrate and bonded to the first dielectric layer;

a plurality of third bonding pads disposed over the second semiconductor die substrate and in the second dielectric layer; and

a plurality of fourth bonding pads disposed over the second semiconductor die substrate and in the second dielectric layer, wherein a width of the fourth bonding pad is greater than a width of each third bonding pad,

wherein the first bonding pads are separated from each other in a first distance, and the second bonding pad is separated from its adjacent first bonding pad in a second distance, and the second distance is greater than the first distance,

wherein the third bonding pads are in physical contact with the first bonding pads, and the fourth bonding pads are in physical contact with the second bonding pads,

wherein a difference between the width of each second bonding pad and the width of each first bonding pad is correlated positively with a size of the semiconductor structure comprising the first semiconductor die substrate, the first bonding pads and the second bonding pads,

wherein a thickness of the first dielectric layer is substantially equal to thicknesses of the first bonding pads and thicknesses of the second bonding pads, and a thickness of the second dielectric layer is substantially equal to thicknesses of the third bonding pads and thicknesses of the fourth bonding pads,

wherein at least one of the second bonding pads has a bottom surface facing the second semiconductor die substrate, and the bottom surface of the second bonding pad is in contact with a top surface of one of the fourth bonding pads throughout a span of the bottom surface.

10. The semiconductor structure of claim 9 , wherein a top surface of the first dielectric layer is substantially aligned with top surfaces of the first bonding pads and top surfaces of the second bonding pads.

11. The semiconductor structure of claim 9 , wherein the difference between the width of each second bonding pad and the width of each first bonding pad is correlated negatively with a thickness of the semiconductor structure.

12. The semiconductor structure of claim 9 , wherein a top surface of the second dielectric layer is substantially aligned with top surfaces of the third bonding pads and top surfaces of the fourth bonding pads.

13. The semiconductor structure of claim 9 , wherein the width of each fourth bonding pad is equal to the width of each second bonding pad.

14. A semiconductor structure comprising:

a first semiconductor die substrate;

a second semiconductor die substrate; and

a bonding structure disposed between the first semiconductor die substrate and the second semiconductor die substrate, wherein the bonding structure comprises:

a dielectric structure comprising a first dielectric layer and a second dielectric layer bonded to each other;

a plurality of first bonding pads disposed in the first dielectric layer;

a plurality of second bonding pads disposed in the first dielectric layer; and

a plurality of third bonding pads and a plurality of fourth bonding pads disposed in the second dielectric layer, wherein each third bonding pad is in direct contact with and bonded to the first bonding pad, and each fourth bonding pad is in direct contact with and bonded to the second bonding pad,

wherein the second bonding pads are arranged to form a frame pattern surrounding the first bonding pads, a width of each first bonding pad is less than a width of each second bonding pad, and a width of each third bonding pad is less than a width of each fourth bonding pad,

wherein a difference between the width of each second bonding pad and the width of each first bonding pad is correlated positively with a size of the semiconductor structure comprising the first semiconductor die substrate, the first bonding pads and the second bonding pads,

wherein a thickness of the first dielectric layer is substantially equal to thicknesses of the first bonding pads and thicknesses of the second bonding pads, and a thickness of the second dielectric layer is substantially equal to thicknesses of the third bonding pads and thicknesses of the fourth bonding pads,

wherein at least one of the first bonding pads has an entire surface facing the second semiconductor die substrate, at least one of the second bonding pads has an entire surface facing the second semiconductor die substrate, and the entire surface of the first bonding pad is flush with the entire surface of the second bonding pad.

15. The semiconductor structure of claim 14 , wherein the width of the third bonding pad is equal to the width of each first bonding pad.

16. The semiconductor structure of claim 14 , wherein sidewalls of the second bonding pad and a portion of a bottom surface of the second bonding pad are in contact with the dielectric structure.

17. The semiconductor structure of claim 14 , wherein the first bonding pads are separated from each other in a first distance, and the second bonding pad is separated from its adjacent first bonding pad in a second distance, and the second distance is greater than the first distance.

18. The semiconductor structure of claim 17 , wherein the third bonding pads separated from each other in a third distance, and the third distance is equal to the first distance.

19. The semiconductor structure of claim 14 , wherein each of the first bonding pads has a first diameter and a second diameter perpendicular to the first diameter, each of the second bonding pads has a first diameter and a second diameter perpendicular to the first diameter, and the first diameter and the second diameter of the second bonding pad are greater than the first diameter and the second diameter of the first bonding pad.

20. The semiconductor structure of claim 14 , wherein the difference between the width of each second bonding pad and the width of each first bonding pad is correlated negatively with a thickness of the semiconductor structure.

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US15/792,346

patent/US10818624B2/en

active

Active

2018

2018-06-11

TW

TW107120035A

patent/TWI796336B/en

active

2018-07-06

CN

CN201810734844.7A

patent/CN109698175B/en

active

Active

2020

2020-10-15

US

US17/071,895

patent/US11018104B2/en

active

Active

2021

2021-05-21

US

US17/327,405

patent/US12237283B2/en

active

Active

2024

2024-07-25

US

US18/783,464

patent/US20240379600A1/en

active

Pending

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( en )

*

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Semiconductor device, electronic device, electronic apparatus, and methods for manufacturing carrier substrate, semiconductor device, and electronic device

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2010-10-21

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2007-06-27

2009-01-16

Shinko Electric Ind Co

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