ABSTRACT
Abstract
A semiconductor element having an interconnect bonding layer with a contact pad and a plasma damage-free low-k dielectric material is disclosed. The contact pad connects an underlying conductive feature through an intervening via. A thin dielectric layer is disposed on and covering the entire sidewalls of the contact pad, the intervening via and the underlying conductive feature, and making an approximately right angle turn to extend along an interface between the low-k dielectric material and a first dielectric layer that at least partially bury the underlying contact feature.
Description
BACKGROUND
Field
The field relates to microelectronics with a bonding layer comprising a low-k dielectric material.
Description of the Related Art
The semiconductor industry has experienced tremendous growth over the past several decades as integrated circuit (IC) engineers have developed chips with ever smaller technology nodes, which create ever smaller transistors on a chip or integrated device die. However, as integration increases, parasitic capacitance or resistance capacitance (RC), which is produced by the conductors and dielectric materials in interconnects, becomes significant enough to cause interconnect-induced delays. The negative effect of RC becomes more profound when the technology nodes get smaller and integration gets higher. With the decreasing of device dimensions, both the resistance and the interline capacitance increase due to the decrease of the conductor cross section, the increase of the wire length, and the reduction of interconnect spacing. Hence, the RC delay is significantly increased with the advance of the technology node. In order to bring down RC delay, new materials have been introduced to the back-end-of-line (BEOL) interconnects. For example, aluminum (Al) has been replaced by copper (Cu) as a conductor because Cu can provide lower resistivity. In the case of the interconnecting nonconductor, dielectric materials with low dielectric constant k have been adopted. Additionally, the changing of conductor to Cu and nonconductive materials to low-k dielectric has pushed fabrication methods to advance. Traditional metal etching approach has been replaced by a damascene process.
BRIEF DESCRIPTION OF THE DRAWINGS
Specific implementations will now be described with reference to the following drawings, which are provided by way of example, and not limitation.
FIG. 1 is a schematic cross-sectional view of a semiconductor element comprising a conductive contact pad embedded in a non-low-k dielectric bonding layer connecting to a underlaying conductive feature through an intervening via.
FIG. 2 is a schematic cross-sectional view of an embodiment of a semiconductor element comprising a plurality of conductive contact pads embedded in a low-k dielectric bonding layer, each of the contact features connecting to an underlying conductive feature through an intervening via.
FIG. 2 A is a detail schematic cross-sectional view showing one of the conductive features in FIG. 2 , including a conductive pad embedded in a low-k dielectric bonding layer and connecting to an underlying conductive feature through an intervening via.
FIGS. 3 - 6 are schematic cross-sectional views illustrating example process steps to fabricate the semiconductor element of FIG. 2 .
FIG. 7 is a schematic cross-sectional view of a semiconductor element that has the same structure as the semiconductor element of FIG. 2 , except there exist voids in the low-k dielectric bonding layer.
FIGS. 8 - 11 are schematic cross-sectional views illustrating example process steps to fabricate another embodiment of a semiconductor element shown in FIG. 11 .
FIG. 12 is a schematic cross-sectional view of a semiconductor element that has the same structure as the semiconductor element of FIG. 11 , except there exist voids in the low-k dielectric bonding layer.
FIG. 13 is a schematic cross-sectional view of another embodiment of a semiconductor element comprising a plurality of conductive contact pads embedded in a low-k dielectric bonding layer, each contact pad connecting to an underlying conductive feature through an intervening via, each contact pad and the connected via formed uniformly through a dual damascene process.
FIG. 14 is a schematic cross-sectional view of a semiconductor element that has the same structure as the semiconductor element of FIG. 2 , except the bonding structure comprises a thin dielectric top layer forming partially the top bonding surface.
FIG. 15 is a schematic cross-sectional view of a bonded structure comprising two semiconductor elements of FIG. 2 directly bonded together.
FIG. 16 is a schematic cross-sectional view of a bonded structure comprising a semiconductor element of FIG. 2 having a low-k dielectric material in the bonding layer directly bonded to semiconductor element having a non-low-k dielectric material in the bonding layer.
FIG. 17 is a schematic cross-sectional view of a bonded structure comprising a plurality of semiconductor elements of FIG. 2 directly bonded to a wafer having a plurality of semiconductor modules having a bonding layer with a low-k dielectric material.
FIG. 18 is a schematic cross-sectional view of the bonded structure of FIG. 17 coated with a protective layer and ready to be singulated.
FIG. 19 is a schematic cross-sectional view of a bonded structure comprising a plurality of semiconductor elements of FIG. 18 after singulation.
FIG. 20 is a schematic cross-sectional view of a bonded structure encapsulated with an ALD coated barrier layer.
FIG. 21 is a schematic cross-sectional view of another bonded structure encapsulated with an ALD coated barrier layer.
FIG. 22 is a schematic cross-sectional view of an embodiment of a semiconductor element comprising a low-k dielectric layer and thin conductive layers in the low-k dielectric layer forming Faraday cages around conductive features.
FIG. 23 is a schematic cross-sectional view of another embodiment of a semiconductor element comprising a low-k dielectric layer and thin conductive layers in the low-k dielectric layer forming Faraday cages around conductive features.
FIG. 24 is a schematic cross-sectional view of two microelectronic elements configured to be bonded together.
FIG. 25 is a schematic cross-sectional view of bonded structure comprising the two microelectronic elements in FIG. 14 bonded together.
DETAILED DESCRIPTION
In damascene processes, plasma technology is widely used because it can provide an isotropic or anisotropic etch process at a fast rate. These changes cause the low-k dielectric material sidewalls to come directly in contact with the plasma, such as in dielectric etching, photo stripping, barrier metal deposition, and surface treatment. Such plasma damage can increase the dielectric constant, moisture absorption, or degrade the desirable properties of the plasma exposed dielectric layer. These plasma related defects are an impediment to successful integration of low-k dielectric materials into semiconductor fabrication processing.
Plasma induced damages to a low-k dielectric material can happen in different ways. For example, under physical and chemical reactions with the plasma, the surface of the low-k dielectric material can be modified, e.g., increase in dielectric constant of exposed dielectric regions, roughened sidewalls of trenches, vias, or undercut, etc. The modification depth is related to the ion energy, diffusion of active radicals (O, H, F, etc.), and porosity and constituents in the low-k material. This type of plasma damage in the low-k dielectric material can be characterized by an increase of the dielectric constant k, changes in bonding configuration, formation of a carbon-depleted layer, film shrinkage, and surface densification.
FIG. 1 shows a schematic cross-sectional view of a portion of a semiconductor element 100 . The semiconductor element 100 can comprise a substrate 102 . such as a semiconductor substrate (e.g., silicon). The substrate 102 can comprise active circuitry and/or other devices formed therein. A first dielectric material layer 104 can be provided over the substrate 102 , and a second nonconductive or dielectric material 106 can be provided over the first dielectric material layer 104 . In various embodiments, an etch stop layer 108 can be provided between the first and second layers
104 , 106 . The semiconductor element can comprise a conductive contact pad 116 at least partially embedded in the second nonconductive or dielectric material 106 , which can have a low dielectric constant k. The dielectric material 106 together with the conductive contact pad 116 forms at least part of an interconnect structure with a top bonding surface 110 , which can be prepared for direct hybrid bonding to another element. The contact pad 116 connects to an underlying metallization layer 112 through an intervening via portion 114 which is narrower than the contact pad 116 . In some embodiments, the contact pad 116 and via portion 114 can comprise a continuous layer formed using a dual damascene process, such that the contact pad 116 and via portion 114 are formed during the same deposition process. In this case, the via portion 114 forms part of the interconnect structure together with the contact pad 116 above and the dielectric material 106 . In some embodiments, the via layer 114 is absent, and the conductive contact pad 116 is in contact with the metallization layer 112 , often with the conductive barrier layer 124 disposed therebetween. In some embodiments, the conductive barrier layer 124 may wrap around or partially surround the conductive contact pad 116 . The metallization layer 112 is buried in the first dielectric material layer 104 , which is separated from the second dielectric material 106 by the thin <figure-callout id="108" label="etch stop layer" filenames="US20240332227A1-20241003-D00001.png" state=
BACKGROUND
Field
The field relates to microelectronics with a bonding layer comprising a low-k dielectric material.
Description of the Related Art
The semiconductor industry has experienced tremendous growth over the past several decades as integrated circuit (IC) engineers have developed chips with ever smaller technology nodes, which create ever smaller transistors on a chip or integrated device die. However, as integration increases, parasitic capacitance or resistance capacitance (RC), which is produced by the conductors and dielectric materials in interconnects, becomes significant enough to cause interconnect-induced delays. The negative effect of RC becomes more profound when the technology nodes get smaller and integration gets higher. With the decreasing of device dimensions, both the resistance and the interline capacitance increase due to the decrease of the conductor cross section, the increase of the wire length, and the reduction of interconnect spacing. Hence, the RC delay is significantly increased with the advance of the technology node. In order to bring down RC delay, new materials have been introduced to the back-end-of-line (BEOL) interconnects. For example, aluminum (Al) has been replaced by copper (Cu) as a conductor because Cu can provide lower resistivity. In the case of the interconnecting nonconductor, dielectric materials with low dielectric constant k have been adopted. Additionally, the changing of conductor to Cu and nonconductive materials to low-k dielectric has pushed fabrication methods to advance. Traditional metal etching approach has been replaced by a damascene process.
BRIEF DESCRIPTION OF THE DRAWINGS
Specific implementations will now be described with reference to the following drawings, which are provided by way of example, and not limitation.
FIG. 1 is a schematic cross-sectional view of a semiconductor element comprising a conductive contact pad embedded in a non-low-k dielectric bonding layer connecting to a underlaying conductive feature through an intervening via.
FIG. 2 is a schematic cross-sectional view of an embodiment of a semiconductor element comprising a plurality of conductive contact pads embedded in a low-k dielectric bonding layer, each of the contact features connecting to an underlying conductive feature through an intervening via.
FIG. 2 A is a detail schematic cross-sectional view showing one of the conductive features in FIG. 2 , including a conductive pad embedded in a low-k dielectric bonding layer and connecting to an underlying conductive feature through an intervening via.
FIGS. 3 - 6 are schematic cross-sectional views illustrating example process steps to fabricate the semiconductor element of FIG. 2 .
FIG. 7 is a schematic cross-sectional view of a semiconductor element that has the same structure as the semiconductor element of FIG. 2 , except there exist voids in the low-k dielectric bonding layer.
FIGS. 8 - 11 are schematic cross-sectional views illustrating example process steps to fabricate another embodiment of a semiconductor element shown in FIG. 11 .
FIG. 12 is a schematic cross-sectional view of a semiconductor element that has the same structure as the semiconductor element of FIG. 11 , except there exist voids in the low-k dielectric bonding layer.
FIG. 13 is a schematic cross-sectional view of another embodiment of a semiconductor element comprising a plurality of conductive contact pads embedded in a low-k dielectric bonding layer, each contact pad connecting to an underlying conductive feature through an intervening via, each contact pad and the connected via formed uniformly through a dual damascene process.
FIG. 14 is a schematic cross-sectional view of a semiconductor element that has the same structure as the semiconductor element of FIG. 2 , except the bonding structure comprises a thin dielectric top layer forming partially the top bonding surface.
FIG. 15 is a schematic cross-sectional view of a bonded structure comprising two semiconductor elements of FIG. 2 directly bonded together.
FIG. 16 is a schematic cross-sectional view of a bonded structure comprising a semiconductor element of FIG. 2 having a low-k dielectric material in the bonding layer directly bonded to semiconductor element having a non-low-k dielectric material in the bonding layer.
FIG. 17 is a schematic cross-sectional view of a bonded structure comprising a plurality of semiconductor elements of FIG. 2 directly bonded to a wafer having a plurality of semiconductor modules having a bonding layer with a low-k dielectric material.
FIG. 18 is a schematic cross-sectional view of the bonded structure of FIG. 17 coated with a protective layer and ready to be singulated.
FIG. 19 is a schematic cross-sectional view of a bonded structure comprising a plurality of semiconductor elements of FIG. 18 after singulation.
FIG. 20 is a schematic cross-sectional view of a bonded structure encapsulated with an ALD coated barrier layer.
FIG. 21 is a schematic cross-sectional view of another bonded structure encapsulated with an ALD coated barrier layer.
FIG. 22 is a schematic cross-sectional view of an embodiment of a semiconductor element comprising a low-k dielectric layer and thin conductive layers in the low-k dielectric layer forming Faraday cages around conductive features.
FIG. 23 is a schematic cross-sectional view of another embodiment of a semiconductor element comprising a low-k dielectric layer and thin conductive layers in the low-k dielectric layer forming Faraday cages around conductive features.
FIG. 24 is a schematic cross-sectional view of two microelectronic elements configured to be bonded together.
FIG. 25 is a schematic cross-sectional view of bonded structure comprising the two microelectronic elements in FIG. 14 bonded together.
DETAILED DESCRIPTION
In damascene processes, plasma technology is widely used because it can provide an isotropic or anisotropic etch process at a fast rate. These changes cause the low-k dielectric material sidewalls to come directly in contact with the plasma, such as in dielectric etching, photo stripping, barrier metal deposition, and surface treatment. Such plasma damage can increase the dielectric constant, moisture absorption, or degrade the desirable properties of the plasma exposed dielectric layer. These plasma related defects are an impediment to successful integration of low-k dielectric materials into semiconductor fabrication processing.
Plasma induced damages to a low-k dielectric material can happen in different ways. For example, under physical and chemical reactions with the plasma, the surface of the low-k dielectric material can be modified, e.g., increase in dielectric constant of exposed dielectric regions, roughened sidewalls of trenches, vias, or undercut, etc. The modification depth is related to the ion energy, diffusion of active radicals (O, H, F, etc.), and porosity and constituents in the low-k material. This type of plasma damage in the low-k dielectric material can be characterized by an increase of the dielectric constant k, changes in bonding configuration, formation of a carbon-depleted layer, film shrinkage, and surface densification.
FIG. 1 shows a schematic cross-sectional view of a portion of a semiconductor element 100 . The semiconductor element 100 can comprise a substrate 102 . such as a semiconductor substrate (e.g., silicon). The substrate 102 can comprise active circuitry and/or other devices formed therein. A first dielectric material layer 104 can be provided over the substrate 102 , and a second nonconductive or dielectric material 106 can be provided over the first dielectric material layer 104 . In various embodiments, an etch stop layer 108 can be provided between the first and second layers
104 , 106 . The semiconductor element can comprise a conductive contact pad 116 at least partially embedded in the second nonconductive or dielectric material 106 , which can have a low dielectric constant k. The dielectric material 106 together with the conductive contact pad 116 forms at least part of an interconnect structure with a top bonding surface 110 , which can be prepared for direct hybrid bonding to another element. The contact pad 116 connects to an underlying metallization layer 112 through an intervening via portion 114 which is narrower than the contact pad 116 . In some embodiments, the contact pad 116 and via portion 114 can comprise a continuous layer formed using a dual damascene process, such that the contact pad 116 and via portion 114 are formed during the same deposition process. In this case, the via portion 114 forms part of the interconnect structure together with the contact pad 116 above and the dielectric material 106 . In some embodiments, the via layer 114 is absent, and the conductive contact pad 116 is in contact with the metallization layer 112 , often with the conductive barrier layer 124 disposed therebetween. In some embodiments, the conductive barrier layer 124 may wrap around or partially surround the conductive contact pad 116 . The metallization layer 112 is buried in the first dielectric material layer 104 , which is separated from the second dielectric material 106 by the thin etch stop layer 108 . The first dielectric layer 104 and the metallization layer 112 buried therein can form part of the interconnect structure.
The contact pad 116 and the via portion 114 in FIG. 1 may be formed by a dual damascene process. During the dual damascene process, a cavity 114 a for the intervening via portion 114 is etched first, followed by etching a cavity 116 a for the contact pad 116 . The two etching steps are normally performed by plasma etching process(es), which causes plasma damage on the sidewalls of the cavities
114 a and 116 a . To remove photoresist layers on the top surface 110 and organic residues on the sidewalls of the dielectric cavity after each of the etching steps, oxygen (O 2 ) is often used as plasma gas due to high reactivity of the O radicals. However, O 2 plasma ashing can cause detrimental damage to low-k dielectric materials. To reduce or minimize the plasma damage, a H 2 -based plasma is an alternative to O 2 plasma. However, to facilitate the removal rate of photoresist with H 2 -based plasma, a higher operation temperature is used, which is not preferred. To grow Cu in the cavities
114 a and 116 a by electroplating, a thin barrier and seeding layer (shown together by reference numeral 124 ) is deposited on the sidewalls and bottom surfaces. In various embodiments, the barrier layer 124 can be deposited by a physical vapor deposition (PVD) sputtering process, by atomic layer deposition (ALD) methods, or by other known methods.
A solution to the problem of plasma damage to the low-k dielectric material in FIG. 1 is presented in FIG. 2 , a schematic cross-sectional view of a semiconductor element 200 . Element 200 can be a microelectronic device having active circuitry (e.g., at least one transistor), and/or passive circuitry or other devices. As shown in FIG. 2 , the semiconductor element 200 comprises a substrate 202 , a first dielectric layer 204 , and a second dielectric layer 206 which may be separated from the first dielectric layer 204 by a thin dielectric barrier layer 242 . The second dielectric layer 206 can have a low dielectric constant k to reduce the resistance capacitance (RC) delay of conductors and dielectric materials in the interconnects. Generally, a low dielectric material (or low-k material) has a dielectric constant k less than 3.9. Therefore, the dielectric constant k of the second dielectric layer 206 can be less than 3.9, for example, less than 3.5. Example low-k materials may include porous silicon oxide, organosilicate glass (SiCOH), polymeric materials, e.g., poly(arylene ether) (PAE), polyimide, polytetrafluoroethylene (PTFE, sold under the trademark TEFLON), and amorphous carbon. Some other low-k materials may have even lower dielectric constant. For example, fluorine doped amorphous carbon may have dielectric constant k in the range of 2.3-2.8.
In FIG. 2 , a plurality of conductive contact pads 216 are at least partially embedded in the second low- k dielectric layer 206 , forming part of an interconnect structure with a top direct hybrid bonding surface 210 . A plurality of conductive features 212 , as extensions of an underlying conductive layer and/or connected to underlying circuitry, are buried partially in the first dielectric layer 204 and partially in the second dielectric layer 206 . The first dielectric layer 204 is disposed on a substrate 202 , e.g., a semiconductor substrate (such as a silicon substrate with one or more devices formed therein or thereon). The structures disposed above the substrate 202 can be considered the interconnect structure. Each of the plurality of contact pads 216 can be connected to one or more conductive features 212 through an intervening via portion 214 buried in the second dielectric layer 206 . As shown in FIG. 2 , the intervening via portion 214 can have a narrower dimension in the horizontal direction than the contact pad 216 and the underlying conductive feature 212 . The hybrid direct bonding surface 210 can be formed on top of the second dielectric layer 206 and the conductive contact pads 216 , ready to directly bond to another semiconductor element or microelectronic device. The contact pads 216 , the intervening via portions 214 , and underlying conductive features 212 can each comprise a metal, e.g., copper (Cu), aluminum (Al), nickel (Ni), and tungsten (W), or non-metal conductive material, e.g., polysilicon.
One characteristic of the thin film structure shown in FIG. 2 is that each of conductor columns embedded in the second dielectric layer 206 a formed by the contact pad 216 , the intervening via portion 214 and the underlying conductive feature 212 stacked connected together. Each conductor column is therefore a combined conductive features or combined conductors. Further, each of these combined conductive features or conductors is surrounded by an extended and continuous thin dielectric barrier layer 242 . For example, each conductive contact pad 216 can be surrounded by a first dielectric barrier layer portion 242 a at its sidewalls and by a second dielectric barrier layer portion 242 b at its bottom side edges. Each of the intervening via portions 214 can be surrounded by a third dielectric barrier layer portion 242 c at its sidewalls. Further, each underlying conductive feature 212 can be partially surrounded by a fourth dielectric barrier layer portion 242 d at its sidewalls and by a fifth dielectric barrier layer portion 242 e at its top side edges. The dielectric
barrier layer portions
242 a , 242 b , 242 c , 242 d , and 242 e can be connected to form a non-stop or continuous dielectric barrier layer 242 , covering all sidewalls, edges, and corners of the conductive features within or exposed to the second, low- k dielectric layer 206 . Therefore, the interconnect structure of the semiconductor element 200 in FIG. 2 can include the combined conductive features formed by the contact pad 216 , the via portion 214 having a bottom conductive barrier layer 226 and the underlying conductive feature 212 connected together, the low- k dielectric layer 206 and the first dielectric layer 204 disposed about the combined conductive features.
FIG. 2 A is a detail schematic cross-sectional view illustrating one of the four modules of combined conductive features or conductor shown in FIG. 2 , magnifying the sidewall and the dielectric barrier layer 242 structures. Since the contact pads 216 , the intervening via portions 214 , and the underlying conductive features 212 are formed by different process steps and have different horizontal dimensions, as shown in FIG. 2 A , the dielectric barrier layer 242 on a combined sidewall may not be vertically straight, but can contains vertical and horizontal sections, and inner and outer corners. Also, at the bottom of the combined sidewall the dielectric barrier layer 242 can form an approximately right angle turn extending horizontally to either reach the sidewall of another underlying conductive feature 212 or to reach an edge of the semiconductor element 200 . These horizontal portion of the dielectric barrier layer 242 can be disposed at an interface between the first dielectric layer 204 and the second dielectric layer 206 . The approximately right angle turn forms an L-shaped or horizontally flipped L-shaped lower portion of the dielectric barrier layer 242 , as illustrated in FIG. 2 A .
Another characteristic of the thin film structure in FIG. 2 and FIG. 2 A is that a second thin conductive barrier layer 228 can be disposed between each connected conductive contact pad 216 and via portion 214 pair. Further, a first thin conductive barrier layer 226 is disposed between each connected via portion 214 and underlying conductive feature 212 pair. The first conductive barrier layer 226 and the second conductive barrier layer may comprise one or more of the following materials, cobalt (Co), ruthenium (Ru), tantalum (Ta), tantalum nitride (TaN), TaN/Ta multilayer, indium oxide (In2O3), tungsten nitride (WN), titanium (Ti), titanium tungsten (TiW), titanium zirconium (NiZr), titanium nitride (TiN), TiN/Ti multilayer, and various alloys and combinations formed by the above listed materials. In some embodiments, the contact pads 216 and the intervening via portions 214 can be formed by a dual damascene process. In this case, the intervening via portions 214 are formed together with the connected contact pads 216 . Therefore, in other embodiments (not shown in FIG. 2 ), there may not be a conductive barrier between each connected contact pad 216 and via portion 214 pair.
The disclosed interconnect structure of the semiconductor element 200 shown in FIG. 2 can be formed to reduce or avoid plasma damage to the low- k dielectric layer 206 . This will be demonstrated by the fabrication process for fabricating such semiconductor element 200 . Certain steps of the fabrication process are illustrated in FIGS. 3 - 6 . As shown in a schematic cross-sectional view of FIG. 3 , the element 200 starts from a conventional back-end-of-line (BEOL) structure, comprising a substrate 202 , a first dielectric layer 204 disposed on the substrate 202 , and one or more (e.g., two) additional dielectric layers
205 a and 205 b disposed above the first dielectric layer 204 . Each of the three
dielectric layers
204 , 205 a and 205 b may comprise a non-low-k dielectric material, e.g., silicon oxide. In other embodiments, the
layers
204 , 205 a , 205 b can comprise a single dielectric layer. As explained above, a plurality of underlying conductive features 212 can be buried in the first dielectric layer 204 . A plurality of conductive contact pads 216 can be at least partially embedded in the top dielectric layer 205 b . In the middle dielectric layer 205 a , a plurality of via portions 214 extend through the thickness of the layer, each connecting to a contact pad 216 above and to an underlying conductive feature 212 below. In some embodiments, the contact pads 216 and the intervening via portions 214 may be formed by a dual damascene process. In such a case, the dielectric layers
205 a and 205 b can comprise one dielectric layer, and each conductive pad 216 and the connected via portion 214 underneath are formed together without a separation layer between them. The top surface 210 a comprises the dielectric material 205 b and conductive contact pads 216 . In some embodiments, the semiconductor element 200 comprises more than one underlying conductive layers having extended underlying conductive features. For example, when two underlying conductive layers are disposed in the semiconductor element 200 with contact pads in a top interconnecting bonding layer, there may exist five dielectric layers, including the layers for via portions connecting the conductive features of the different conductive layers.
As shown in FIG. 3 , in each dielectric layer, e.g., silicon oxide (SiO 2 ), the conductive features are surrounded by a thin conductive barrier layer and in various embodiments another seeding layer. In the first dielectric layer 204 , the underlying conductive features 212 are surrounded by a thin conductive barrier layer 222 at the sidewalls and the bottom surface. In the middle dielectric layer 205 a , the intervening via portions 214 are surrounded by a thin conductive barrier layer portion 224 a at its sidewalls and a first thin conductive barrier layer portion 226 at its bottom surface. The thin barrier layer portions
224 a and 226 are deposited together. As such they are connected forming a continuous barrier layer. In the top dielectric layer 205 b , the conductive contact pads 216 are surrounded by a thin barrier layer portion 224 b at its sidewalls and a second thin conductive barrier layer portion 228 at its bottom surface. Likewise, the thin barrier layer portions
224 b and 228 are connected forming a continuous barrier layer. As disclosed previously, the conductive barrier layer portions
224 a and 226 , surrounding the via portions 214 and the conductive barrier layer portions
224 b and 228 surrounding the contact pads 216 may comprise one or more of the following materials, cobalt (Co), ruthenium (Ru), tantalum (Ta), tantalum nitride (TaN), TaN/Ta multilayer, indium oxide (In2O3), tungsten nitride (WN), titanium (Ti), titanium tungsten (TiW), titanium zirconium (NiZr), titanium nitride (TiN), TiN/Ti multilayer, and various alloys and combinations formed by the above listed materials. These thin conductive barrier layers can be provided to impede the diffusion of the conductive material into the dielectric material. In some embodiments, another seeding layer is disposed between the barrier layer and the surrounded
CLAIMS
Claims ( 63 )
1 . An element comprising:
a substrate; an interconnect structure over the substrate, the interconnect structure having at least one conductor at least partially embedded in a dielectric material, the dielectric material comprising a first dielectric layer and a second dielectric layer disposed on the first dielectric layer; a first dielectric barrier layer disposed on the at least one conductor and between the first dielectric layer and the second dielectric layer; and a second conductive barrier layer disposed on the first dielectric barrier layer.
2 . The element of claim 1 , wherein the at least one conductor is completely buried in the dielectric material.
3 . The element of claim 2 , wherein each of the at least one conductor comprises a contact pad, the contact pad forming part of a hybrid bonding surface.
4 . The element of claim 3 , wherein each of the conductor further comprises a via portion connected to the contact pad.
5 . The element of claim 1 , wherein the second dielectric layer comprises a low-k dielectric material.
6 . (canceled)
7 . An element comprising:
an interconnect structure having an upper hybrid bonding surface; a contact pad extending at least partially through the interconnect structure; a dielectric barrier layer disposed on and covering entire sidewalls of the contact pad; and a low-k dielectric layer disposed about the contact pad and the dielectric barrier layer.
8 . The element of claim 7 , wherein the contact pad is connected to an underlying conductive feature with a first conductive barrier layer disposed between the contact pad and the underlying conductive feature.
9 . The element of claim 8 , wherein the contact pad is connected to the underlying conductive feature by way of an intervening via portion.
10 . The element of claim 9 , wherein a second conductive barrier layer is disposed between the contact pad and the intervening via portion.
11 . The element of claim 10 , wherein the low-k dielectric layer extends to a depth covering the second conductive barrier layer, and wherein the dielectric barrier layer is disposed on and covers entire sidewalls formed by the contact pad and edges of the second conductive barrier layer.
12 . The element of claim 10 , wherein the low-k dielectric layer extends to a depth covering a partial thickness of the underlying conductive feature, and wherein the dielectric barrier layer is disposed on and covers entire sidewalls formed by the contact pad, the intervening via portion and the partial thickness of the underlying conductive feature.
13 . The element of claim 8 , wherein the underlying conductive feature is embedded in a first dielectric layer, and wherein the dielectric barrier layer extends between the low-k dielectric layer and the first dielectric layer.
14 . The element of claim 13 , wherein the dielectric barrier layer disposed on each sidewall has a corner.
15 . The element of claim 13 , wherein an approximately right angle turn is formed in the dielectric barrier layer between each sidewall and an interface between the low-k dielectric layer and the first dielectric layer.
16 . The element of claim 9 , wherein the contact pad and the intervening via portion are formed uniformly.
17 . (canceled)
18 . The element of claim 8 , wherein the contact pad directly connects to the underlying conductive feature without an intervening via portion.
19 . The element of claim 7 , further comprising an upper dielectric layer disposed on the low-k dielectric layer, the upper dielectric layer forming at least part of the upper hybrid bonding surface.
20 . (canceled)
21 . (canceled)
22 . (canceled)
23 . (canceled)
24 . (canceled)
25 . (canceled)
26 . A bonded structure comprising the element of claim 7 and a second element comprising a third dielectric layer and a second contact pad at least partially embedded in the third dielectric layer, wherein the low-k dielectric layer is directly bonded to the third dielectric layer without an adhesive and the contact pad is directly bonded to the second contact pad without an adhesive.
27 . (canceled)
28 . A device comprising:
a substrate; an interconnect structure disposed on the substrate, the interconnect structure having an upper hybrid bonding surface, the interconnect structure comprising:
a first dielectric layer disposed on the substrate;
a plurality of conductors at least partially embedded in the interconnect structure;
a dielectric barrier layer having a first portion disposed on and covering at least a portion of sidewalls of the plurality of the conductors;
a second dielectric layer disposed about the first portion of the dielectric barrier layer; and
wherein a second portion of the dielectric barrier layer extends between the first dielectric layer and second dielectric layer, the second portion of the dielectric barrier layer is angled relative to the first portion of the dielectric barrier layer.
29 . The device of claim 28 , wherein the interconnect structure further comprising a conductive barrier layer disposed on the entire dielectric barrier layer.
30 . (canceled)
31 . (canceled)
32 . (canceled)
33 . (canceled)
34 . (canceled)
35 . (canceled)
36 . (canceled)
37 . (canceled)
38 . (canceled)
39 . (canceled)
40 . (canceled)
41 . (canceled)
42 . (canceled)
43 . (canceled)
44 . (canceled)
45 . (canceled)
46 . (canceled)
47 . (canceled)
48 . (canceled)
49 . (canceled)
50 . (canceled)
51 . (canceled)
52 . (canceled)
53 . (canceled)
54 . (canceled)
55 . (canceled)
56 . (canceled)
57 . (canceled)
58 . (canceled)
59 . (canceled)
60 . (canceled)
61 . (canceled)
62 . (canceled)
63 . (canceled)
US18/194,544
2023-03-31
2023-03-31
Semiconductor element with bonding layer having low-k dielectric material
Pending
US20240332227A1
( en )
Priority Applications (3)
Application Number
Priority Date
Filing Date
Title
US18/194,544
US20240332227A1
( en )
2023-03-31
2023-03-31
Semiconductor element with bonding layer having low-k dielectric material
PCT/US2024/021526
WO2024206337A1
( en )
2023-03-31
2024-03-26
Semiconductor element with bonding layer having low-k dielectric material
TW113111536A
TW202445815A
( en )
2023-03-31
2024-03-27
Semiconductor element with bonding layer having low-k dielectric material
Applications Claiming Priority (1)
Application Number
Priority Date
Filing Date
Title
US18/194,544
US20240332227A1
( en )
2023-03-31
2023-03-31
Semiconductor element with bonding layer having low-k dielectric material
Publications (1)
Publication Number
Publication Date
US20240332227A1
true
US20240332227A1 ( en )
2024-10-03
Family
ID=92897023
Family Applications (1)
Application Number
Title
Priority Date
Filing Date
US18/194,544
Pending
US20240332227A1
( en )
2023-03-31
2023-03-31
Semiconductor element with bonding layer having low-k dielectric material
Country Status (3)
Country
Link
US
( 1 )
US20240332227A1
( en )
TW
( 1 )
TW202445815A
( en )
WO
( 1 )
WO2024206337A1
( en )
Cited By (46)
* Cited by examiner, â Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
US20230299123A1
( en )
*
2022-03-18
2023-09-21
Intel Corporation
Inductors for hybrid bonding interconnect architectures
US12218107B2
( en )
2019-12-23
2025-02-04
Adeia Semiconductor Bonding Technologies Inc.
Electrical redundancy for bonded structures
US12255176B2
( en )
2019-11-07
2025-03-18
Adeia Semiconductor Technologies Llc
Scalable architecture for reduced cycles across SOC
US12266650B2
( en )
2016-05-19
2025-04-01
Adeia Semiconductor Bonding Technologies Inc.
Stacked dies and methods for forming bonded structures
US12266640B2
( en )
2018-07-06
2025-04-01
Adeia Semiconductor Bonding Technologies Inc.
Molded direct bonded and interconnected stack
US12272677B2
( en )
2019-06-26
2025-04-08
Adeia Semiconductor Bonding Technologies Inc.
Direct bonded stack structures for increased reliability and improved yield in microelectronics
US12272730B2
( en )
2018-03-29
2025-04-08
Adeia Semiconductor Inc.
Transistor level interconnection methodologies utilizing 3D interconnects
US12300661B2
( en )
2020-03-31
2025-05-13
Adeia Semiconductor Bonding Technologies Inc.
Reliable hybrid bonded apparatus
US12300634B2
( en )
2021-08-02
2025-05-13
Adeia Semiconductor Bonding Technologies Inc.
Protective semiconductor elements for bonded structures
US12300662B2
( en )
2018-04-20
2025-05-13
Adeia Semiconductor Bonding Technologies Inc.
DBI to SI bonding for simplified handle wafer
US12308332B2
( en )
2019-12-23
2025-05-20
Adeia Semiconductor Bonding Technologies Inc.
Circuitry for electrical redundancy in bonded structures
US12322650B2
( en )
2017-10-06
2025-06-03
Adeia Semiconductor Bonding Technologies Inc.
Diffusion barrier for interconnects
US12322718B2
( en )
2020-09-04
2025-06-03
Adeia Semiconductor Bonding Technologies Inc.
Bonded structure with interconnect structure
US12322667B2
( en )
2017-03-21
2025-06-03
Adeia Semiconductor Bonding Technologies Inc.
Seal for microelectronic assembly
US12341025B2
( en )
2018-07-06
2025-06-24
Adeia Semiconductor Bonding Technologies Inc.
Microelectronic assemblies
US12347820B2
( en )
2018-05-15
2025-07-01
Adeia Semiconductor Bonding Technologies Inc.
Stacked devices and methods of fabrication
US12374656B2
( en )
2017-06-15
2025-07-29
Adeia Semiconductor Bonding Technologies Inc.
Multi-chip modules formed using wafer-level processing of a reconstituted wafer
US12374641B2
( en )
2019-06-12
2025-07-29
Adeia Semiconductor Bonding Technologies Inc.
Sealed bonded structures and methods for forming the same
US12374556B2
( en )
2016-12-28
2025-07-29
Adeia Semiconductor Bonding Technologies Inc.
Processing stacked substrates
US12381128B2
( en )
2020-12-28
2025-08-05
Adeia Semiconductor Bonding Technologies Inc.
Structures with through-substrate vias and methods for forming the same
US12381173B2
( en )
2017-09-24
2025-08-05
Adeia Semiconductor Bonding Technologies Inc.
Direct hybrid bonding of substrates having microelectronic components with different profiles and/or pitches at the bonding interface
US12381168B2
( en )
2015-08-25
2025-08-05
Adeia Semiconductor Bonding Technologies Inc.
Conductive barrier direct hybrid bonding
US12406959B2
( en )
2018-07-26
2025-09-02
Adeia Semiconductor Bonding Technologies Inc.
Post CMP processing for hybrid bonding
US12406975B2
( en )
2018-02-15
2025-09-02
Adeia Semiconductor Bonding Technologies Inc.
Techniques for processing devices
US12417950B2
( en )
2019-04-22
2025-09-16
Adeia Semiconductor Bonding Technologies Inc.
Mitigating surface damage of probe pads in preparation for direct bonding of a substrate
US12431460B2
( en )
2017-04-21
2025-09-30
Adeia Semiconductor Bonding Technologies Inc.
Die processing
US12438129B2
( en )
2012-08-30
2025-10-07
Adela Semiconductor Bonding Technologies Inc.
Heterogeneous annealing method and device
US12451445B2
( en )
2019-04-12
2025-10-21
Adeia Semiconductor Bonding Technologies Inc.
Protective elements for bonded structures
US12451439B2
( en )
2019-04-12
2025-10-21
Adeia Semiconductor Bonding Technologies Inc.
Bonded structure including an obstructive element directly bonded to a semiconductor element without an adhesive
US12456662B2
( en )
2020-12-28
2025-10-28
Adeia Semiconductor Bonding Technologies Inc.
Structures with through-substrate vias and methods for forming the same
US12482776B2
( en )
2018-06-13
2025-11-25
Adeia Semiconductor Bonding Technologies Inc.
Metal pads over TSV
US12506114B2
( en )
2022-12-29
2025-12-23
Adeia Semiconductor Bonding Technologies Inc.
Directly bonded metal structures having aluminum features and methods of preparing same
US12525572B2
( en )
2021-03-31
2026-01-13
Adeia Semiconductor Bonding Technologies Inc.
Direct bonding and debonding of carrier
US12543577B2
( en )
2021-09-24
2026-02-03
Adeia Semiconductor Bonding Technologies Inc.
Bonded structure with active interposer
US12543568B2
( en )
2021-12-20
2026-02-03
Adeia Semiconductor Bonding Technologies Inc.
Thermoelectric cooling for die packages
US12550799B2
( en )
2021-03-31
2026-02-10
Adeia Semiconductor Bonding Technologies Inc.
Direct bonding methods and structures
US12545010B2
( en )
2022-12-29
2026-02-10
Adeia Semiconductor Bonding Technologies Inc.
Directly bonded metal structures having oxide layers therein
US12557615B2
( en )
2021-12-13
2026-02-17
Adeia Semiconductor Technologies Llc
Methods for bonding semiconductor elements
US12564086B2
( en )
2016-10-27
2026-02-24
Adeia Semiconductor Technologies Llc
Structures for low temperature bonding using nanoparticles
US12563749B2
( en )
2021-10-28
2026-02-24
Adeia Semiconductor Bonding Technologies Inc
Stacked electronic devices
US12591005B2
( en )
2022-05-23
2026-03-31
Adeia Semiconductor Bonding Technologies Inc.
Testing elements for bonded structures
US12598962B2
( en )
2023-03-14
2026-04-07
Adeia Semiconductor Bonding Technologies Inc.
System and method for bonding transparent conductor substrates
US12604771B2
( en )
2021-10-28
2026-04-14
Adeia Semiconductor Bonding Technologies Inc.
Direct bonding methods and structures
US12616050B2
( en )
2018-08-31
2026-04-28
Adeia Semiconductor Bonding Technologie
Bonded structure including a first microelectronic device direct hybrid bonded to a second microelectronic device
US12622307B2
( en )
2021-12-23
2026-05-05
Adeia Semiconductor Bonding Technologies Inc.
Controlled grain growth for bonding and bonded structure with controlled grain growth
TWI925316B
( en )
2024-10-30
2026-05-11
財åæ³äººå·¥æ¥æè¡ç 究é¢
Stacked substrate structure and manufacturing method thereof
Citations (2)
* Cited by examiner, â Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
US20140117546A1
( en )
*
2012-06-05
2014-05-01
Taiwan Semiconductor Manufacturing Company, Ltd.
Hybrid bonding mechanisms for semiconductor wafers
US20190385963A1
( en )
*
2018-06-15
2019-12-19
Taiwan Semiconductor Manufacturing Co., Ltd.
Die structure, die stack structure and method of fabricating the same
Family Cites Families (5)
* Cited by examiner, â Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
US8710660B2
( en )
*
2012-07-20
2014-04-29
Taiwan Semiconductor Manufacturing Company, Ltd.
Hybrid interconnect scheme including aluminum metal line in low-k dielectric
US9659856B2
( en )
*
2014-10-24
2017-05-23
Taiwan Semiconductor Manufacturing Company, Ltd.
Two step metallization formation
US9953941B2
( en )
*
2015-08-25
2018-04-24
Invensas Bonding Technologies, Inc.
Conductive barrier direct hybrid bonding
US11824079B2
( en )
*
2021-02-23
2023-11-21
Microchip Technology Incorporated
Thin-film resistor (TFR) having a TFR element providing a diffusion barrier for underlying TFR heads
US11605558B2
( en )
*
2021-03-26
2023-03-14
Taiwan Semiconductor Manufacturing Co., Ltd.
Integrated circuit interconnect structure having discontinuous barrier layer and air gap
2023
2023-03-31
US
US18/194,544
patent/US20240332227A1/en
active
Pending
2024
2024-03-26
WO
PCT/US2024/021526
patent/WO2024206337A1/en
not_active
Ceased
2024-03-27
TW
TW113111536A
patent/TW202445815A/en
unknown
Patent Citations (2)
* Cited by examiner, â Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
US20140117546A1
( en )
*
2012-06-05
2014-05-01
Taiwan Semiconductor Manufacturing Company, Ltd.
Hybrid bonding mechanisms for semiconductor wafers
US20190385963A1
( en )
*
2018-06-15
2019-12-19
Taiwan Semiconductor Manufacturing Co., Ltd.
Die structure, die stack structure and method of fabricating the same
Cited By (50)
* Cited by examiner, â Cited by third party
Publication number
Priority date
Publication date
Assignee
Title
US12438129B2
( en )
2012-08-30
2025-10-07
Adela Semiconductor Bonding Technologies Inc.
Heterogeneous annealing method and device
US12381168B2
( en )
2015-08-25
2025-08-05
Adeia Semiconductor Bonding Technologies Inc.
Conductive barrier direct hybrid bonding
US12266650B2
( en )
2016-05-19
2025-04-01
Adeia Semiconductor Bonding Technologies Inc.
Stacked dies and methods for forming bonded structures
US12564086B2
( en )
2016-10-27
2026-02-24
Adeia Semiconductor Technologies Llc
Structures for low temperature bonding using nanoparticles
US12374556B2
( en )
2016-12-28
2025-07-29
Adeia Semiconductor Bonding Technologies Inc.
Processing stacked substrates
US12322667B2
( en )
2017-03-21
2025-06-03
Adeia Semiconductor Bonding Technologies Inc.
Seal for microelectronic assembly
US12381119B2
( en )
2017-03-21
2025-08-05
Adeia Semiconductor Bonding Technologies Inc.
Seal for microelectronic assembly
US12431460B2
( en )
2017-04-21
2025-09-30
Adeia Semiconductor Bonding Technologies Inc.
Die processing
US12374656B2
( en )
2017-06-15
2025-07-29
Adeia Semiconductor Bonding Technologies Inc.
Multi-chip modules formed using wafer-level processing of a reconstituted wafer
US12381173B2
( en )
2017-09-24
2025-08-05
Adeia Semiconductor Bonding Technologies Inc.
Direct hybrid bonding of substrates having microelectronic components with different profiles and/or pitches at the bonding interface
US12322650B2
( en )
2017-10-06
2025-06-03
Adeia Semiconductor Bonding Technologies Inc.
Diffusion barrier for interconnects
US12406975B2
( en )
2018-02-15
2025-09-02
Adeia Semiconductor Bonding Technologies Inc.
Techniques for processing devices
US12272730B2
( en )
2018-03-29
2025-04-08
Adeia Semiconductor Inc.
Transistor level interconnection methodologies utilizing 3D interconnects
US12300662B2
( en )
2018-04-20
2025-05-13
Adeia Semiconductor Bonding Technologies Inc.
DBI to SI bonding for simplified handle wafer
US12438122B2
( en )
2018-04-20
2025-10-07
Adeia Semiconductor Bonding Technologies Inc.
DBI to Si bonding for simplified handle wafer
US12401011B2
( en )
2018-05-15
2025-08-26
Adeia Semiconductor Bonding Technologies Inc.
Stacked devices and methods of fabrication
US12347820B2
( en )
2018-05-15
2025-07-01
Adeia Semiconductor Bonding Technologies Inc.
Stacked devices and methods of fabrication
US12482776B2
( en )
2018-06-13
2025-11-25
Adeia Semiconductor Bonding Technologies Inc.
Metal pads over TSV
US12341025B2
( en )
2018-07-06
2025-06-24
Adeia Semiconductor Bonding Technologies Inc.
Microelectronic assemblies
US12266640B2
( en )
2018-07-06
2025-04-01
Adeia Semiconductor Bonding Technologies Inc.
Molded direct bonded and interconnected stack
US12406959B2
( en )
2018-07-26
2025-09-02
Adeia Semiconductor Bonding Technologies Inc.
Post CMP processing for hybrid bonding
US12616050B2
( en )
2018-08-31
2026-04-28
Adeia Semiconductor Bonding Technologie
Bonded structure including a first microelectronic device direct hybrid bonded to a second microelectronic device
US12451439B2
( en )
2019-04-12
2025-10-21
Adeia Semiconductor Bonding Technologies Inc.
Bonded structure including an obstructive element directly bonded to a semiconductor element without an adhesive
US12451445B2
( en )
2019-04-12
2025-10-21
Adeia Semiconductor Bonding Technologies Inc.
Protective elements for bonded structures
US12417950B2
( en )
2019-04-22
2025-09-16
Adeia Semiconductor Bonding Technologies Inc.
Mitigating surface damage of probe pads in preparation for direct bonding of a substrate
US12374641B2
( en )
2019-06-12
2025-07-29
Adeia Semiconductor Bonding Technologies Inc.
Sealed bonded structures and methods for forming the same
US12272677B2
( en )
2019-06-26
2025-04-08
Adeia Semiconductor Bonding Technologies Inc.
Direct bonded stack structures for increased reliability and improved yield in microelectronics
US12255176B2
( en )
2019-11-07
2025-03-18
Adeia Semiconductor Technologies Llc
Scalable architecture for reduced cycles across SOC
US12218107B2
( en )
2019-12-23
2025-02-04
Adeia Semiconductor Bonding Technologies Inc.
Electrical redundancy for bonded structures
US12308332B2
( en )
2019-12-23
2025-05-20
Adeia Semiconductor Bonding Technologies Inc.
Circuitry for electrical redundancy in bonded structures
US12431449B2
( en )
2019-12-23
2025-09-30
Adeia Semiconductor Bonding Technologies Inc.
Circuitry for electrical redundancy in bonded structures
US12300661B2
( en )
2020-03-31
2025-05-13
Adeia Semiconductor Bonding Technologies Inc.
Reliable hybrid bonded apparatus
US12322718B2
( en )
2020-09-04
2025-06-03
Adeia Semiconductor Bonding Technologies Inc.
Bonded structure with interconnect structure
US12456662B2
( en )
2020-12-28
2025-10-28
Adeia Semiconductor Bonding Technologies Inc.
Structures with through-substrate vias and methods for forming the same
US12381128B2
( en )
2020-12-28
2025-08-05
Adeia Semiconductor Bonding Technologies Inc.
Structures with through-substrate vias and methods for forming the same
US12525572B2
( en )
2021-03-31
2026-01-13
Adeia Semiconductor Bonding Technologies Inc.
Direct bonding and debonding of carrier
US12550799B2
( en )
2021-03-31
2026-02-10
Adeia Semiconductor Bonding Technologies Inc.
Direct bonding methods and structures
US12300634B2
( en )
2021-08-02
2025-05-13
Adeia Semiconductor Bonding Technologies Inc.
Protective semiconductor elements for bonded structures
US12543577B2
( en )
2021-09-24
2026-02-03
Adeia Semiconductor Bonding Technologies Inc.
Bonded structure with active interposer
US12604771B2
( en )
2021-10-28
2026-04-14
Adeia Semiconductor Bonding Technologies Inc.
Direct bonding methods and structures
US12563749B2
( en )
2021-10-28
2026-02-24
Adeia Semiconductor Bonding Technologies Inc
Stacked electronic devices
US12557615B2
( en )
2021-12-13
2026-02-17
Adeia Semiconductor Technologies Llc
Methods for bonding semiconductor elements
US12543568B2
( en )
2021-12-20
2026-02-03
Adeia Semiconductor Bonding Technologies Inc.
Thermoelectric cooling for die packages
US12622307B2
( en )
2021-12-23
2026-05-05
Adeia Semiconductor Bonding Technologies Inc.
Controlled grain growth for bonding and bonded structure with controlled grain growth
US20230299123A1
( en )
*
2022-03-18
2023-09-21
Intel Corporation
Inductors for hybrid bonding interconnect architectures
US12591005B2
( en )
2022-05-23
2026-03-31
Adeia Semiconductor Bonding Technologies Inc.
Testing elements for bonded structures
US12545010B2
( en )
2022-12-29
2026-02-10
Adeia Semiconductor Bonding Technologies Inc.
Directly bonded metal structures having oxide layers therein
US12506114B2
( en )
2022-12-29
2025-12-23
Adeia Semiconductor Bonding Technologies Inc.
Directly bonded metal structures having aluminum features and methods of preparing same
US12598962B2
( en )
2023-03-14
2026-04-07
Adeia Semiconductor Bonding Technologies Inc.
System and method for bonding transparent conductor substrates
TWI925316B
( en )
2024-10-30
2026-05-11
財åæ³äººå·¥æ¥æè¡ç 究é¢
Stacked substrate structure and manufacturing method thereof
Also Published As
Publication number
Publication date
TW202445815A
( en )
2024-11-16
WO2024206337A1
( en )
2024-10-03
Similar Documents
Publication
Publication Date
Title
WO2024206337A1
( en )
2024-10-03
Semiconductor element with bonding layer having low-k dielectric material
US20240186268A1
( en )
2024-06-06
Directly bonded structure with frame structure
US12545010B2
( en )
2026-02-10
Directly bonded metal structures having oxide layers therein
US20240387419A1
( en )
2024-11-21
Direct hybrid bond pad having tapered sidewall
JP2025542482A
( en )
2025-12-25
Direct bonded metal structure with aluminum features and method of making same
US20250218903A1
( en )
2025-07-03
Via reveal processing and structures
TWI602273B
( en )
2017-10-11
Semiconductor device
CN101789417B
( en )
2013-03-20
Through-silicon via sidewall isolation structure
TWI497591B
( en )
2015-08-21
Structure and method for fabricating interconnect structure with self-aligning dielectric cap
US20090212438A1
( en )
2009-08-27
Integrated circuit device comprising conductive vias and method of making the same
<a href="/pa