ABSTRACT
Abstract
A semiconductor structure has a frontside and a backside. The semiconductor structure includes an isolation structure at the backside; one or more transistors at the frontside, wherein the one or more transistors have source/drain epitaxial features; two metal plugs through the isolation structure and contacting two of the source/drain electrodes from the backside; and a dielectric liner filling a space between the two metal plugs, wherein the dielectric liner partially or fully surrounds an air gap between the two metal plugs.
Description
PRIORITY
This is a continuation application of U.S. application Ser. No. 17/873,903, filed Jul. 26, 2022, which is a divisional application of U.S. application Ser. No. 16/888,217, filed May 29, 2020, each of which is herein incorporated by reference in its entirety.
BACKGROUND
The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs. Hence, semiconductor manufacturing processes need continued improvements. One area of improvements is how to reduce stray capacitance among features of field effect transistors.
It is generally desirable to reduce stray capacitance between metal features, such as metal lines and/or metal plugs, in order to increase switching speed, decrease switching power consumption, and/or decrease coupling noise of the circuits. Certain low-k materials have been suggested as insulator materials to reduce stray capacitance. However, as semiconductor technology progresses to smaller geometries, the distances between the metal features are further reduced, which increases stray capacitance. Therefore, although existing approaches in semiconductor fabrication have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.
BRIEF DESCRIPTION OF THE DRAWINGS
The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
FIGS. 1 A and 1 B show a flow chart of a method of forming a semiconductor device with air gap on a backside of a wafer, according to various aspects of the present disclosure.
FIGS. 2 A and 2 B illustrate a perspective view and a cross-sectional view of a portion of a semiconductor device, according to some embodiments, in an intermediate step of fabrication according to an embodiment of the method of FIGS. 1 A and 1 B .
FIG. 2 C illustrates a perspective view of a portion of the semiconductor device in FIG. 2 A , according to some embodiments.
FIGS. 2 D and 2 E illustrate cross-sectional views of a portion of the semiconductor device in FIG. 2 C along the A-A line and the B-B line in FIG. 2 C , respectively, according to an embodiment.
FIGS. 2 D- 1 and 2 E- 1 illustrate cross-sectional views of a portion of the semiconductor device in FIG. 2 C along the A-A line and the B-B line in FIG. 2 C , respectively, according to another embodiment.
FIG. 3 illustrates a cross-sectional view of a portion of the semiconductor device of FIG. 2 A in an intermediate step of fabrication according to an embodiment of the method of FIGS. 1 A and 1 B .
FIGS. 4 , 5 A, 6 A, 7 A, 8 A, 9 A, 10 A, and 11 A illustrate perspective views of a portion of a semiconductor device, according to some embodiments, in intermediate steps of fabrication according to an embodiment of the method of FIGS. 1 A and 1 B .
FIGS. 5 B, 6 B, 7 B, 8 B, 9 B, 10 B, 11 B, and 11 B- 1 illustrate cross-sectional views of a portion of a semiconductor device along the Cut-1 line in FIGS. 5 A, 6 A, 7 A, 8 A, 9 A, 10 A, and 11 A respectively, according to some embodiments.
FIG. 10 C illustrates a cross-sectional view of a portion of a semiconductor device along the Cut-2 line in FIG. 10 A , according to some embodiments.
DETAILED DESCRIPTION
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as âbeneath,â âbelow,â âlower,â âabove,â âupperâ and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Still further, when a number or a range of numbers is described with âabout,â âapproximate,â and the like, the term encompasses numbers that are within certain variations (such as +/â10% or other variations) of the number described, in accordance with the knowledge of the skilled in the art in view of the specific technology disclosed herein, unless otherwise specified. For example, the term âabout 5 nmâ may encompass the dimension range from 4.5 nm to 5.5 nm, 4.0 nm to 5.0 nm, etc.
The present disclosure generally relates to a semiconductor fabrication process and the structure thereof. More particularly, the present disclosure relates to fabricating dielectric layer(s) and metal layer(s) on a backside of a structure (such as a wafer) where devices (such as transistors) have been fabricated on a frontside of the structure. As semiconductor technology progresses to smaller geometries, it is desirable to move some of the connectivity layers to the backside of a wafer, such as power rails connecting to transistors' source and/or drain (source/drain) features. This will free up some area at the frontside of the wafer and further increase the device integration. This also presents new challenges. One of the challenges is how to deal with the stray capacitance (or coupling capacitance) between the conductors on the backside, such as metal plugs that reach into the source/drain features from the backside. The small distance between those conductors could mean large stray capacitance if not dealt with properly. According to some embodiments of the present disclosure, the backside dielectric layer(s) are provided with air gaps for reducing stray capacitance and increasing isolation between conductors. These and other aspects of the present disclosure are further described by referring to the accompanied figures.
FIGS. 1 A and 1 B are a flow chart of a method 10 for fabricating a semiconductor device according to various aspects of the present disclosure. Additional processing is contemplated by the present disclosure. Additional operations can be provided before, during, and after method 10 , and some of the operations described can be moved, replaced, or eliminated for additional embodiments of method 10 .
Method 10 is described below in conjunction with FIG. 2 A through FIG. 11 B- 1 that illustrate various perspective and cross-sectional views of a semiconductor device (or a semiconductor structure) 100 at various steps of fabrication according to the method 10 , in accordance with some embodiments. In some embodiments, the device 100 is a portion of an IC chip, a system on chip (SoC), or portion thereof, that includes various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), FinFET, nanosheet FETs, nanowire FETs, other types of multi-gate FETs, metal-oxide semiconductor field effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, memory devices, other suitable components, or combinations thereof. FIGS. 2 A through 11 B- 1 have been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in the device 100 , and some of the features described below can be replaced, modified, or eliminated in other embodiments of the device 100 .
At operation 12 , the method 10 ( FIG. 1 A ) provides a structure (or a workpiece) of the device 100 , an embodiment of which is illustrated in FIGS. 2 A and 2 B . Particularly, FIG. 2 A illustrates a perspective view of a portion of the device 100 and FIG. 2 B illustrates a cross-sectional view of a portion of the device 100 , according to an embodiment. The device 100 includes a substrate 102 , a device layer 152 over the substrate 102 , and an interconnect structure (or a multilayer interconnect) 162 over the device layer 152 . The device 100 may include other layers or features not shown in FIG. 2 A , such as a passivation layer over the interconnect structure 162 . The substrate 102 is at a backside of the device 100 , and the interconnect structure 162 is at a frontside of device 100 . In other words, the substrate 102 , the device layer 152 , and the interconnect structure 162 are disposed one over another from the backside to the frontside of the device 100 .
The substrate 102 is a bulk silicon (Si) substrate in the present embodiment, such as a silicon wafer. In alternative embodiments, the substrate 102 includes other elementary semiconductors such as germanium (Ge); a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP); or an alloy semiconductor, such as silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenic phosphide (GaAsP), and gallium indium phosphide (GaInP). In some embodiments, the substrate 102 may include silicon on insulator (SOI) substrate, be strained and/or stressed for performance enhancement, include epitaxial regions, doped regions, and/or include other suitable features and layers.
The device layer 152 includes semiconductor active regions (such as semiconductor fins), and various active devices (e.g., tran
PRIORITY
This is a continuation application of U.S. application Ser. No. 17/873,903, filed Jul. 26, 2022, which is a divisional application of U.S. application Ser. No. 16/888,217, filed May 29, 2020, each of which is herein incorporated by reference in its entirety.
BACKGROUND
The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs. Hence, semiconductor manufacturing processes need continued improvements. One area of improvements is how to reduce stray capacitance among features of field effect transistors.
It is generally desirable to reduce stray capacitance between metal features, such as metal lines and/or metal plugs, in order to increase switching speed, decrease switching power consumption, and/or decrease coupling noise of the circuits. Certain low-k materials have been suggested as insulator materials to reduce stray capacitance. However, as semiconductor technology progresses to smaller geometries, the distances between the metal features are further reduced, which increases stray capacitance. Therefore, although existing approaches in semiconductor fabrication have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.
BRIEF DESCRIPTION OF THE DRAWINGS
The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
FIGS. 1 A and 1 B show a flow chart of a method of forming a semiconductor device with air gap on a backside of a wafer, according to various aspects of the present disclosure.
FIGS. 2 A and 2 B illustrate a perspective view and a cross-sectional view of a portion of a semiconductor device, according to some embodiments, in an intermediate step of fabrication according to an embodiment of the method of FIGS. 1 A and 1 B .
FIG. 2 C illustrates a perspective view of a portion of the semiconductor device in FIG. 2 A , according to some embodiments.
FIGS. 2 D and 2 E illustrate cross-sectional views of a portion of the semiconductor device in FIG. 2 C along the A-A line and the B-B line in FIG. 2 C , respectively, according to an embodiment.
FIGS. 2 D- 1 and 2 E- 1 illustrate cross-sectional views of a portion of the semiconductor device in FIG. 2 C along the A-A line and the B-B line in FIG. 2 C , respectively, according to another embodiment.
FIG. 3 illustrates a cross-sectional view of a portion of the semiconductor device of FIG. 2 A in an intermediate step of fabrication according to an embodiment of the method of FIGS. 1 A and 1 B .
FIGS. 4 , 5 A, 6 A, 7 A, 8 A, 9 A, 10 A, and 11 A illustrate perspective views of a portion of a semiconductor device, according to some embodiments, in intermediate steps of fabrication according to an embodiment of the method of FIGS. 1 A and 1 B .
FIGS. 5 B, 6 B, 7 B, 8 B, 9 B, 10 B, 11 B, and 11 B- 1 illustrate cross-sectional views of a portion of a semiconductor device along the Cut-1 line in FIGS. 5 A, 6 A, 7 A, 8 A, 9 A, 10 A, and 11 A respectively, according to some embodiments.
FIG. 10 C illustrates a cross-sectional view of a portion of a semiconductor device along the Cut-2 line in FIG. 10 A , according to some embodiments.
DETAILED DESCRIPTION
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as âbeneath,â âbelow,â âlower,â âabove,â âupperâ and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Still further, when a number or a range of numbers is described with âabout,â âapproximate,â and the like, the term encompasses numbers that are within certain variations (such as +/â10% or other variations) of the number described, in accordance with the knowledge of the skilled in the art in view of the specific technology disclosed herein, unless otherwise specified. For example, the term âabout 5 nmâ may encompass the dimension range from 4.5 nm to 5.5 nm, 4.0 nm to 5.0 nm, etc.
The present disclosure generally relates to a semiconductor fabrication process and the structure thereof. More particularly, the present disclosure relates to fabricating dielectric layer(s) and metal layer(s) on a backside of a structure (such as a wafer) where devices (such as transistors) have been fabricated on a frontside of the structure. As semiconductor technology progresses to smaller geometries, it is desirable to move some of the connectivity layers to the backside of a wafer, such as power rails connecting to transistors' source and/or drain (source/drain) features. This will free up some area at the frontside of the wafer and further increase the device integration. This also presents new challenges. One of the challenges is how to deal with the stray capacitance (or coupling capacitance) between the conductors on the backside, such as metal plugs that reach into the source/drain features from the backside. The small distance between those conductors could mean large stray capacitance if not dealt with properly. According to some embodiments of the present disclosure, the backside dielectric layer(s) are provided with air gaps for reducing stray capacitance and increasing isolation between conductors. These and other aspects of the present disclosure are further described by referring to the accompanied figures.
FIGS. 1 A and 1 B are a flow chart of a method 10 for fabricating a semiconductor device according to various aspects of the present disclosure. Additional processing is contemplated by the present disclosure. Additional operations can be provided before, during, and after method 10 , and some of the operations described can be moved, replaced, or eliminated for additional embodiments of method 10 .
Method 10 is described below in conjunction with FIG. 2 A through FIG. 11 B- 1 that illustrate various perspective and cross-sectional views of a semiconductor device (or a semiconductor structure) 100 at various steps of fabrication according to the method 10 , in accordance with some embodiments. In some embodiments, the device 100 is a portion of an IC chip, a system on chip (SoC), or portion thereof, that includes various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), FinFET, nanosheet FETs, nanowire FETs, other types of multi-gate FETs, metal-oxide semiconductor field effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, memory devices, other suitable components, or combinations thereof. FIGS. 2 A through 11 B- 1 have been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in the device 100 , and some of the features described below can be replaced, modified, or eliminated in other embodiments of the device 100 .
At operation 12 , the method 10 ( FIG. 1 A ) provides a structure (or a workpiece) of the device 100 , an embodiment of which is illustrated in FIGS. 2 A and 2 B . Particularly, FIG. 2 A illustrates a perspective view of a portion of the device 100 and FIG. 2 B illustrates a cross-sectional view of a portion of the device 100 , according to an embodiment. The device 100 includes a substrate 102 , a device layer 152 over the substrate 102 , and an interconnect structure (or a multilayer interconnect) 162 over the device layer 152 . The device 100 may include other layers or features not shown in FIG. 2 A , such as a passivation layer over the interconnect structure 162 . The substrate 102 is at a backside of the device 100 , and the interconnect structure 162 is at a frontside of device 100 . In other words, the substrate 102 , the device layer 152 , and the interconnect structure 162 are disposed one over another from the backside to the frontside of the device 100 .
The substrate 102 is a bulk silicon (Si) substrate in the present embodiment, such as a silicon wafer. In alternative embodiments, the substrate 102 includes other elementary semiconductors such as germanium (Ge); a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP); or an alloy semiconductor, such as silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenic phosphide (GaAsP), and gallium indium phosphide (GaInP). In some embodiments, the substrate 102 may include silicon on insulator (SOI) substrate, be strained and/or stressed for performance enhancement, include epitaxial regions, doped regions, and/or include other suitable features and layers.
The device layer 152 includes semiconductor active regions (such as semiconductor fins), and various active devices (e.g., transistors) built in or on the semiconductor active regions. The device layer 152 may also include passive devices such as capacitors, resistors, and inductors. The device layer 152 further includes local interconnects, isolation structures, and other structures. In the embodiment shown in FIG. 2 B , the device layer 152 includes semiconductor fins (or fins) 103 that extend upwardly from the substrate 102 , epitaxial features 104 over the semiconductor fins 103 , and dielectric isolation features 154 between the semiconductor active regions. The epitaxial features 104 may be source or drain (S/D) electrodes of transistors. Thus, they are also referred to as S/D features 104 . The semiconductor fins 103 may include silicon or other suitable semiconductor materials such as silicon germanium. The device layer 152 also includes conductors 156 and 158 (such as local interconnects, vias, and/or plugs) that provide connectivity to the S/D electrodes of the transistors, as well as gate electrodes though not shown in this figure. Some of the conductors 158 are connected to the interconnect structure 162 . The conductors
156 and 158 may comprise copper, tungsten, ruthenium, cobalt, or other suitable materials.
The interconnect structure 162 is over the device layer 152 and includes conductors 166 (such as metal lines or metal wires and vias) embedded in one or more dielectric layers 164 . The conductors 166 provide connectivity to the devices in the device layer 152 . The conductors 166 may also provide power rails and ground planes for the device 100 . The conductors 166 may comprise copper, aluminum, or other suitable materials, and may be formed using single damascene process, dual damascene process, or other suitable processes. The dielectric layers 164 may comprise silicon nitride, silicon oxynitride, silicon nitride with oxygen (O) or carbon (C) elements, tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials.
FIG. 2 C illustrates a perspective view of a portion of the device 100 according to an embodiment, which includes a semiconductor fin 103 and a gate stack 118 . The fin 103 is oriented lengthwise generally along the âxâ direction, and the gate stack 118 is oriented lengthwise generally along the âyâ direction perpendicular to the âxâ direction. FIG. 2 D illustrates a cross-sectional view of a portion of the device 100 along the A-A line in FIG. 2 C according to an embodiment which is cut parallel to and through the fin 103 . FIG. 2 E illustrates a cross-sectional view of a portion of the device 100 along the B-B line in FIG. 2 C according to an embodiment, which is cut parallel to and through the gate stack 118 . The transistor illustrated in the embodiment of FIGS. 2 D and 2 E is a FinFET 101 a . FIGS. 2 D- 1 and 2 E- 1 illustrate cross-sectional views of a portion of the device 100 along the A-A line and the B-B line in FIG. 2 C , respectively, according to another embodiment, where the transistor is a gate-all-around (GAA) FET 101 b . The device 100 may include any number of fins 103 , any number of gate stacks 118 , any number of FinFETs and/or GAA FETs, and other types of devices, in various embodiments.
Referring to FIGS. 2 C- 2 E collectively, the device 100 includes the substrate 102 , over which the fin 103 and the gate stack 118 are formed. The device 100 includes an isolation structure 105 (which is part of the isolation structure 154 in FIG. 2 B ) for isolating the fin 103 from other active regions or fins. The fin 103 extends from the substrate 102 and above the isolation structure 105 . The gate stack 118 is disposed above the isolation structure 105 and on three sides of the fin 103 . The device 100 further includes gate spacers 108 on sidewalls of the gate stack 118 . The epitaxial S/D features 104 are disposed on top of the fin 103 and on both sides of the gate stack 118 .
The fin 103 may include one or more layers of semiconductor materials such as silicon or silicon germanium. The fin 103 may be patterned by any suitable method. For example, the fin 103 may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers, or mandrels, may then be used as a masking element for patterning the fin 103 . For example, the masking element may be used for etching recesses into semiconductor layers over or in the substrate 102 , leaving the fin 103 on the substrate 102 . The etching process may include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes. For example, a dry etching process may implement an oxygen-containing gas, a fluorine-containing gas (e.g., CF 4 , SF 6 , CH 2 F 2 , CHF 3 , and/or C 2 F 6 ), a chlorine-containing gas (e.g., Cl 2 , CHCl 3 , CCl 4 , and/or BCl 3 ), a bromine-containing gas (e.g., HBr and/or CHBr 3 ), an iodine-containing gas, other suitable gases and/or plasmas, and/or combinations thereof. For example, a wet etching process may comprise etching in diluted hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO 3 ), and/or acetic acid (CH 3 COOH); or other suitable wet etchant. Numerous other embodiments of methods to form the fin 103 may be suitable.
The S/D features 104 include epitaxially grown semiconductor materials such as epitaxially grown silicon, germanium, or silicon germanium. The S/D features 104 can be formed by any epitaxy processes including chemical vapor deposition (CVD) techniques (for example, vapor phase epitaxy and/or Ultra-High Vacuum CVD), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. The S/D features 104 may be doped with n-type dopants and/or p-type dopants. In some embodiments, for n-type transistors, the S/D features 104 include silicon and can be doped with carbon, phosphorous, arsenic, other n-type dopant, or combinations thereof (for example, forming Si:C epitaxial S/D features, Si:P epitaxial S/D features, or Si:C:P epitaxial S/D features). In some embodiments, for p-type transistors, the S/D features 104 include silicon germanium or germanium, and can be doped with boron, other p-type dopant, or combinations thereof (for example, forming Si:Ge:B epitaxial S/D features). The S/D features 104 may include multiple epitaxial semiconductor layers having different levels of dopant density. In some embodiments, annealing processes (e.g., rapid thermal annealing (RTA) and/or laser annealing) are performed to activate dopants in the epitaxial S/D features 104 .
The isolation structure 105 may include silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), fluoride-doped silicate glass (FSG), a low-k dielectric material, and/or other suitable insulating material. In an embodiment, the isolation structure 105 is formed by etching trenches in or over the substrate 102 (e.g., as part of the process of forming the fins 103 ), filling the trenches with an insulating material, and performing a chemical mechanical planarization (CMP) process and/or an etching back process to the insulating material, leaving the remaining insulating material as the isolation structure 105 . Other types of isolation structure may also be suitable, such as field oxide and LOCal Oxidation of Silicon (LOCOS). The isolation structure 105 may include a multi-layer structure, for example, having one or more liner layers (e.g., silicon nitride) on surfaces of the substrate 102 and the fin 103 and a main isolating layer (e.g., silicon dioxide) over the one or more liner layers.
In the present embodiment, the gate stack 118 includes a gate dielectric layer 120 and a gate electrode layer 122 over the gate dielectric layer 120 . The gate dielectric layer 120 may include a high-k dielectric material such as HfO 2 , HfSiO, HfSiO 4 , HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO x , ZrO, ZrO 2 , ZrSiO 2 , A 10 , AlSiO, Al 2 O 3 , TiO, TiO 2 , LaO, LaSiO, Ta 2 O 3 , Ta 2 O 5 , Y 2 O 3 , SrTiO 3 , BaZrO, BaTiO 3 (BTO), (Ba,Sr)TiO 3 (BST), Si 3 N 4 , hafnium dioxide-alumina (HfO 2 âAl 2 O 3 ) alloy, other suitable high-k dielectric material, or combinations thereof. High-k dielectric material generally refers to dielectric materials having a high dielectric constant, for example, greater than that of silicon oxide (kâ3.9). The gate dielectric layer 120 may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and/or other suitable methods. In the present embodiment, the gate stack 118 further includes an interfacial layer 106 between the gate dielectric layer 120 and the fin 103 . The interfacial layer 106 may include silicon dioxide, silicon oxynitride, or other suitable materials. In some embodiments, the gate electrode layer 122 includes an n-type or a p-type work function layer and a metal fill layer. For example, an n-type work function layer may comprise a metal with sufficiently low effective work function such as titanium, aluminum, tantalum carbide, tantalum carbide nitride, tantalum silicon nitride, or combinations thereof. For example, a p-type work function layer may comprise a metal with a sufficiently large effective work function, such as titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or combinations thereof. For example, a metal fill layer may include aluminum, tungsten, cobalt, copper, and/or other suitable materials. The gate electrode layer 122 may be formed by CVD, PVD, plating, and/or other suitable processes. Since the gate stack 118 includes a high-k dielectric layer and metal layer(s), it is also referred to as a high-k metal gate.
Each of the gate spacers 108 may be a single layer or multi-layer structure. In some embodiments, the spacers 108 include a dielectric material, such as silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), other dielectric material, or combination thereof. In an example, the spacers 108 are formed by deposition and etching (e.g., anisotropic etching) processes. In some embodiment, the gate spacers 108 include La 2 O 3 , Al 2 O 3 , SiOCN, SiOC, SiCN, SiO 2 , SiC, ZnO, ZrN, Zr 2 Al 3 O 9 , TiO 2 , TaO 2 , ZrO 2 , HfO 2 , Si 3 N 4 , Y 2 O 3 , AlON, TaCN, ZrSi, or other suitable material(s).
In the present embodiment, the device 100 further includes a gate cap 124 over the gate stack 118 . The gate cap 124 may include a material such as La 2 O 3 , Al 2 O 3 , SiOCN, SiOC, SiCN, SiO 2 , SiC, ZnO, ZrN, Zr 2 Al 3 O 9 , TiO 2 , TaO 2 , ZrO 2 , HfO 2 , Si 3 N 4 , Y 2 O 3 , AlON, TaCN, ZrSi, or other material(s). The gate cap 124 may be formed by recessing the gate stack 118 between the opposing gate spacers 108 ; depositing one or more materials over the recessed gate stack 118 ; and performing a CMP process to the one or more materials. The gate cap 124 may be deposited by atomic layer deposition (ALD), CVD, and/or other suitable methods.
The device 100 further includes a contact etch stop layer (CESL 114 ) and an inter-layer dielectric (ILD) layer 116 , which are part of the isolation structure 154 in FIG. 2 B . The CESL 114 is disposed over sidewalls of the spacers 108 and the S/D features 104 . The ILD layer 116 is disposed over the CESL 114 . The CESL 114 may include La 2 O 3 , Al 2 O 3 , SiOCN, SiOC, SiCN, SiO 2 , SiC, ZnO, ZrN, Zr 2 Al 3 O 9 , TiO 2 , TaO 2 , ZrO 2 , HfO 2 , Si 3 N 4 , Y 2 O 3 , AlON, TaCN, ZrSi, or other suitable material(s); and may be formed by CVD, PVD, ALD, or other suitable methods. The ILD layer 116 may comprise tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fluoride-doped silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. The ILD layer 116 may be formed by PECVD (plasma enhanced CVD), FCVD (flowable CVD), or other suitable methods.
In some embodiment such as shown in FIGS. 2 D- 1 and 2 E- 1 , the device 100 includes gate-all-around transistors such as nanosheet FETs or nanowire FETs. Most of the features in FIGS. 2 D- 1 and 2 E- 1 are the same as or similar to those in FIGS. 2 D and 2 E with like reference numerals denoting like features among the figures. Referring to FIGS. 2 D- 1 and 2 E- 1 , in this embodiment, the device 100 further includes multiple layers 103 a of semiconductor materials (such as silicon) that are vertically stacked over the substrate 102 (along the âzâ direction) and horizontally connect the S/D features 104 . The layers 103 a are channel layers of the transistor and may be considered as part of the fin 103 . The layers 103 a may be in the shape of rods, bars, sheets, or other shapes in various embodiments. Portions of the gate stack 118 wrap around each of the multiple layers 103 a . The device 100 further includes inner spacers 108 a horizontally between the S/D features 104 and the portions of the gate stack 118 and vertically between the layers 103 a . In some embodiment, the inner spacers 108 a include La 2 O 3 , Al 2 O 3 , SiOCN, SiOC, SiCN, SiO 2 , SiC, ZnO, ZrN, Zr 2 Al 3 O 9 , TiO 2 , TaO 2 , ZrO 2 , HfO 2 , Si 3 N 4 , Y 2 O 3 , AlON, TaCN, ZrSi, or other suitable material(s).
At operation 14 , the method 10 ( FIG. 1 A ) attaching the frontside of the device 100 to a carrier substrate 220 , such as shown in FIG. 3 . This makes the device 100 accessible from the backside of the device 100 for further processing. The operation 14 may use any suitable attaching processes, such as direct bonding, hybrid bonding, using adhesive, or other bonding methods. The operation 14 may further include alignment, annealing, and/or other processes. The carrier substrate 220 may be a silicon wafer in some embodiment. In FIG. 3 (as well as in other figures to be described below), the âzâ direction points from the backside of the device 100 to the frontside of the device 100 , while the ââzâ direction points from the frontside of the device 100 to the backside of the device 100 .
At operation 16 , the method 10 ( FIG. 1 A ) thins down the device 100 from the backside of the device 100 . The thinning process may include a mechanical grinding process and/or a chemical thinning process. A substantial amount of substrate material may be first removed from the substrate 102 during a mechanical grinding process. Afterwards, a chemical thinning process may apply an etching chemical to the backside of the substrate 102 to further thin down the substrate 102 . In the present embodiment, the device 100 is thinned down until the active regions (such as the fins 103 ) and the isolation structure 105 are exposed from the backside of the device 100 , such as shown in FIG. 4 . For the purposes of simplicity, FIG. 4 does not show all components of the device 100 .
At operation 18 , the method 10 ( FIG. 1 A ) etches holes 168 through the active regions (such as the fins 103 ) to reach some of the S/D features 104 from the backside of the device 100 . An example of the device 100 with the holes 168 is shown in FIGS. 5 A and 5 B where FIG. 5 B is a cross-sectional view of the <figure-callout id="100" label="device" filenames="US12224212-20250211-D00000.png,US12224212-20250211-D00003.png" state="{{stat
CLAIMS
Claims ( 20 )
What is claimed is:
1. A semiconductor structure having a frontside and a backside, comprising:
an isolation structure at the backside;
one or more transistors at the frontside, the one or more transistors having source/drain epitaxial features;
two metal plugs through the isolation structure and contacting two of the source/drain epitaxial features from the backside; and
a dielectric liner filling a space between the two metal plugs, wherein the dielectric liner partially or fully surrounds an air gap between the two metal plugs.
2. The semiconductor structure of claim 1 , wherein side portions of the dielectric liner directly contact the two metal plugs, and the side portions vary in thickness to form an over-hang profile.
3. The semiconductor structure of claim 1 , wherein a side portion of the dielectric liner closer towards the backside is thicker than another side portion of the dielectric liner further from the backside.
4. The semiconductor structure of claim 1 , wherein a top portion of the air gap closer to the backside is narrower than a middle portion of the air gap further from the backside.
5. The semiconductor structure of claim 1 , wherein side portions of the dielectric liner have a thickness in a range from about 0.5 nm to 10 nm, and the space between the two metal plugs has a width in a range from about 10 nm to about 500 nm.
6. The semiconductor structure of claim 1 ,
wherein the one or more transistors further includes an active region between the two source/drain epitaxial features,
wherein the space between the two metal plugs is wider than a width of the active region in a cross-section view cut along a first direction from one of the two metal plugs to another one of the two metal plugs.
7. The semiconductor structure of claim 6 , wherein the two source/drain epitaxial features and the active region are each separated from the air gap by a bottom portion of the dielectric liner.
8. The semiconductor structure of claim 7 , wherein the bottom portion of the dielectric liner has a thickness in a range from about 0.5 nm to 10 nm in a vertical direction.
9. The semiconductor structure of claim 1 , wherein the dielectric liner partially surrounds the air gap, further comprising:
an interconnect structure over the dielectric liner and the metal plugs and at the backside, wherein the interconnect structure and the dielectric liner collectively fully surround the air gap.
10. The semiconductor structure of claim 1 , wherein the dielectric liner fully surrounds the air gap.
11. The semiconductor structure of claim 1 , wherein the dielectric liner includes a low-k dielectric material having Si, O, N, or C.
12. A semiconductor structure, comprising:
a semiconductor feature;
an isolation structure disposed on sidewalls of the semiconductor feature;
a gate structure disposed on sidewalls and a top surface of the semiconductor feature and on a top surface of the isolation structure;
first and second source/drain features sandwiching the semiconductor feature;
first and second metal plugs through the isolation structure and contacting bottom surfaces of the first and second source/drain features, respectively; and
a dielectric liner contacting sidewalls of the isolation structure and sidewalls of the first and second metal plugs, wherein an air gap between the first and second metal plugs is partially or fully surrounded by the dielectric liner.
13. The semiconductor structure of claim 12 , wherein a middle portion of the dielectric liner is thinner than both a topmost portion and a bottommost portion of the dielectric liner.
14. The semiconductor structure of claim 12 , wherein the dielectric liner includes a porous dielectric material.
15. The semiconductor structure of claim 12 , further comprising:
a first interconnect structure over the gate structure and the first and second source/drain features; and
a second interconnect structure under the dielectric liner and the first and second metal plugs, wherein the second interconnect structure and the dielectric liner together fully surrounds the air gap.
16. The semiconductor structure of claim 15 , wherein the second interconnect structure includes:
a metal line directly contacting one of the metal plugs; and
a dielectric layer over the dielectric liner and the air gap, and the dielectric layer is exposed in the air gap.
17. A semiconductor structure having a frontside and a backside, comprising:
an isolation structure at the backside;
one or more transistors at the frontside, the one or more transistors having source/drain electrodes;
two metal plugs through the isolation structure and contacting two of the source/drain electrodes from the backside;
a dielectric liner contacting sidewalls of the isolation structure and sidewalls of the two metal plugs; and
an interconnect structure over the dielectric liner at the backside,
wherein an air gap between the two metal plugs is sealed by the dielectric liner and the interconnect structure.
18. The semiconductor structure of claim 17 , wherein a first portion of the dielectric liner is thicker than a second portion of the dielectric liner, wherein the first portion of the dielectric liner is more towards the backside than the second portion of the dielectric liner.
19. The semiconductor structure of claim 17 , wherein a bottom portion of the dielectric liner directly lands on each of the two source/drain electrodes.
20. The semiconductor structure of claim 17 , wherein a bottom portion of the dielectric liner directly lands on an active region of the one or more transistors, and the active region is disposed between the two source/drain electrodes.
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