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Semiconductor device and method for forming the same — Taiwan Semiconductor Manufacturing Co., Ltd. (US12112998B2)

ABSTRACT

Abstract

A semiconductor device includes a substrate, a semiconductor fin, a source/drain structure, a first buried power line, a contact, a first through substrate via (TSV), and a second TSV. The substrate has a well region extending a front-side surface of the substrate into the substrate. The semiconductor fin is on the well region. The source/drain structure is on the semiconductor fin. The first buried power line is electrically coupled to the source/drain structure on the first semiconductor fin. The first buried power line has a length extending along a lengthwise direction of the first semiconductor fin and a height extending within the well region. The first TSV extends from a back-side surface of the substrate through the substrate to the first buried power line. The second TSV extends from the back-side surface of the substrate to the well region.

Description

PRIORITY CLAIM AND CROSS-REFERENCE

The present application is a Divisional application of the U.S. application Ser. No. 17/196,623, filed on Mar. 9, 2021, which claims priority to U.S. Provisional Application Ser. No. 63/053,234, filed Jul. 17, 2020, which is herein incorporated by reference in its entirety, which is herein incorporated by reference in its entirety.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIGS. 1 A and 1 B are flow charts of a method M 1 for forming a semiconductor device in accordance with some embodiments of the present disclosure.

FIGS. 2 - 13 , 14 A, 15 - 17 , 18 A, 19 , 20 A, and 20 B illustrate a method for manufacturing a semiconductor device at various stages in accordance with some embodiments of the present disclosure.

FIG. 14 B illustrates another wafer at a stage corresponding to FIG. 14 A according to some alternative embodiments of the present disclosure.

FIG. 18 B illustrates another wafer at a stage corresponding to FIG. 18 A according to some alternative embodiments of the present disclosure.

FIG. 21 illustrates a top view of a wafer according to some alternative embodiments of the present disclosure.

FIG. 22 illustrates a top view of a wafer according to some alternative embodiments of the present disclosure.

FIG. 23 illustrates a top view of a wafer according to some alternative embodiments of the present disclosure.

FIG. 24 is a flow chart of a method M 2 for forming a semiconductor device in accordance with some embodiments of the present disclosure.

FIGS. 25 - 36 illustrate a method for manufacturing a semiconductor device at various stages in accordance with some embodiments of the present disclosure.

FIGS. 37 - 45 , 46 A, and 47 - 50 illustrate a method for manufacturing a semiconductor device at various stages in accordance with some embodiments of the present disclosure.

FIG. 46 B illustrates another semiconductor device at a stage corresponding to FIG. 46 A according to some alternative embodiments of the present disclosure.

FIGS. 51 - 56 illustrate a method for manufacturing a semiconductor device at various stages in accordance with some embodiments of the present disclosure.

FIGS. 57 - 63 illustrate a method for manufacturing a semiconductor device at various stages in accordance with some embodiments of the present disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, “around,” “about,” “approximately,” or “substantially” shall generally mean within 20 percent, or within 10 percent, or within 5 percent of a given value or range. Numerical quantities given herein are approximate, meaning that the term “around,” “about,” “approximately,” or “substantially” can be inferred if not expressly stated.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Embodiments of the present disclosure are directed to, but not otherwise limited to, a fin-like field-effect transistor (FinFET) device. The FinFET device, for example, may be a complementary metal-oxide-semiconductor (CMOS) device including a P-type metal-oxide-semiconductor (PMOS) FinFET device and an N-type metal-oxide-semiconductor (NMOS) FinFET device. The following disclosure will continue with one or more FinFET examples to illustrate various embodiments of the present disclosure. It is understood, however, that the application should not be limited to a particular type of device, except as specifically claimed.

The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. The double-patterning or the multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins.

Referring now to FIGS. 1 A and 1 B , illustrated is an exemplary method M 1 for fabrication of a semiconductor device in accordance with some embodiments. The method M 1 includes a relevant part of the entire manufacturing process. It is understood that additional operations may be provided before, during, and after the operations shown by FIGS. 1 A and 1 B , and some of the operations described below can be replaced or eliminated for additional embodiments of the method. The order of the operations/processes may be interchangeable. The method M includes fabrication of a FinFET device. However, the fabrication of FinFET device is merely example for describing the manufacturing process according to some embodiments of the present disclosure.

FIGS. 2 - 20 B illustrate a wafer W 1 at various stages of the method M 1 according to some embodiments of the present disclosure. FIG. 2 is a top view of the wafer W 1 . FIGS. 2 - 19 and 20 A are cross-sectional views corresponding to line A-A in FIG. 2 . FIG. 20 B is cross-sectional views along line B-B in FIG. 2 and corresponds to FIG. 20 A . The method M 1 begins at block S 101 where semiconductor fins are formed on a substrate. Referring to FIG. 3 , in some embodiments of block S 101 , a wafer W 1 undergoes a series of deposition and photolithography processes, such that a patterned photoresist layer (not shown) and a mask layer 130 are formed on a substrate 110 of the wafer W 1 . In some embodiments, the mask layer 130 includes a hard mask layer and a pad layer. In some embodiments, the substrate 110 is a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. An SOI substrate includes a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate 110 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof.

As shown in FIG. 3 , well regions

116 and 118 in the substrate 110 which divide the substrate 110 into separate regions for different types of devices or transistors. Example materials of the well regions

116 and 118 include, but are not limited to, semiconductor materials doped with various types of p-type dopants and/or n-type dopants. In some embodiments, the well region 116 includes a p-type dopant and may be referred to as a P-type well region, and the well region 118 includes an n-type dopant and may be referred to as an N-type well region. In the example configuration in FIG. 3 , the N- type well region 118 is a region for forming p-channel metal-oxide semiconductor (PMOS) transistors, and the P- type well region 116 is a region for forming n-channel metal-oxide semiconductor (NMOS) transistors. The described conductivity of the well regions

116 and 118 herein is an example. Other arrangements are within the scope of various embodiments.

In some embodiments, the pad layer is a thin film including silicon oxide formed using, for example, a thermal oxidation process. The pad layer may act as an adhesion layer between the substrate 110 and the hard mask layer. The pad layer may also act as an etch stop layer for etching the hard mask layer. In some embodiments, the hard mask layer is formed of silicon nitride, for example, using low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). The hard mask layer is used as a hard mask during subsequent photolithography processes. A photoresist layer is formed on the mask layer 130 and is then patterned, forming openings in the photoresist layer, so that regions of the mask layer 130 are exposed.

Then, the substrate 110 is patterned to form one or more semiconductor fins

152 and

PRIORITY CLAIM AND CROSS-REFERENCE

The present application is a Divisional application of the U.S. application Ser. No. 17/196,623, filed on Mar. 9, 2021, which claims priority to U.S. Provisional Application Ser. No. 63/053,234, filed Jul. 17, 2020, which is herein incorporated by reference in its entirety, which is herein incorporated by reference in its entirety.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIGS. 1 A and 1 B are flow charts of a method M 1 for forming a semiconductor device in accordance with some embodiments of the present disclosure.

FIGS. 2 - 13 , 14 A, 15 - 17 , 18 A, 19 , 20 A, and 20 B illustrate a method for manufacturing a semiconductor device at various stages in accordance with some embodiments of the present disclosure.

FIG. 14 B illustrates another wafer at a stage corresponding to FIG. 14 A according to some alternative embodiments of the present disclosure.

FIG. 18 B illustrates another wafer at a stage corresponding to FIG. 18 A according to some alternative embodiments of the present disclosure.

FIG. 21 illustrates a top view of a wafer according to some alternative embodiments of the present disclosure.

FIG. 22 illustrates a top view of a wafer according to some alternative embodiments of the present disclosure.

FIG. 23 illustrates a top view of a wafer according to some alternative embodiments of the present disclosure.

FIG. 24 is a flow chart of a method M 2 for forming a semiconductor device in accordance with some embodiments of the present disclosure.

FIGS. 25 - 36 illustrate a method for manufacturing a semiconductor device at various stages in accordance with some embodiments of the present disclosure.

FIGS. 37 - 45 , 46 A, and 47 - 50 illustrate a method for manufacturing a semiconductor device at various stages in accordance with some embodiments of the present disclosure.

FIG. 46 B illustrates another semiconductor device at a stage corresponding to FIG. 46 A according to some alternative embodiments of the present disclosure.

FIGS. 51 - 56 illustrate a method for manufacturing a semiconductor device at various stages in accordance with some embodiments of the present disclosure.

FIGS. 57 - 63 illustrate a method for manufacturing a semiconductor device at various stages in accordance with some embodiments of the present disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, “around,” “about,” “approximately,” or “substantially” shall generally mean within 20 percent, or within 10 percent, or within 5 percent of a given value or range. Numerical quantities given herein are approximate, meaning that the term “around,” “about,” “approximately,” or “substantially” can be inferred if not expressly stated.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Embodiments of the present disclosure are directed to, but not otherwise limited to, a fin-like field-effect transistor (FinFET) device. The FinFET device, for example, may be a complementary metal-oxide-semiconductor (CMOS) device including a P-type metal-oxide-semiconductor (PMOS) FinFET device and an N-type metal-oxide-semiconductor (NMOS) FinFET device. The following disclosure will continue with one or more FinFET examples to illustrate various embodiments of the present disclosure. It is understood, however, that the application should not be limited to a particular type of device, except as specifically claimed.

The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. The double-patterning or the multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins.

Referring now to FIGS. 1 A and 1 B , illustrated is an exemplary method M 1 for fabrication of a semiconductor device in accordance with some embodiments. The method M 1 includes a relevant part of the entire manufacturing process. It is understood that additional operations may be provided before, during, and after the operations shown by FIGS. 1 A and 1 B , and some of the operations described below can be replaced or eliminated for additional embodiments of the method. The order of the operations/processes may be interchangeable. The method M includes fabrication of a FinFET device. However, the fabrication of FinFET device is merely example for describing the manufacturing process according to some embodiments of the present disclosure.

FIGS. 2 - 20 B illustrate a wafer W 1 at various stages of the method M 1 according to some embodiments of the present disclosure. FIG. 2 is a top view of the wafer W 1 . FIGS. 2 - 19 and 20 A are cross-sectional views corresponding to line A-A in FIG. 2 . FIG. 20 B is cross-sectional views along line B-B in FIG. 2 and corresponds to FIG. 20 A . The method M 1 begins at block S 101 where semiconductor fins are formed on a substrate. Referring to FIG. 3 , in some embodiments of block S 101 , a wafer W 1 undergoes a series of deposition and photolithography processes, such that a patterned photoresist layer (not shown) and a mask layer 130 are formed on a substrate 110 of the wafer W 1 . In some embodiments, the mask layer 130 includes a hard mask layer and a pad layer. In some embodiments, the substrate 110 is a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. An SOI substrate includes a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate 110 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof.

As shown in FIG. 3 , well regions

116 and 118 in the substrate 110 which divide the substrate 110 into separate regions for different types of devices or transistors. Example materials of the well regions

116 and 118 include, but are not limited to, semiconductor materials doped with various types of p-type dopants and/or n-type dopants. In some embodiments, the well region 116 includes a p-type dopant and may be referred to as a P-type well region, and the well region 118 includes an n-type dopant and may be referred to as an N-type well region. In the example configuration in FIG. 3 , the N- type well region 118 is a region for forming p-channel metal-oxide semiconductor (PMOS) transistors, and the P- type well region 116 is a region for forming n-channel metal-oxide semiconductor (NMOS) transistors. The described conductivity of the well regions

116 and 118 herein is an example. Other arrangements are within the scope of various embodiments.

In some embodiments, the pad layer is a thin film including silicon oxide formed using, for example, a thermal oxidation process. The pad layer may act as an adhesion layer between the substrate 110 and the hard mask layer. The pad layer may also act as an etch stop layer for etching the hard mask layer. In some embodiments, the hard mask layer is formed of silicon nitride, for example, using low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). The hard mask layer is used as a hard mask during subsequent photolithography processes. A photoresist layer is formed on the mask layer 130 and is then patterned, forming openings in the photoresist layer, so that regions of the mask layer 130 are exposed.

Then, the substrate 110 is patterned to form one or more semiconductor fins

152 and 154 . The mask layer 130 is etched through the photoresist layer exposing the underlying well regions

116 and 118 . The exposed well regions

116 and 118 are then etched, forming trenches T. Portions of the well regions

116 and 118 between neighboring trenches T can be referred to as semiconductor fins

152 and 154 . After etching the well regions

116 and 118 , the photoresist layer is removed. Next, a cleaning step may be optionally performed to remove a native oxide of the semiconductor substrate 110 . The cleaning may be performed using diluted hydrofluoric (HF) acid, for example. According to the various aspects of the present disclosure, the semiconductor fins

152 and 154 extend along a first direction. In some embodiments, the semiconductor fins

152 and 154 may also be referred to as oxide-definition (OD) regions. In some embodiments, the well region 116 and/or 118 has a thickness in a range about 10 nm to about 100 nm by way of example but not limitation.

Returning to FIG. 1 A , the method M 1 then proceeds to block S 102 where a first isolation dielectric is formed to cover the semiconductor fins. With reference to FIG. 4 , in some embodiments of block S 102 , an isolation dielectric 160 is formed to overfill the trenches T and cover the semiconductor fins

152 and 154 . The isolation dielectric 160 in the trenches T can be referred to as a shallow trench isolation (STI) structure. In some embodiments, the isolation dielectric 160 is made of silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), or other low-K dielectric materials. In some embodiments, the isolation dielectric 160 may be formed using a high-density-plasma (HDP) chemical vapor deposition (CVD) process, using silane (SiH 4 ) and oxygen (O 2 ) as reacting precursors. In some other embodiments, the isolation dielectric 160 may be formed using a sub-atmospheric CVD (SACVD) process or high aspect-ratio process (HARP), in which process gases may include tetraethylorthosilicate (TEOS) and ozone (O 3 ). In yet other embodiments, the isolation dielectric 160 may be formed using a spin-on-dielectric (SOD) process, such as hydrogen silsesquioxane (HSQ) or methyl silsesquioxane (MSQ). Other processes and materials may be used. In some embodiments, the isolation dielectric 160 can have a multi-layer structure, for example, a thermal oxide liner layer with silicon nitride formed over the liner. Thereafter, a thermal annealing may be optionally performed to the isolation dielectric 160 .

Returning to FIG. 1 A , the method M 1 then proceeds to block S 103 where a planarization process is performed to the first isolation dielectric. With reference to FIG. 5 , in some embodiments of block S 103 , a planarization process such as chemical mechanical polish (CMP) is performed to remove the excess isolation dielectric 160 over the semiconductor fins

152 and 154 . In some other embodiments, the planarization process stops when the mask layer 130 is exposed. In such embodiments, the mask layer 130 may act as the CMP stop layer in the planarization. In some embodiments, the planarization process may also remove the mask layer 130 such that top surfaces of the semiconductor fins

152 and 154 are exposed. If the mask layer 130 is not removed by the planarization process, the mask layer 130 , if formed of silicon nitride, may be remove by a wet process using hot H 3 PO 4 , and if formed of silicon oxide, may be removed using diluted HF.

Returning to FIG. 1 A , the method M 1 then proceeds to block S 104 where trenches are formed to extend through the first isolation dielectric into the substrate adjacent to the semiconductor fins. With reference to FIG. 6 , in some embodiments of block S 104 , a patterned mask layer (not shown) is formed over the isolation dielectric 160 . In some embodiments, the mask layer is formed by spin coating a resist material (e.g., the mask layer may be also referred to as a photo resist layer), followed by a process, such as a soft baking process and a hard baking process (may be also referred to as a pre-exposure baking). In some embodiments, the mask layer is a DUV resist such as a krypton fluoride (KrF) resist or an argon fluoride (ArF) resist. In some embodiments, the mask layer is an I-line resist, a EUV resist, an electron beam (e-beam) resist, or an ion beam resist. In some embodiments, the mask layer is a positive resist. The positive resist is insoluble in a developer but becomes soluble upon radiation. One exemplary positive resist is a chemically amplified resist (CAR) that contains backbone polymer protected by acid labile groups (ALGs) and further contains photo-acid generators (PAGs). The PAGs can produce an acid upon radiation and the acid can catalyze the cleaving of the ALGs from the backbone polymer, increasing the polymer's solubility to a positive tone developer. In some embodiments, the mask layer is a negative resist. The negative resist is soluble in a developer but becomes insoluble upon radiation.

After coating the mask layer over the isolation dielectric 160 , the mask layer is exposed to a radiation through a mask. After exposing the mask layer to the radiation is complete, the exposed mask layer undergoes one or more post-exposure baking (PEB) processes. Then, a developing process is performed, such that portions of the exposed mask layer are removed, and the mask layer may act as an etch mask to protect the rest of the isolation dielectric 160 from the etching process. Referring to FIG. 6 , when the etching process is complete, the trenches

160 a and 160 b are formed to run through the isolation dielectric 160 and to have bottoms at positons in the well regions

116 and 118 . In some embodiments, the trench 160 a and/or 160 b in the well region 116 and/or 118 has a depth T 2 in a range from about 30 nm to about 200 nm by way of example but not limitation.

In some embodiments, the etching process is an anisotropic dry etching process (e.g., a reactive-ion etching (RIE) process or an atomic layer etching (ALE) process). By way of example and not limitation, a dry etching process may implement an oxygen-containing gas, a fluorine-containing gas (e.g., CF 4 , SF 6 , CH 2 F 2 , CHF 3 , and/or C 2 F 6 ), a chlorine-containing gas (e.g., Cl 2 , CHCl 3 , CCl 4 , and/or BCl 3 ), a bromine-containing gas (e.g., HBr and/or CHBR 3 ), an iodine-containing gas, other suitable gases and/or plasmas, and/or combinations thereof.

Returning to FIG. 1 A , the method M 1 then proceeds to block S 105 where a conductive material is formed over the first isolation dielectric and filled in the trenches. With reference to FIG. 7 , in some embodiments of block S 105 , the trenches

160 a and 160 b are filled with a conductive material 170 . In some embodiments, the conductive material 170 may include metal, such as tungsten (W), ruthenium (Ru), aluminum (Al), copper (Cu), or other suitable conductive material. In some embodiments, the conductive material 170 may be deposited by CVD, physical vapor deposition (PVD), sputter deposition, or other techniques suitable for depositing conductive materials.

Returning to FIG. 1 A , the method M 1 then proceeds to block S 106 where a planarization process is performed to the conductive material. With reference to FIG. 8 , in some embodiments of block S 106 , a planarization process such as chemical mechanical polish (CMP) is performed to remove the excess conductive material 170 over the isolation dielectric 160 . In some other embodiments, the planarization process stops when the isolation dielectric 160 is exposed. In such embodiments, the isolation dielectric 160 may act as the CMP stop layer in the planarization.

Returning to FIG. 1 A , the method M 1 then proceeds to block S 107 where the conductive material is etched in the trenches down to a given depth, leaving a portion of conductive material in the trenches thus forming buried power rails of this height. With reference to FIG. 9 , in some embodiments of block S 107 , an etching process is performed to thin down the conductive material 170 , such that a top surface of the conductive material 170 is lowered to a level below a top surface of the isolation dielectric 160 , and thus buried power rails

170 a and 170 b are formed. In some embodiments, the buried power rails

170 a and 170 b may also be referred to as conductive rails

170 a and 170 b . In some embodiments, the buried power rail 170 a and/or 170 b may also be referred to as a supply power rail and/or ground reference rail. For example, the buried power rail 170 a may be referred to as a ground reference rail and the buried power rail 170 b may be referred to as a supply power rail. The buried power rail 170 a and/or 170 b extends along a lengthwise direction of the semiconductor fin 152 and/or 154 as shown in FIG. 2 . In some embodiments, the thinning down of the conductive material 170 may include a dry etching process or other suitable etching processes. In some embodiments, the etch process include using a technique and etchant selected to etch the conductive material 170 without significant etching of the surrounding structures (i.e., isolation dielectric 160 ).

In some embodiments, the etching process is an anisotropic dry etching process (e.g., a reactive-ion etching (RIE) process or an atomic layer etching (ALE) process). By way of example and not limitation, a dry etching process may implement an oxygen-containing gas, a fluorine-containing gas (e.g., CF 4 , NF 3 , SF 6 , CH 2 F 2 , CHF 3 , C 2 F 6 , and/or C 4 F 8 ), a chlorine-containing gas (e.g., Cl 2 , HCl, CHCl 3 , CCl 4 , and/or BCl 3 ), a bromine-containing gas (e.g., HBr and/or CHBR 3 ), an iodine-containing gas, other suitable gases and/or plasmas, and/or combinations thereof.

Returning to FIG. 1 A , the method M 1 then proceeds to block S 108 where a second isolation dielectric is formed over the first isolation dielectric and filled in the trenches to land on the buried power rails. With reference to FIG. 10 , in some embodiments of block S 108 , an isolation dielectric 165 is formed to overfill the trenches

160 a and 160 b to land on the buried power rails

170 a and 170 b and covers the isolation dielectric 160 . The isolation dielectric 165 in the trenches

160 a and 160 b can be referred to as a shallow trench isolation (STI) structure. In some embodiments, the isolation dielectric 165 is made of silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), or other low-K dielectric materials. In some embodiments, the isolation dielectric 165 has a material different than the isolation dielectric 160 . In some embodiments, the isolation dielectric 165 has a material the same as the isolation dielectric 160 .

In some embodiments, the isolation dielectric 165 may be formed using a high-density-plasma (HDP) chemical vapor deposition (CVD) process, using silane (SiH 4 ) and oxygen (O 2 ) as reacting precursors. In some other embodiments, the isolation dielectric 165 may be formed using a sub-atmospheric CVD (SACVD) process or high aspect-ratio process (HARP), in which process gases may include tetraethylorthosilicate (TEOS) and ozone (O 3 ). In yet other embodiments, the isolation dielectric 165 may be formed using a spin-on-dielectric (SOD) process, such as hydrogen silsesquioxane (HSQ) or methyl silsesquioxane (MSQ). Other processes and materials may be used. In some embodiments, the isolation dielectric 165 can have a multi-layer structure, for example, a thermal oxide liner layer with silicon nitride formed over the liner. Thereafter, a thermal annealing may be optionally performed to the isolation dielectric 165 .

Returning to FIG. 1 A , the method M 1 then proceeds to block S 109 where the second isolation dielectric over the first isolation dielectric is removed. With reference to FIG. 11 , in some embodiments of block S 109 , a planarization process such as chemical mechanical polish (CMP) is performed to remove the excess isolation dielectric 165 over the isolation dielectric 160 . In some other embodiments, the planarization process stops when the isolation dielectric 160 is exposed. In such embodiments, the isolation dielectric 160 may act as the CMP stop layer in the planarization. In some other embodiments, the planarization process stops when the mask layer 130 is exposed. In such embodiments, the mask layer 130 may act as the CMP stop layer in the planarization. In some embodiments, the planarization process may also remove the mask layer 130 such that top surfaces of the semiconductor fins

152 and 154 are exposed.

Returning to FIG. 1 A , the method M 1 then proceeds to block S 110 where the first and second isolation dielectrics are recessed. With reference to FIG. 12 , in some embodiments of block S 110 , the isolation dielectrics

160 and 165 are recessed, for example, through an etching operation, in which diluted HF, SiCoNi (including HF and NH 3 ), or the like, may be used as the etchant. After recessing the isolation dielectric 165 , a portion of the semiconductor fin 152 and a portion of the semiconductor fin 154 are higher than a top surface of the isolation dielectric 160 and higher than a top surface of the isolation dielectric 165 .

It is understood that the blocks S 101 -S 110 described above are merely an example of how the semiconductor fins

152 and 154 , the isolation dielectrics

160 and 165 , and the buried power rails

170 a and 170 b are formed. In other embodiments, a dielectric layer can be formed over a top surface of the substrate 110 ; trenches can be etched through the dielectric layer; homoepitaxial structures can be epitaxially grown in the trenches; and the dielectric layer can be recessed such that the homoepitaxial structures protrude from the dielectric layer to form fins. In still other embodiments, heteroepitaxial structures can be used for the fin. For example, the semiconductor fins

152 and 154 can be recessed, and a material different from the recessed semiconductor fins

152 and 154 is epitaxially grown in its place. In even further embodiments, a dielectric layer can be formed over a top surface of the substrate 110 ; trenches can be etched through the dielectric layer; heteroepitaxial structures can be epitaxially grown in the trenches using a material different from the substrate 110 ; and the dielectric layer can be recessed such that the heteroepitaxial structures protrude from the dielectric layer to form fins. In some embodiments where homoepitaxial or heteroepitaxial structures are epitaxially grown, the grown materials may be in-situ doped during growth, which may obviate prior implanting of the fins although in-situ and implantation doping may be used together. In some embodiments, the semiconductor fin 152 or the semiconductor fin 154 may include silicon germanium (Si x Ge 1-x , where x can be between approximately 0 and 1), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, the available materials for forming III-V compound semiconductor include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, or the like.

As used herein, the term “in-situ” is used to describe processes that are performed while a device or substrate remains within a processing system (e.g., including a load lock chamber, transfer chamber, processing chamber, or any other fluidly coupled chamber), and where for example, the processing system allows the substrate to remain under vacuum conditions. As such, the term “in-situ” may also be used to refer to processes in which the device or substrate being processed is not exposed to an external environment (e.g., external to the processing system).

This is followed by the gate formation which is shown in FIG. 2 , and which may be done by a technique, for example a replacement gate technique. The gate structures

182 and 184 shown in FIG. 2 are formed perpendicularly to the semiconductor fins

152 and 154 .

Returning to FIG. 1 B , the method M 1 then proceeds to block S 111 where source/drain features are formed on the semiconductor fins. With reference to FIG. 13 , in some embodiments of block S 111 , the source/drain features 172 and 174 may be formed by performing an epitaxial growth process that provides epitaxy materials

162 and 164 cladding the portions of the semiconductor fins

152 and 154 . Source/drain features 172 and 174 are formed on the substrate 110 adjacent to the gate structures

182 and 184 shown in FIG. 2 . The source/drain features 172 and 174 include m

CLAIMS

Claims ( 20 )

What is claimed is:

1. A semiconductor device, comprising:

a substrate having a well region extending from a front-side surface of the substrate into the substrate;

a first semiconductor fin on the well region;

a shallow trench isolation (STI) structure laterally surrounding a portion of the first semiconductor fin;

a source/drain structure on the first semiconductor fin;

a first buried power line electrically coupled to the source/drain structure on the first semiconductor fin, the first buried power line having a length extending along a lengthwise direction of the first semiconductor fin and a height extending from within the STI structure to within the well region;

a first through substrate via (TSV) extending from a back-side surface of the substrate to the first buried power line; and

a second TSV extending from the back-side surface of the substrate to the well region, wherein a front-side surface of the second TSV exposes in the well region to form an interface with the well region.

2. The semiconductor device of claim 1 , wherein in a plan view, the second TSV is between the first semiconductor fin and the first buried power line.

3. The semiconductor device of claim 1 , further comprising a second semiconductor fin on the well region, wherein in a plan view, the second TSV is between the first and second semiconductor fins.

4. The semiconductor device of claim 1 , further comprising a second buried power line having a length extending along the lengthwise direction of the first semiconductor fin, wherein the first semiconductor fin is between the second buried power line and the first buried power line.

5. The semiconductor device of claim 1 , wherein in a plan view, the second TSV non-overlaps the first semiconductor fin.

6. The semiconductor device of claim 1 , further comprising a gate structure extending across the first semiconductor fin, wherein in a plan view, the second TSV overlaps the gate structure.

7. The semiconductor device of claim 1 , wherein the second TSV has substantially the same depth as the first TSV.

8. The semiconductor device of claim 1 , wherein an interface formed by the first TSV and the first buried power line is substantially level with an interface formed by the well region and the second TSV.

9. The semiconductor device of claim 1 , wherein the well region is an N-type well region.

10. The semiconductor device of claim 1 , wherein the well region is a P-type well region.

11. A semiconductor device, comprising:

a substrate having a P-type well region and an N-type well region adjacent to the P-type well region, wherein the P-type well region and the N-type well region extend from a front-side surface of the substrate into the substrate;

a first semiconductor fin upwardly extending from the P-type well region in a vertical direction;

a second semiconductor fin upwardly extending from the N-type well region in the vertical direction;

a first through substrate via (TSV) extending from a back-side surface of the substrate to the P-type well region, wherein the first TSV overlaps the first semiconductor fin in the vertical direction; and

a second TSV extending from the back-side surface of the substrate to the N-type well region.

12. The semiconductor device of claim 11 , further comprising:

a third semiconductor fin on the substrate;

a source/drain structure on the third semiconductor fin;

a buried power line partially embedded in the substrate;

a source/drain contact electrically connecting the source/drain structure to the buried power line; and

a third TSV extending from the back-side surface of the substrate to the buried power line.

13. The semiconductor device of claim 11 , further comprising:

a third semiconductor fin over the substrate;

first and second source/drain structures respectively on the first and third semiconductor fins;

a multilayer interconnect stack over the first and second source/drain structures; and

a third TSV extending from the back-side surface of the substrate to the multilayer interconnect stack.

14. The semiconductor device of claim 11 , further comprising a doping layer between the first TSV and the P-type well region and doped with a p-type dopant.

15. The semiconductor device of claim 11 , wherein a front-side surface of the second TSV forms an interface with the N-type well region.

16. The semiconductor device of claim 11 , further comprising a metal silicide layer between the first TSV and the P-type well region.

17. A semiconductor device, comprising:

a semiconductive substrate having a well region extending from a front-side surface of the semiconductive substrate into the semiconductive substrate;

a first fin on the well region;

a second fin on the well region;

a gate across the first and second fins;

first source/drain features on the first fin and at opposite sides of the gate;

second source/drain features on the second fin and at opposite sides of the gate; and

a first through substrate via (TSV) extending from a back-side of the semiconductive substrate to the well region, wherein from a top view, the first TSV is between the first and second fins, and an entirety of a front-side surface of the first TSV forms an interface with the well region.

18. The semiconductor device of claim 17 , further comprising:

a buried power rail having a first portion in the well region and a second portion exposed from the front-side surface of the semiconductive substrate, wherein the buried power rail is electrically connected to one of the first source/drain features, wherein the first TSV non-overlaps the buried power rail from the top view.

19. The semiconductor device of claim 18 , further comprising:

a second TSV extending from the back-side of the semiconductive substrate to the buried power rail.

20. The semiconductor device of claim 17 , wherein the first TSV overlaps the gate from the top view.

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