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Backside contact of a semiconductor device — Qualcomm Incorporated (US11081559B1)

Qualcomm Incorporated · Google Patents

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patent, google patents, intellectual property, US11081559B1, Qualcomm Incorporated, Qingqing Liang, en, 2021

ABSTRACT

Abstract

Certain aspects of the present disclosure generally relate to a semiconductor device having a backside gate contact. An example semiconductor device generally includes a transistor disposed above a substrate, wherein the transistor comprises a gate region, a channel region, a source region, and a drain region and wherein the gate region is disposed adjacent to the channel region. The semiconductor device further includes a backside gate contact that is electrically coupled to a bottom surface of the gate region and that extends below a bottom surface of the substrate.

Description

BACKGROUND

Field of the Disclosure

Certain aspects of the present disclosure generally relate to electronic circuits and, more particularly, to a semiconductor device having a backside contact.

Description of Related Art

As electronic devices are getting smaller and faster, the demand for integrated circuits (ICs) with higher I/O count, faster data processing rate, and/or better signal integrity greatly increases. The ICs may include various conductors (e.g., conductive contacts and/or metal layers), which are often formed during a back-end-of-line (BEOL) fabrication process. The conductors facilitate electrical wiring to various electrical components including transistors, amplifiers, inverters, control logic, memory, power management circuits, buffers, filters, resonators, capacitors, inductors, resistors, etc.

SUMMARY

The systems, methods, and devices of the disclosure each have several aspects, no single one of which is solely responsible for its desirable attributes. Without limiting the scope of this disclosure as expressed by the claims which follow, some features will now be discussed briefly. After considering this discussion, and particularly after reading the section entitled âDetailed Description,â one will understand how the features of this disclosure provide advantages that include improved gate contacts for a semiconductor device.

Certain aspects of the present disclosure provide a semiconductor device. The semiconductor device generally includes a transistor disposed above a substrate, wherein the transistor comprises a gate region, a channel region, a source region, and a drain region, wherein the gate region is disposed adjacent to the channel region. The semiconductor device further includes a backside gate contact that is electrically coupled to a bottom surface of the gate region and that extends below a bottom surface of the substrate.

Certain aspects of the present disclosure provide a method of fabricating a semiconductor device. The method generally includes forming a transistor above a substrate, wherein the transistor comprises a gate region, a channel region, a source region, and a drain region, wherein the gate region is adjacent to the channel region. The method further includes forming a backside gate contact that is electrically coupled to a bottom surface of the gate region and that extends below a bottom surface of the substrate.

To the accomplishment of the foregoing and related ends, the one or more aspects comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative features of the one or more aspects. These features are indicative, however, of but a few of the various ways in which the principles of various aspects may be employed, and this description is intended to include all such aspects and their equivalents.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above-recited features of the present disclosure can be understood in detail, a more particular description, briefly summarized above, may be had by reference to aspects, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only certain typical aspects of this disclosure and are therefore not to be considered limiting of its scope, for the description may admit to other equally effective aspects.

FIG. 1A is a top view of an example semiconductor device having a backside gate contact, in accordance with certain aspects of the present disclosure.

FIG. 1B is a cross-sectional view taken along line segment AAâ² of FIG. 1A , in accordance with certain aspects of the present disclosure.

FIG. 2 is a cross-sectional view taken along line segment BBâ² of FIG. 1A illustrating the fan-out in different metal layers, in accordance with certain aspects of the present disclosure.

FIG. 3 illustrates another portion of the semiconductor device of FIG. 1A taken along a cross-section orthogonal to that of the cross-section depicted in FIG. 2 , in accordance with certain aspects of the present disclosure.

FIG. 4 illustrates a cross-sectional view of an example gate-all-around (GAA) transistor with a backside gate contact, in accordance with certain aspects of the present disclosure.

FIG. 5 illustrates an isometric view of an example of the GAA transistor of FIG. 4 , in accordance with certain aspects of the present disclosure.

FIGS. 6-12 illustrate various top and cross-sectional views of example operations for fabricating a semiconductor device, in accordance with certain aspects of the present disclosure.

FIG. 13 is a flow diagram of example operations for fabricating a semiconductor device, in accordance with certain aspects of the present disclosure.

DETAILED DESCRIPTION

Aspects of the present disclosure generally relate to a semiconductor device having backside contacts and various methods for fabricating such a semiconductor device.

In certain cases, a backside contact may be used to provide electrical routing below an active electrical device, such as a transistor. For example, the backside contact may provide a conductive contact coupled between metal layers disposed above and below a substrate and/or a conductive contact coupled between a source/drain region and a metal layer disposed below the substrate. In certain cases, layer-transfer technologies may allow the formation of backside contacts that are coupled directly to one or more diffusion regions, such as a source or drain region of a transistor. The process of backside silicidation may increase the complexity of the fabrication process, resulting in yield loss risks. The silicidation process may also produce a higher thermal budget, which may have adverse effects on the device performance, back-end-of-line (BEOL) integrity of frontside contacts, and, in radio frequency (RF) applications, possible loss of RF performance, such as harmonics or distortion products (e.g., the input intercept point (IIP)).

Aspects of the present disclosure provide a semiconductor device having a backside contact that is coupled directly to a gate region, such as a polycrystalline silicon layer of the gate region. As described herein with respect to the backside gate contact, the direct contact to the gate region may improve device design space/options and electrical routing approaches of the semiconductor device. For example, the backside gate contact may enable improved design space and options by reducing the electrical routing to the gates of transistors via the backside of the semiconductor device. As an example, the backside gate contacts may enable electrical routing options on the frontside where routing would have been used to connect to the gate contacts. In certain cases, the backside gate contacts may facilitate electrical routing to decoupling capacitors or other passive components attached on the landside of the semiconductor device. Such electrical routing may enable improved performance of the semiconductor device, for example, by reducing parasitic losses encountered with electrical routing on the frontside. In certain aspects, layer transfer processes may be performed to couple the various backside contacts and metal layers disposed below an active electrical device, such as a transistor.

Example Backside Contact

FIGS. 1A and 1B illustrate a top view and a cross-sectional view, respectively, of an example semiconductor device 100 that has a backside gate contact coupled to a gate region of a transistor, in accordance with certain aspects of the present disclosure. FIG. 1B illustrates the semiconductor device 100 across the cross-section AAâ² as depicted in FIG. 1A . As shown in FIGS. 1A and 1B , the semiconductor device 100 may include a transistor 102 , a substrate 104 , and one or more backside gate contacts 106 (shown in FIG. 1B ). In certain aspects, the semiconductor device 100 may further include frontside contacts

108 and 109 , frontside dielectric layers 110 , frontside conductive vias (not shown), frontside conductive traces 112 (e.g., metal layer one (M1)), backside dielectric layers 114 , backside conductive traces 116 (e.g., first, second, and third backside metal layers labeled âBSM1,â âBSM2,â âBSM3â), and backside conductive vias 118 .

In aspects, the transistor 102 may be formed during a front-end-of-line (FEOL) fabrication process. The frontside aspects (including the frontside contacts

108 and 109 , frontside dielectric layers 110 , and frontside conductive traces 112 ) may be formed during the BEOL fabrication process. In certain aspects, the backside aspects (including the backside dielectric layers 114 , backside conductive traces 116 , and backside conductive vias 118 ) may be formed during a layer transfer process of the BEOL fabrication process.

The transistor 102 is disposed above the substrate 104 . The transistor 102 may include a metal-oxide-semiconductor field-effect transistor (MOSFET), and the MOSFET may include a finFET and/or a GAA FET. In the example depicted in FIGS. 1A and 1B , the transistor 102 is a finFET.

The transistor 102 may include a gate region 120 , a channel region 122 , a source region 124 , and a drain region 126 . As the transistor 102 is a finFET, the channel region 122 may include one or more semiconductor fin structures. In certain aspects, the semiconductor fin structures may extend above the substrate 104 . In certain aspects, the channel region 122 may include nanosheets and/or nanowires (not shown), for example, in cases where the transistor 102 is a GAA FET.

In aspects, the gate region 120 may include a conductive layer disposed adjacent (e.g., above) at least one dielectric layer (not shown). The conductive layer may include one or more layers of electrically conductive materials such as polycrystalline silicon (polysilicon) or various work function metals including titanium nitride (TiN), aluminum (Al), tantalum nitride (TaN), titanium aluminide (TiAl), tungsten (W), etc. In aspects, the dielectric layer may include a dielectric material (e.g., hafnium dioxide (HfO 2 ), zirconium dioxide (ZrO 2 ), and/or titanium dioxide (TiO 2 )) with a dielectric constant (Îº) higher than silicon dioxide (SiO 2 ) (e.g., Îº=3.9). In some aspects, the dielectric material may be referred to as a high-Îº dielectric.

In aspects, the gate region 120 includes an upper surface 128 and a bottom surface 130 . The upper su

BACKGROUND

Field of the Disclosure

Certain aspects of the present disclosure generally relate to electronic circuits and, more particularly, to a semiconductor device having a backside contact.

Description of Related Art

SUMMARY

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a top view of an example semiconductor device having a backside gate contact, in accordance with certain aspects of the present disclosure.

FIG. 1B is a cross-sectional view taken along line segment AAâ² of FIG. 1A , in accordance with certain aspects of the present disclosure.

FIG. 2 is a cross-sectional view taken along line segment BBâ² of FIG. 1A illustrating the fan-out in different metal layers, in accordance with certain aspects of the present disclosure.

FIG. 4 illustrates a cross-sectional view of an example gate-all-around (GAA) transistor with a backside gate contact, in accordance with certain aspects of the present disclosure.

FIG. 5 illustrates an isometric view of an example of the GAA transistor of FIG. 4 , in accordance with certain aspects of the present disclosure.

FIGS. 6-12 illustrate various top and cross-sectional views of example operations for fabricating a semiconductor device, in accordance with certain aspects of the present disclosure.

FIG. 13 is a flow diagram of example operations for fabricating a semiconductor device, in accordance with certain aspects of the present disclosure.

DETAILED DESCRIPTION

Aspects of the present disclosure generally relate to a semiconductor device having backside contacts and various methods for fabricating such a semiconductor device.

Example Backside Contact

In aspects, the transistor 102 may be formed during a front-end-of-line (FEOL) fabrication process. The frontside aspects (including the frontside contacts

In aspects, the gate region 120 includes an upper surface 128 and a bottom surface 130 . The upper surface 128 of the gate region 120 may be disposed above the substrate 104 and coupled to the frontside contacts 109 , and the bottom surface 130 of the gate region 120 may be embedded in the substrate 104 and coupled to the backside gate contacts 106 . That is, the backside gate contacts 106 may engage the bottom surface 130 of the gate region 120 .

In aspects, the gate region 120 wraps around a portion of an upper surface 140 , a portion of a first lateral surface 144 , and a portion of a second lateral surface 146 of the channel region 122 . As shown, the channel region 122 may also have a bottom surface 142 disposed below the upper surface 140 . In certain aspects, the gate region 120 comprises a first portion 148 disposed above the portion of the upper surface 140 of the channel region 122 , a second portion 150 extending orthogonally from the first portion 148 and disposed adjacent to the portion of the first lateral surface 144 of the channel region 122 , and a third portion 152 extending orthogonally from the first portion 148 and disposed adjacent to the portion of the second lateral surface 146 of the channel region 122 . The backside gate contacts 106 may be electrically coupled to a bottom surface 130 of the second and/or third portions 150 , 152 of the gate region 120 .

In aspects, a conductive layer 132 (e.g., tungsten (W)) may be disposed above the gate region 120 . The conductive layer 132 may be electrically coupled between the gate region 120 and the frontside contacts 109 .

In aspects, the gate region 120 may be disposed between gate spacers 134 . In certain aspects, the gate spacers 134 may serve as a mold for forming the gate region 120 .

As shown, the gate region 120 is disposed adjacent to the channel region 122 . For example, the gate region 120 may surround a portion of the semiconductor fin structures of the channel region 122 . In certain cases, for example, where the transistor 102 is a GAA FET, the gate region 120 may wrap around the channel region 122 , as further described herein with respect to FIGS. 4A and 4B .

Referring to FIG. 1A , the source and drain regions

124 , 126 may be adjacent to the gate region 120 , such that the gate region 120 is disposed between the source and drain regions

124 , 126 . In certain aspects, the transistor 102 may be configured as an n-type metal-oxide-semiconductor (NMOS) transistor. For example, the source region 124 and drain region 126 of the transistor 102 may be n+ doped semiconductors. In other aspects, the transistor 102 may be a p-type MOS (PMOS) transistor. For example, the source region 124 and drain region 126 of the transistor 102 may be p+ doped semiconductors.

The substrate 104 may be, for example, a portion of a semiconductor wafer including a silicon wafer. In certain aspects, the substrate 104 may be a silicon-on-insulator (SOI) substrate having an electrical insulator layer disposed between layers of silicon, for example, as further described herein with respect to FIG. 6 . In aspects, the insulator layer may include a dielectric region, which may be composed of any of various suitable electrically insulating materials, such as silicon dioxide (SiO 2 ).

The substrate 104 may have an upper surface 136 and a bottom surface 138 . The frontside dielectric layers 110 may be disposed above the upper surface 136 of the substrate 104 , and the backside dielectric layers 114 may be disposed below the bottom surface 138 of the substrate 104 .

The backside gate contacts 106 may be electrically conductive local interconnects disposed below the transistor 102 and electrically coupled to the gate region 120 of the transistor 102 . The backside gate contacts 106 may enable improved electrical routing approaches for the semiconductor device 100 . For example, the backside gate contacts 106 may facilitate electrical routing to decoupling capacitors or other passive components attached on the landside (or die-side) of the semiconductor device 100 . In certain cases, the backside gate contacts 106 may enable electrical routing to a power distribution network that enters via the landside (or die-side) of the semiconductor device 100 . In certain cases, the backside gate contacts 106 may improve the performance of the semiconductor device, for example, by reducing parasitic losses encountered with electrical routing on the frontside.

The frontside contacts

108 and 109 may be electrically conductive interconnects disposed above the transistor 102 and electrically coupled to the transistor 102 . For example, as shown in FIG. 1A , the source and/or drain regions

124 , 126 of the transistor 102 may be electrically coupled to the frontside contacts 108 . As shown in FIG. 1B , the gate region 120 may be electrically coupled to the frontside contacts 109 .

The frontside conductive traces 112 are disposed above the transistor 102 . The frontside conductive traces 112 may be electrically coupled to the transistor 102 via the frontside contacts 109 . In aspects, additional layers of frontside conductive traces (not shown) may be disposed above the transistor 102 , for example, as depicted in FIG. 2 .

The frontside dielectric layers 110 are disposed above the transistor 102 and/or the substrate 104 . The frontside contacts

108 and 109 and frontside conductive traces 112 may be embedded in the frontside dielectric layers 110 . In aspects, the frontside dielectric layers 110 may comprise an oxide, such as silicon dioxide.

The backside conductive traces 116 are disposed below the substrate 104 . The backside conductive traces 116 may be electrically coupled to the transistor 102 via the backside gate contacts 106 . The backside conductive vias 118 are disposed between layers of the backside conductive traces 116 and below the substrate 104 . The backside conductive vias 118 may include an electrically conductive material.

The backside dielectric layers 114 are disposed below the substrate 104 . The backside conductive traces 116 and backside conductive vias 118 may be embedded in the backside dielectric layers 114 . In aspects, the backside dielectric layers 114 may comprise an oxide, such as silicon dioxide.

The various conductors (such as the frontside and backside traces, vias, and contacts) provide electrical routing between the transistor 102 and other electrical components (not shown), including, for example, other transistors, capacitors, inductors, resistors, an integrated passive device, a power management IC (PMIC), a memory chip, etc.

In aspects, the semiconductor device 100 may be a flip-chip ball grid array (FC-BGA) integrated circuit having multiple solder bumps (not shown) electrically coupled to under-bump conductive pads (not shown). In aspects, the under-bump conductive pads may be disposed above the various frontside conductors or below the various backside conductors. In certain cases, the semiconductor device 100 may have conductive pillars (e.g., copper (Cu) pillars) that electrically couple the semiconductor device 100 to a package substrate, an interposer, or a circuit board, for example.

In certain aspects, the backside gate contacts 106 may directly engage the channel region 122 . For example, the backside gate contacts 106 may engage the bottom surface 142 of the channel region 122 . In such a case, the backside gate contact 106 may facilitate forming a bipolar junction transistor (BJT).

FIG. 2 illustrates the semiconductor device 100 across the cross-section BBâ² as depicted in FIG. 1A . As shown in FIG. 2 , the backside gate contact 106 is electrically coupled to the gate region 120 and extends below the substrate 104 .

In certain aspects, the backside conductive traces 116 may be electrically coupled to other backside contacts, such as a backside contact 206 . Referring to FIG. 2 , the backside contact 206 may be laterally spaced from the backside gate contact 106 and extend below the substrate 104 . In aspects, the backside contact 206 may be an electrically conductive local interconnect that intersects the substrate 104 . The backside contact 206 may be electrically coupled to a frontside contact 208 , which is disposed above the backside contact 206 . The frontside contact 208 may be disposed above the substrate 104 and electrically coupled to the frontside conductive traces 112 .

In this example, frontside conductive vias 214 are disposed between layers of the frontside conductive traces 112 and above the substrate 104 .

In certain aspects, the backside contact 206 may be electrically coupled to a source or drain of the transistor 102 or of another transistor. For example, FIG. 3 illustrates another portion of the semiconductor device 100 across a cross-section orthogonal to that of the cross-section depicted in FIG. 2 . Referring to FIG. 3 , the backside contact 206 is electrically coupled to a source region 340 of a second transistor 302 . The second transistor 302 includes a channel region 310 , a gate region 320 , the source region 340 , and a drain region 342 . The drain region 342 of the second transistor 302 may be electrically coupled to a frontside contact 308 , which is disposed above the drain region 342 . The frontside contact 308 may be electrically coupled to the frontside conductive traces 112 . The second transistor 302 may function as an electrical switch between the backside contact 206 and the frontside contact 308 .

In aspects, a backside gate contact 306 may be disposed below the channel region 310 of the second transistor 302 and extend below the substrate 104 . A portion of the substrate may be disposed between the channel region 310 and the backside gate contact 306 . In aspects, the backside gate contact 306 may serve as a gate terminal of the second transistor 302 disposed below the channel region 310 .

In certain aspects, a backside gate contact may be coupled to the gate region of a GAA transistor. For example, FIG. 4 illustrates an example of a semiconductor device 400 that has a backside gate contact coupled to a gate region of a GAA transistor, in accordance with certain aspects of the present disclosure. As shown, the semiconductor device 400 includes a GAA transistor 402 , a substrate 404 , and a backside gate contact 406 .

In aspects, the GAA transistor 402 may be disposed above the substrate 404 . The GAA transistor 402 may include a stack structure 408 , a gate region 410 , a source region 412 , and a drain region 414 . The stack structure 408 may in

CLAIMS

Claims ( 20 )

The invention claimed is:

1. A semiconductor device comprising:

a transistor disposed above a substrate, wherein the transistor comprises a gate region, a channel region, a source region, and a drain region, wherein the gate region is disposed adjacent to the channel region, and wherein the gate region comprises:

a first portion disposed above a portion of an upper surface of the channel region; and

a second portion extending orthogonally from the first portion and disposed adjacent to a portion of a first lateral surface of the channel region; and

a backside gate contact that is electrically coupled to a bottom surface of the second portion of the gate region and that extends below a bottom surface of the substrate.

2. The semiconductor device of claim 1 , wherein the gate region wraps around the portion of the upper surface, the portion of the first lateral surface, and a portion of a second lateral surface of the channel region.

3. The semiconductor device of claim 2 , wherein:

the gate region further comprises a third portion extending orthogonally from the first portion and disposed adjacent to the portion of the second lateral surface of the channel regio; and

the backside gate contact is electrically coupled to a bottom surface of the third portion of the gate region.

4. The semiconductor device of claim 1 , wherein the gate region comprises polycrystalline silicon.

5. The semiconductor device of claim 1 , wherein the transistor is a fin field-effect transistor (finFET).

6. The semiconductor device of claim 1 , wherein the channel region includes one or more semiconductor fin structures.

7. The semiconductor device of claim 1 , wherein the transistor is a gate-all-around transistor.

8. The semiconductor device of claim 7 , wherein the channel region includes one or more nanosheets that intersect the gate region.

9. The semiconductor device of claim 1 , further comprising another backside contact electrically coupled to the source region or the drain region, wherein the other backside contact intersects a portion of the substrate and extends below the bottom surface of the substrate.

10. The semiconductor device of claim 1 , further comprising a frontside gate contact electrically coupled to the gate region and disposed above the gate region.

11. A method of fabricating a semiconductor device, comprising:

forming a transistor above a substrate, wherein the transistor comprises a gate region, a channel region, a source region, and a drain region, wherein the gate region is adjacent to the channel region, and wherein the gate region comprises:

a first portion disposed above a portion of an upper surface of the channel region; and

a second portion extending orthogonally from the first portion and disposed adjacent to a portion of a first lateral surface of the channel region; and

forming a backside gate contact that is electrically coupled to a bottom surface of the second portion of the gate region and that extends below a bottom surface of the substrate.

12. The method of claim 11 , wherein forming the transistor comprises:

forming the channel region from a semiconductor region disposed above the substrate; and

forming the gate region that wraps around the portion of the upper surface, the portion of the first lateral surface, and a portion of a second lateral surface of the channel region.

13. The method of claim 11 , wherein forming the backside gate contact comprises forming the backside gate contact below the gate region of the transistor.

14. The method of claim 13 , wherein forming the backside gate contact comprises:

forming dielectric layers above another substrate;

forming the backside gate contact in the dielectric layers; and

coupling the dielectric layers and the backside gate contact to the bottom surface of the substrate.

15. The method of claim 11 , wherein forming the transistor comprises forming the gate region using polycrystalline silicon.

16. The method of claim 11 , wherein forming the transistor comprises forming a fin field-effect transistor (finFET).

17. The method of claim 11 , wherein forming the transistor comprises forming the channel region as a fin structure disposed above the substrate.

18. The method of claim 11 , wherein forming the transistor comprises forming a gate-all-around transistor.

19. The method of claim 11 , wherein forming the transistor comprises forming the channel region as one or more nanosheets that intersect the gate region.

20. The method of claim 11 , further comprising forming another backside contact electrically coupled to the source region or the drain region, wherein the other backside contact intersects a portion of the substrate.

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