ABSTRACT
Abstract
A FET IC structure made using a back-side access process that mitigates or eliminates thermal conductivity problems. In some embodiments, electrically-isolated thermal paths are formed adjacent the FET and configured to conduct heat laterally away from the FET to generally orthogonal thermal pathways, and thence to thermal pads externally accessible at the âtopâ of the completed IC. In some embodiments having a thermally-conductive handle wafer, electrically-isolated thermal paths are formed adjacent a FET and configured to conduct heat laterally away from the FET. Thermal vias are formed sufficiently so as to be in thermal contact with the handle wafer and with the conventional metallization layers of the device superstructure, at least one of which is in thermal contact with the lateral thermal paths. In some embodiments, the lateral thermal paths may use dummy gates configured to conduct heat laterally away from a FET to generally orthogonal thermal pathways.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS AND CLAIM OF PRIORITY
The present application is a continuation of International Patent Application No. PCT/US2019/041898 filed on Jul. 15, 2019, which in turn is a continuation of U.S. Non-Provisional application Ser. No. 16/040,295, filed on Jul. 19, 2018 for âThermal Extraction of Single Layer Transfer Integrated Circuitsâ, issuing as U.S. Pat. No. 10,658,386 on May 19, 2020, the disclosures of which are incorporated herein by reference in their entirety.
The present application may be related to the following patents and patent applications, the contents of all of which are incorporated herein by reference in their entirety:
U.S. patent application Ser. No. 15/920,321, filed Mar. 13, 2018, entitled âSemiconductor-on-Insulator Transistor with Improved Breakdown Characteristicsâ; U.S. Pat. No. 9,837,412, issued Dec. 5, 2017, entitled âS-Contact for SOIâ; U.S. Pat. No. 9,960,098, issued May 1, 2018, entitled âSystems and Methods for Thermal Conduction Using S-Contactsâ; U.S. Pat. No. 10,276,371, issued Apr. 30, 2019, entitled âManaged Substrate Effects for Stabilized SOI FETsâ; U.S. patent application Ser. No. 16/040,411, filed Jul. 19, 2018, entitled âHigh-Q Integrated Circuit Inductor Structure and Methodsâ; and U.S. patent application Ser. No. 16/040,390, filed Jul. 19, 2018, entitled âSLT Integrated Circuit Capacitor Structure and Methodsâ.
BACKGROUND
(1) Technical Field
This invention relates to electronic integrated circuits, and more particularly to electronic integrated circuits having transistors fabricated with semiconductor-on-insulator technology.
(2) Background
Virtually all modern electronic productsâincluding laptop computers, mobile telephones, and electric carsâutilize complementary metal oxide semiconductor (CMOS) transistor integrated circuits (ICs), and in many cases CMOS ICs fabricated using a semiconductor-on-insulator process, such as silicon-on-insulator (SOI) or germanium-on-insulator. SOI transistors in which the electrical insulator is aluminum oxide (i.e., sapphire) are called silicon-on-sapphire or âSOSâ devices. Another example of a semiconductor-on-insulator technology is âsilicon-on-glassâ, and other examples are known to those of ordinary skill in the art.
Taking SOI as one example of semiconductor-on-insulator, SOI technology encompasses the use of a layered silicon-insulator-silicon substrate in place of conventional âbulkâ silicon substrates in semiconductor manufacturing. More specifically, SOI transistors are generally fabricated on a layer of silicon dioxide, SiO 2 (often called a âburied oxideâ or âBOXâ layer) formed on a bulk silicon substrate. The BOX layer reduces certain parasitic effects typical of bulk silicon CMOS processes, thereby improving performance. SOI-based devices thus differ from conventional bulk silicon devices in that the silicon regions of the CMOS transistors are fabricated on an electrical insulator (typically silicon dioxide or aluminum oxide) rather than on a bulk silicon substrate.
As a specific example of a semiconductor on insulator process for fabricating ICs, FIG. 1A is a stylized cross-sectional view of a typical prior art SOI IC structure 100 for a single metal-oxide-semiconductor (MOS) field effect transistor (FET), or MOSFET. The SOI structure 100 includes a substrate 102 , a buried-oxide (BOX) insulator layer 104 , and an active layer 106 (note that the dimensions for the elements of the SOI IC structure 100 are not to scale; some dimensions have been exaggerated for clarity or emphasis). The substrate 102 is typically a semiconductor material such as silicon. The BOX layer 104 is a dielectric, and is often SiO 2 formed as a âtopâ surface 102 T of the silicon substrate 102 , such as by oxidation, layer transfer, or implantation. The active layer 106 may include some combination of implants and/or layers that include dopants, dielectrics, polysilicon, metal wiring, passivation, and other materials to form active and/or passive electronic components and/or mechanical structures. For example, in the illustrated embodiment, a FET (encircled by a dashed oval 108 ) is shown, with the FET 108 comprising a source S, a drain D, and a primary gate G atop an insulating gate oxide (GOX) layer 110 . A body B is defined below the primary gate G, between the source S and the drain D. In typical operation (e.g., an enhancement-mode MOSFET), a âconduction channelâ (also called an âinversion channelâ) is generated within the body B between the source S and the drain D and proximate the GOX layer 110 (e.g., within about the top 100 â« of the body B). A body contact (not shown), which generally comprises a region with the same doping as the body B, may be resistively coupled to the body B through an extension of the semiconductor island typically extending in the width direction of the transistor (in FIG. 1A , that would be in/out of the plane of the image) to provide a fourth terminal to the FET 108 . As is known, the body contact is commonly coupled to a bias node such as a power supply, to circuit ground, or to the source S (although other connection nodes are possible). If an SOI transistor has a body contact, it is known as body-contacted transistor, otherwise it is known as a floating-body transistor.
If the source S and drain D are highly doped with N type material, the FET is an N-type FET, or NMOS device. Conversely, if the source S and drain D are highly doped with P type material, the FET is a P-type FET, or PMOS device. Thus, the source S and drain D doping type determines whether a FET is an N-type or a P-type. CMOS devices comprise N-type and P-type FETs co-fabricated on a single IC die, in known fashion. The gate G is typically formed from polysilicon.
A superstructure 112 of various elements, regions, and structures may be fabricated in known fashion above the FET 108 in order to implement particularly functionality. The superstructure 112 may include, for example, conductive interconnections from the illustrated FET 108 to other components (including other FETs) and/or external contacts, passivation layers and regions, and protective coatings. The conductive interconnections may be, for example, copper or other suitable metal or electrically conductive material.
For example, FIG. 1B is a stylized cross-sectional view of a typical prior art SOI IC structure 120 for a single FET, showing details of the superstructure 112 . In this example, the superstructure 112 includes conductive (e.g., metal) interconnect levels M1 (closest to the FET 108 ), M2, M3, M4, and M5 (in this example, the âtop metalâ), separated in places by insulating and/or passivation layers or regions (generally indicated as âoxideâ, but other materials may be used); as is known in the art, more or fewer than five interconnect levels may be used. The M5 layer may be covered in whole or in part by another conductive material (commonly aluminum) to form what is commonly known as a âredistribution layerâ, or RDL, shown in FIG. 1B as within a sub-portion 112 â² of the superstructure 112 . Top-side RDLs are generally added near the end of or even after the CMOS fabrication process and are often of much thicker and wider dimensions than the CMOS metallization (e.g., M1-M5 layers). Top-side RDLs are often used to distribute high current power around an IC chip or to render high-Q inductors (and sometimes capacitors) for RF circuits. As can be seen in FIG. 1B , top-side RDLs are often connected to the M5 layer of the IC for subsequent packaging. An aluminum layer may also be used as a capping layer over final copper metal structures, which generally cannot be left exposed in order to avoid oxidation of the copper. Thus, an aluminum layer may be both an RDL and a capping layer.
Other elements, regions, and structures may be included for particular circuit designs. For example, referring to FIG. 1A , conductive substrate contact (S-contacts) (shown as the structure âSCâ) may be formed from the superstructure 112 through the active layer 106 to the BOX layer 104 or to conductive regions or wells formed in and/or above the BOX layer 104 . S-contacts may be used, for example, to mitigate accumulated charge effects that adversely affect the FET, for shielding, and/or for thermal conduction. Examples of applications of S-contacts are set forth in U.S. Pat. No. 9,837,412, issued Dec. 5, 2017, entitled âS-Contact for SOIâ, in U.S. patent application Ser. No. 15/194,114, filed Jun. 27, 2016, entitled âSystems and Methods for Thermal Conduction Using S-Contactsâ, and in U.S. patent application Ser. No. 15/600,588, filed May 19, 2017, entitled âManaged Substrate Effects for Stabilized SOI FETsâ, all of which are hereby incorporated by reference.
As should be appreciated by one of ordinary skill in the art, a single IC die may embody from one electronic componentâsuch as FET 108 âto millions of electronic components. Further, the various elements of the superstructure 112 may extend in three-dimensions and have quite complex shapes. In general, the details of the superstructure 112 will vary from IC design to IC design.
The BOX layer 104 , while enabling many beneficial characteristics for SOI IC's, also introduces some problems, such as capacitive coupling to the substrate 102 , a thermal barrier to heat flow, and a voltage breakdown path to the substrate 102 . Capacitive coupling with the substrate 102 alone can cause numerous side effects compared to an ideal SOI transistor, such as increased leakage current, lower breakdown voltage, signal cross-coupling, and linearity degradation. However, the most serious capacitive coupling effect caused by the BOX layer 104 is often the âback-channelâ effect.
Referring back to FIG. 1A , the structure of a secondary parasitic back-channel FET (shown in a dashed square 120 ) is formed by the source S, the drain D, the BOX layer 104 (functioning as a gate insulator), and the substrate 102 (effectively functioning as a secondary gate). FIG. 1C is an equivalent schematic diagram of the FET structure shown in FIG. 1A , showing how the secondary parasitic back- channel FET 120 is coupled in parallel with the primary FET 108 . Notably, the voltages and charge accumulations in and around the secondary gate (i.e., the substrate 102 ) may vary and in general are not well controlled. Accordingly, as is widely known, the presence of the secondary parasitic back- channel FET 120 adjacent the FET 108 can place the bottom of the FET 108 in uncontrolled states, often in a subthreshold leakage regime, which in turn may create uncontrollable source-drain leakage currents.
It is possible to mitigate some of the side effects of the secondary parasitic back- channel FET 120 . One known mitigating technique utilizes âsingle layer transferâ, or SLT, as part of the IC fabrication process. The SLT pro
CROSS-REFERENCE TO RELATED APPLICATIONS AND CLAIM OF PRIORITY
The present application is a continuation of International Patent Application No. PCT/US2019/041898 filed on Jul. 15, 2019, which in turn is a continuation of U.S. Non-Provisional application Ser. No. 16/040,295, filed on Jul. 19, 2018 for âThermal Extraction of Single Layer Transfer Integrated Circuitsâ, issuing as U.S. Pat. No. 10,658,386 on May 19, 2020, the disclosures of which are incorporated herein by reference in their entirety.
The present application may be related to the following patents and patent applications, the contents of all of which are incorporated herein by reference in their entirety:
U.S. patent application Ser. No. 15/920,321, filed Mar. 13, 2018, entitled âSemiconductor-on-Insulator Transistor with Improved Breakdown Characteristicsâ; U.S. Pat. No. 9,837,412, issued Dec. 5, 2017, entitled âS-Contact for SOIâ; U.S. Pat. No. 9,960,098, issued May 1, 2018, entitled âSystems and Methods for Thermal Conduction Using S-Contactsâ; U.S. Pat. No. 10,276,371, issued Apr. 30, 2019, entitled âManaged Substrate Effects for Stabilized SOI FETsâ; U.S. patent application Ser. No. 16/040,411, filed Jul. 19, 2018, entitled âHigh-Q Integrated Circuit Inductor Structure and Methodsâ; and U.S. patent application Ser. No. 16/040,390, filed Jul. 19, 2018, entitled âSLT Integrated Circuit Capacitor Structure and Methodsâ.
BACKGROUND
(1) Technical Field
This invention relates to electronic integrated circuits, and more particularly to electronic integrated circuits having transistors fabricated with semiconductor-on-insulator technology.
(2) Background
Virtually all modern electronic productsâincluding laptop computers, mobile telephones, and electric carsâutilize complementary metal oxide semiconductor (CMOS) transistor integrated circuits (ICs), and in many cases CMOS ICs fabricated using a semiconductor-on-insulator process, such as silicon-on-insulator (SOI) or germanium-on-insulator. SOI transistors in which the electrical insulator is aluminum oxide (i.e., sapphire) are called silicon-on-sapphire or âSOSâ devices. Another example of a semiconductor-on-insulator technology is âsilicon-on-glassâ, and other examples are known to those of ordinary skill in the art.
Taking SOI as one example of semiconductor-on-insulator, SOI technology encompasses the use of a layered silicon-insulator-silicon substrate in place of conventional âbulkâ silicon substrates in semiconductor manufacturing. More specifically, SOI transistors are generally fabricated on a layer of silicon dioxide, SiO 2 (often called a âburied oxideâ or âBOXâ layer) formed on a bulk silicon substrate. The BOX layer reduces certain parasitic effects typical of bulk silicon CMOS processes, thereby improving performance. SOI-based devices thus differ from conventional bulk silicon devices in that the silicon regions of the CMOS transistors are fabricated on an electrical insulator (typically silicon dioxide or aluminum oxide) rather than on a bulk silicon substrate.
As a specific example of a semiconductor on insulator process for fabricating ICs, FIG. 1A is a stylized cross-sectional view of a typical prior art SOI IC structure 100 for a single metal-oxide-semiconductor (MOS) field effect transistor (FET), or MOSFET. The SOI structure 100 includes a substrate 102 , a buried-oxide (BOX) insulator layer 104 , and an active layer 106 (note that the dimensions for the elements of the SOI IC structure 100 are not to scale; some dimensions have been exaggerated for clarity or emphasis). The substrate 102 is typically a semiconductor material such as silicon. The BOX layer 104 is a dielectric, and is often SiO 2 formed as a âtopâ surface 102 T of the silicon substrate 102 , such as by oxidation, layer transfer, or implantation. The active layer 106 may include some combination of implants and/or layers that include dopants, dielectrics, polysilicon, metal wiring, passivation, and other materials to form active and/or passive electronic components and/or mechanical structures. For example, in the illustrated embodiment, a FET (encircled by a dashed oval 108 ) is shown, with the FET 108 comprising a source S, a drain D, and a primary gate G atop an insulating gate oxide (GOX) layer 110 . A body B is defined below the primary gate G, between the source S and the drain D. In typical operation (e.g., an enhancement-mode MOSFET), a âconduction channelâ (also called an âinversion channelâ) is generated within the body B between the source S and the drain D and proximate the GOX layer 110 (e.g., within about the top 100 â« of the body B). A body contact (not shown), which generally comprises a region with the same doping as the body B, may be resistively coupled to the body B through an extension of the semiconductor island typically extending in the width direction of the transistor (in FIG. 1A , that would be in/out of the plane of the image) to provide a fourth terminal to the FET 108 . As is known, the body contact is commonly coupled to a bias node such as a power supply, to circuit ground, or to the source S (although other connection nodes are possible). If an SOI transistor has a body contact, it is known as body-contacted transistor, otherwise it is known as a floating-body transistor.
If the source S and drain D are highly doped with N type material, the FET is an N-type FET, or NMOS device. Conversely, if the source S and drain D are highly doped with P type material, the FET is a P-type FET, or PMOS device. Thus, the source S and drain D doping type determines whether a FET is an N-type or a P-type. CMOS devices comprise N-type and P-type FETs co-fabricated on a single IC die, in known fashion. The gate G is typically formed from polysilicon.
A superstructure 112 of various elements, regions, and structures may be fabricated in known fashion above the FET 108 in order to implement particularly functionality. The superstructure 112 may include, for example, conductive interconnections from the illustrated FET 108 to other components (including other FETs) and/or external contacts, passivation layers and regions, and protective coatings. The conductive interconnections may be, for example, copper or other suitable metal or electrically conductive material.
For example, FIG. 1B is a stylized cross-sectional view of a typical prior art SOI IC structure 120 for a single FET, showing details of the superstructure 112 . In this example, the superstructure 112 includes conductive (e.g., metal) interconnect levels M1 (closest to the FET 108 ), M2, M3, M4, and M5 (in this example, the âtop metalâ), separated in places by insulating and/or passivation layers or regions (generally indicated as âoxideâ, but other materials may be used); as is known in the art, more or fewer than five interconnect levels may be used. The M5 layer may be covered in whole or in part by another conductive material (commonly aluminum) to form what is commonly known as a âredistribution layerâ, or RDL, shown in FIG. 1B as within a sub-portion 112 â² of the superstructure 112 . Top-side RDLs are generally added near the end of or even after the CMOS fabrication process and are often of much thicker and wider dimensions than the CMOS metallization (e.g., M1-M5 layers). Top-side RDLs are often used to distribute high current power around an IC chip or to render high-Q inductors (and sometimes capacitors) for RF circuits. As can be seen in FIG. 1B , top-side RDLs are often connected to the M5 layer of the IC for subsequent packaging. An aluminum layer may also be used as a capping layer over final copper metal structures, which generally cannot be left exposed in order to avoid oxidation of the copper. Thus, an aluminum layer may be both an RDL and a capping layer.
Other elements, regions, and structures may be included for particular circuit designs. For example, referring to FIG. 1A , conductive substrate contact (S-contacts) (shown as the structure âSCâ) may be formed from the superstructure 112 through the active layer 106 to the BOX layer 104 or to conductive regions or wells formed in and/or above the BOX layer 104 . S-contacts may be used, for example, to mitigate accumulated charge effects that adversely affect the FET, for shielding, and/or for thermal conduction. Examples of applications of S-contacts are set forth in U.S. Pat. No. 9,837,412, issued Dec. 5, 2017, entitled âS-Contact for SOIâ, in U.S. patent application Ser. No. 15/194,114, filed Jun. 27, 2016, entitled âSystems and Methods for Thermal Conduction Using S-Contactsâ, and in U.S. patent application Ser. No. 15/600,588, filed May 19, 2017, entitled âManaged Substrate Effects for Stabilized SOI FETsâ, all of which are hereby incorporated by reference.
As should be appreciated by one of ordinary skill in the art, a single IC die may embody from one electronic componentâsuch as FET 108 âto millions of electronic components. Further, the various elements of the superstructure 112 may extend in three-dimensions and have quite complex shapes. In general, the details of the superstructure 112 will vary from IC design to IC design.
The BOX layer 104 , while enabling many beneficial characteristics for SOI IC's, also introduces some problems, such as capacitive coupling to the substrate 102 , a thermal barrier to heat flow, and a voltage breakdown path to the substrate 102 . Capacitive coupling with the substrate 102 alone can cause numerous side effects compared to an ideal SOI transistor, such as increased leakage current, lower breakdown voltage, signal cross-coupling, and linearity degradation. However, the most serious capacitive coupling effect caused by the BOX layer 104 is often the âback-channelâ effect.
Referring back to FIG. 1A , the structure of a secondary parasitic back-channel FET (shown in a dashed square 120 ) is formed by the source S, the drain D, the BOX layer 104 (functioning as a gate insulator), and the substrate 102 (effectively functioning as a secondary gate). FIG. 1C is an equivalent schematic diagram of the FET structure shown in FIG. 1A , showing how the secondary parasitic back- channel FET 120 is coupled in parallel with the primary FET 108 . Notably, the voltages and charge accumulations in and around the secondary gate (i.e., the substrate 102 ) may vary and in general are not well controlled. Accordingly, as is widely known, the presence of the secondary parasitic back- channel FET 120 adjacent the FET 108 can place the bottom of the FET 108 in uncontrolled states, often in a subthreshold leakage regime, which in turn may create uncontrollable source-drain leakage currents.
It is possible to mitigate some of the side effects of the secondary parasitic back- channel FET 120 . One known mitigating technique utilizes âsingle layer transferâ, or SLT, as part of the IC fabrication process. The SLT process essentially flips an entire SOI transistor structure upside down onto a âhandle waferâ, with the original substrate (e.g., substrate 102 in FIG. 1A ) then being removed, thereby eliminating the substrate 102 . For example, FIG. 2 is a stylized cross-sectional view of a typical prior art SOI IC structure 100 for a single FET, fabricated using an SLT process. Essentially, after most or all of the superstructure 112 of FIGS. 1A and 1B is completed, a first passivation layer 202 (e.g., SiO 2 ) is generally applied on top of the superstructure 112 , and then the original substrate 102 and the layers denoted as âXâ in FIG. 1A are flipped over and attached or bonded in known fashion to a handle wafer 204 , as shown in FIG. 2 . The handle wafer 204 is typically silicon with a bonding layer of SiO 2 (e.g., thermally grown oxide) on the surface facing the first passivation layer 202 . Thereafter, the original substrate 102 is removed (e.g., by mechanical and/or chemical means), thus exposing the BOX layer 104 . A non-conductive second passivation layer 206 , which may be a conventional interlayer dielectric (ILD) material, may be formed on the exposed BOX layer 104 .
In the structure of FIG. 2 , the portions of the FET 108 formerly closest to the original substrate 102 are now found near the ânew topâ of the IC structure, farthest away from the handle wafer 204 . Conversely, those portions of the FET 108 formerly farthest away from the original substrate 102 are now found in the interior of the IC structure, situated closest to the handle wafer 204 . Consequently, the gate G (and thus connections to the gate) of the FET 108 is now oriented towards the handle wafer 204 , and the BOX layer 104 in the structure of FIGS. 1A and 1B âpreviously adjacent to the original substrate 102 âis now very close to the ânew topâ of the IC structure.
Although not exactly to scale, the BOX layer 104 in FIG. 1A exhibits relatively high capacitive coupling to the original substrate 102 , causing the above-mentioned side effects. Referring to FIG. 2 , while the BOX layer 104 is still present with the inverted IC structure, the âbacksideâ of the FET 108 is now near the ânew topâ of the IC structure, but with no adjacent semiconductive âbackside gateâ material (i.e., the original substrate 102 ).
While the IC structure of FIG. 2 may be preferred to the closely coupled substrate IC structure of FIG. 1A , where the original substrate 102 serves as a gate for the secondary parasitic back- channel FET 120 , the electrical characteristics of the regions of the FET 108 adjacent the BOX layer 104 are still not well controlled. Further, while SOI FETs have been used in the examples above, similar problems exist in other semiconductor-on-insulator technologies.
The problems caused by the secondary parasitic back-channel FET of conventional FET IC structures are mitigated or eliminated by the structures and methods taught in co-pending and commonly owned U.S. patent application Ser. No. 15/920,321, referenced above. Embodiments of that invention enable full control of the secondary parasitic back-channel FET of semiconductor-on-insulator IC primary FETs by fabricating such ICs using a process which allows access to the backside of the FET, such as an SLT process (collectively, a âback-side access processâ). Thereafter, a conductive aligned supplemental (CAS) gate structure is fabricated relative to the BOX layer and juxtaposed to a primary FET such that a control voltage applied to the CAS gate can regulate the electrical characteristics of the regions of the primary FET adjacent the BOX layer. Such a FET may also be referred to as a âCAS-gated FETâ.
While the disclosure in U.S. patent application Ser. No. 15/920,321 mitigates or eliminates the problems caused by the secondary parasitic back-channel FET of conventional FET IC structures, in some cases, some embodiments exhibit poor thermal conductivity, which can cause reliability, performance, and other problems in an IC. The problem of poor thermal conductivity thus also applies generally to ICs made by a back-side access process, such as the SLT process.
Accordingly, there is a need for a FET IC structure made using a back-side access process that mitigates or eliminates thermal conductivity problems arising from such structures. The present invention addresses these needs and more.
SUMMARY
The present invention encompasses an FET IC structure made using a back-side access process that mitigates or eliminates thermal conductivity problems arising from such structures.
In some embodiments of the invention, during fabrication of a FET made using a back-side access process, one or more electrically-isolated thermal paths are formed adjacent the FET and configured to conduct heat laterally away (e.g., âhorizontallyâ) from the FET to generally orthogonal (e.g., âverticalâ) thermal pathways (e.g., vias or other heat pipes), and thence to corresponding thermal pads externally accessible at the âtopâ of the completed integrated circuit (IC).
In some embodiments of the invention that utilize a thermally-conductive handle wafer, during fabrication of a FET made using a back-side access process, one or more electrically-isolated thermal paths are formed adjacent a FET and configured to conduct heat laterally away from the FET. Thermal vias or pathways are formed sufficiently through a separating passivation layer so as to be in thermal contact with the handle wafer and with the conventional metallization layers of the device superstructure, at least one of which is in thermal contact with the lateral thermal paths. Accordingly, heat is conducted from the FET through the lateral thermal paths, then through the metallization layers and thermal vias to the thermally-conductive handle wafer, and thus to the âbottomâ or âbacksideâ of the completed integrated circuit (IC), which may be placed in thermal contact with a heat sink.
In some embodiments, the lateral thermal paths may use dummy gates specially configured to conduct heat laterally away from a FET to generally orthogonal thermal pathways or interconnection metallization structures.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.
DESCRIPTION OF THE DRAWINGS
FIG. 1A is a stylized cross-sectional view of a typical prior art SOI IC structure for a single metal-oxide-semiconductor (MOS) field effect transistor (FET).
FIG. 1B is a stylized cross-sectional view of a typical prior art SOI IC structure for a single FET, showing details of the superstructure.
FIG. 1C is an equivalent schematic diagram of the FET structure shown in FIG. 1A , showing how the secondary parasitic back-channel FET is coupled in parallel with the primary FET.
FIG. 2 is a stylized cross-sectional view of a typical prior art SOI IC structure for a single FET, fabricated using an SLT process.
FIG. 3A is a stylized cross-sectional view of an SOI IC structure for a single primary FET, showing a CAS gate formed after application of an SLT process.
FIG. 3B is a simplified IC structure essentially corresponding to the IC structure of FIG. 3A , redrawn for enhanced clarity of the various structural elements, with the scale of selected elements enlarged relative to other elements for emphasis.
FIG. 4A is a stylized cross-sectional view of one embodiment of an SOI IC structure for a single FET made using a back-side access process and configured to conduct heat away from the FET to the âtopâ of the IC structure.
FIG. 4B is a top plan view of an SOI IC FET structure at an intermediate stage of fabrication, before applying an SLT process to âflipâ the FET structure.
FIG. 4C is a cross-sectional view of the SOI IC FET structure of FIG. 4B at a later stage of fabrication, taken along dashed line A-B of FIG. 4B .
FIG. 5 is a stylized cross-sectional view of one embodiment of an SOI IC structure for a single FET made using a back-side access process and configured to conduct heat away from the FET to the âbottomâ of the IC structure.
FIG. 6A is a top plan view of a conventional SOI IC FET structure at an intermediate stage of fabrication.
FIG. 6B is a cross-sectional view of the SOI IC FET structure of FIG. 6A at a later stage of fabrication, taken along line A-B of FIG. 6A .
FIG. 7A is a top plan view of a SOI IC FET structure at an intermediate stage of fabrication, including thermally-coupled dummy gates.
FIG. 7B is a âcollapsedâ cross-sectional view of the SOI IC FET structure of FIG. 7A after application of back-side access process, such as SLT.
FIG. 8 is a process flow chart showing one method for making a thermal conduction structure a thermal conduction structure for an integrated circuit transistor device made using a back-side access process and mounted on a handle wafer such that a gate of the transistor device is oriented towards the handle wafer.
Like reference numbers and designations in the various drawings indicate like elements.
DETAILED DESCRIPTION
The present invention encompasses an FET IC structure made using a back-side access process that mitigates or eliminates thermal conductivity problems arising from such structures. Embodiments of the invention are applicable to conductive aligned supplemental (CAS) FET IC structures made in accordance with the teachings of U.S. patent application Ser. No. 15/920,321).
Thermal Conductivity Challenges of CAS-Gated FETs
To better understand the thermal conductivity problems of integrated circuits (ICs) made using a back-side access process (such as an SLT process, and including CAS-gated FET IC structures), it is useful to consider details of how such structures are formed. For convenience, the example below describes a CAS-gated silicon-on-insulator (SOI) FET made using a single layer transfer (SLT) process as one example of a FET made by a back-side access process. While SOI FETs are used in the example below, similar problems exist in other semiconductor-on-insulator technologies.
FIG. 3A is a stylized cross-sectional view of an SOI IC structure 300 for a single primary FET 108 , showing a CAS gate formed after application of an SLT process. FIG. 3B is a simplified IC structure 310 essentially corresponding to the IC structure 300 of FIG. 3A , redrawn for enhanced clarity of the various structural elements, with the scale of selected elements enlarged relative to other elements for emphasis. The IC structures
300 , 310 are in part similar to the SLT wafer of FIG. 2 , except that the second passivation layer 206 of FIG. 2 is modified by the creation of a specially aligned and patterned backside contact pattern (BCP) 302 , which may be formed, for example, using known redistribution layer (RDL) techniques. The BCP 302 is patterned to define the CAS gate, which is at least partially aligned with a corresponding primary FET 108 adjacent the (former) back-channel of the primary FET 108 and electrically isolated from the rest of the BCP 302 . The BCP 302 (and thus the CAS gate) may be formed from aluminum or similar material in the same manner as conventional RDLs are formed on the top-side of the superstructure 112 of non-SLT wafers, such as is shown in FIG. 1B . Note that the new top of the IC structure 300 may be patterned and covered in places with a deposited or formed protective or passivation layer (not shown), which may be, for example, a conventional interlayer dielectric (ILD) material and/or a conventional moisture and contaminant barrier. Further details and examples of how to fabricate such an IC structure are set forth in U.S. patent application Ser. No. 15/920,321.
For the structure shown in FIG. 3A , the passivation layer 202 is a relatively poor thermal conductor. The handle wafer 204 itself is relatively thickâand thus inhibits heat flowâand may be a poor thermal conductor, such as glass. In addition, the superstructure 112 is shown in FIG. 3A as being much thicker than the conductive layer 350 used for the BCP 302 . However, the RDL process used to create the BCP 302 often results in the BCP 302 being much thicker than the superstructure 112 , and thus an inhibitor of heat flow. The non-conductive second passivation layer 206 (typically SiO2) interposed between the FET 108 and the CAS gate is also relatively thick, in addition to being a relatively poor thermal conductor.
Due to the presence of the heat conduction inhibitors that result from the back-side access (e.g., SLT) and CAS-gate fabrication processes, removing heat from a CAS-gated FET 108 can be difficult, leading to degradations to reliability, performance, and other characteristics. This issue is highlighted in FIG. 3A by considering the FET 108 encircled by a dashed oval. The superstructure 112 includes a significant amount of metallization that, in a conventional FET, would be at the top of the IC and aid in conducting heat away from the FET 108 , as shown in FIG. 1B . However, in a FET made by a back-side access process, including a CAS-gated FET structure, the superstructure 112 is butted against the first passivation layer 202 . Accordingly, the passivation layer 202 and the handle wafer 204 inhibit conduction of heat (symbolized by an arrow 360 ) from the FET 108 âdownwardsâ to a heat sink (not shown). In addition, the FET 108 is sandwiched between the superstructure 112 and the combination of the BOX layer 104 , the non-conductive second passivation layer 206 , and the BCP 302 (for a CAS-gated FET), which inhibit conduction of heat (symbolized by an arrow 362 ) from the FET 108 âupwardsâ to a heat sink, such as to open air or a surface-mounted cooling structure (not shown). Moreover, there is no place to put conventional thermal pads to conduct heat away from the FET 108 .
The result is that heat generated by the FET 108 does not readily dissipate, which may cause a severe temperature rise when the FET 108 is operated in a high power mode, such as in a power amplifier (PA). Some embodiments of conventional SLT SOI FETs have shown temperature increases of 76%-135% when compared to conventional non-SLT SOI FETs.
Relative Dimensions and Orientations in the Drawings
With respect to the figures referenced in the examples below, note that the dimensions for the various elements are not to scale; some dimensions have been exaggerated vertically and/or horizontally for clarity or emphasis. In addition, references to orientations and directions (e.g., âtopâ, âbottomâ, âaboveâ, âbelowâ, âlateralâ, âorthogonalâ etc.) are relative to the example drawings, and not necessarily absolute orientations or directions.
First Example Embodiment
In some embodiments of the invention, during fabrication of a FET made using a back-side access process, one or more electrically-isolated, laterally-extending thermal paths are formed adjacent the FET and configured to conduct heat laterally away (e.g., âhorizontallyâ) from the FET to generally orthogonal (e.g., âverticalâ) thermal pathways (e.g., vias or heat pipes), and thence to corresponding thermal pads externally accessible at the âtopâ of the completed integrated circuit (IC). Such a âtop sideâ thermal extraction configuration is particularly useful for ICs mounted in a âflip-chipâ package.
For example, FIG. 4A is a stylized cross-sectional view of one embodiment of an SOI IC structure 400 for a single FET 402 made using a back-side access process and configured to conduct heat away from the FET 402 to the âtopâ of the IC structure 400 . In the illustrated example, the IC structure 400 is configured with electrically-isolated, laterally-extending thermal paths 404 formed adjacent the FET 402 and configured to conduct heat away from the FET 402 to externally accessible thermal pads 406 . Arrows 408 show the direction of heat flow, initially laterally away from the FET 402 along the laterally-extending thermal paths 404 , and then âupwardsâ to the âtopâ of the IC structure 400 to the externally accessible thermal pads 406 . If desired, the FET 402 can be further processed to become a CAS-gated FET by adding the second passivation layer 206 and CAS gate âaboveâ the BOX layer, as shown in FIGS. 3A and 3B (omitted from FIG. 4A for clarity).
FIG. 4B is a top plan view of an SOI IC FET structure 420 at an intermediate stage of fabrication, before applying an SLT process to âflipâ the FET structure 420 . FIG. 4C is a cross-sectional view of the SOI IC FET structure 420 of FIG. 4B at a later stage of fabrication, taken along dashed line A-B of FIG. 4B . In this example, a silicon island 422 has been formed within a field oxide region 424 . A silicide layer may be formed in a conventional manner on the exposed surface of the silicon island 422 . Within the silicon island 422 , a FET device 402 has been formed. In addition, the silicon island 422 is patterned to create electrically isolating structures 428 to electrically isolate the portion of the silicon island 422 containing the FET device 402 from edge portions
422 a , 422 b of the silicon island 422 . Such electrically isolating structures 428 may be made, for example, using shallow trench isolation (STI), a known technique commonly used for preventing electric current leakage between adjacent semiconductor device components. One STI process involves etching a pattern of trenches in the silicon island 422 , depositing one or more dielectric materials (such as silicon dioxide) to fill the trenches, and removing the excess dielectric using a technique such as chemical-mechanical planarization. However, other techniques may be used for forming the electrically isolating structures 428 , such as local oxidation of the silicon regions between transistors (also known as LOCOS isolation).
During the formation of the first metallization connection layer (commonly called â metal 1â or âM1â) for the IC FET structure 420 , electrical connections 426 are made to the various terminals of the FET device 402 (e.g., source, drain, gate). In addition, in the illustrated example, the M1 layerâwhich is also thermally conductive and patterned over a first interlevel dielectric layer (ILD)âis patterned to form one or more electrically-isolated, laterally-extending thermal paths 404 each comprising (1) a near portion 404 a in thermal contact, through the ILD, with the edge portion
422 a , 422 b adjacent the FET device 402 , and (2) a far portion 404 b spaced away from the edge portions
422 a , 422 b adjacent FET device 402 in a lateral direction (e.g., âhorizontallyâ in FIG. 4C ). The <figure-callout
CLAIMS
Claims ( 21 )
What is claimed is:
1. A thermal conduction structure for an integrated circuit transistor device made using a back-side access process and mounted on a handle wafer such that a gate of the transistor device is oriented towards the handle wafer, including:
(a) at least one dummy gate electrically isolated from the transistor device by a gate oxide and in thermal contact with the transistor device;
(b) at least one thermal path electrically isolated from the transistor device and in thermal contact with at least one dummy gate; and
(c) at least one generally orthogonal thermal pathway thermally coupled to at least one thermal path and configured to convey heat from the at least one thermal path to at least one of (i) at least one externally accessible thermal pad, or (ii) the handle wafer.
2. The invention of claim 1 , wherein the dummy gate comprises polysilicon.
3. The invention of claim 1 , wherein at least one thermal path is formed at least in part by at least one metallization layer overlaying at least a portion of at least one dummy gate and extending laterally from the transistor device.
4. The invention of claim 1 , wherein the integrated circuit transistor device is made using a silicon-on-insulator (SOI) process.
5. A thermal conduction structure for an integrated circuit transistor device, including:
(a) at least one dummy gate electrically isolated from the transistor device by a gate oxide and in thermal contact with the transistor device;
(b) at least one thermal path electrically isolated from the transistor device and in thermal contact with at least one dummy gate, the at least one thermal path configured to convey heat from the transistor device to a heat sink.
6. The invention of claim 5 , wherein the dummy gate comprises polysilicon.
7. The invention of claim 5 , wherein at least one thermal path is formed at least in part by at least one metallization layer overlaying at least a portion of at least one dummy gate and extending laterally from the transistor device.
8. The invention of claim 5 , wherein the integrated circuit transistor device is made using a silicon-on-insulator (SOI) process.
9. A thermal conduction structure for an integrated circuit transistor device, including:
(a) at least one dummy gate electrically isolated from the transistor device by a gate oxide and in thermal contact with the transistor device;
(b) at least one thermal path electrically isolated from the transistor device and in thermal contact with at least one dummy gate; and
(c) at least one generally orthogonal thermal pathway thermally coupled to at least one thermal. path and configured to convey heat from the at least one thermal path.
10. The invention of claim 9 , wherein the dummy gate comprises polysilicon.
11. The invention of claim 9 , wherein at least one thermal path is formed at least in part by at least one metallization layer overlaying at least a portion of at least one dummy gate and extending laterally from the transistor device.
12. The invention of claim 9 , wherein the integrated circuit transistor device is made using a silicon-on-insulator (SOI) process.
13. A thermal conduction structure for an integrated circuit transistor device, including:
(a) a silicon island formed within a field oxide region of a semiconductor wafer structure;
(b) a transistor device formed within a portion of the silicon island;
(c) at least one electrically isolating structure formed within the silicon island, each electrically isolating structure positioned so as to electrically isolate the portion of the silicon island containing the transistor device from an edge portion of the silicon island, each edge portion located in a lateral direction from the transistor device but thermally coupled through a respective electrically isolating structure to the portion of the silicon island containing the transistor device;
(d) an interlevel dielectric layer formed over at least one of the at least one electrically isolating structure;
(e) at least one thermal path having a first portion in thermal contact, through the interlevel dielectric layer, with a respective edge portion of the silicon island, and a second portion spaced away from the respective edge portion of the silicon island in a lateral direction from the transistor device so that the second portion may be coupled to a generally orthogonal thermal pathway without the generally orthogonal thermal pathway being blocked by or interfering with the transistor device, each thermal path being substantially electrically isolated from the transistor device;
(f) a handle wafer affixed to the semiconductor wafer structure such that a gate of the transistor device is oriented towards the handle wafer; and
(g) at least one generally orthogonal thermal pathway thermally coupled to the second portion of a respective one of the at least one thermal path and configured to convey heat from the respective one of the at least one thermal path to at least one of (i) at least one externally accessible thermal pad, or (ii) the handle wafer.
14. The invention of claim 13 , wherein the at least one electrically isolating structure is formed by a shallow trench isolation process.
15. The invention of claim 13 , wherein at least one thermal path is formed at least in part by at least one metallization layer.
16. The invention of claim 13 , wherein the handle wafer is spaced from the transistor device by a passivation layer, and the at least one generally orthogonal thermal pathway includes at least one thermal via formed through the passivation layer so as to be thermally coupled to the handle wafer.
17. The invention of claim 13 , wherein the integrated circuit transistor device is made using a silicon-on-insulator (SOI) process.
18. A thermal conduction structure for an integrated circuit transistor device, including:
(a) a silicon island formed within a field oxide region of a semiconductor wafer structure;
(b) an insulating gate oxide formed over the silicon island;
(c) a transistor device including a gate formed on the insulating gate oxide and a source and a drain formed within a portion of the silicon island;
(d) at least one dummy gate formed on the insulating gate oxide over the silicon island and having a portion extending beyond at least one edge of the silicon island, the at least one dummy gate being electrically isolated from the transistor device and in thermal contact with the transistor device through the insulating gate oxide;
(e) at least one thermally conductive structure formed in thermal contact with the portion of at least one of the at least one dummy gate extending beyond the at least one edge of the silicon island, and electrically isolated from the transistor device;
(f) a handle wafer affixed to the semiconductor wafer structure such that the gate of the transistor device is oriented towards the handle wafer; and
(g) at least one generally orthogonal thermal pathway thermally coupled to a respective one of the at least one thermally conductive structure and configured to convey heat from the respective thermally conductive structure to at least one of (i) at least one externally accessible thermal pad, or (ii) the handle wafer.
19. The invention of claim 18 , wherein the at least one dummy gate comprises polysilicon.
20. The invention of claim 18 , wherein at least one of the at least one thermally conductive structure extends over at least a portion of a length of a respective dummy gate.
21. The invention of claim 18 , wherein the integrated circuit transistor device is made using a silicon-on-insulator (SOI) process.
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