Google Patentsopen access

Chip package structure — Taiwan Semiconductor Manufacturing Company, Ltd. (US12033969B2)

ABSTRACT

Abstract

A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip over the substrate. The chip package structure includes a bump and a first dummy bump between the chip and the substrate. The bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, and the first dummy bump is wider than the bump. The chip package structure includes a first dummy solder layer under the first dummy bump and having a curved bottom surface facing and spaced apart from the substrate.

Description

PRIORITY CLAIM AND CROSS-REFERENCE

This application is a Continuation of U.S. application Ser. No. 17/097,572, filed on Nov. 13, 2020, which is a Continuation of U.S. application Ser. No. 16/424,125, filed on May 28, 2019, which claims the benefit of U.S. Provisional Application No. 62/783,432, filed on Dec. 21, 2018, and entitled “CHIP PACKAGE WITH SEAL RING AND METHOD FOR FORMING THE SAME”, the entirety of which is incorporated by reference herein.

BACKGROUND

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements.

Dozens or hundreds of integrated circuits are typically manufactured on a single semiconductor wafer. The individual dies are singulated by sawing the integrated circuits along scribe lines. The individual dies are then packaged separately. The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. However, since feature sizes continue to decrease, fabrication processes continue to become more difficult to perform. Therefore, it is a challenge to form reliable packages with electronic components with high integration density.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIGS. 1 A- 1 G are cross-sectional views of various stages of a process for forming a chip package structure, in accordance with some embodiments.

FIG. 1 A- 1 is a top view of a substrate of FIG. 1 A , in accordance with some embodiments.

FIG. 1 A- 2 is a bottom view of a chip of FIG. 1 A , in accordance with some embodiments.

FIG. 1 B- 1 is a top view of the chip package structure of FIG. 1 B , in accordance with some embodiments.

FIG. 1 D- 1 is a top view of the chip package structure of FIG. 1 D , in accordance with some embodiments.

FIG. 1 F- 1 is a top view of the chip package structure of FIG. 1 F , in accordance with some embodiments.

FIG. 1 G- 1 is a top view of the chip package structure of FIG. 1 G , in accordance with some embodiments.

FIG. 2 A is a cross-sectional view of a chip package structure, in accordance with some embodiments.

FIG. 2 B is a top view of the chip package structure of FIG. 2 A , in accordance with some embodiments.

FIG. 3 is a top view of a chip package structure, in accordance with some embodiments.

FIG. 4 is a cross-sectional view of a chip package structure, in accordance with some embodiments.

FIG. 5 A is a cross-sectional view of a chip package structure, in accordance with some embodiments.

FIG. 5 B is a top view of the chip package structure of FIG. 5 A , in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. It should be understood that additional operations can be provided before, during, and after the method, and some of the operations described can be replaced or eliminated for other embodiments of the method.

Some embodiments of the disclosure are described. Additional operations can be provided before, during, and/or after the stages described in these embodiments. Some of the stages that are described can be replaced or eliminated for different embodiments. Additional features can be added to the semiconductor device structure. Some of the features described below can be replaced or eliminated for different embodiments. Although some embodiments are discussed with operations performed in a particular order, these operations may be performed in another logical order.

FIGS. 1 A- 1 G are cross-sectional views of various stages of a process for forming a chip package structure, in accordance with some embodiments. FIG. 1 A- 1 is a top view of a substrate of FIG. 1 A , in accordance with some embodiments. FIG. 1 A- 2 is a bottom view of a chip of FIG. 1 A , in accordance with some embodiments. FIG. 1 A is a cross-sectional view illustrating the substrate along a sectional line I-I′ in FIG. 1 A- 1 and illustrating the chip along a sectional line II-II′ in FIG. 1 A- 2 , in accordance with some embodiments.

As shown in FIGS. 1 A and 1 A- 1 , a substrate 110 is provided, in accordance with some embodiments. In some embodiments, the substrate 110 is an interposer wafer. The substrate 110 includes a semiconductor structure 111 , conductive vias 112 , an insulating layer 113 , and a redistribution structure 114 , in accordance with some embodiments.

The semiconductor structure 111 has surfaces

111 a and 111 b , in accordance with some embodiments. In some embodiments, the semiconductor structure 111 is made of an elementary semiconductor material including silicon or germanium in a single crystal, polycrystal, or amorphous structure.

In some other embodiments, the semiconductor structure 111 is made of a compound semiconductor (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or indium arsenide), an alloy semiconductor (e.g., SiGe or GaAsP), or a combination thereof. The semiconductor structure 111 may also include multi-layer semiconductors, semiconductor on insulator (SOI) (such as silicon on insulator or germanium on insulator), or a combination thereof.

The conductive vias 112 are formed in the semiconductor structure 111 , in accordance with some embodiments. The conductive vias 112 may be formed to extend from the surface 111 a into the semiconductor structure 111 . The insulating layer 113 is formed over the semiconductor structure 111 , in accordance with some embodiments. The insulating layer 113 is between the conductive vias 112 and the semiconductor structure 111 , in accordance with some embodiments.

The insulating layer 113 is configured to electrically insulate the conductive vias 112 from the semiconductor structure 111 , in accordance with some embodiments. The insulating layer 113 is made of an oxide-containing material such as silicon oxide, in accordance with some embodiments. The insulating layer 113 is formed using an oxidation process, a deposition process, or another suitable process.

In some embodiments, the substrate 110 is a device wafer that includes various device elements. In some embodiments, the various device elements are formed in and/or over the substrate 110 . The device elements are not shown in figures for the purpose of simplicity and clarity. Examples of the various device elements include active devices, passive devices, other suitable elements, or a combination thereof. The active devices may include transistors or diodes (not shown) formed at the surface 111 a . The passive devices include resistors, capacitors, or other suitable passive devices.

For example, the transistors may be metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high-voltage transistors, high-frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), etc. Various processes, such as front-end-of-line (FEOL) semiconductor fabrication processes, are performed to form the various device elements. The FEOL semiconductor fabrication processes may include deposition, etching, implantation, photolithography, annealing, planarization, one or more other applicable processes, or a combination thereof.

In some embodiments, isolation features (not shown) are formed in the substrate 110 . The isolation features are used to define active regions and electrically isolate various device elements formed in the active regions. In some embodiments, the isolation features include shallow trench isolation (STI) features, local oxidation of silicon (LOCOS) features, other suitable isolation features, or a combination thereof.

The <figure-callout id="114" label="redistribution structure" filenames="US12033969-20240709-D00000.png,US12033969

PRIORITY CLAIM AND CROSS-REFERENCE

This application is a Continuation of U.S. application Ser. No. 17/097,572, filed on Nov. 13, 2020, which is a Continuation of U.S. application Ser. No. 16/424,125, filed on May 28, 2019, which claims the benefit of U.S. Provisional Application No. 62/783,432, filed on Dec. 21, 2018, and entitled “CHIP PACKAGE WITH SEAL RING AND METHOD FOR FORMING THE SAME”, the entirety of which is incorporated by reference herein.

BACKGROUND

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements.

Dozens or hundreds of integrated circuits are typically manufactured on a single semiconductor wafer. The individual dies are singulated by sawing the integrated circuits along scribe lines. The individual dies are then packaged separately. The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. However, since feature sizes continue to decrease, fabrication processes continue to become more difficult to perform. Therefore, it is a challenge to form reliable packages with electronic components with high integration density.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIGS. 1 A- 1 G are cross-sectional views of various stages of a process for forming a chip package structure, in accordance with some embodiments.

FIG. 1 A- 1 is a top view of a substrate of FIG. 1 A , in accordance with some embodiments.

FIG. 1 A- 2 is a bottom view of a chip of FIG. 1 A , in accordance with some embodiments.

FIG. 1 B- 1 is a top view of the chip package structure of FIG. 1 B , in accordance with some embodiments.

FIG. 1 D- 1 is a top view of the chip package structure of FIG. 1 D , in accordance with some embodiments.

FIG. 1 F- 1 is a top view of the chip package structure of FIG. 1 F , in accordance with some embodiments.

FIG. 1 G- 1 is a top view of the chip package structure of FIG. 1 G , in accordance with some embodiments.

FIG. 2 A is a cross-sectional view of a chip package structure, in accordance with some embodiments.

FIG. 2 B is a top view of the chip package structure of FIG. 2 A , in accordance with some embodiments.

FIG. 3 is a top view of a chip package structure, in accordance with some embodiments.

FIG. 4 is a cross-sectional view of a chip package structure, in accordance with some embodiments.

FIG. 5 A is a cross-sectional view of a chip package structure, in accordance with some embodiments.

FIG. 5 B is a top view of the chip package structure of FIG. 5 A , in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. It should be understood that additional operations can be provided before, during, and after the method, and some of the operations described can be replaced or eliminated for other embodiments of the method.

Some embodiments of the disclosure are described. Additional operations can be provided before, during, and/or after the stages described in these embodiments. Some of the stages that are described can be replaced or eliminated for different embodiments. Additional features can be added to the semiconductor device structure. Some of the features described below can be replaced or eliminated for different embodiments. Although some embodiments are discussed with operations performed in a particular order, these operations may be performed in another logical order.

FIGS. 1 A- 1 G are cross-sectional views of various stages of a process for forming a chip package structure, in accordance with some embodiments. FIG. 1 A- 1 is a top view of a substrate of FIG. 1 A , in accordance with some embodiments. FIG. 1 A- 2 is a bottom view of a chip of FIG. 1 A , in accordance with some embodiments. FIG. 1 A is a cross-sectional view illustrating the substrate along a sectional line I-I′ in FIG. 1 A- 1 and illustrating the chip along a sectional line II-II′ in FIG. 1 A- 2 , in accordance with some embodiments.

As shown in FIGS. 1 A and 1 A- 1 , a substrate 110 is provided, in accordance with some embodiments. In some embodiments, the substrate 110 is an interposer wafer. The substrate 110 includes a semiconductor structure 111 , conductive vias 112 , an insulating layer 113 , and a redistribution structure 114 , in accordance with some embodiments.

The semiconductor structure 111 has surfaces

111 a and 111 b , in accordance with some embodiments. In some embodiments, the semiconductor structure 111 is made of an elementary semiconductor material including silicon or germanium in a single crystal, polycrystal, or amorphous structure.

In some other embodiments, the semiconductor structure 111 is made of a compound semiconductor (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or indium arsenide), an alloy semiconductor (e.g., SiGe or GaAsP), or a combination thereof. The semiconductor structure 111 may also include multi-layer semiconductors, semiconductor on insulator (SOI) (such as silicon on insulator or germanium on insulator), or a combination thereof.

The conductive vias 112 are formed in the semiconductor structure 111 , in accordance with some embodiments. The conductive vias 112 may be formed to extend from the surface 111 a into the semiconductor structure 111 . The insulating layer 113 is formed over the semiconductor structure 111 , in accordance with some embodiments. The insulating layer 113 is between the conductive vias 112 and the semiconductor structure 111 , in accordance with some embodiments.

The insulating layer 113 is configured to electrically insulate the conductive vias 112 from the semiconductor structure 111 , in accordance with some embodiments. The insulating layer 113 is made of an oxide-containing material such as silicon oxide, in accordance with some embodiments. The insulating layer 113 is formed using an oxidation process, a deposition process, or another suitable process.

In some embodiments, the substrate 110 is a device wafer that includes various device elements. In some embodiments, the various device elements are formed in and/or over the substrate 110 . The device elements are not shown in figures for the purpose of simplicity and clarity. Examples of the various device elements include active devices, passive devices, other suitable elements, or a combination thereof. The active devices may include transistors or diodes (not shown) formed at the surface 111 a . The passive devices include resistors, capacitors, or other suitable passive devices.

For example, the transistors may be metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high-voltage transistors, high-frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), etc. Various processes, such as front-end-of-line (FEOL) semiconductor fabrication processes, are performed to form the various device elements. The FEOL semiconductor fabrication processes may include deposition, etching, implantation, photolithography, annealing, planarization, one or more other applicable processes, or a combination thereof.

In some embodiments, isolation features (not shown) are formed in the substrate 110 . The isolation features are used to define active regions and electrically isolate various device elements formed in the active regions. In some embodiments, the isolation features include shallow trench isolation (STI) features, local oxidation of silicon (LOCOS) features, other suitable isolation features, or a combination thereof.

The redistribution structure 114 is formed over the semiconductor structure 111 , in accordance with some embodiments. The redistribution structure 114 includes a dielectric layer 114 a , wiring layers 114 b , conductive vias 114 c , conductive pads 114 d , and dummy pads 114 e , in accordance with some embodiments. The dielectric layer 114 a is formed over the surface 111 a , in accordance with some embodiments. The wiring layers 114 b are formed in the dielectric layer 114 a , in accordance with some embodiments.

As shown in FIG. 1 A , the conductive vias 114 c are electrically connected between different wiring layers 114 b and between the wiring layer 114 b and the conductive pads 114 d , in accordance with some embodiments. For the sake of simplicity, FIG. 1 A only shows one of the wiring layers 114 b , in accordance with some embodiments.

The conductive vias 112 are electrically connected to the conductive pads 114 d through the wiring layers 114 b and the conductive vias 114 c , in accordance with some embodiments. The conductive pads 114 d and the dummy pads 114 e are formed over the dielectric layer 114 a , in accordance with some embodiments. The dummy pads 114 e are electrically insulated from the wiring layers 114 b , in accordance with some embodiments.

As shown in FIGS. 1 A and 1 A- 1 , the dummy pads 114 e surround the conductive pads 114 d , in accordance with some embodiments. As shown in FIG. 1 A- 1 , the dummy pads 114 e have an L-like shape, in accordance with some embodiments. The wiring layers 114 b , the conductive vias 114 c , the conductive pads 114 d , and the dummy pads 114 e are made of a conductive material, such as copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), nickel (Ni), or another suitable material, in accordance with some embodiments.

As shown in FIGS. 1 A and 1 A- 1 , bumps 115 a and dummy bumps 115 b are respectively formed over the conductive pads 114 d and the dummy pads 114 e , in accordance with some embodiments. As shown in FIG. 1 A- 1 , the dummy bumps 115 b have an L-like shape, in accordance with some embodiments.

As shown in FIG. 1 A- 1 , the dummy bump 115 b is wider than the bump 115 a , in accordance with some embodiments. That is, a width W1 of the dummy bump 115 b is greater than a width W2 of the bump 115 a , in accordance with some embodiments. The bumps 115 a and dummy bumps 115 b are made of a conductive material, such as copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), nickel (Ni), or another suitable material, in accordance with some embodiments.

As shown in FIGS. 1 A and 1 A- 1 , solder layers 115 c and dummy solder layers 115 d are respectively formed over the bumps 115 a and the dummy bumps 115 b , in accordance with some embodiments. The solder layers 115 c and the dummy solder layers 115 d are made of a conductive material, such as Tin (Sn) or another suitable material, in accordance with some embodiments.

As shown in FIGS. 1 A and 1 A- 2 , a chip 120 is provided, in accordance with some embodiments. The chip 120 includes a system on chip (SoC), in accordance with some embodiments. The chip 120 includes various device elements, in accordance with some embodiments. In some embodiments, the various device elements are formed in the chip 120 .

The device elements are not shown in figures for the purpose of simplicity and clarity. Examples of the various device elements include active devices, passive devices, other suitable elements, or a combination thereof. The active devices may include transistors or diodes (not shown). The passive devices include resistors, capacitors, or other suitable passive devices.

For example, the transistors may be metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high-voltage transistors, high-frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), etc. Various processes, such as front-end-of-line (FEOL) semiconductor fabrication processes, are performed to form the various device elements. The FEOL semiconductor fabrication processes may include deposition, etching, implantation, photolithography, annealing, planarization, one or more other applicable processes, or a combination thereof.

In some embodiments, isolation features (not shown) are formed in the chip 120 . The isolation features are used to define active regions and electrically isolate various device elements formed in the active regions. In some embodiments, the isolation features include shallow trench isolation (STI) features, local oxidation of silicon (LOCOS) features, other suitable isolation features, or a combination thereof.

As shown in FIGS. 1 A and 1 A- 2 , bumps 132 and dummy bumps 134 are formed over the chip 120 , in accordance with some embodiments. The dummy bumps 134 are respectively close to corners 122 of the chip 120 , in accordance with some embodiments. As shown in FIG. 1 A- 2 , the dummy bump 134 is wider than the bump 132 , in accordance with some embodiments. That is, a width W3 of the dummy bump 134 is greater than a width W4 of the bump 132 , in accordance with some embodiments. As shown in FIG. 1 A- 2 , the dummy bump 134 is between the bump 132 and the corner 122 , in accordance with some embodiments. As shown in FIG. 1 A- 2 , the dummy bumps 134 have an L-like shape, in accordance with some embodiments.

As shown in FIGS. 1 A and 1 A- 2 , solder layers 136 and dummy solder layers 138 are respectively formed over the bumps 132 and the dummy bumps 134 , in accordance with some embodiments. The solder layers 136 and the dummy solder layers 138 are made of a conductive material, such as Tin (Sn) or another suitable material, in accordance with some embodiments.

FIG. 1 B- 1 is a top view of the chip package structure of FIG. 1 B , in accordance with some embodiments. FIG. 1 B is a cross-sectional view illustrating the chip package structure along a sectional line I-I′ in FIG. 1 B- 1 , in accordance with some embodiments. As shown in FIGS. 1 B and 1 B- 1 , the chip 120 is disposed over the substrate 110 , in accordance with some embodiments. Thereafter, a reflow process is performed over the solder layers 136 and 115 c , in accordance with some embodiments.

After the reflow process, each solder layer 136 and the solder layer 115 c thereunder melt and mix together to form a solder ball 139 , in accordance with some embodiments. Therefore, the chip 120 is bonded to the substrate 110 through the bumps

132 and 115 a and the solder balls 139 , in accordance with some embodiments.

After the chip 120 is bonded to the substrate 110 , the dummy bumps 115 b and 134 and the dummy solder layers 115 d and 138 are between the chip 120 and the substrate 110 , in accordance with some embodiments. The dummy bumps 134 and the dummy solder layers 138 are electrically insulated from the substrate 110 , in accordance with some embodiments. The dummy bumps 115 b and the dummy solder layers 115 d are electrically insulated from the chip 120 , in accordance with some embodiments.

The dummy bumps 115 b are respectively close to the corners 122 of the chip 120 , in accordance with some embodiments. The dummy bump 115 b is wider than the bump 132 , in accordance with some embodiments. In some embodiments (such as those illustrated in FIG. 1 B- 1 ), the dummy bumps 115 b and 134 have the same shape, in accordance with some embodiments. The dummy bumps 115 b surround the dummy bumps 134 , in accordance with some embodiments. As shown in FIG. 1 B- 1 , the dummy bump 115 b is between the corner 122 and the dummy bump 134 , in accordance with some embodiments.

As shown in FIG. 1 B , an underfill layer 140 is formed into a gap G 1 between the substrate 110 and the chip 120 , in accordance with some embodiments. The underfill layer 140 is also referred to as a protective layer, in accordance with some embodiments. The underfill layer 140 surrounds the bumps

132 and 115 a , the solder balls 139 , and the chip 120 , in accordance with some embodiments. The underfill layer 140 is partially between the dummy bumps 134 (or the dummy solder layers 138 ) and the substrate 110 , in accordance with some embodiments.

The underfill layer 140 is partially between the dummy bumps 115 b (or the dummy solder layers 115 d ) and the chip 120 , in accordance with some embodiments. The underfill layer 140 is partially between the dummy bumps 134 and 115 b , in accordance with some embodiments. The underfill layer 140 is partially between the dummy solder layers 138 and 115 d , in accordance with some embodiments. The underfill layer 140 includes a polymer material, in accordance with some embodiments.

Since the stress tends to concentrate at the corners 122 of the chip 120 and tends to induce cracks in the underfill layer 140 closed to the corners 122 , the dummy bumps 134 and 115 b and the dummy solder layers 138 and 115 d are closed to the corners 122 and are able to stop the cracks, in accordance with some embodiments. Therefore, the dummy bumps 134 and 115 b and the dummy solder layers 138 and 115 d prevent the bumps

132 and 115 a and the solder balls 139 from damage resulting from cracks induced by the stress concentrating at the corners 122 , in accordance with some embodiments. As a result, the dummy bumps 134 and 115 b and the dummy solder layers 138 and 115 d improve the yield of the bumps

132 and 115 a and the solder balls 139 , in accordance with some embodiments.

As shown in FIGS. 1 B and 1 B- 1 , a molding layer 150 is formed over the substrate 110 , in accordance with some embodiments. The molding layer 150 surrounds the chip 120 , the underfill layer 140 , the bumps

132 and 115 a , and the solder balls 139 , in accordance with some embodiments. The molding layer 150 includes a polymer material, in accordance with some embodiments. The top surface

124 and 152 of the chip 120 and the molding layer 150 are substantially coplanar, in accordance with some embodiments.

As shown in FIG. 1 C , a lower portion of the semiconductor structure 111 is removed, in accordance with some embodiments. The removal process includes a chemical mechanical polishing (CMP) process, in accordance with some embodiments. After the removal process, the conductive vias 112 and the insulating layer 113 are exposed, in accordance with some embodiments.

The conductive vias 112 and the insulating layer 113 pass through the semiconductor structure 111 , in accordance with some embodiments. The conductive vias 112 are also referred to as through-substrate vias or through-silicon vias when the semiconductor structure 111 is a silicon substrate, in accordance with some embodiments.

FIG. 1 D- 1 is a top view of the chip package structure of FIG. 1 D , in accordance with some embodiments. FIG. 1 D is a cross-sectional view illustrating the chip package structure along a sectional line I-I′ in FIG. 1 D- 1 , in accordance with some embodiments.

As shown in FIGS. 1 D and 1 D- 1 , the semiconductor structure 111 is flipped upside down, in accordance with some embodiments. As shown in FIG. 1 D , an insulating layer 116 is formed over the surface 111 b , in accordance with some embodiments. The insulating layer 116 is configured to electrically insulate wiring layers subsequently formed thereon from the semiconductor structure 111 , in accordance with some embodiments. The insulating layer 116 is made of an oxide-containing material such as silicon oxide, in accordance with some embodiments. The insulating layer 116 is formed using an oxidation process, a deposition process, or another suitable process.

In some embodiments, a redistribution structure 117 is formed over the surface 111 b of the semiconductor structure 111 , in accordance with some embodiments. The redistribution structure 117 includes a dielectric layer 117 a , wiring layers 117 b , conductive vias 117 c , dummy lines 117 d , and dummy vias 117 e , in accordance with some embodiments. The wiring layers 117 b , the conductive vias 117 c , the dummy lines 117 d , and the dummy vias 117 e are formed in the dielectric layer 117 a , in accordance with some embodiments.

As shown in FIG. 1 D , pads 118 a and dummy pads 118 b are formed over the redistribution structure 117 , in accordance with some embodiments. The conductive vias 117 c are electrically connected between different wiring layers 117 b and between the wiring layer 117 b and the conductive pads 118 a , in accordance with some embodiments. For the sake of simplicity, FIG. 1 D only shows one of the wiring layers 117 b , in accordance with some embodiments.

The conductive vias 112 are electrically connected to the conductive pads 118 a through the wiring layers 117 b and the conductive vias 117 c , in accordance with some embodiments. The dummy vias 117 e are connected between the dummy pad

CLAIMS

Claims ( 20 )

What is claimed is:

1. A chip package structure, comprising:

a substrate;

a chip over the substrate;

a bump and a first dummy bump between the chip and the substrate, wherein the bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, and the first dummy bump is wider than the bump; and

a first dummy solder layer under the first dummy bump and having a curved bottom surface facing and spaced apart from the substrate.

2. The chip package structure as claimed in claim 1 , further comprising:

a solder ball between the bump and the substrate, wherein the solder ball has a planar bottom surface facing the substrate.

3. The chip package structure as claimed in claim 1 , wherein the first dummy bump is between the bump and a corner of the chip.

4. The chip package structure as claimed in claim 1 , further comprising:

an underfill layer between the chip and the substrate, wherein the underfill layer separates the first dummy solder layer from the substrate.

5. The chip package structure as claimed in claim 1 , further comprising:

a second dummy bump between the chip and the substrate, wherein the second dummy bump is connected to the substrate and electrically insulated from the chip; and

a second dummy solder layer over the second dummy bump and electrically insulated from the chip.

6. The chip package structure as claimed in claim 5 , wherein the second dummy solder layer has a curved top surface facing and spaced apart from the chip.

7. The chip package structure as claimed in claim 5 , wherein the first dummy solder layer and the second dummy solder layer are spaced apart from each other.

8. The chip package structure as claimed in claim 7 , further comprising:

an underfill layer between the chip and the substrate, wherein the underfill layer separates the first dummy solder layer from the second dummy solder layer.

9. A chip package structure, comprising:

a substrate;

a chip over the substrate; and

a bump and a dummy bump between the chip and the substrate, wherein the bump is electrically connected between the chip and the substrate, the dummy bump is electrically insulated from the substrate, the dummy bump is wider than the bump, the dummy bump has a first strip portion and a second strip portion, and the first strip portion is not parallel to the second strip portion.

10. The chip package structure as claimed in claim 9 , wherein the first strip portion is substantially parallel to a first edge of the chip.

11. The chip package structure as claimed in claim 10 , wherein the second strip portion is substantially parallel to a second edge of the chip.

12. The chip package structure as claimed in claim 11 , wherein the first edge and the second edge meet at a corner of the chip.

13. The chip package structure as claimed in claim 12 , wherein the dummy bump has an L-shape in a top view of the dummy bump.

14. The chip package structure as claimed in claim 12 , wherein the dummy bump is between the bump and the corner of the chip.

15. A chip package structure, comprising:

a package comprising a wiring substrate and a chip over the wiring substrate; and

a substrate, wherein the package is over and bonded to the substrate, the substrate comprises a redistribution structure comprising a dielectric structure and a dummy structure in the dielectric structure, the dummy structure is electrically insulated from the package, the dummy structure has a first L-shape in a top view of the package and the substrate, and a first corner of the wiring substrate is between a second corner of the dummy structure and a third corner of the chip in the top view.

16. The chip package structure as claimed in claim 15 , wherein the dummy structure has a second L-shape in a cross-sectional view of the dummy structure.

17. The chip package structure as claimed in claim 15 , wherein a first edge of the package overlaps the dummy structure.

18. The chip package structure as claimed in claim 17 , wherein a second edge of the package overlaps the dummy structure.

19. The chip package structure as claimed in claim 17 , wherein the first edge of the package extends across a second edge of the dummy structure in the top view.

20. The chip package structure as claimed in claim 15 , wherein a corner of the package overlaps the dummy structure.

US17/873,673

2018-12-21

2022-07-26

Chip package structure

Active

US12033969B2

( en )

Priority Applications (1)

Application Number

Priority Date

Filing Date

Title

US17/873,673

US12033969B2

( en )

2018-12-21

2022-07-26

Chip package structure

Applications Claiming Priority (4)

Application Number

Priority Date

Filing Date

Title

US201862783432P

2018-12-21

2018-12-21

US16/424,125

US10847485B2

( en )

2018-12-21

2019-05-28

Chip package structure and method for forming the same

US17/097,572

US11437334B2

( en )

2018-12-21

2020-11-13

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2020-11-24

Taiwan Semiconductor Manufacturing Co., Ltd.

Chip package structure and method for forming the same

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2019-05-07

2022-05-24

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2020-03-27

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Package structure and fabricating method thereof

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2020-04-24

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삼성전자주식회사

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Package structure and circuit layer structure including dummy trace and manufacturing method therefor

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芯盟科技有限公司

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US20210066230A1

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US10847485B2

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2020-06-25

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