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Integrated circuit structure and fabrication thereof — Taiwan Semiconductor Manufacturing Company, Ltd. (US11456182B1)

Taiwan Semiconductor Manufacturing Company, Ltd. · Google Patents

Google Patents · Patents · License: Open Access

ltd.taiwansemiconductormanufacturingcompany yu

patent, google patents, intellectual property, US11456182B1, Taiwan Semiconductor Manufacturing Company, Ltd., Yu-Hsien Lin, en, 2022

ABSTRACT

Abstract

A method includes forming a fin structure extending above a substrate; forming dummy gate structures extending across the fin structure, each of the dummy gate structures including a dummy gate electrode layer and a hard mask layer over the dummy gate electrode layer; performing an ion implantation process to dope the hard mask layers of the dummy gate structures; after performing the ion implantation process to dope the hard mask layers of the dummy gate structures, performing a first etching process to etch a source/drain region of the fin structure between the dummy gate structures to form a recess in the source/drain region of the fin structure; forming an epitaxial structure in the recess; and replacing the dummy gate structures with metal gate structures.

Description

BACKGROUND

Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIGS. 1, 2, 3, 4, 5A, 6A, 7A, 8A, and 9A are perspective views of intermediate stages in fabricating an integrated circuit structure in accordance with some embodiments of the present disclosure.

FIGS. 5B, 6B, 7B, 8B, 9B, 9C, 10A-17A, and 18-29 are cross-sectional views of intermediate stages in fabricating the integrated circuit structure along a first cut, which is along a lengthwise direction of semiconductor channels and perpendicular to a top surface of the substrate.

FIG. 9D illustrates an exemplary ion distribution chart of the tilt ion implantation in accordance with some embodiments of the present disclosure.

FIG. 9E is an example graph illustrating a dopant concentration in doped regions as a function of depth within the doped regions, in accordance with some embodiments of the present disclosure.

FIG. 17B is a cross-sectional view of an intermediate stage in fabricating the integrated circuit structure along a second cut, which is in the gate region and perpendicular to the lengthwise direction of the semiconductor channels.

FIGS. 30 and 31A are perspective views of intermediate stages in fabricating an integrated circuit structure in accordance with some embodiments of the present disclosure.

FIGS. 31B and 32-41 are cross-sectional views of intermediate stages in fabricating the integrated circuit structure in accordance with some embodiments of the present disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as âbeneath,â âbelow,â âlower,â âabove,â âupperâ and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. As used herein, âaround,â âabout,â âapproximately,â or âsubstantiallyâ shall generally mean within 20 percent, or within 10 percent, or within 5 percent of a given value or range. Numerical quantities given herein are approximate, meaning that the term âaround,â âabout,â âapproximately,â or âsubstantiallyâ can be inferred if not expressly stated.

The present disclosure is generally related to integrated circuit (IC) structures and methods of forming the same, and more particularly to fabricating transistors (e.g., fin field-effect transistors (FinFETs), gate-all-around (GAA) transistors) and hard masks over gate structures of the transistors. It is also noted that the present disclosure presents embodiments in the form of multi-gate transistors. Multi-gate transistors include those transistors whose gate structures are formed on at least two-sides of a channel region. These multi-gate devices may include a p-type metal-oxide-semiconductor device or an n-type metal-oxide-semiconductor device. Specific examples may be presented and referred to herein as FinFETs, on account of their fin-like structure. A FinFET has a gate structure formed on three sides of a channel region (e.g., wrapping around an upper portion of a channel region in a semiconductor fin). Also presented herein are embodiments of a type of multi-gate transistor referred to as a GAA device. A GAA device includes any device that has its gate structure, or portion thereof, formed on 4-sides of a channel region (e.g., surrounding a portion of a channel region). Devices presented herein also include embodiments that have channel regions disposed in nanosheet channel(s), nanowire channel(s), and/or other suitable channel configuration.

In order to create more routing space for an integrated circuit (IC) structure having a large number of GAA transistors, backside metal lines (e.g., backside power rails) connected to backside of source regions and/or drain regions of GAA transistors using backside metal vias are being studied as an alternative to some front-side metal lines (e.g., front-side power rails) formed on front-side of transistors. A backside metal via can be fabricated by using, for example, first forming a sacrificial epitaxial plug in the substrate in the front-end-of-line (FEOL) processing, followed by replacing the sacrificial epitaxial plug with a metal via after the back-end-of-line (BEOL) processing of forming a multilayer interconnect structure. In some embodiments, formation of the sacrificial epitaxial plug includes, for example, etching a recess in the substrate between dummy gate structures by using suitable photolithography and etching techniques, and forming the sacrificial epitaxial plug in the recess in the substrate by using epitaxy growth. However, etching the recess in the substrate may result in a non-negligible loss in dummy gate hard masks (e.g., oxide masks) of the dummy gate structures, because the dummy gate hard masks have insufficient etch resistance against this etching step. One solution to address this issue is forming thicker dummy gate hard masks. However, thickened dummy gate hard masks would lead to an increased aspect ratio of the dummy gate structures (i.e., a ratio of height to width of a dummy gate structure), which in turn may cause an increased collapse risk in the dummy gate structures. Collapse of dummy gate structures may further lead to under-etching in subsequent etching processing of forming source/drain epitaxial structures and/or forming sacrificial epitaxial plugs.

Therefore, the present disclosure in various embodiments provides an addition ion implantation step to enhance the etch resistance of the dummy gate hard masks. For example, the ion implantation step creates doped regions in the dummy gate hard masks with a different material composition and hence a different etch selectivity than original dummy gate hard masks. The doped regions in the dummy gate hard masks thus allow for slowing down the etch rate of the dummy gate hard masks during the etching step of recessing the substrate, which in turn reduces the hard mask loss caused by the etching step of recessing the substrate.

FIGS. 1-29 illustrate perspective views and cross-sectional views of intermediate stages in formation of an integrated circuit having multi-gate devices, in accordance with some embodiments of the present disclosure. As used herein, the term âmulti-gate deviceâ is used to describe a device (e.g., a semiconductor transistor) that has at least some gate material disposed on multiple sides of at least one channel of the device. In some examples, the multi-gate device may be referred to as a GAA device or a nanosheet device having gate material disposed on at least four sides of at least one channel of the device. The channel region may be referred to as a ânanowire,â which as used herein includes channel regions of various geometries (e.g., cylindrical, bar-shaped) and various dimensions.

FIGS. 1, 2, 3, 4, 5A, 6A, 7A, 8A, and 9A are perspective views of intermediate stages in fabricating an integrated circuit structure 100 in accordance with some embodiments of the present disclosure. FIGS. 5B, 6B, 7B, 8B, 9B, 9C, 10A-17A, and 18-29 are cross-sectional views of intermediate stages in fabricating the integrated circuit structure along a first cut (e.g., cut X-X in FIG. 5A ), which is along a lengthwise direction of semiconductor channels and perpendicular to a top surface of the substrate. FIG. 9D illustrates an exemplary ion distribution chart of the tilt ion implantation in accordance with some embodiments of the present disclosure. FIG. 17B is a cross-sectional view of an intermediate stage in fabricating the integrated circuit structure 100 along a second cut (e.g., cut Y-Y in FIG. 5A ), which is in the gate region and perpendicular to the lengthwise direction of the semiconductor channels.

As with the other method embodiments and exemplary devices discussed herein, it is understood that parts of the integrated circuit structure 100 may be fabricated by a CMOS technology process flow, and thus some processes are only briefly described herein. Further, the exemplary integrated circuit structure may include various other devices and features, such as other types of devices such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, static random access memory (SRAM) and/or other logic circuits, etc., but is simplified for a better understanding of the concepts of the present disclosure. In some embodiments, the exemplary integrated circuit structure includes a plurality of semiconductor devices (e.g., transistors), including PFETs, NFETs, etc., which may be interconnected. Moreover, it is noted that the process steps of fabricating the integrated circuit structure 100 , including any descriptions given with reference to FIGS. 1-29 , as with the remainder of the method and exemplary figures provided in this disclosure, are merely exemplary and are not intended to be limiting beyond what is specifically recited in the claims that follow.

FIG. 1 illustrates a perspective view of an initial structure. The initial structure includes a substrate 110 . In some embodiments, the substrate 110 is a semiconductor-on-insulator (SOI) substrate that is comprised of a base substrate 111 , a buried insulator layer 113 and a semiconductor layer 115 . The base substrate 111 may comprise silicon, gallium arsenide, gallium nitride, strained silicon, silicon germanium, silicon carbide, carbide, diamond, an epitaxy layer, and/or other materials. The buried insulator layer 113 may comprise silicon oxide, silicon nitride, silicon oxynitride, and/or other dielectric materials. The semiconductor layer 115 may comprise silicon, gallium arsenide, gallium nitride, strained silicon, silicon germanium, silicon carbide, carbide, diamond, and/or other materials. The buried insulator layer 113 and the semiconductor layer 115 may be formed using various SOI technologies. For example, the buried insulator layer 113 may be formed on a semiconductor wafer by a process referred to as separation by implanted oxygen (SIMOX). The SIMOX technology is based on ion-implanting a high-dose of oxygen ions into a silicon wafer, such that the peak concentration lies beneath the silicon surface. After implantation the wafer is subjected to a high-temperature anneal to form a continuous stoichiometric subsurface-layer of silicon dioxide. Thus formed dielectric layer 113 , also referred to as buried oxide (BOX), electrically separates the semiconductor layer 115 and the base substrate 111 .

FIG. 2 illustrates a perspective view of an epitaxial stack 120 formed over the substrate 110 . The epitaxial stack 120 includes epitaxial layers 122 of a first composition interposed by epitaxial layers 124 of a second composition. The first and second compositions can be different. In some embodiments, the epitaxial layers 122 are SiGe and the epitaxial layers 124 are silicon (Si). However, other embodiments are possible including those that provide for a first composition and a second composition having different oxidation rates and/or etch selectivity. In some embodiments, the epitaxial layers 122 include SiGe and where the epitaxial layers 124 include Si, the Si oxidation rate of the <figure-callout id="124" label="epitaxial layers" filenames="US11456182-20220927-D00000.png,US11456182-20220927-D00002.png" state="{{state

BACKGROUND

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1, 2, 3, 4, 5A, 6A, 7A, 8A, and 9A are perspective views of intermediate stages in fabricating an integrated circuit structure in accordance with some embodiments of the present disclosure.

FIG. 9D illustrates an exemplary ion distribution chart of the tilt ion implantation in accordance with some embodiments of the present disclosure.

FIG. 9E is an example graph illustrating a dopant concentration in doped regions as a function of depth within the doped regions, in accordance with some embodiments of the present disclosure.

FIGS. 30 and 31A are perspective views of intermediate stages in fabricating an integrated circuit structure in accordance with some embodiments of the present disclosure.

FIGS. 31B and 32-41 are cross-sectional views of intermediate stages in fabricating the integrated circuit structure in accordance with some embodiments of the present disclosure.

DETAILED DESCRIPTION

FIG. 2 illustrates a perspective view of an epitaxial stack 120 formed over the substrate 110 . The epitaxial stack 120 includes epitaxial layers 122 of a first composition interposed by epitaxial layers 124 of a second composition. The first and second compositions can be different. In some embodiments, the epitaxial layers 122 are SiGe and the epitaxial layers 124 are silicon (Si). However, other embodiments are possible including those that provide for a first composition and a second composition having different oxidation rates and/or etch selectivity. In some embodiments, the epitaxial layers 122 include SiGe and where the epitaxial layers 124 include Si, the Si oxidation rate of the epitaxial layers 124 is less than the SiGe oxidation rate of the epitaxial layers 122 .

The epitaxial layers 124 or portions thereof may form nanosheet channel(s) of the multi-gate transistor. The term nanosheet is used herein to designate any material portion with nanoscale, or even microscale dimensions, and having an elongate shape, regardless of the cross-sectional shape of this portion. Thus, this term designates both circular and substantially circular cross-section elongate material portions, and beam or bar-shaped material portions including for example a cylindrical in shape or substantially rectangular cross-section. The use of the epitaxial layers 124 to define a channel or channels of a device is further discussed below.

It is noted that three layers of the epitaxial layers 122 and three layers of the epitaxial layers 124 are alternately arranged as illustrated in FIG. 2 , which is for illustrative purposes only and not intended to be limiting beyond what is specifically recited in the claims. It can be appreciated that any number of epitaxial layers can be formed in the epitaxial stack 120 ; the number of layers depending on the desired number of channels regions for the transistor. In some embodiments, the number of epitaxial layers 124 is between 2 and 10.

In some embodiments, each epitaxial layer 122 has a thickness ranging from about 1 nanometers (nm) to about 10 nm, but other ranges are within the scope of various embodiments of the present disclosure. The epitaxial layers 122 may be substantially uniform in thickness. In some embodiments, each epitaxial layer 124 has a thickness ranging from about 1 nm to about 10 nm, but other ranges are within the scope of various embodiments of the present disclosure. In some embodiments, the epitaxial layers 124 of the stack are substantially uniform in thickness. As described in more detail below, the epitaxial layers 124 may serve as channel region(s) for a subsequently-formed multi-gate device and the thickness is chosen based on device performance considerations. The epitaxial layers 122 in channel regions(s) may eventually be removed and serve to define a vertical distance between adjacent channel region(s) for a subsequently-formed multi-gate device and the thickness is chosen based on device performance considerations. Accordingly, the epitaxial layers 122 may also be referred to as sacrificial layers, and epitaxial layers 124 may also be referred to as channel layers.

By way of example, epitaxial growth of the layers of the stack 120 may be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and/or other suitable epitaxial growth processes. In some embodiments, the epitaxially grown layers such as, the epitaxial layers 124 include the same material as the semiconductor layer 115 of the substrate 110 . In some embodiments, the epitaxially grown layers

122 and 124 include a different material than the semiconductor layer 115 of the substrate 110 . As stated above, in at least some examples, the epitaxial layers 122 include an epitaxially grown silicon germanium (SiGe) layer and the epitaxial layers 124 include an epitaxially grown silicon (Si) layer. Alternatively, in some embodiments, either of the epitaxial layers

122 and 124 may include other materials such as germanium, a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide, an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP, or combinations thereof. As discussed, the materials of the epitaxial layers

122 and 124 may be chosen based on providing differing oxidation and/or etching selectivity properties. In some embodiments, the epitaxial layers

122 and 124 are substantially dopant-free (i.e., having an extrinsic dopant concentration from about 0 cm â3 to about 1Ã10 18 cm â3 ), where for example, no intentional doping is performed during the epitaxial growth process.

FIG. 3 illustrates a perspective view of formation of a plurality of semiconductor fins 130 extending from the buried insulator layer 113 of the substrate 110 . In various embodiments, each of the fins 130 includes a portion of the semiconductor layer 115 protruding from the buried insulator layer 113 and portions of each of the epitaxial layers of the epitaxial stack including epitaxial layers

122 and 124 . The fins 130 may be fabricated using suitable processes including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers, or mandrels, may then be used to pattern the fins 130 by etching initial epitaxial stack 120 (illustrated in FIG. 2 ). The etching process can include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes.

In the embodiment as illustrated in FIGS. 2 and 3 , a fin hard mask (HM) layer 810 is formed over the epitaxial stack 120 prior to patterning the fins 130 . In some embodiments, the fin HM layer includes an oxide layer 812 (e.g., a pad oxide layer that may include SiO 2 ) and a nitride layer 814 (e.g., a pad nitride layer that may include Si 3 N 4 ) formed over the oxide layer. The oxide layer 812 may act as an adhesion layer between the epitaxial stack 120 and the nitride layer 814 and may act as an etch stop layer for etching the nitride layer 814 . In some examples, the HM oxide layer 812 includes thermally grown oxide, chemical vapor deposition (CVD)-deposited oxide, and/or atomic layer deposition (ALD)-deposited oxide. In some embodiments, the HM nitride layer 814 is deposited on the HM oxide layer 812 by CVD and/or other suitable techniques.

The fins 130 may subsequently be fabricated using suitable processes including photolithography and etch processes. The photolithography process may include forming a photoresist layer (not shown) over the fin HM layer 810 , exposing the photoresist to a pattern, performing post-exposure bake processes, and developing the resist to form a patterned mask including the resist. In some embodiments, patterning the resist to form the patterned mask element may be performed using an electron beam (e-beam) lithography process or an extreme ultraviolet (EUV) lithography process using light in EUV region, having a wavelength of, for example, about 1-100 nm. The patterned mask may then be used to protect regions of the substrate 110 , and layers formed thereupon, while an etch process forms trenches 102 in unprotected regions through the fin HM layer 810 , through the epitaxial stack 120 , and into the substrate 110 , thereby leaving the plurality of extending fins 130 . The trenches 102 may be etched using a dry etch (e.g., reactive ion etching), a wet etch, and/or combination thereof. Numerous other embodiments of methods to form the fins on the substrate may also be used including, for example, defining the fin region (e.g., by mask or isolation regions) and epitaxially growing the epitaxial stack 120 in the form of the fins 130 .

FIG. 4 illustrates a perspective view of formation of a shallow trench isolation (STI) structure 140 laterally surrounding lower portions of the fins 130 . By way of example and not limitation, a dielectric layer is first deposited over the substrate 110 , filling the trenches 102 with the dielectric material. In some embodiments, the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and/or other suitable materials. In various examples, the dielectric layer may be deposited by a CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a physical vapor deposition (PVD) process, and/or other suitable process. In some embodiments, after deposition of the dielectric layer, the integrated circuit structure 100 may be annealed, for example, to improve the quality of the dielectric layer. In some embodiments, the dielectric layer (and subsequently formed STI structure 140 ) may include a multi-layer structure, for example, having one or more liner layers.

In some embodiments of forming the STI features, after deposition of the dielectric layer, the deposited dielectric material is thinned and planarized, for example by a chemical mechanical polishing (CMP) process. In some embodiments, the fin HM layer 810 (as illustrated FIG. 3 ) functions as a CMP stop layer. The STI structure 140 around the fins 130 is then recessed. Referring to the example of FIG. 4 , the STI structure 140 is recessed providing the fins 130 extending above the STI structure 140 . In some embodiments, the recessing process may include a dry etching process, a wet etching process, and/or a combination thereof. The fin HM layer 810 may also be removed before, during, and/or after the recessing of the STI structure 140 . The nitride layer 814 of the HM layer 810 may be removed, for example, by a wet etching process using H 3 PO 4 or other suitable etchants. In some embodiments, the oxide layer 812 of the HM layer 810 is removed by the same etchant used to recess the STI structure 140 . In some embodiments, a recessing depth is controlled (e.g., by controlling an etching time) so as to result in a target height of the exposed upper portions of the fins 130 . In the illustrated embodiment, the target height exposes each of the layers of the epitaxial stack 120 in the fins 130 .

FIGS. 5A and 5B illustrate a perspective view and a cross-sectional view of formation of a gate structure 150 . In some embodiments, the gate structure 150 is a dummy (sacrificial) gate structure that is subsequently removed. Thus, in some embodiments using a gate-last process, the gate structure 150 is a dummy gate structure and will be replaced by the final gate structure at a subsequent processing stage of the integrated circuit structure 100 . In particular, the dummy gate structure 150 may be replaced at a later processing stage by a high-k dielectric layer (HK) and metal gate electrode (MG) as discussed below. In some embodiments, the dummy gate structure 150 is formed over the substrate 110 and is at least partially disposed over the fins 130 . The portion of the fins 130 underlying the dummy gate structure 150 may be referred to as the channel region. The dummy gate structure 150 may also define a source/drain (S/D) region of the fins 130 , for example, the regions of the fin 130 adjacent and on opposing sides of the channel region.

In the illustrated embodiment, dummy gate fabrication first forms a dummy gate dielectric layer 152 over the fins 130 . In some embodiments, the dummy gate dielectric layer 152 may include SiO 2 , silicon nitride, a high-k dielectric material and/or other suitable material. In various examples, the dummy gate dielectric layer 152 may be deposited by a CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable process. By way of example, the dummy gate dielectric layer 152 may be used to prevent damages to the fins 130 by subsequent processes (e.g., subsequent formation of the dummy gate structure). Subsequently, other portions of the dummy gate structure 150 are formed, including a dummy gate electrode layer 154 and a hard mask structure that may include multiple hard masks 156 and 158 (e.g., a silicon nitride layer 156 and a silicon oxide layer 158 ). In some embodiments, the dummy gate structure 150 is formed by various process steps such as layer deposition, patterning, etching, as well as other suitable processing steps. Exemplary layer deposition processes include CVD (including both low-pressure CVD and plasma-enhanced CVD), PVD, ALD, thermal oxidation, e-beam evaporation, or other suitable deposition techniques, or combinations thereof. In forming the gate structure for example, the patterning process includes a lithography process (e.g., photolithography or e-beam lithography) which may further include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, photoresist developing, rinsing, drying (e.g., spin-drying and/or hard baking), other suitable lithography techniques, and/or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and/or other etching methods. In some embodiments, the dummy gate electrode layer 154 may include polycrystalline silicon (polysilicon). In some embodiments, the hard mask structure includes a nitride mask 156 such as a pad nitride layer that may include Si 3 N 4 or silicon oxynitride, and an oxide mask 158 such as a pad oxide layer that may include SiO 2 . In some embodiments, after patterning the dummy gate electrode layer 154 , the dummy gate dielectric layer 152 is removed from the S/D regions of the fins 130 . The etch process may include a wet etch, a dry etch, and/or a combination thereof. The etch process is chosen to selectively etch the dummy gate dielectric layer 152 without substantially etching the fins 130 , the dummy gate electrode layer 154 , the nitride layer 156 and the oxide layer 158 .

In some embodiments, as illustrated in FIG. 5A , the dummy gate electrode layer 154 has a height 154 H in a range from about 50 nm to about 60 nm, the nitride mask 156 has a thickness 156 T in a range from about 15 nm to about 25 nm (e.g., about 20 nm), and the oxide mask 158 has a thickness 158 T in a range from about 20 nm to about 30 nm. If the oxide mask thickness 158 T is excessively large (e.g., greater than about 30 nm), the dummy gate structures 150 may have an excessively large aspect ratio, which in turn may result in an increased collapse risk in the dummy gate structures 150 . If the oxide mask thickness 158 T is excessively small (e.g., less than about 20 nm), the oxide mask 158 may be too thin to resist against the subsequent etching processing.

In some embodiments, the dummy gate structures 150 have an aspect ratio that is the ratio of dummy gate height (i.e., sum of the dummy gate electrode height 154 H, nitride mask thickness 156 T, and the oxide mask thickness 158 T) to dummy gate width. The aspect ratio of the dummy gate structures 150 is in a range from about 5:1 to about 10:1. If the aspect ratio of the dummy gate structures 150 is excessively large (e.g., greater than about 10:1), the dummy gate structures 150 may collapse. If the aspect ratio of the dummy gate structures 150 is excessively small (e.g., less than about 5:1), the oxide mask thickness 158 T may be too thin to resist against the subsequent etching processing.

FIGS. 5A and 5B also illustrate formation of gate spacers 160 . In some embodiments, a spacer material layer is deposited on the substrate. The spacer material layer may be a conformal layer that is subsequently etched back to form gate sidewall spacers. In the illustrated embodiment, a spacer material layer 160 is disposed conformally on top and sidewalls of the dummy gate structure 150 . The spacer material layer 150 may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN films, silicon oxycarbide, SiOCN films, and/or combinations thereof. In some embodiments, the spacer material layer 160 includes multiple layers, such as a first spacer layer 162 and a second spacer layer 164 (illustrated in FIG. 5B ) formed over the first spacer layer 162 , wherein the first spacer layer 162 has a lower dielectric constant than the second spacer layer 164 . For example, the first spacer layer 162 includes porous silicon oxide, and the second spacer layer 164 includes silicon nitride or silicon oxynitride. The spacer material layer 160 may be formed by depositing a dielectric material over the gate structure 150 using processes such as, CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable process. An anisotropic etching process is then performed on the deposited spacer material layer 160 to expose portions of the fins 130 not covered by the dummy gate structure 150 (e.g., in source/drain regions of the fins 130 ). Portions of the spacer material layer directly above the <figure-callout id="150" label="dummy gate structure" filenames="US11456182-20220927-D

CLAIMS

Claims ( 20 )

What is claimed is:

1. A method comprising:

forming a fin structure extending above a substrate;

forming dummy gate structures extending across the fin structure, each of the dummy gate structures including a dummy gate electrode layer and a hard mask layer over the dummy gate electrode layer;

performing an ion implantation process to dope the hard mask layers of the dummy gate structures;

after performing the ion implantation process to dope the hard mask layers of the dummy gate structures, performing a first etching process to etch a source/drain region of the fin structure between the dummy gate structures to form a recess in the source/drain region of the fin structure;

forming an epitaxial structure in the recess; and

replacing the dummy gate structures with metal gate structures.

2. The method of claim 1 , wherein the ion implantation process is performed at a tilt angle.

3. The method of claim 1 , wherein the fin structure is not doped by the ion implantation process.

4. The method of claim 1 , wherein the ion implantation process forms doped regions in the hard mask layers of the dummy gate structures, while leaving other regions of the hard mask layers of the dummy gate structures un-doped.

5. The method of claim 4 , wherein the doped regions of the hard mask layers have a higher etch resistance to the first etching process than that of the un-doped regions of the hard mask layers.

6. The method of claim 1 , further comprising:

after performing the ion implantation process and before performing the first etching process, forming a patterned organic material over the substrate, the patterned organic material having an opening over the source/drain region of the fin structure,

wherein the first etching process etches the patterned organic material at a faster etch rate than etching the doped hard mask layers.

7. The method of claim 1 , further comprising:

forming a source/drain epitaxial structure on the epitaxial structure; and

after forming the source/drain epitaxial structure on the epitaxial structure, replacing the epitaxial structure with a backside metal via.

8. The method of claim 1 , further comprising:

after forming the dummy gate structures and before performing the ion implantation process, performing a second etching process to etch the source/drain region of the fin structure, wherein the fin structure comprises a stack of alternating first semiconductor layers and second semiconductor layers, and the second etching process is performed until a top surface of the source/drain region of the fin structure is below a bottommost one of the second semiconductor layers.

9. The method of claim 8 , wherein the first semiconductor layers and the second semiconductor layers are not doped by the ion implantation process.

10. The method of claim 8 , further comprising:

after performing the second etching process, laterally recessing the first semiconductor layers; and

forming inner spacers on end surfaces of the laterally recessed first semiconductor layers, wherein the ion implantation process is performed after the inner spacers are formed.

11. The method of claim 10 , wherein the inner spacers are not doped by the ion implantation process.

12. The method of claim 8 , wherein replacing the dummy gate structures with the metal gate structures comprises:

removing the dummy gate structures;

after removing the dummy gate structures, removing the first semiconductor layers such that the second semiconductor layers are suspended above the substrate; and

forming the metal gate structures surrounding each of the suspended second semiconductor layers.

13. An integrated circuit (IC) structure comprising:

a gate structure;

gate spacers on either side of the gate structure;

source/drain epitaxial structures adjacent to the gate spacers, respectively;

a front-side interconnection structure on a front-side of the source/drain epitaxial structures;

a backside dielectric layer on a backside of the source/drain epitaxial structures; and

a backside via extending through the backside dielectric layer to the backside of a first one of the source/drain epitaxial structures, wherein the gate spacers have a concentration of a dopant decreasing toward the backside via.

14. The IC structure of claim 13 , further comprising:

a plurality of semiconductor channel layers arranged one above another in a spaced apart manner, the plurality of semiconductor channel layers laterally extending from the first one of the source/drain epitaxial structures to a second one of the source/drain epitaxial structures, the gate structure surrounding each of the plurality of semiconductor channel layers.

15. The IC structure of claim 14 , further comprising:

a plurality of inner spacers alternately arranged with the plurality of semiconductor channel layers, wherein the plurality of inner spacers has a lower concentration of the dopant of the gate spacers.

16. The IC structure of claim 14 , wherein the plurality of semiconductor channel layers has a lower concentration of the dopant of the gate spacers.

17. The IC structure of claim 13 , wherein the dopant is a Group III element or a Group V element.

18. A method comprising:

forming a dummy gate structure over a substrate, and gate spacers on opposite sides of the dummy gate structure;

epitaxially growing source/drain structures on regions of the substrate beyond the dummy gate structure and the gate spacers;

forming an interlayer dielectric (ILD) layer over the source/drain structures;

replacing the dummy gate structure with a metal gate structure;

recessing the metal gate structure to fall below top ends of the gate spacers;

forming a gate hard mask over the recessed metal gate structure;

performing an ion implantation process to dope the gate hard mask;

after performing the ion implantation process to dope the gate hard mask, etching the ILD layer to form source/drain contact openings over the source/drain structures, respectively; and

forming source/drain contacts in the source/drain contact openings, respectively.

19. The method of claim 18 , wherein the ion implantation process is performed at a tilt angle.

20. The method of claim 18 , wherein the ion implantation process also dopes the gate spacers.

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